TW569317B

TW569317B - Method for producing silicon interconnect with various dopants

Info

Publication number: TW569317B
Application number: TW91135267A
Authority: TW
Inventors: Zin-Chein Wei; Chuan-Chieh Huang; Chih Hsiung Lee
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-12-05
Filing date: 2002-12-05
Publication date: 2004-01-01
Also published as: TW200410319A

Abstract

A method for producing a silicon interconnect with various dopants comprises defining a plurality of silicon interconnects on a semiconductor substrate; and using a means of protecting the semiconductor substrate by alternatively forming a protective layer and a mask layer to perform an ion implantation on the to-be-doped silicon interconnects to form silicon interconnects with various dopants.

Description

569317569317

發明所屬之技術領域：本發明係有關於一在一半導體基底上形成先前技術：種形成矽連線之方法，特別有關於不同摻質型矽連線的方法。曰^ 1則，在半導體製程中，有兩種形成N/p不同摻質複 :石匕!方法。第一種方法是在半導體基底上形成兩個複 :石S < ，分別進行離子植入而形成N型複晶矽層以及p型稷晶矽層。然而該方法必須直接對半導體基底進行離子入，對淺接合區將有不良影響，因而在製程上並不是 hh rs T八 I 土第二種方法，請參照第1A〜1C圖，是先於如第1A圖所不之半導體基底100上全面形成一複晶矽層11〇，以離子植入，如第1 B圖所示，分別植入N型以及p型離子後，再予以蝕刻形成如第1C圖所示之N型矽連線丨丨2以及p型矽連線u 4 :第Γ種t法中，為了避免干擾到後續的NLDD植入，通常是在定義複晶矽層（p〇ly define)之前進行離子植入 (imPlantation)。在這樣的情形下，針對不同摻質之矽連線的相異蝕刻特·性，必須調整蝕刻的參數等等以得到良好輪廓（profile)的複晶矽層。然而，上述方法不容易得到良好的外型圖案（line pattern)，特別是在不同的植入劑量以及植入的離子種類的操作條件下。也就是說，若以蝕刻同時形成N/PM0S，將增加控制蝕刻步驟的困難度，進而影響產品良率。發明内容：The technical field to which the invention belongs: The present invention relates to a method for forming a silicon substrate on the prior art: a method for forming a silicon connection, and more particularly, a method for forming a silicon connection with different dopant types. ^ 1, in the semiconductor process, there are two ways to form different N / p dopant complex: stone dagger! Method. The first method is to form two complexes: stone S < on the semiconductor substrate, and perform ion implantation to form an N-type polycrystalline silicon layer and a p-type holmium silicon layer. However, this method must be directly ion-implanted into the semiconductor substrate, which will have an adverse effect on the shallow junction area. Therefore, it is not the second method of hh rs T eight I soil in the manufacturing process. Please refer to Figures 1A ~ 1C before As shown in FIG. 1B, after implanting N-type and p-type ions, the polycrystalline silicon layer 11 is formed on the semiconductor substrate 100 as shown in FIG. 1A. The N-type silicon connection shown in Figure 1C 丨 2 and the p-type silicon connection u 4: In the Γ t method, in order to avoid interference with subsequent NLDD implantation, a polycrystalline silicon layer is usually defined (p.o. ly define) before performing ion implantation (imPlantation). In such a case, for different etching characteristics of differently doped silicon wires, it is necessary to adjust etching parameters and the like to obtain a good-profile polycrystalline silicon layer. However, the above method is not easy to obtain a good line pattern, especially under the operating conditions of different implant doses and implanted ion types. That is, if N / PM0S is simultaneously formed by etching, it will increase the difficulty of controlling the etching step, and then affect the product yield. Summary of the invention:

569317 五、發明說明（2) 方法有^ ί此，本發明提供一種形成不同摻質型矽連線的第1故、^括·· a)在一半導體基底上形成一第一矽連線及一線， '’、b)形成一第一蝕刻材料層以覆蓋該第一矽連中該第一 2成第一蝕刻材料層以覆蓋該第二矽連線，其執行一第一=::::蝕刻率高於該第二#刻材料層；c) 入一楚4A蝕刻〆驟使該第一矽連線露出摻雜表面，· d)植心d質於該第一石夕連線，形成-第-摻質型石夕連線，第_ 1 °a弟蝕刻材料層及第二蝕刻材料層；f)形成蝕刻材料声以矽連線，以及形成該第-驟料笛-覆第二石夕連線；g) #行一第二钱刻步質於i第Σ = 露出㈣表面；以及h)才直入一第二摻 ' 一夕連線，形成一第二摻質型矽連線。 =本發明之另—實施例，#步驟包括：a)在_ 一二=u形成了第=石夕連線及一第二石夕連線；b)形成一第 χΙ材料層以覆蓋該第一矽連線以及該第二矽連線.、 Γ:: Γη㈣步驟使該第一靖及該第二石夕連線露。出569317 V. Description of the invention (2) The method has the following advantages: The present invention provides a first method for forming different doped silicon connections, including: a) forming a first silicon connection on a semiconductor substrate and One line, '', b) forming a first etching material layer to cover the first 20% first etching material layer in the first silicon connection to cover the second silicon connection, which performs a first = :::: The etch rate is higher than the second #etched material layer; c) A 4A etching step is performed to expose the first silicon connection to the doped surface, and d) a heart implant d is formed on the first stone connection to form -The first doped-type Shi Xi line, the first etched material layer and the second etched material layer; f) forming the etching material and the silicon line, and forming the first-burst flute-covered second Shi Xi connection; g) # 行一 second money engraving step i i Σ = exposed ㈣ surface; and h) directly into a second doped 'yixi connection to form a second doped silicon connection . = Another embodiment of the present invention, # The steps include: a) forming a second Shixi connection and a second Shixi connection at _12 = u; b) forming a χΙ material layer to cover the first A silicon connection and the second silicon connection. The Γ :: Γη㈣ step exposes the first Jing and the second Shixi connection. Out

雜=植= 該第二彻U 第-摻質型石夕連線；e)移除該第一遮蔽層以及該而：刻材料層；f)形成一第二蝕刻材料層以覆蓋爷^ — 推質型石夕連線以及該第二矽連線；g)進行一第二二^一驟使該第-摻質型料線及該第二料線露出摻/步 h)形成一第二遮蔽層以覆蓋該第一換 x ，表面，植入一第二推質於該第二心之？質連表义 0503-6924TWF(Nl) ； TSMC2001-0890'0914 ； Phoebe.ptd 第5頁 569317 五、發明說明（3) 第第型矽連線’·以及^ #除該第二遮蔽層以及該系一蝕刻材料層。方法為1 ^ Ϊ本發明，本發明之形成不同摻質型矽連線的質型的功4 ^義出複晶矽層，再加以離子植入形成不同摻免，線，並利用光阻層作為遮蔽層保護半導體基底 ί?;:子植入過程受到影響。料，由於本發明之石夕連中:ΐίϊΪ子植入前先定義其圖案，因此沒有習知技術 ·心蝕刻製程中控制成良好圖案或者蝕刻偏壓品^ )的問題，而能減低製程的複雜度，並提高產下々^ I Ϊ本發明之上述目㈤、特徵和優點更明顯易懂，、牛較佳貫施例，並配合所附圖示，作詳細說明如 r · 實施方式：不π il二^第2Α 2 1目’其顯示本發明之實施例中，形成不同摻負型矽連線的製程剖面圖。石“士： ί 1、在一半導體基板10 0上全面性形成·^如以複晶 : 之矽層109，接著如第2Α圖形成光阻120後蝕刻道Μ β 4 矽連線ill及第二矽連線112於半導體基板100上’如第2B圖所示。、：:後’如第2C圖所示，分別形成第-蝕刻材料層122 1及第二钱刻材料層124用以覆蓋該等長條狀矽連線111、。δ亥蝕刻材料層為例如一具有第一感光度之光阻 •’而該第二蝕刻材料層為例如一具有第二感光度之光阻，Miscellaneous = plant = the second U-doped-type stone line; e) remove the first shielding layer and: etched material layer; f) form a second etched material layer to cover the ^^ The push-type Shixi connection and the second silicon connection; g) perform a second two-two step to expose the first dopant-type material line and the second material line to dope / step h) to form a second A masking layer to cover the surface of the first change x, implant a second pusher on the second heart? Tandem expression 0503-6924TWF (Nl); TSMC2001-0890'0914; Phoebe.ptd page 5 569317 5. Description of the invention (3) The first type of silicon connection 'and ^ # Except the second shielding layer and the A layer of etching material. The method is as follows: In the present invention, the work of forming the quality of different doped silicon connections in the present invention is defined as a polycrystalline silicon layer, and ion implantation is performed to form different doped silicon wires, and a photoresist layer is used. As a shielding layer, the semiconductor substrate is protected; the sub-implantation process is affected. It is expected that because the Shi Xilianzhong of the present invention: defines the pattern before implantation, there is no problem of controlling the pattern into a good pattern or etching bias product in the conventional technology · heart etching process, and it can reduce the complexity of the process And increase the productivity. The above-mentioned objectives, features, and advantages of the present invention are more obvious and easier to understand. The embodiments are better implemented in conjunction with the accompanying drawings and described in detail as r. π il 2 ^ 2A 2 1 'It shows a cross-sectional view of a process for forming different negatively doped silicon connections in the embodiment of the present invention. Shi Shi: ί 1. Fully formed on a semiconductor substrate 100, such as a polycrystalline silicon layer 109, and then form a photoresist 120 as shown in FIG. 2A, and then etch the channel M β 4 and the silicon connection ill and the first. As shown in FIG. 2B, two silicon lines 112 are formed on the semiconductor substrate 100. As shown in FIG. 2C, a first etching material layer 1221 and a second coining material layer 124 are formed to cover The long silicon connection lines 111, δ, and the etched material layer are, for example, a photoresist having a first sensitivity, and the second etching material layer is, for example, a photoresist with a second sensitivity.

)69317) 69317

較佳於該第二感光度。該第-感光度光阻為= :光阻材料，"該第二感光度光阻光後，由 ^ ^ ,g之光阻材料。對該等光阻進行曝來可選摞你：nV特性之差異’被蝕刻率不同，因此接下 ;用或釺電漿以乾式顯影執行㈣，移除部分之餘刻材料層122而露出第一石夕連線ui之摻質表面如第_=材料層124則保持覆蓋著該第4連線ιΐ2. 接著，對露出之第一矽連植入而形成P型矽連線130，如知方法移除剩餘的第二蝕刻材 122。線U 1之摻質表面進行離子第2 E圖所示。然後以一般習料層1 24及第一蝕刻材料層、，重複上述步驟於半導體基板1 〇〇上分別形成第一蝕刻材，層122覆蓋該第二矽連線112以及第二蝕刻材料層124 覆蓋該P型矽連線丨30，如第2F圖所示。該等蝕刻材料層之感光度的限制與上述相同，也就是第一蝕刻材料層之感光度大於該第二蝕刻材料層之感光度。接著，與上述相同進行曝光後，以〇2或Ar電漿進行乾蝕刻該第一蝕刻材料層 122而露出該第二矽連線丨12之摻質表面並保留覆蓋該p型石夕連線130之第二蝕刻材料層124，如第2G圖所示。接著對露出之該第二矽連線11 2之摻質表面進行離子植入，而形成N型矽連線132，如第2H圖所示。最後，移除第一蝕刻材料層1 22以及第二蝕刻材料層1 24而得如第2 I圖所示之N型矽連線132與P型矽連線130。Better than the second sensitivity. The first-sensitivity photoresist is =: photoresist material, and the second-sensitivity photoresist is made of ^^, g photoresist material. Exposure to these photoresistors is optional: you: the difference in nV characteristics' is different in the etching rate, so next; use or 釺 plasma to perform dry development㈣, remove part of the remaining material layer 122 to expose the first The dopant surface of the first lithography connection ui such as the _ = material layer 124 remains covered with the fourth connection ι2. Then, the exposed first silicon connection is implanted to form a P-type silicon connection 130, as known The method removes the remaining second etching material 122. The doped surface of line U 1 is ionized as shown in Figure 2E. Then, using the general material layer 1 24 and the first etching material layer, the above steps are repeated to form a first etching material on the semiconductor substrate 1000, and the layer 122 covers the second silicon connection line 112 and the second etching material layer 124. Cover the P-type silicon connection 30, as shown in Figure 2F. The limitation of the sensitivity of the etching material layers is the same as that described above, that is, the sensitivity of the first etching material layer is greater than that of the second etching material layer. Next, after the exposure is performed in the same manner as described above, the first etching material layer 122 is dry-etched with O 2 or Ar plasma to expose the doped surface of the second silicon connection 12 and retain the p-type stone evening connection. The second etching material layer 124 of 130 is shown in FIG. 2G. Then, ion implantation is performed on the exposed doped surface of the second silicon connection 112, to form an N-type silicon connection 132, as shown in FIG. 2H. Finally, the first etching material layer 122 and the second etching material layer 124 are removed to obtain an N-type silicon connection 132 and a P-type silicon connection 130 as shown in FIG. 2I.

〇503-6924TWF(Nl) ； TSMC2001-0890'0914 ； Phoebe.ptd 第7頁 569317 五、發明說明（5) 說明本發明之另一實施例，請參照第3Α〜3ι圖， ^半V體基板200上全面性形成一矽層2〇9，接著 =么阻220後餘刻該石夕層2°9而形成兩個長條狀的^- 二石夕連線212於該半導體基板2°〇上，如第然後全面性形成一第一蝕刻材料層222 連線m及該第二料線212以及該半導體基底州弟^ 3^所不。接著以蝕刻移除部分第一蝕刻材料層&露出圖矽ί線211及該第二矽連線212的摻質表面，如第3D 二不。接下來，再形成一第一遮蔽層224覆蓋該第二矽連^212，然後，如第3Ε圖所示對露出之第一矽連線之摻質表面進行離子植入而形成ρ型矽連線23〇後，移除該一遮蔽層224與該第一蝕刻材料層2 22。上述之第一遮°蔽芦與該第-钕刻材料層係可選擇相同或相異之光阻材料，言二光阻材料例如為底部抗反射塗料（Bottom〇503-6924TWF (Nl); TSMC2001-0890'0914; Phoebe.ptd page 7 569317 5. Description of the invention (5) To describe another embodiment of the present invention, please refer to FIGS. 3A to 3m. A silicon layer 209 was comprehensively formed on 200, and then the stone layer 2 ° 9 was formed after the resistance 220 to form two long ^-two stone lines 212 on the semiconductor substrate 2 °. As described above, a first etched material layer 222, a line m, the second material line 212, and the semiconductor substrate are completely formed as described above. Then, a part of the first etching material layer & is exposed by etching to expose the doped surface of the silicon line 211 and the second silicon line 212, as shown in 3D. Next, a first shielding layer 224 is formed to cover the second silicon connection 212, and then, as shown in FIG. 3E, the doped surface of the exposed first silicon connection is ion-implanted to form a p-type silicon connection. After line 230, the shielding layer 224 and the first etching material layer 22 are removed. The first shielding layer and the first-neodymium engraved material layer may be the same or different photoresist materials. The second photoresist material is, for example, a bottom anti-reflective coating (Bottom

Anti-ref lection coating; BARC)。接著’重新再形成一第二姓刻材料層2 2 6覆蓋該半導體基板20 0及該第二矽連線212與ρ型矽連線23〇，如第”圖所示。接著，以與上述同樣的電漿蝕刻步驟移除部分之^ 第二蝕刻材料層226露出該第二矽連線212的摻質表面與jT 型石夕連線230的頂部，如第3G圖所示。、 ^然後形成第二遮蔽層228用以覆蓋該ρ型矽連線23〇。如第3H圖所示，再對露出之該第二矽連線212的摻質表面進行離子植入而形成N型矽連線232。上述之第二遮蔽層與Anti-ref lection coating; BARC). Then 're-form a second engraved material layer 2 2 6 to cover the semiconductor substrate 200 and the second silicon connection 212 and the p-type silicon connection 23, as shown in the figure.' The same plasma etching step removes a part of the second etching material layer 226 to expose the doped surface of the second silicon line 212 and the top of the jT-type stone line 230, as shown in FIG. 3G. A second shielding layer 228 is formed to cover the p-type silicon connection 23. As shown in FIG. 3H, an ion implantation is performed on the exposed doped surface of the second silicon connection 212 to form an N-type silicon connection. Line 232. The second shielding layer described above and

569317 五、發明說明（6) 該第二蝕刻材料層係為相同或底部抗反射塗料。最後移除該二遮蔽層2 2 8而得到具有N型石夕半導體基板20 0。上述兩個實施例中皆是先連線，但不限於此，亦可先形線。在完成上述步驟形成N及P 下列步驟，利用離子植入步驟 (L D D )區域之源/汲極，並以極連線，構成NMOS及PMOS電晶雖然本發明已以較佳實施限定本發明，任何熟習此技藝和範圍内，當可作些許之更動範圍當視後附之申請專利範圍相異之光阻材料所形成，如第二颠刻材料層2 2 6及該第連線232與p型矽連線23〇的形成？型矽連線再形成N型矽成N型矽連線再形成p型矽連型石夕連線後，可進一步執行於半導體基底形成具淡摻雜該不同摻質型矽連線作為閘體。例揭露如上，然其並非用以者，在不脫離本發明之精神與潤飾，因此本發明之保護所界定者為準。 ' "569317 5. Description of the invention (6) The second etching material layer is the same or bottom anti-reflective coating. Finally, the two shielding layers 2 2 8 are removed to obtain an N-type Shixi semiconductor substrate 20 0. In the above two embodiments, the wires are connected first, but are not limited thereto, and the wires may be formed first. After completing the above steps to form N and P, the source / drain of the ion implantation step (LDD) region is used and the electrodes are connected to form NMOS and PMOS transistors. Although the present invention has been limited to the present invention by a preferred implementation, Anyone who is familiar with this technique and scope can make some slight changes to the scope. It is formed by the photoresist materials with different patent scopes attached, such as the second inversion material layer 2 2 6 and the first connection lines 232 and p. Formation of Type Silicon Connection 23〇? After the N-type silicon connection is formed into the N-type silicon connection and then the p-type silicon connection is formed, the silicon connection can be further performed on the semiconductor substrate to form a lightly doped silicon connection with different dopants as a gate body. . The example is disclosed as above, but it is not intended to be used without departing from the spirit and retouching of the present invention. Therefore, what is defined by the protection of the present invention shall prevail. '"

569317 圖式簡單說明第1 A〜1 C圖係顯示習知技術之形成不同摻質型矽連線的製程剖面圖。第2 A〜2 I圖係顯示本發明之一實施例的製程剖面圖。第3A〜31圖係顯示本發明之另一實施例的製程剖面圖。 [符號說明] 100、2 0 0〜半導體基底； I 0 9〜矽層； 111〜第一矽連線； II 2〜第二石夕連線；569317 Brief description of the diagrams Figures 1 A to 1 C are cross-sectional views showing the processes of forming silicon doped wires of different dopant types using conventional techniques. Figures 2A to 2I are cross-sectional views of a manufacturing process according to an embodiment of the present invention. 3A to 31 are cross-sectional views showing a process of another embodiment of the present invention. [Symbol description] 100, 2000 ~ semiconductor substrate; I 0 9 ~ silicon layer; 111 ~ first silicon connection; II 2 ~ second Shixi connection;

120、220、222〜蝕刻材料層； 1 0 9、2 0 9〜複晶矽層； 114、130、23 0〜P型矽連線； U2、132、232〜N型矽連線； 122、222〜第一蝕刻材料層； 124、226〜第二蝕刻材料層； 224〜第一遮蔽層； 228〜第二遮蔽層。120, 220, 222 ~ etched material layer; 109, 209 ~ multi-crystalline silicon layer; 114, 130, 230 ~ P type silicon connection; U2, 132, 232 ~ N type silicon connection; 122, 222 ~ first etching material layer; 124,226 ~ second etching material layer; 224 ~ first shielding layer; 228 ~ second shielding layer.

0503-6924TWF(Nl) ； TSMC2001-0890'0914 ； Phoebe.ptd 第10頁0503-6924TWF (Nl); TSMC2001-0890'0914; Phoebe.ptd page 10

Claims

569317 六、申請專利範圍 1 · 一種形成不同摻質型矽連線之方法，包括下列步驟 (a)在一半導體基底上形成一第一矽連線及，第二發及形(Γ—形第成二—Λ一材银料刻/Λ層—以Λ蓋該第一石夕連線，以 -兹刻材料層之颠刻率；二η::連線’其中該第 —挪〜手问於該第一蝕刻材料層；面；執订第一蝕刻步驟使該第一矽連線露出摻雜表連線 (石入一第一摻質於該第一矽連線，形成質型矽連線； (e)移除該第-(〇形成該第第一敍刻執行一第植入一第線。申請專利，其中該申請專利，其中該該第二蝕一感光度及形成該(g) 面；以及(h) 質型矽連 2 ·如線之方法 3.如線之方法光阻；而其中該第第一摻一姓刻材料層及該第二蝕刻材料層；二餘刻材料層以覆蓋該第一矽連線材料層以覆蓋該第二矽連線；一餘刻步驟使該第二矽連線露出摻雜表一換質於該第二矽連線，形成一第二摻 I色圍第1項所述之形成不同摻質型矽連石夕連線為複晶矽。範圍第1項所述之形成不同摻質型矽連第一姓刻材料層為一具有第一感光度之刻材料層為一具有第二感光度之光阻，高於該第二感光度。以569317 VI. Scope of patent application1. A method for forming different doped silicon connections, including the following steps (a) forming a first silicon connection on a semiconductor substrate, and Into two-Λ 一材银料刻 / Λ layer-cover the first stone line with Λ, and-engraving rate of the material layer; two η :: connection 'where the first-move ~ hand ask A first etching step is performed on the first etching material layer; the first etching step is performed to expose the first silicon connection to the doped surface connection (a first dopant is added to the first silicon connection to form a quality silicon connection; (E) Remove the first-(0) to form the first etch and perform a first implant-first line. Apply for a patent, where the patent application, where the second etch a sensitivity and form the (g ) Surface; and (h) qualitative silicon connection 2 · method such as wire 3. method such as wire photoresist; and wherein the first doped first material layer and the second etched material layer; two remaining material Layer to cover the first silicon connection material layer to cover the second silicon connection; a step of exposing the second silicon connection to expose the doped surface; The second silicon connection forms a second doped I color doped silicon connection stone as described in item 1 above, which is polycrystalline silicon. The range described in item 1 forms different doped silicon. Even the first engraved material layer is a engraved material layer with a first sensitivity, which is a photoresist with a second sensitivity, which is higher than the second sensitivity.

569317569317

線之·如申凊專利範圍第3項所述之形成不同摻質型矽連阻材3法’其中該第一感光度光阻為實質上完全感光之光从、M料’而该第二感光度光阻為實質上完全不感光之光阻線 ·如申請專利範圍第4項所述之形成不同摻質型矽連 ^ ^ 其中步驟（b )係透過曝光步驟使該第一感光度先阻餘刻率高於該第二感光度光阻。線6 ·如申睛專利範圍第1項所述之形成不同摻質型矽連、之方法’其中步驟（c)係以乾式顯影執行蝕刻，使該第一石夕連線露出摻雜表面。 7 ·如申請專利範圍第1項所述之形成不同摻質型矽連、1之方法’其中步驟（g)係以乾式顯影執行蝕刻，使該第一秒連線露出摻雜表面。 8 ·如申清專利範圍第1項所述之形成不同摻質型石夕連 ί之方法，其中該第一摻質為P型摻質，該第二摻質為N型摻質。 9 ·如申请專利範圍第1項所述之形成不同摻質型矽連 f之方法’其中更包括下列步驟：利用離子植入步驟於該半導體基底形成具淡摻雜（LDD)區域之源/汲極，並以該不同摻質型矽連線作為閘極連線，構成NM〇s &pM〇s 體。 10· —種形成不同摻質型矽連線之方法，其包括步驟： (a)在一半導體基底上形成一第一矽連線及一第二矽The method of forming a different doped silicon interconnect material as described in item 3 of the Shen's patent scope 'where the first photoresist is a substantially completely light-sensitive photoconductor, and the second Sensitivity photoresist is a photoresist line that is substantially completely non-photosensitive. Forming different doped silicon chains as described in item 4 of the scope of patent application ^ ^ wherein step (b) is to make the first sensitivity first through the exposure step. The retardation ratio is higher than the second sensitivity photoresist. Line 6: The method of forming different doped silicon chains as described in item 1 of the Shenjing patent scope, wherein step (c) is performed by dry development to expose the first stone line to the doped surface. 7 · The method for forming different doped silicon interconnects, 1 as described in item 1 of the scope of the patent application, wherein step (g) is performed by dry development to expose the first second connection line to the doped surface. 8. The method for forming different dopant type Shi Xilian as described in item 1 of the scope of Shenqing patent, wherein the first dopant is a P-type dopant and the second dopant is an N-type dopant. 9 · The method for forming different doped silicon chains f as described in item 1 of the scope of the patent application, which further includes the following steps: using an ion implantation step to form a source of lightly doped (LDD) regions on the semiconductor substrate / The drain and the different doped silicon connections are used as gate connections to form a NMs & pMos body. 10. · A method of forming different doped silicon connections, comprising the steps of: (a) forming a first silicon connection and a second silicon on a semiconductor substrate;

六、申請專利範圍連線； (b)形成—楚一該第二矽連線；刻材料層以覆蓋該第一矽連線以及連線露^Ι'Ά—㈣步驟使該第-料線及該第二石夕 (d) 形成_繁_ 面，植入-第一摻質於蔽該層以一覆蓋該第二石夕連線之摻雜表第一摻質型矽連線；、、/ 連線之摻質表面而形成一 (e) 移除該第一被γ a (f) 形成一ί _ί 及該第一蝕刻材料層；線以及該第二矽連線；J材料層以覆蓋該第一摻質型矽連 *二步驟使該第-推質型料線及該旅形成一第二遮蔽層以覆蓋該第一摻質型矽連蝮之摻雜表面，植入一筮一边^ ^ 只土’思琛之形成一第一 Ξ二第-摻質於該第二矽連線之摻質表面而开ν成第一摻質型矽連線；以及移除該第二遮蔽層％不一延敝層以及該第二蝕刻材料層。 1 1 ·如申請專利範圍第丨〇項所述之形成不同摻質型石夕連線之方法，其中該第一蝕刻材料層以及該第二蝕刻材料層係為一般光阻材料。 12·如申請專利範圍第11項所述之形成不同摻質型石夕連線之方法，其中該光阻材料為底部抗反射塗料（Barc： )° 13 ·如申請專利範圍第1 〇項所述之形成不同摻質型矽6. The connection line for patent application; (b) forming—the second silicon connection; etch a material layer to cover the first silicon connection and the connection exposure; And the second stone evening (d) forms a _traditional_plane, implanted-first dopant on the layer that covers the second stone evening with a doping table of the first stone doped silicon connection; And / or the doped surface of the connection to form an (e), remove the first substrate γ a (f) to form a __ and the first etching material layer; the line and the second silicon connection; the J material layer is The first step of covering the first doped silicon wafer is performed in two steps to form a second shielding layer for the first push-type material line and the bridging layer to cover the doped surface of the first doped silicon wafer and implant a stack of silicon oxide. On one side ^ ^ the formation of a first silicon doped first-doped silicon doped on the second silicon connection to form a first doped silicon connection; and removing the second shielding The layer% is not an extension layer and the second etching material layer. 1 1 · The method for forming different doped-type stone wires as described in the scope of the patent application, wherein the first etching material layer and the second etching material layer are general photoresist materials. 12. The method for forming different dopant-type Shixi lines as described in item 11 of the scope of patent application, wherein the photoresist material is a bottom anti-reflective coating (Barc:) ° 13. As described in the scope of patent application No. 10 Formation of different doped silicon

第13頁 0503-6924TWF(Nl) ； TSMC2001-0890'0914 ； Phoebe.ptd — 569317 六、申請專利範圍連線之方法，其中該第一遮蔽層以及該第二遮蔽層係以一般光阻材料形成。 1 4.如申請專利範圍第1 3項所述之形成不同摻質型矽連線之方法，其中該光阻材料為底部抗反射塗料（BARC )° 1 5 ·如申請專利範圍第1 0項所述之形成不同摻質型矽連線之方法，其中步驟（c)係以乾式顯影執行蝕刻，使該第一矽連線露出摻雜表面。 1 6.如申請專利範圍第1 0項所述之形成不同摻質型矽連線之方法，其中（g)係以乾式顯影執行蝕刻，使該第二矽連線露出摻雜表面。 1 7.如申請專利範圍第1 0項所述之形成不同摻質型矽連線之方法，其中該第一摻質為P型摻質，第二摻質為N型摻質。 1 8.如申請專利範圍第1 0項所述之形成不同摻質矽連線之方法，其中更包括下列步驟：利用離子植入步驟於半導體基底形成具淡換雜（LDD)區域之源/汲極5並以該不同摻質型矽連線作為閘極連線，構成NMOS及PMOS電晶體。Page 13 0503-6924TWF (Nl); TSMC2001-0890'0914; Phoebe.ptd — 569317 6. Method for connecting patent applications, wherein the first shielding layer and the second shielding layer are formed of a general photoresist material . 1 4. The method of forming different doped silicon connections as described in item 13 of the scope of patent application, wherein the photoresist material is a bottom anti-reflective coating (BARC) ° 1 5 · as item 10 of the scope of patent application The method for forming different doped silicon connections, wherein step (c) is performing dry etching to expose the first silicon connection to the doped surface. 16. The method for forming different doped silicon connections as described in item 10 of the scope of the patent application, wherein (g) is performed by dry development to expose the second silicon connection to the doped surface. 1 7. The method for forming different dopant-type silicon connections as described in item 10 of the scope of the patent application, wherein the first dopant is a P-type dopant and the second dopant is an N-type dopant. 1 8. The method for forming different doped silicon connections as described in item 10 of the scope of the patent application, which further includes the following steps: using an ion implantation step to form a source with a lightly doped (LDD) region on the semiconductor substrate / The drain 5 uses the different doped silicon connections as gate connections to form NMOS and PMOS transistors.

0503-6924TWF(Nl) ； TSMC2001-0890'0914 ； Phoebe.ptd 第14頁0503-6924TWF (Nl); TSMC2001-0890'0914; Phoebe.ptd page 14