TW565856B - Switch circuit able to improve the memory write timing and the operating method thereof - Google Patents

Switch circuit able to improve the memory write timing and the operating method thereof Download PDF

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Publication number
TW565856B
TW565856B TW091115764A TW91115764A TW565856B TW 565856 B TW565856 B TW 565856B TW 091115764 A TW091115764 A TW 091115764A TW 91115764 A TW91115764 A TW 91115764A TW 565856 B TW565856 B TW 565856B
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Taiwan
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data
memory
signal
timing
improving
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TW091115764A
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Chinese (zh)
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Jiin Lai
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Via Tech Inc
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Priority to US10/247,664 priority Critical patent/US6717885B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

A switch circuit able to improve the memory write timing and the operating method thereof. The present invention makes the data effective interval of the received data increase by the timing control circuit and the latch, therefore it can improve the memory write timing between the memory controller and the memory. In addition, the present invention makes the received data strobe signal delay a specific time by the delay circuit so that the memory write timing has the enough timing margin more than the memory setup time.

Description

經濟部智慧財產局員工消費合作社印製 565856 A7 8314twf.doc/006 B7 五、發明說明（I) 本發明是有關於一種開關電路，且特別是有關於一種 能改善記憶體寫入時序的開關電路及其運作方法。 動態隨機存取記憶體（Dynamic Random Access Memory，簡稱DRAM)已由非同步DRAM，例如早期的快 頁（Fast-Page)DRAM 及延伸資料輸出（Extended Data 〇Utput)EDO DRAM，發展到同步動態隨機存取記憶體 (Synchronous Dynamic Random Access Memory，簡稱 SDRAM)。而目前高速匯流排都是採用同步源的方法來達 成資料的傳輸，例如雙倍資料速率(Double Data Rate)同步 動態隨機存取記憶體(簡稱DDR記憶體）匯流排，圖形加 速;t阜(Accelerated Graphic Port，簡稱 AGP)匯流排、或者 藍巴士（RAMBUS)記憶體匯流排等。此外這些高速的匯流 排還需要差動訊號來輔助資料的傳輸。因此，以目前的技 術，同時結合同步源與差動訊號就可達成高速資料傳輸的 目的。 、 DRAM工業的市場非常龐大，但是它的發展很緩慢， 通常需要三到五年才會有新的標準。因此，如何提昇DRAM 的頻寬變的愈來愈重要。在網際網路的應用上，DRAM頻 寬的不足變的特別明顯。因爲網際網路需要大量轉移資 料，而如果DRAM頻寬不足，會由於資料傳遞過慢，而 使使用者既耗時又耗財。 由於DDR記憶體可在一個時脈週期內，傳送兩筆資 料，比SDRAM的資料傳輸率多了一倍，所以DDR記憶 體已漸漸成爲記憶體元件的主流。而爲了能更提昇記憶體 __________4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -— — — — — — II _1111111 ^^ I — — — — — — — — — — — — — — — — — — — — — — - 565856 經濟部智慧財產局員工消費合作社印製 A7 8314twf.doc/006 gy 五、發明說明 的頻寬’ Kentron Technologies發展出一種四倍傳輸率的 g己憶體模組（Quad Band Memory，簡稱QBM)，其係利用二 個DDR記憶體以及開關電路達到在一個時脈週期內傳送 四筆資料的架'構。請參照第1圖，其繪示的是QBM及其 控制晶片之架構。QBM(IO)包括場效電晶體（Field Effect Transistor，簡稱FET)開關，電路i〇8、第一排區dDR記憶 體102第一排區DDR g己憶體104及鎖相迴路(Phase Locked Loop ’簡稱PLL)106。由此圖可知，QBM(10)係連接到控 制晶片12中的記憶體控制器14，其中，記憶體控制器14 的資料選通訊號（DQS)與資料罩幕(DQM)腳位分別耦接到 FET開關電路1〇8的第一資料選通訊號(DQS1)與第二資料 選通訊號(DQS2)腳位。而第一排區DDR記憶體1〇2的資 料選通訊號（DQSA)與資料訊號(DQA)腳位，以及第二排區 DDR記憶體1〇4的資料選通訊號(DQSB)與資料訊號(DqB) 腳位係連接到FET開關電路108。QBM(10)係藉由FET開 關電路108在第一排區DDR記憶體102與第二排區DDR 記憶體104之間的多工選擇，而達成四倍資料率的傳輸。 而鎖相迴路106係接收記憶體時脈(以下簡稱CLK)而產生 二倍於記憶體時脈（以下簡稱CLKX2)作爲選擇第一排區 DDR記憶體102或者第二排區DDR記憶體1〇4的模組選 擇訊號（以下簡稱BANKSEL)。在第1圖中僅繪示資料選 通訊號以及資料訊號之連接關係，而其他之控制訊號則根 據QBM的規格書連接即可。 第2圖繪示的是習知QBM記憶體模組內的FET開關 _ _ ___5_______ >紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) " " -- (請先閱讀背面之注意事項再填寫本頁) ________^—------— — —--------------------- 經濟部智慧財產局員工消費合作社印製 565856 A? 8314twf.doc/006 B7 五、發明說明（>) 電路示意圖。FET開關電路108係耦接至控制晶片12中 的記憶體控制器14、第一排區DDR記憶體102及第二排 區DDR記憶體104。FET開關電路108中包括第一資料選 通路徑，第二資料選通路徑，讀取資料路釋，寫入資料路 徑，以及開關控制器240。 在第一資料選通路徑上，FET開關202根據一開關 致能訊號（FET-Enable)來決定此路徑的導通與否，而並聯 的FET開關204與206分別作爲讀取以及寫入時的資料選 通訊號路徑。而FET開關204係由一 ΕΝ0訊號來控制， 而FET開關206係由一 EN1訊號來控制206。在讀取時， DQSA可經由FET開關204以及FET開關202傳至DQS1。 在寫入時，DQS1可經由FET開關,202以及FET開關206 傳至DQSA ° 在第二資料選通路徑上，FET開關212根據上述開 關致能訊號來決定此路徑的導通與否，而並聯的FET開關 214與216分別作爲讀取以及寫入時的資料選通訊號路 徑。而FET開關214係由一 EN2訊號來控制而FET開關 216係由一 EN3訊號來控制206。在讀取時，DQSB可經 由FET開關214以及FET開關212傳至DQS2。在寫入時， DQS2可經由FET開關212以及FET開關216傳至DQSB。 在讀取資料路徑上，FET開關222根據上述開關致 能訊號來決定此路徑的導通與否，而交替的開啓並聯的 FET開關224與226，可在讀取時交替的由第一排區DDR 記憶體以及第二排區DDR記憶體接收資料訊號。 _____6__ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) · I I ϋ I I I I 11111111 I I ϋ n ϋ I ϋ ϋ I I n — — — — — — n — — — — — _ 565856 A7 8314twf.doc/006 B7 五、發明說明（it) (請先閱讀背面之注意事項再填寫本頁) 在寫入資料路徑上，FET開關222根據上述開關致 能訊號來決定此路徑的導通與否，而開啓並聯的FET開關 228與230，在寫入時，可將記憶體控制器所輸出的資料 訊號送至第一排區DDR記憶體以及第二排區DDR記憶 體，並由第一資料選通路徑以及第二資料選通路徑上的資 料選通訊號來閂鎖DDR記憶體所要的資料訊號。 而開關控制器240的動作原理請配合下表：Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565856 A7 8314twf.doc / 006 B7 V. Description of the Invention (I) The present invention relates to a switching circuit, and in particular to a switching circuit capable of improving the writing timing of memory. And how it works. Dynamic Random Access Memory (DRAM) has been developed from asynchronous DRAM, such as early Fast-Page DRAM and Extended Data 〇Utput EDO DRAM, to synchronous dynamic random access. Access Memory (Synchronous Dynamic Random Access Memory, SDRAM for short). At present, high-speed buses use a synchronous source method to achieve data transmission, such as double data rate (Double Data Rate) synchronous dynamic random access memory (DDR memory) buses, graphics acceleration; tfu ( Accelerated Graphic Port (AGP) bus, or RAMBUS memory bus. In addition, these high-speed buses also need differential signals to assist data transmission. Therefore, the current technology can be used to achieve high-speed data transmission by combining a synchronous source and a differential signal. The market for the DRAM industry is very large, but its development is slow. It usually takes three to five years for new standards to emerge. Therefore, how to increase the bandwidth of DRAM becomes more and more important. In Internet applications, the lack of DRAM bandwidth becomes particularly apparent. Because the Internet requires a large amount of data to be transferred, and if the DRAM bandwidth is insufficient, it will be time-consuming and expensive for users due to slow data transfer. Because DDR memory can transmit two data in one clock cycle, the data transfer rate is twice as high as SDRAM, so DDR memory has gradually become the mainstream of memory components. And in order to improve the memory __________4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page)--— — — — — II _1111111 ^^ I — — — — — — — — — — — — — — — — — — — — — — — 565856 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 8314twf.doc / 006 gy Kentron Technologies has developed a Quad Band Memory (Quad Band Memory, QBM) with four times the transmission rate. It uses two DDR memories and a switching circuit to transmit four data in one clock cycle. Frame 'structure. Please refer to Figure 1, which shows the architecture of QBM and its control chip. The QBM (IO) includes a Field Effect Transistor (FET) switch, a circuit i08, a first bank dDR memory 102, a first bank DDR g memory 104, and a phase locked loop (Phase Locked Loop). 'Referred to as PLL) 106. It can be seen from this figure that QBM (10) is connected to the memory controller 14 in the control chip 12, wherein the data selection communication number (DQS) of the memory controller 14 and the data mask (DQM) pins are respectively coupled. The first data selection signal (DQS1) and the second data selection signal (DQS2) to the FET switch circuit 108. The data selection signal (DQSA) and data signal (DQA) pin of the DDR memory 102 in the first bank, and the data selection signal (DQSB) and data signal of the DDR memory 104 in the second bank. The (DqB) pin is connected to the FET switch circuit 108. QBM (10) achieves four times the data rate transmission by multiplexing the FET switch circuit 108 between the first bank DDR memory 102 and the second bank DDR memory 104. The phase-locked loop 106 receives the memory clock (hereinafter referred to as CLK) and generates twice the memory clock (hereinafter referred to as CLKX2) as the first bank DDR memory 102 or the second bank DDR memory 1. 4 module selection signal (hereinafter referred to as BANKSEL). In Figure 1, only the data selection signal and the connection relationship of the data signal are shown, and other control signals can be connected according to the QBM specifications. Figure 2 shows the FET switch in the conventional QBM memory module. _ _ ___5_______ > The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) " "--(please first Read the notes on the back and fill out this page) ________ ^ -------------- ------------------------ Consumption by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative 565856 A? 8314twf.doc / 006 B7 V. Description of the invention (>) Circuit diagram. The FET switch circuit 108 is coupled to the memory controller 14, the first bank DDR memory 102, and the second bank DDR memory 104 in the control chip 12. The FET switch circuit 108 includes a first data strobe path, a second data strobe path, a read data path, a write data path, and a switch controller 240. On the first data strobe path, the FET switch 202 determines whether the path is conducting or not according to a switch enable signal (FET-Enable), and the parallel FET switches 204 and 206 are used as data for reading and writing, respectively. Select the signal path. The FET switch 204 is controlled by an EN0 signal, and the FET switch 206 is controlled by an EN1 signal 206. During reading, DQSA can be transmitted to DQS1 via FET switch 204 and FET switch 202. At the time of writing, DQS1 can be transmitted to DQSA through FET switch, 202 and FET switch 206 ° On the second data strobe path, FET switch 212 determines whether the path is conductive or not according to the above-mentioned switch enable signal. The FET switches 214 and 216 serve as data selection signal paths for reading and writing, respectively. The FET switch 214 is controlled by an EN2 signal and the FET switch 216 is controlled by an EN3 signal 206. During reading, DQSB can be transmitted to DQS2 via FET switch 214 and FET switch 212. During writing, DQS2 can be transmitted to DQSB via FET switch 212 and FET switch 216. On the data reading path, the FET switch 222 determines whether the path is turned on or off according to the above-mentioned enable signal of the switch, and alternately turns on the parallel FET switches 224 and 226, which can be alternately determined by the first row of DDR during reading. The memory and the second row of DDR memory receive data signals. _____6__ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) · II ϋ IIII 11111111 II ϋ n ϋ I ϋ ϋ II n — — — — — — N — — — — — — 565856 A7 8314twf.doc / 006 B7 V. Description of the invention (it) (Please read the precautions on the back before filling this page) On the data path, the FET switch 222 is based on the above The switch enables the signal to determine the continuity of this path. When the parallel FET switches 228 and 230 are turned on, the data signal output by the memory controller can be sent to the first row of DDR memory and the first row during writing. The two rows of DDR memory are latched by the data selection signals on the first data strobe path and the second data strobe path. Please refer to the following table for the operation principle of the switch controller 240:

ΕΝ0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 FET_RW 1 0 1 0 1 1 0 0 BANKSEL 0 X 1 X 0 1 X X 其中，FET_WR訊號爲”1”代表讀取，”〇”代表寫入。 而BANSEL訊號在讀取時才爲有效，在讀取時BANSEL 訊號爲”1”代表選取第一排區DDR記憶體102，”0”代表選 取第二排區DDR記憶體104。ΕΝ0〜EN7即根據FET_RW 訊號以及BANSEL訊號來決定。再者，QBM記憶體模組 在動作時FETJENABLE訊號會被設定爲”1”。 經濟部智慧財產局員工消費合作社印製 假設QBM記憶體模組讀取操作時(FET_RW=1)，所 以ΕΝ0與EN4在BANSEL=0時開啓。而EN2與EN5在 BANSEL-1時開啓。由於BANSEL訊號係操作於二倍記憶 體時脈(CLKX2)，所以DQ線上的資料就是由BANSEL訊 號交替選取第一排區DDR記憶體102的資料線（DQA)以及 第二排區DDR記憶體104的資料線(DQB)來獲得。如第3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 565856 A7 8314twf.doc/006 B7 五、發明說明（f) 圖即繪示出QBM之讀取時序的波型。其中1代表資料係 讀自第一排區DDR記憶體，2代表資料係讀自第二排區 DDR記憶體。 第4圖繪示的是QBM記憶體模組之寫入時序的波 型。其中，CLK係記憶體時脈訊號，CLK_90係表示比記 憶體時脈訊號CLK落後1/4週期。以及CS(0，1)係晶片選 擇訊號，當選擇訊號CS(0，1)致能時，QBM開始做寫入操 作。此時控制晶片上的DQS腳位發出DQS1所示之資料 選通訊號(與CLK同相）。而控制晶片上的DQM腳位發出 DQS2所示之資料選通訊號(與CLK_90同相）。再者，在寫 入時(FET_RW=0)，FET 開關電路 108 中的 EN1，EN3，EN6， EN7皆開啓。因此，DQS1即可成爲第一排區DDR記憶體 102的資料選通訊號(DQSA)，而DQS2即可成爲第二排區 DDR記憶體104的資料選通訊號(DQSB)。而控制晶片上 的資料訊號DQ會以四倍速的速率輸出至DQA與DQB。 由於，第一排區DDR 102係根據DQSA來閂鎖資料，所 以僅有A、C、E、G能夠寫入第一排區DDR ;同理，第 二排區DDR 1〇4係根據DQSB來閂鎖資料，所以僅有B、 D、F、Η能夠寫入第二排區DDR。 假設記憶體時脈CLK的週期爲Τ。一般來說，記憶 體控制器14所產生的資料選通訊號（DQS)及資料訊號 (DQ)，在最佳時序時，對應於資料選通訊號（DQS)，資料 訊號（DQ)的組成時間（setup time)爲0.125T及保持時間 (hold time)爲0.125T。亦即，資料選通訊號（DQS)的上升 ___ 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·祖 I I I I I I 111111 ^^ I — — — — — — — — — — — — — — — — — — — — — 1* 565856 A7 8314twf.doc/006 B7 五、發明說明（G) 或者下降緣係位於資料訊號（DQ)上每筆資料有效區間 (Data valid window)的中間位置。 而這些訊號在實際的電路上傳輸，還會導致許多的 偏差（Skew)因而產生資料選通訊號（DQS)與資料訊號（DQ) 的相位變化。例如，SKEW。。lm。1k係資料選通訊號DQS及 資料訊號DQ在記憶體控制器(controller)輸出上的偏差； SKEW_eMB係資料選通訊號DQS及資料訊號DQ在主機 板（motherboard，簡稱MB)走線（trace)的偏差； SKEWFETswiteh係資料選通訊號DQS及資料訊號DQ在FET 開關（switch)電路上的偏差；SKEWm()dule係資料選通訊號 DQS及資料訊號DQ在記憶體模組(module)上的偏差。 因此，考慮到以上的偏差時，當第一排區DDR記憶 體102或者第二排區DDR記憶體104在接收到資料選通 訊號（DQSA，DQSB)與資料訊號（DQA，DQB)之間的相位 關係會成爲： 0.125T-SKEWcontro 丨丨 er-SKEWtraceMB-SKEWFETswitch-SKEWmodu,e 而上式的結果如果大於第一排區DDR記憶體102或 者第二排區DDR記憶體104規格書中所載明的組成時間 (Setup time)，則第一排區DDR記憶體102或者第二排區 DDR記憶體104即可正常動作。 同理，保持時間（Hold time)也必須要考慮到上述之偏 差因素。由上述可知，當QBM做寫入操作時，不只是以 更嚴格的四倍資料傳輸率時序加諸於二倍資料率的DDR 記憶體上。相較於二倍資料率的DDR記憶體還有額外的 _____Q_______ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -·1111!11 — — — — — — — — — I — — — — — — — — — — — — — — — — — — — — — I. 565856 8314twf.doc/006 A7 B7 五、發明說明（q) 偏差因素（SKEWFETswiuh)也就是FET開關（switch)電路上 的偏差，所以寫入的時序非常的緊。因此，習知的QBM 在速度的提昇上僅能夠到達一定的極限，一般來說記憶體 時脈到達100MHz之後就沒有辦法再提昇了。 有鑑於此，本發明提出一種能改善記憶體寫入時序 的場效電晶體開關電路及其運作方法。因爲本發明藉由時 序控制電路及閂鎖器，而使接收到的資料之資料有效區間 增加’因此能改善記憶體控制器到記億體間的記憶體寫入 時序。 、 ” 爲達成上述及其他目的，本發明提出一種能改善記 憶體寫入時序的開關電路。其耦接至記憶體控制器，第一 排區DDR記憶體與一第二排區DDR記憶體，包括：資料 寫入路徑，用以同時由記億體控制器提供多筆資料，其中 每一筆資料的資料有效區間皆相同；第一閂鎖器連接於資 料寫入路徑與第一排區DDR記憶體之資料路徑，用以延 長奇數筆資料之些資料有效區間；第二閂鎖器連接於資料 寫入路徑與第二排區DDR記憶體之資料路徑之間，用以 延長偶數筆資料之資料有效區間。 本發明還提出一種能改善記憶體寫入時序的開關電 路。其耦接於記憶體控制器與記憶體之間，用以將記憶體 控制器所送出之第一記憶體資料訊號轉換成第二記憶體資 料訊號而送至記憶體，其中第二記憶體資料訊號的資料傳 輸率小於第一記億體資料訊號的資料傳輸率’而此開關電 路之特徵爲··具有一個閂鎖器，用以根據記憶體控制器送 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^ ·1111111 I - - -----—II — I-----— — — — — . 565856 A7 8314twf.doc/006_ B7 五、發明說明（δ ) (靖先閱讀背面之>1$項再填寫本頁> 出之多筆資料選通訊號之組合邏輯結果，而輸出一閂鎖訊 號至閂鎖器，以控制閂鎖器閂鎖住第一記憶體資料訊號， 而輸出第二記憶體資料訊號，使第二記憶體資料訊號中之 資料有效時間得以較第一記憶體資料訊號中之資料有效時 間爲長。 本發明還提出一種能改善記憶體寫入時序的開關電 路之運作方法。在此運作方法中，首先，接收多筆資料， 其中每一筆資料的資料有效區間皆相同；再來，延長奇數 筆資料之資料有效區間，並送至第一記憶體；以及，延長 偶數筆資料之資料有效區間，並送至第二記憶體。 綜上所述，本發明藉由時序控制電路及閂鎖器，而使 接收到的資料之資料有效區間增加，因此能改善記憶體控 制器到記憶體間的記憶體寫入時序。另外，本發明還可以 藉由延遲電路，使接收到的資料選通訊號延遲一特定時 間’而使得記憶體寫入時序具有大於記憶體組成時間之足 夠的時序邊限。 經濟部智慧財產局員工消費合作社印製 爲讓本發明之上述和其他目的、特徵和優點，能更加 明顯易懂’下文特舉較佳實施例，並配合所附圖示，做詳 細說明如下： 圖式簡單說明： 第1圖繪示的是QBM的方塊圖； 第2圖繪示的是習知QBM記憶體模組內的FET開關 電路示意圖； 第3圖繪示的是習知QBM之讀取時序的波型； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 565856 14twf Hnr/Ofi^ 五、發明說明（1) 第4圖繪示的是QBM之寫入時序的波； 第5圖繪示的是根據本發明之FET開關電路之第一較 佳實施例； 第6圖繪示的是根據本發明第一實施例之QBM寫入 時序的波型； 第7圖繪示的是根據本發明之FET開關電路之第二較 佳實施例；以及 第8圖繪示的是根據本發明第二實施例之QBM寫入 時序的波型。 重要元件標號：ΕΝ0 EN1 EN2 EN3 EN4 EN5 EN6 EN7 FET_RW 1 0 1 0 1 1 0 0 BANKSEL 0 X 1 X 0 1 X X Wherein, the FET_WR signal is "1" for reading, and "〇" for writing. The BANSEL signal is only valid when reading. When the BANSEL signal is “1”, it means that the first bank DDR memory 102 is selected, and “0” means that the second bank DDR memory 104 is selected. ENE0 ~ EN7 are determined according to the FET_RW signal and the BANSEL signal. Furthermore, the FETJENABLE signal will be set to "1" when the QBM memory module is operating. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Assuming that the QBM memory module is read (FET_RW = 1), ENE0 and EN4 are turned on when BANSEL = 0. EN2 and EN5 are turned on during BANSEL-1. Since the BANSEL signal operates at double the memory clock (CLKX2), the data on the DQ line is the data line (DQA) of the DDR memory 102 in the first bank and the DDR memory 104 in the second bank by the BANSEL signal. Data line (DQB) to get. For example, the third paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565856 A7 8314twf.doc / 006 B7 V. Description of the invention (f) Picture is drawn The waveform of the read timing of the QBM is shown. Among them, 1 indicates that the data is read from the first row of DDR memory, and 2 indicates that the data is read from the second row of DDR memory. Figure 4 shows the waveform of the write timing of the QBM memory module. Among them, CLK is the memory clock signal, and CLK_90 is 1/4 cycle behind the memory clock signal CLK. And CS (0,1) is a chip selection signal. When the selection signal CS (0,1) is enabled, QBM starts writing. At this time, the DQS pin on the control chip sends out the data selection signal (shown in phase with CLK) as shown in DQS1. The DQM pin on the control chip sends out the data selection communication number shown in DQS2 (in phase with CLK_90). Moreover, at the time of writing (FET_RW = 0), EN1, EN3, EN6, and EN7 in the FET switch circuit 108 are all turned on. Therefore, DQS1 can become the data selection signal (DQSA) of the DDR memory 102 in the first bank, and DQS2 can become the data selection signal (DQSB) of the DDR memory 104 in the second bank. The data signal DQ on the control chip is output to DQA and DQB at four times the speed. Since the first bank DDR 102 latches data according to the DQSA, only A, C, E, and G can write to the first bank DDR; similarly, the second bank DDR 104 is based on the DQSB. Data is latched, so only B, D, F, and Η can write to the second bank DDR. Assume that the cycle of the memory clock CLK is T. Generally, the data selection signal (DQS) and data signal (DQ) generated by the memory controller 14 correspond to the data selection signal (DQS) and the composition time of the data signal (DQ) at the optimal timing. (Setup time) is 0.125T and hold time is 0.125T. That is, the rise of DQS ___ 8 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) · Zu IIIIII 111111 ^^ I — — — — — — — — — — — — — — — — — — — — 1 * 565856 A7 8314twf.doc / 006 B7 V. Explanation of the invention (G) or falling edge is located in the data signal ( DQ) is the middle position of each data valid window. And these signals are transmitted on the actual circuit, and it will also cause many deviations (Skew), which will cause the phase change of the data selection signal (DQS) and the data signal (DQ). For example, SKEW. . lm. 1k is the deviation of data selection signal DQS and data signal DQ on the output of the memory controller; SKEW_eMB is the data selection signal DQS and data signal DQ on the motherboard (MB) trace. Deviation; SKEWFETswiteh is the deviation of the data selection signal DQS and data signal DQ on the FET switch circuit; SKEWm () dule is the deviation of the data selection signal DQS and data signal DQ on the memory module. Therefore, when considering the above deviation, when the first bank DDR memory 102 or the second bank DDR memory 104 receives the data selection signal (DQSA, DQSB) and the data signal (DQA, DQB) The phase relationship will become: 0.125T-SKEWcontro 丨 er-SKEWtraceMB-SKEWFETswitch-SKEWmodu, e. If the result of the above formula is greater than the first bank DDR memory 102 or the second bank DDR memory 104 specification, Setup time, the first bank DDR memory 102 or the second bank DDR memory 104 can operate normally. Similarly, the hold time must also take into account the above-mentioned deviation factors. From the above, it can be known that when QBM is performing a write operation, it is not only added to the double-data-rate DDR memory with a more stringent four-times data transfer rate timing. Compared with the double data rate of DDR memory, there is an extra _____Q_______ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Economy Printed by the Consumer Property Cooperative of the Ministry of Intellectual Property Bureau-· 1111! 11 — — — — — — — — — — I — — — — — — — — — — — — — — — — — — — — — I. 565856 8314twf. doc / 006 A7 B7 V. Explanation of the Invention (q) The deviation factor (SKEWFETswiuh) is also the deviation on the FET switch circuit, so the timing of writing is very tight. Therefore, the conventional QBM can only reach a certain limit in speed increase. Generally speaking, there is no way to increase the memory clock after it reaches 100MHz. In view of this, the present invention provides a field-effect transistor switching circuit capable of improving memory write timing and an operation method thereof. Because the present invention uses a timing control circuit and a latch to increase the effective range of the data of the received data, it can improve the memory writing timing from the memory controller to the memory. In order to achieve the above and other objectives, the present invention proposes a switch circuit capable of improving memory write timing. The switch circuit is coupled to a memory controller, a first bank DDR memory and a second bank DDR memory. Including: a data write path, which is used to provide multiple pieces of data from the memory controller at the same time, each data has the same data valid range; the first latch is connected to the data write path and the first row of DDR memory The data path is used to extend the valid range of some odd data. The second latch is connected between the data write path and the data path of the second row of DDR memory to extend the data validity of even data. The invention also proposes a switching circuit capable of improving the writing timing of the memory, which is coupled between the memory controller and the memory, and is used for converting the first memory data signal sent by the memory controller into The second memory data signal is sent to the memory, where the data transfer rate of the second memory data signal is less than the data transfer rate of the first billion data signal 'and this switch The characteristic of the road is that it has a latch to send the paper according to the memory controller. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Please read the precautions on the back before filling in this. Page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ · 1111111 I-------— II — I -----— — — — — 565856 A7 8314twf.doc / 006_ B7 V. Description of the Invention (Δ) (Jing first reads the > 1 $ item on the back and then fills in this page > The result of the combination of multiple data selection signals and the logic result is output, and a latch signal is output to the latch to control the latch of the latch. The first memory data signal is locked, and the second memory data signal is output, so that the valid time of the data in the second memory data signal is longer than the valid time of the data in the first memory data signal. The invention also proposes A method for operating a switching circuit capable of improving memory write timing. In this method of operation, first, a plurality of pieces of data are received, and the data valid range of each piece of data is the same; and then, the data valid range of the odd-numbered pieces of data is extended. , and To the first memory; and extend the data valid interval of the even data and send it to the second memory. In summary, the present invention makes the data of the received data through the timing control circuit and the latch. The effective range is increased, so the memory writing timing from the memory controller to the memory can be improved. In addition, the present invention can also delay the received data selection signal by a specific time through a delay circuit, thereby making the memory The write timing has a sufficient timing margin that is greater than the memory composition time. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to make the above and other objects, features, and advantages of the present invention more comprehensible. The preferred embodiment and the accompanying drawings are described in detail as follows: Brief description of the diagram: Figure 1 shows a block diagram of QBM; Figure 2 shows a FET in a conventional QBM memory module Schematic diagram of the switch circuit; Figure 3 shows the waveform of the reading sequence of the conventional QBM; This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Printed by the Property Cooperative Consumer Cooperative 565856 14twf Hnr / Ofi ^ V. Description of the Invention (1) Figure 4 shows the write timing wave of QBM; Figure 5 shows the FET switch circuit according to the present invention. First preferred embodiment; FIG. 6 illustrates a waveform of a QBM write timing according to a first embodiment of the present invention; FIG. 7 illustrates a second preferred implementation of a FET switch circuit according to the present invention Example; and FIG. 8 shows a waveform of a QBM write timing according to a second embodiment of the present invention. Important component numbers:

10 ： QBM10: QBM

12、52、82 :控制晶片 14、54、84 :記憶體控制器 56、86、102 :第一排區 DDR 58、88、104 :第二排區 DDR 50，80 :本發明的FET開關電路 106 ： PLL 108 :習知的FET開關電路 202 、 204 、 206 、 212 、 214 、 216 、 222 、 224 、 226 、 228 、 230、508 、510、5 12、5 14、5 16、5 18、520、522、524、 526、528、808、810、812、818、820、822、824、826、 828、830、832 : FET 開關 240、540、840 ··開關控制器 502、802 :時序控制電路 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 ) (請先閲讀背面之注意事項再填寫本頁) i 參 —1 — — — — — 1111111 ^^ I — — — — — — — — — — — — — — — — — — — — I· 經濟部智慧財產局員工消費合作社印製 565856 Α7 8314twf.doc/006 B7 五、發明說明（fo) 504、804 :第一閂鎖器 506、806 :第二閂鎖器 814 :第一延遲電路 816 :第二延遲電路 較佳實施例: 請參照第5圖，其繪示的是根據本發明之能改善記 憶體寫入.時序的FET開關電路之第一較佳實施例的方塊 圖。在FET開關電路中寫入第一排區DDR記憶體以及第 二排區DDR記憶體的寫入資料路徑中各加入一個閂鎖器 (Latch)5〇4、5〇6，用以延長傳輸至每一排區DDR記憶體 的資料有效區間（Data valid window)，並且加入一時序控 制電路502用以根據第一資料選通訊號（DQS1)以及第二資 料選通訊號(DQS2)的控制來開啓第一閂鎖器504與第二閂 鎖器506。 其中，LTA與LTB爲時序控制電路502用以控制第 一^問鎖器504與第一►問鎖益506之時脈訊號。 LTA=〜(DQS1ADQS2) LTB=DQS1ADQS2 (〃符號代表X0R，〜符號代表NOT) 請參照弟6圖其爲根據本發明第一實施例之QBM寫 入時序的波型。在寫入時，控制晶片上的DQS腳位發出 DQS1所示之資料選通訊號（與CLK同相）。而控制晶片上 的DQM腳位發出DQS2所示之資料選通訊號（與CLK_90 同相）。再者，在寫入時（FET—RW=0)，FET開關電路50 中的ΕΝ 1，EN3，EN6，EN7皆開啓。因此，DQS 1即可成 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 ϋ ) ~ (請先閱讀背面之注意事項再填寫本頁) -I --------^--------------------------------- 565856 8314twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f /) 爲第一排區DDR記憶體的資料選通訊號(DQSA)，而DQS2 即可成爲第二排區DDR記憶體的資料選通訊號(1)(588)。 由於寫入資料路徑上各串接了一個問鎖器504、506， 因此會改變DQA與DQB的資料訊號波形。 由於LTA=〜(DQS1ADQS2)，當DQS1訊號等於DQS2 時，LTA=“1” ；當 DQS1 訊號不等於 DQS2 時，LTA=“0”。 而閂鎖器504係在LTA爲“1”準位時將Dq上的資料訊號 傳輸至DQA，LTA爲“0”準位時，閂鎖器504不動作並維 持住原輸出資料。因此，對於“A”、“C”、“E”、“G”資料， 問鎖器504可延長其資料有效區間。而“B”、“D”、“F”資 料則縮小其資料有效區間。由於，第一排區DDR記憶體 僅根據第一資料選通訊號（DQS1)來接收資料，因此僅有 “A”、“C”、“E”、“G”資料會被第一排區DDR記憶體所接 收。所以延長“A”、“C”、“E”、“G”資料的資料有效區間， 可提供第一排區記憶體足夠的時序邊限。 同理，由於LTB=DQS1ADQS2，當DQS1訊號不等於 DQS2 時，LTB=“1”；當 DQS1 訊號等於 DQS2 時，LTB=“0”。 而閂鎖器506係在LTB爲“Γ準位時將DQ上的資料訊號 傳輸至DQB，LTB爲“〇，，準位時，閂鎖器506不動作並維 持住原輸出資料。因此，對於“B”、“D”、“F”資料，閂鎖 器506可延長其資料有效區間。而“A，，、“c，，、“E，，、‘‘G，，資 料則縮小其資料有效區間。由於，第二排區DDR記憶體 僅根據第二資料選通訊號（DqS2)來接收資料，因此僅有 “B”、“D”、“F”資料會被第二排區DDR記憶體所接收。所 本紙張/Γ度適財_家標準χ 297 ^-- (請先Μ讀背面之注意事項再填寫本頁) * · emmm «1 I I ϋ I I · ϋ I ϋ ϋ mmmmm n ·1 I -ϋ ϋ n _1 ϋ ϋ n ϋ ϋ n ϋ ϋ ·1 ϋ H ϋ ϋ βϋ H ϋ I H ^1 · 經濟部智慧財產局員工消費合作社印製 565856 8314twf.doc/006 五、發明說明 以延長“B”、“D”、“F”資料的資料有效區間，可提供第二 排區記憶體足夠的時序邊限。 由於本發明之FET開關電路5〇可有效的延長資料的 資料有效區間，因此可以更進一步的提昇，QBM的存取 速度。 請參照第7圖’其繪示的是根據本發明之能改善記 憶體寫入時序的FET開關電路之第二較佳實施例的方塊 圖。相較於第一實施例，本實施例係在FET開關電路中的 寫入第一資料選通路徑以及第二資料選通路徑上各串接一 延遲電路814、816。由於第一延遲電路814以及第二延遲 電路816的加入，因此可控制第一資料選通訊號(DQS1)與 第二資料選通訊號(DQS2)至資料有效區間的中央位置，因 此更可以提供第一排區記憶體與第二排區記憶體足夠的時 序邊限。 在本發明的實施例中，所使用的開關電路爲FET開 關電路，但是並不侷限於FET開關電路，只要能達成本發 明的開關電路都可適用之。 在此實施例中，假設第一延遲電路814及第二延遲 電路816的延遲時間均爲Td(Td=0.125T)。所以記憶體寫 入時序之組成時間的方程式可以下列方程式表示： (1) 從記憶體控制器84到FET開關電路80的寫入 時序僅需滿足下式即可： 0.125T-SKEWcontro丨丨er-SKEWtraceMB>Setup—FET。 (2) 從FET開關電路80到第一排區DDR(86)的寫 ______ ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公b (請先閲讀背面之注意事項再填寫本頁) ·---------訂----- -----線— ----------------------- 565856 A7 8314twf.doc/006 _ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（/>) 入時序’僅需滿足下式即可： Td-SKEWFETswiteh-SKEWmodule> Setup—DRAM 〇 由上述可知，藉由第一延遲電路814及第二延遲電 路814，可改善記憶體寫入的時序。 綜上所述，本發明具有如下的優點： 1.本發明藉由時序控制電路及閂鎖器，而使接收到 的資料之資料有效區間增加，因此能改善記憶體控制器到 記憶體間的記憶體寫入時序。 2.本發明可藉由延遲電路，使接收到的資料選通訊號 延遲一段時間，而使得記憶體寫入時序具有大於記憶體組 成時間之時序邊限。 雖然本發明已以較佳實施例揭露於上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所介定者爲準。 (請先閱讀背面之注意事項再填寫本頁) -IAW---I----訂-------- 線—4^----------------------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）12, 52, 82: control chips 14, 54, 84: memory controllers 56, 86, 102: first bank DDR 58, 88, 104: second bank DDR 50, 80: FET switch circuit of the present invention 106: PLL 108: conventional FET switch circuits 202, 204, 206, 212, 214, 216, 222, 224, 226, 228, 230, 508, 510, 5 12, 5 14, 5 16, 5 18, 520 , 522, 524, 526, 528, 808, 810, 812, 818, 820, 822, 824, 826, 828, 830, 832: FET switches 240, 540, 840. · Switch controller 502, 802: Sequential control circuit This paper size applies to China National Standard (CNS) A4 specification (210 X 297) (Please read the precautions on the back before filling out this page) i Reference—1 — — — — — 1111111 ^^ I — — — — — — — — — — — — — — — — — — — I · Printed by the Intellectual Property Bureau of the Ministry of Economy Employees' Cooperatives 565856 Α7 8314twf.doc / 006 B7 V. Description of the invention (fo) 504, 804: First latch 506 , 806: second latch 814: first delay circuit 816: second delay circuit preferred embodiment: please refer to FIG. 5, Are shown according to the present invention can improve the body write memorized first preferred embodiment of a block diagram of the FET switch circuit timing. In the FET switch circuit, a latch (Latch) 504 and 506 are added to the write data path of the first row of DDR memory and the second row of DDR memory to extend the transmission to The data valid window (Data valid window) of each row of DDR memory, and a timing control circuit 502 is added to open according to the control of the first data selection communication number (DQS1) and the second data selection communication number (DQS2). The first latch 504 and the second latch 506. Among them, LTA and LTB are timing signals used by the timing control circuit 502 to control the first interlock 504 and the first interlock 506. LTA = ~ (DQS1ADQS2) LTB = DQS1ADQS2 (〃 symbol represents X0R, ~ symbol represents NOT) Please refer to Fig. 6 which shows the waveform of the QBM write timing according to the first embodiment of the present invention. When writing, the DQS pin on the control chip sends out the data selection communication number (in phase with CLK) shown by DQS1. The DQM pin on the control chip sends the data selection communication signal (in phase with CLK_90) shown in DQS2. Furthermore, at the time of writing (FET-RW = 0), ENE 1, EN3, EN6, EN7 in the FET switch circuit 50 are all turned on. Therefore, DQS 1 can be converted into ^ paper size applicable to China National Standard (CNS) A4 specifications (210 X 297 ϋ) ~ (Please read the precautions on the back before filling this page) -I -------- ^ --------------------------------- 565856 8314twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (f /) is the data selection communication number (DQSA) of the DDR memory in the first bank, and DQS2 can be the data selection communication number (1) (588) of the DDR memory in the second bank. Because an interlocker 504 and 506 are connected in series on the write data path, the data signal waveforms of DQA and DQB will be changed. Since LTA = ~ (DQS1ADQS2), when DQS1 signal is equal to DQS2, LTA = “1”; when DQS1 signal is not equal to DQS2, LTA = “0”. The latch 504 transmits the data signal on Dq to DQA when the LTA is at the "1" level. When the LTA is at the "0" level, the latch 504 does not operate and maintains the original output data. Therefore, for "A", "C", "E", "G" data, the interrogator 504 can extend the data valid interval. The “B”, “D”, and “F” data narrowed the valid range of the data. Because the first row of DDR memory only receives data according to the first data selection communication number (DQS1), only "A", "C", "E", and "G" data will be used by the first row of DDR data. Received by memory. Therefore, extending the data valid interval of the data of "A", "C", "E", and "G" can provide sufficient timing margins for the memory of the first row. Similarly, because LTB = DQS1ADQS2, when the DQS1 signal is not equal to DQS2, LTB = “1”; when the DQS1 signal is equal to DQS2, LTB = “0”. The latch 506 transmits the data signal on the DQ to the DQB when the LTB is “Γ” level, and the LTB is “0”. When the LTB is in the level, the latch 506 does not operate and maintains the original output data. Therefore, for "B", "D", and "F" data, the latch 506 can extend the data valid range. The data of "A ,,," c ,,, "E ,,," "G," narrows the data valid range. Because the DDR memory in the second row only selects the communication number (DqS2) based on the second data. Receive data, so only "B", "D", and "F" data will be received by the second row of DDR memory. All papers / Γdegrees are suitable for money_ 家 标准 χ 297 ^-(please first M Read the notes on the back and fill in this page) * · emmm «1 II ϋ II · ϋ I ϋ ϋ mmmmm n · 1 I -ϋ ϋ n _1 ϋ ϋ n ϋ ϋ n ϋ 1 · 1 ϋ H ϋ ϋ βϋ H ϋ IH ^ 1 · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565856 8314twf.doc / 006 V. Description of the invention to extend the valid range of the data of "B", "D", "F" data, and provide the second row memory Sufficient timing margins. Because the FET switch circuit 50 of the present invention can effectively extend the data valid range of the data, it can further improve the access speed of QBM. Please refer to FIG. Block diagram of a second preferred embodiment of a FET switch circuit capable of improving memory write timing according to the present invention. In the first embodiment, this embodiment writes a first data strobe path and a second data strobe path in the FET switch circuit in series with a delay circuit 814, 816. Since the first delay circuit 814 and the first The addition of two delay circuits 816 can control the first data selection signal (DQS1) and the second data selection signal (DQS2) to the central position of the data valid range, so it can provide the first bank memory and the second The bank memory has sufficient timing margins. In the embodiment of the present invention, the switching circuit used is a FET switching circuit, but it is not limited to the FET switching circuit, as long as it can reach the switching circuit of the invention. In this embodiment, it is assumed that the delay times of the first delay circuit 814 and the second delay circuit 816 are both Td (Td = 0.125T). Therefore, the equation of the composition time of the memory write timing can be expressed by the following equation: (1) The writing sequence from the memory controller 84 to the FET switch circuit 80 only needs to satisfy the following formula: 0.125T-SKEWcontro 丨 er-SKEWtraceMB> Setup_FET. (2) From the FET switch circuit 80 to the first bank DDR (86) Write ______ ^ The paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 maleb (please read the precautions on the back before filling out this page) · --------- Order- ---- ----- Line — ----------------------- 565856 A7 8314twf.doc / 006 _ B7 Employee Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Cooperative printed 5. Description of the invention (/ >) The input sequence 'only needs to satisfy the following formula: Td-SKEWFETswiteh-SKEWmodule> Setup-DRAM 〇 As can be seen from the above, the first delay circuit 814 and the second delay circuit 814 , Can improve the timing of memory write. In summary, the present invention has the following advantages: 1. The present invention increases the data valid range of the received data by using a timing control circuit and a latch, so it can improve the memory controller to memory. Memory write timing. 2. The present invention can delay the received data selection signal by a delay circuit for a period of time, so that the memory write timing has a timing margin that is greater than the memory composition time. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) -IAW --- I ---- Order -------- Line—4 ^ -------------- --------- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

565856 A8 R8 C8 8314twf.doc/006 D8 六、申請專利範圍 1. 一種能改善記憶體寫入時序的開關電路，耦接至 一記憶體控制器，一第一排區DDR記憶體與一第二排區 DDR記憶體，包括： 一資料寫入路徑，用以同時由該記憶體控制器提供 複數筆資料，其中每一該資料的一資料有效區間皆相同； 一第一閂鎖器，連接於該資料寫入路徑與該第一排 區DDR記憶體之資料路徑.，用以延長該些資料之中的奇 數筆資料之該些資料有效區間； 一第二閂鎖器，連接於該資料寫入路徑與該第二排 區DDR記憶體之資料路徑之間，用以延長該些資料之中 的偶數筆資料之該些資料有效區間。 2. 如申請專利範圍第1項所述之能改善記憶體寫入 時序的開關電路，其中該開關電路更包括： 一第一資料選通路徑，用以由該記憶體控制器提供 該第一排區DDR記憶體一第一資料選通訊號；以及 一第二資料選通路徑，用以由該記憶體控制器提供 該第二排區DDR記憶體一第二資料選通訊號。 3. 如申請專利範圍第2項所述之能改善記憶體寫入 時序的開關電路，其中該開關電路更包括： 一時序控制電路，用以根據該第一資料選通訊號以 及該第二資料選通訊號的複數個組合邏輯結果來控制該第 一閂鎖器與該第二閂鎖器。 4. 如申請專利範圍第2項所述之能改善記憶體寫入 時序的開關電路，其中該開關電路更包括： 17 $紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ 297公坌） -------I--·丨！ ί 丨訂 i ! (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印裂 565856 A8 B8 C8 8314twf.doc/006 D8 六、申請專利範圍 一第一延遲電路串接於該第一資料選通路徑，用以 延遲該第一資料選通訊號一第一特定時間；以及 (請先閱讀背面之注意事項再填寫本頁) 一第二延遲電路串接於該第二資料選通路徑，用以 延遲該第二資料選通訊號一第二特定時間。 5. 如申請專利範圍第4項所述之能改善記憶體寫入 時序的開關電路，其中該第一特定時間等於該第二特定時 間。 6. —種能改善記憶體寫入時序的開關電路，耦接於 一記憶體控制器與一記憶體之間，用以將該記憶體控制器 所送出之一第一記憶體資料訊號轉換成一第二記憶體資料 訊號而送至該記憶體，其中該第二記憶體資料訊號的資料 傳輸率小於該第一記憶體資料訊號的資料傳輸率，該開關 電路之特徵爲： 經濟部智慧財產局員工消費合作社印放 具有一閂鎖器，用以根據該記憶體控制器送出之複 數筆資料選通訊號之一組合邏輯結果，而輸出一閂鎖訊號 至該閂鎖器，以控制該閂鎖器閂鎖住該第一記憶體資料訊 號，而輸出該第二記憶體資料訊號，使該第二記憶體資料 訊號中之資料有效時間得以較該第一記憶體資料訊號中之 資料有效時間爲長。 7. 如申請專利範圍第6項所述之能改善記憶體寫入 時序的開關電路，其中該組合邏輯係由一時序控制電路根 據該些資料選通訊號來操作。 8. 如申請專利範圍第6項所述之能改善記憶體寫入 時序的開關電路，其中更包括一延遲電路用以延遲對應於 18 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ 297公釐） 565856 • 戠 C8 8314twf.doc/006 D8 六、申請專利範圍 該第一資料訊號的該資料選通訊號一第一特定時間。 9. 一種能改善記憶體寫入時序的開關電路之運作方 法，該運作方法包括下列步驟： 接收複數筆資料，其中每一該資料的一資料有效區 間皆相同； 延長該些資料之中的奇數筆資料之該些資料有效區 間，並送至一第一記憶體；以及 延長該些資料之中的偶數筆資料之該些資料有效區 間，並送至一第二記憶體。 10. 如申請專利範圍第9項所述之能改善記憶體寫入 時序的開關電路之運作方法，其中更包括延遲該些奇數筆 資料所對應之一資料選通訊號一特定時間。 11. 如申請專利範圍第9項所述之能改善記憶體寫入 時序的開關電路之運作方法，其中更包括延遲該些偶數筆 資料所對應之一資料選通訊號一特定時間。 ----------·丨丨丨丨丨丨丨訂·丨！ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印焚 19 本紙張尺度適用中國國家標準（CNS)A4規格（210 X !?97公髮)565856 A8 R8 C8 8314twf.doc / 006 D8 6. Scope of patent application 1. A switching circuit capable of improving memory write timing, coupled to a memory controller, a first bank of DDR memory and a second The banked DDR memory includes: a data write path for providing a plurality of data by the memory controller at the same time, a data valid range of each of the data is the same; a first latch connected to The data writing path and the data path of the DDR memory in the first row are used to extend the valid interval of the data of the odd data among the data; a second latch connected to the data writing Between the access path and the data path of the DDR memory in the second bank, the valid interval of the data for extending the even data among the data is extended. 2. The switch circuit capable of improving the memory write timing as described in the first item of the patent application scope, wherein the switch circuit further includes: a first data strobe path for providing the first by the memory controller. A first data selection communication number of the bank DDR memory; and a second data gating path for providing the second data selection communication number of the second bank DDR memory by the memory controller. 3. The switch circuit capable of improving the memory write timing as described in the second item of the patent application scope, wherein the switch circuit further includes: a timing control circuit for selecting a communication number and the second data according to the first data A plurality of combined logic results of the communication number are selected to control the first latch and the second latch. 4. The switch circuit capable of improving the memory write timing as described in item 2 of the scope of the patent application, wherein the switch circuit further includes: 17 $ Paper size is applicable to China National Standard (CNS) A4 specification (2) 〇χ 297 公坌) ------- I-- · 丨! ί 丨 Order i! (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565856 A8 B8 C8 8314twf.doc / 006 D8 VI. Application scope of patents-First delay circuit in series Use the first data strobe path to delay the first data strobe signal number for a first specific time; and (Please read the precautions on the back before filling this page) A second delay circuit is connected in series to the second The data strobe path is used to delay the second data strobe signal for a second specific time. 5. The switching circuit capable of improving the memory write timing as described in item 4 of the scope of the patent application, wherein the first specific time is equal to the second specific time. 6. —A switching circuit capable of improving the writing timing of the memory, coupled between a memory controller and a memory, for converting a first memory data signal sent by the memory controller into a The second memory data signal is sent to the memory, wherein the data transmission rate of the second memory data signal is less than the data transmission rate of the first memory data signal, and the characteristics of the switch circuit are: Intellectual Property Bureau of the Ministry of Economic Affairs The employee consumer cooperative print has a latch for selecting a logical result of one of the communication numbers based on the plurality of data sent from the memory controller, and outputting a latch signal to the latch to control the latch. The device latches the first memory data signal and outputs the second memory data signal, so that the valid time of the data in the second memory data signal can be longer than the valid time of the data in the first memory data signal. long. 7. The switching circuit capable of improving the writing timing of the memory as described in item 6 of the scope of the patent application, wherein the combinational logic is operated by a timing control circuit based on the data selection signals. 8. The switching circuit capable of improving the memory write timing as described in item 6 of the scope of the patent application, which further includes a delay circuit for delaying corresponding to the Chinese paper standard (CNS) A4 specification corresponding to 18 paper standards (2) 〇χ 297 mm) 565856 • 戠 C8 8314twf.doc / 006 D8 VI. Patent application scope The first data signal of the first data signal is selected for the first specific time. 9. A method of operating a switching circuit capable of improving memory write timing, the method of operation includes the following steps: receiving a plurality of pieces of data, each of which has a data valid interval being the same; extending an odd number of the pieces of data The data valid intervals of the pieces of data are sent to a first memory; and the data valid intervals of an even number of pieces of data are extended and sent to a second memory. 10. As described in item 9 of the scope of the patent application, the operation method of the switching circuit capable of improving the memory writing timing further includes delaying a data selection signal number corresponding to the odd number of data for a specific time. 11. As described in item 9 of the scope of the patent application, the operation method of the switching circuit capable of improving the memory writing timing further includes delaying a data selection signal corresponding to the even number of data for a specific time. ---------- · 丨 丨 丨 丨 丨 丨 丨 Ordering! 丨! (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 19 The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X!? 97 issued)
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