TW564454B - Method of and apparatus for, manufacturing field emission-type electron source - Google Patents

Abstract

An electron source 10 has an n-type silicon substrate 1, a drift layer 6 formed on one surface of the substrate 1, and a surface electrode 7 formed on the drift layer 6. A voltage is applied so that the surface electrode 7 becomes positive in polarity relevant to the substrate 1, whereby electrons injected from the substrate 1 into the drift layer 6 drift within the drift layer 6, and are emitted through the surface electrode 7. In a process for manufacturing this electron source 10, when the drift layer 6 is formed, a porous semiconductor layer containing a semiconductor nanocrystal is formed in accordance with anodic oxidation. Then, an insulating film is formed on the surface of each semiconductor nanocrystal. Anodic oxidation is carried out while emitting light that essentially contains a wavelength in a visible light region relevant to the semiconductor layer.

Description

564454 Α7 _ Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（1 ) 發明背景 發明領域 本發明是關於包含強力場致漂流層（strong field di ift layer )以便由電子場致發射發射電子光束之場致發 射式電子源之製造方法以及裝置。 相關技藝的說明 有熟知由多孔氧化半導體層係形成於電子導電基底的 一表面上’且表面電極係形成於漂流層上構成之強力場致 漂流層（以下，簡稱爲、'漂流層〃）之場致發射式電子源 (以下’簡稱爲、、電子源〃）（例如，日本專利案號 2966842 ’日本專利案號2987140與日本專 利案號3 0 7 9 0 8 6 )。當作電子導電基底，例如，有 使用：電阻率比較接近導體的導電率之半導體基底；以及 具有於玻璃基底（絕緣基底）或其類似的一表面上形成之 電子導電層之基底。 例如，如圖2 6所示，在此類的電子源1 〇 -中，漂 流層6 /由氧化多孔多晶砂層係形成於爲電子導電基底之 η型矽基底1的主表面上構成。表面電極7係形成於漂流 層6 /上。歐姆電極2係形成於η型矽基底1的背面上。 圖2 6所示之範例中，由非摻雜多晶矽層構成之半導體層 3係介於η型矽基底1與漂流層6 /之間。然而，已提出 了具有於η型矽基底1的主表面上形成之漂流層6 —不需 介於半導體層3之電子源。 本紙張尺度適用中國國家標準（CNS ) Α4規格( 210X297公釐） 卿 ~ -4- (請先閲讀背面之注意事項再填寫本頁) 564454 經濟部智慈財產局員工消費合作社印製 A7 ____B7 ___五、發明説明（2 ) 圖2 6所示之電子源1 0 /中，電子係根據下列過程 發射。首先，集極電極2 1係置於表面電極7的對面。同 時真空被提供於表面電極7與集極電極2 1間，直流電壓 V P s係用於表面電極7與η型矽基底1之間以致於表面 電極7在相對於η型矽基底（歐姆電極2) 1之電位（正 極性）變高。另一方面，直流電壓V c係用於集極電極 2 1與表面電極7之間之致於集極電極2 1在相對於表面 電極7之電位變高。當直流電壓V p s與V c被正確地設 定時，自η型矽基底1注入之電子漂流層6 >，且係經由 表面電極7發射（圖2 6之單點鏈線表示經由表面電極7 發射之電子'' e 〃的流動）。表面電極7係具有小逸出功 (work function )之材料（例如，金）形成的。表面電極 7的厚度係設在大約1 0 n m至1 5 n m。 在此，流於表面電極7與歐姆電極2間之電流被稱爲 二極體電流I p s，且流於集極電極2 1與表面電極7間 之電流被稱爲發射電流（發射電子流）I e。此時，如發 射電流I e相對於二極體電流I p s的比例（=I e / I P s )增加，電子發射效率高。 電子源1 0 /中，即使用於表面電極7與歐姆電極2 間之直流電壓V p s被定爲大約1 〇 V至2 0 V的低電壓 ，電子可被發射。此外，電子源1 〇 >中，電子發射特徵 之真空的程度之相依性可被減少，且電子可在電子發射期 間以高發射效率不產生跳躍（hopping )現象而被發射。 製造電子源1 0 的過程中，形成漂流層6 "的步驟 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -5 - 564454 A7 ______ B7 五、發明説明（3 ) 包括膜形成步驟，陽極氧化處理步驟，及氧化步驟。膜形 成步驟中，非摻雜多晶矽層被置於爲電子導電基底之η型 矽基底1之一表面上。陽極氧化處理步驟中，多晶矽層係 陽極地氧化，藉此包含多晶矽粒及矽奈米晶體之多孔多晶 矽層被形成。氧化步驟中，多孔多晶矽層係根據快速熱氧 化技術氧化，且薄氧化膜分別被形成於矽奈米晶體與晶粒 的表面上。陽極氧化處理步驟中，由以1 : 1混合氟化氫 水溶劑與乙醇獲得之混合液被用作陽極氧化使用之電解液 。氧化步驟中，燈退火（lamp annealing )設備被使用。 在基底溫度已以乾氧短時間自室溫被增加至9 0 0 °C後， 基底被維持在9 0 Ot —小時，且基底被氧化。接著，基 底溫度被降低至室溫。 如圖2 7所示，因此形成之漂流層6 /被認爲構成有 :至少一圓柱多晶砂粒5 1 ;於晶粒5 1的表面上形成之 薄氧化矽膜5 2 ;橫跨晶粒5 1介於它之間具有奈米級之 矽奈米晶體6 3 ;以及於矽奈米晶體6 3的表面上形成且 具有較小於矽奈米晶體6 3的晶粒大小的膜厚度之氧化矽 膜6 4。也就是，在漂流層6 >中，在實行陽極氧化處理 前包含在多晶層之各晶粒5 1的表面被做成多孔且結晶狀 態被維持在各晶粒5 1的中心部分。 所以，大多數用至漂流層6 /之電場被徹底地應用至 氧化矽膜6 4。結果，經注入的電子係由氧化矽膜6 4有 關之強力電場加速，且由箭頭A表示之方向在晶粒5 1間 漂向該表面。因此，電子發射效率可被改進。在此，電子 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 -6- (請先閱讀背面之注意事項再填寫本頁) ί1· 訂 經濟部智慧財產局8工消費合作社印製 564454 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（4 ) 源1 0 /利用由設定矽奈米晶體6 3的大小（結晶粒大小 )與氧化矽膜6 4的膜厚度發生之衝擊導電現象等於或小 於當電子隧穿現象發生時之膜厚（電子平均自由路徑的程 度）。到達漂流層6 /的表面之電子被認爲是熱電子。這 些電子輕易地隧穿表面電極7，且被發射入進入真空。在 包含漂流層6 /之電子源1 0 /中，電子發射期間於漂流 層6 /產生之熱係經由晶粒5 1發散。因此，於漂流層 6 /產生之熱可被有效地發散，且衝擊現象的發生可被限 制。 如圖2 8所示，提出了具有於不使用η型矽基底作電 子導電基底之玻璃基底構成之絕緣基底1 1的一表面上形 成之電子導電層1 2之電子源1 0。圖2 8中，像類似於 圖2 6所示之電子源1 0 /之構成元素係由線參考數字表 示。其說明在此被省略。圖2 8所示之電子源1 0 /的漂 流層6 >係根據類似於圖2 6所示之電子源1 0 /的例子 形成。 發射自圖2 8所示之電子源1 0 /之電子之程序基本 上是類似於圖2 6所示之電子1 0 /的例子的程序。然而 ，該程序在直流電壓V p s被應用於表面電極7與電子導 電層1 2間以致於表面電極7在相對於電子導電層1 2之 電位（正極）變高方面彼此不同。以此方式，甚至在圖 2 8所示之電子源1 0 /中，電子可以與圖2 6所示之電 子源1 0 /相同的方式發射。 近年來，如包含包括具有在陽極由氧化半導體層形成 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -7- 564454 經濟部智慈財產局員工消費合作社印製 A7 B7五、發明説明（5 ) 一些奈米級之半導體奈米晶體之多孔半導體層之裝置，提 出了利用在奈米區發生之操作的新原理之記憶體元件（例 如，曰本專利公開案號2 0 0 1 — 2 2 2 8 9 2 )。此記 憶體元件包括由密閉載體於具有能夠密閉載體之奈米級半 導體奈米晶體而儲存資訊之儲存層，該載體係覆與絕緣膜 〇 然而，上述習知的電子源1 0 /中，雖然電子可以高 電子發射效率固定地發射，電介質強度是稍微低，且服務 壽命稍微短。所以，較長的服務壽命與電介質強度的改進 被期待。 在形成上述習知的電子源1 0 /的漂流層6 >的步驟 中，氧化步驟係在陽極氧化處理步驟後實行。如果氟成分 或水成分於陽極氧化處理步驟中形成之多孔多晶矽層中剩 下，殘留的成分影響氧化矽膜5 2與6 4。因此，有電子 源1 0 >由於絕緣破壞或服務壽命被減少之危險。也就是 ，氧化矽膜5 2與6 4係根據快速加熱技術形成之熱氧化 膜。因此，如果氟成分或水成分剩下，當氧化矽膜5 2與 6 4被形成時，殘留的成分如氟成分或水成分彼此反應或 被混合。以此方式，氧化矽膜5 2與6 4的膜厚度變非均 勻或膜品質被降級。結果，有電介質強度失效發生之問題 ，且產量降低。 此外，製造上述電子源1 0 /之處理，陽極氧化處理 是濕處理，且因此，多孔區的厚度或矽奈米晶體的大小及 它的分佈在平面上變非均勻。結果，漂流層6 /之矽奈米 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -8- 564454 A7 B7 經濟部智慧財產局g(工消費合作社印製 五、發明説明（6 ) 晶體6 3的大小或分佈變非均勻。因此，平面上分佈由於 電子發射特徵（如電子發射效率或發射電流的電流密度） 發生，且缺陷區域地發生。有絕緣破壞發生，且服務壽命 被減少之問題。此外，有獲得平面上分佈的均勻度是困難 的，且產生大量面積是困難的之問題。 同時，形成上述電子源1 0 /的漂流層6 /的步驟， 陽極氧化處理步驟後之多孔多晶矽層被作動。因此，如果 一膜係在陽極氧化處理步驟與氧化步驟（例如，未完成項 目的停留期間）間曝露於空氣中，自然氧化膜被形成於矽 奈米晶體的表面上且多晶矽各使多孔多晶矽層成形。結果 ，有此自然氧化膜影響氧化矽膜5 2與6 4的電介質強度 之危險，電子源1 0 /由於絕緣破壞，或服務壽命被減少 而失效。也就是，氧化矽膜5 2與6 4是具有奈米級之薄 氧化膜，且因此，氧化矽膜5 2與6 4的整個膜厚度佔據 之自然氧化膜的膜厚度的比例增加。因此，具有高缺陷密 度之氧化矽膜5 2與6 4由於自然氧化膜的出現而形成， 且控制氧化矽膜5 2與6 4的膜厚度已變困難。結果’發 生了電介質強度電壓失效或類似情況發生之問題，且產量 降低。 如圖2 9所示，在具有由利用陽極氧化處理形成之漂 流層6 /之電子源1 0 /中，漂流層6 /中爲半導體奈米 晶體之矽奈米晶體6 3的大小（結晶粒大小）偏離。因此 ，覆與表面是絕緣膜之氧化矽膜6 4之矽奈米晶體6 3彼 此偏離，且不連續地被形成。接著，矽奈米晶體6 3的分 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) - 9 - 564454 經濟部智慧財產局g(工消費合作社印製 A7 B7五、發明説明（7 ) 佈變非均勻。結果，有電子的分散或然率增加之問題，且 電子發射效率降低。進一步，有由於電子分散之增加隨時 間經過降低發生，且電子源1 0 /的服務壽命被減少之問 題。 在具有利用陽極氧化處理形成之儲存層之記憶體元件 中，當半導體奈米晶體的大小彼此偏離，且被不連續地形 成，且半導體奈米晶體的分佈變非均勻時，發生了控制在 儲存層之資訊的寫位置困難，且儲存容量被減少之問題。 如事先已說明，上述習知電子源1 0 >之漂流層6 > 中，多孔多晶矽層被氧化，藉此薄氧化矽膜被形成於一些 矽奈米晶體與一些包含在多孔多晶矽層中之晶粒個別表面 上。爲了形成具有良好膜質之氧化矽膜於所有矽奈米晶體 與晶粒上，當漂流層6 /被形成時，多孔多晶矽層係在由 如1莫耳/公升硫酸或氮酸之水溶劑構成之電解液中被電 化地氧化。電解液在量比例包含9 0 %或更多（9 0 w t % )的水。多孔多晶矽層被電化地氧化，藉此處理溫 度可較快速加熱多孔多晶砂層的例子減少，藉此形成漂流 層6 >，且因此，基底材料上之限制被減少。所以，大面 積之電子源1 0 /與成本減少可達成。 然而，在多孔多晶矽層在含如硫酸或氮酸之水溶劑構 成之電解液中被電化氧化之電子源中，藉此形成漂流層， 而有發射電流I e或電子發射效率在工業運用的觀點上小 (不足）之問題。此外，有二極體電流I p s逐漸增加， 且發射電流I e逐漸降低之問題。此問題被認爲發生因素 $紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -10- 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（8 ) ，當漂流層6 /被形成時，多孔多晶矽層的氧化係在由如 硫酸或氮酸之水溶劑構成之電解液中實行。也就是，9 〇 • % w t或更多的水被包含在電解液中。因此，大量與水 分子有關之結合如Si— Η，Si— H2，或Si —〇Η 存在於漂流層6 /中形成之氧化矽膜。所以，被認爲氧化 矽膜的良性削弱，電子的分散輕易地發生，且電介質強度 被降低。 發明的節要 爲了解決前述的問題而產生了本發明。本發明的目的 是提供製造輕易地改進電介質強度，輕易地展延服務壽命 ，且輕易地達成大面積之電子源之方法以及裝置。 本發明的另一目的是提供製造能夠控制半導體奈米晶 體的分佈或大小之電子源之方法以及裝置。 本發明進一步的目的是提供製造隨著時間經過具有高 電子發射特徵與高安全性之電子源之方法以及裝置。 根據本發明之方法製造之電子源（場致發射式電子源 )包括：電子導電基底；於電子導電基底的一側上形成之 漂流層（強力場致漂流層）；以及於漂流層上形成之電子 導電薄膜。在此電子源中，電壓被採用以致於電子導電薄 膜在電子導電基底有關之極性上變正的。以此方式，自電 子導電基底注入漂流層之電子漂移於漂流層的內部，且係 經由電子導電薄膜發射。製造此電子源的方法包括：當漂 流層被形成時，根據陽極氧化形成包含半導體奈米晶體之 (請先閲讀背面之注意事項再填寫本頁)564454 Α7 _ Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention (1) Background of the invention The present invention relates to the inclusion of a strong field di ift layer to emit electrons from the electron field emission Method and device for manufacturing field emission electron source of light beam. The description of the related art includes the well-known strong field drift layer (hereinafter referred to as 'drift layer') composed of a porous oxidized semiconductor layer system formed on one surface of an electronic conductive substrate and a surface electrode system formed on the drift layer. Field emission type electron source (hereinafter referred to as ", electron source") (for example, Japanese Patent Case No. 2986842 'Japanese Patent Case No. 2987140 and Japanese Patent Case No. 3 0 7 9 0 8 6). As the electronic conductive substrate, for example, there are used: a semiconductor substrate having a resistivity relatively close to that of a conductor; and a substrate having an electronic conductive layer formed on a glass substrate (insulating substrate) or a similar surface. For example, as shown in FIG. 26, in this type of electron source 10-, the drift layer 6 / is composed of an oxidized porous polycrystalline sand layer system formed on the main surface of the n-type silicon substrate 1 which is an electronically conductive substrate. The surface electrode 7 is formed on the drift layer 6 /. The ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. In the example shown in FIG. 26, a semiconductor layer 3 composed of an undoped polycrystalline silicon layer is interposed between the n-type silicon substrate 1 and the drift layer 6 /. However, it has been proposed to have a drift layer 6 formed on the main surface of the n-type silicon substrate 1-no electron source interposing the semiconductor layer 3 is required. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) Qing ~ -4- (Please read the precautions on the back before filling this page) 564454 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ____B7 __ V. Description of the invention (2) In the electron source 10 / shown in FIG. 26, the electrons are emitted according to the following process. First, the collector electrode 21 is placed opposite the surface electrode 7. At the same time, a vacuum is provided between the surface electrode 7 and the collector electrode 21, and a DC voltage VP s is applied between the surface electrode 7 and the n-type silicon substrate 1 so that the surface electrode 7 is opposite to the n-type silicon substrate (ohmic electrode 2). ) The potential (positive polarity) of 1 becomes high. On the other hand, the DC voltage V c is applied between the collector electrode 21 and the surface electrode 7 so that the potential of the collector electrode 21 with respect to the surface electrode 7 becomes high. When the DC voltages V ps and V c are set correctly, the electron drift layer 6 injected from the n-type silicon substrate 1 is emitted through the surface electrode 7 (the single-dot chain line in FIG. The flow of emitted electrons '' e 〃). The surface electrode 7 is formed of a material (for example, gold) having a small work function. The thickness of the surface electrode 7 is set to about 10 nm to 15 nm. Here, the current flowing between the surface electrode 7 and the ohmic electrode 2 is called a diode current I ps, and the current flowing between the collector electrode 21 and the surface electrode 7 is called an emission current (emission electron flow). I e. At this time, if the ratio of the emission current I e to the diode current I p s (= I e / I P s) is increased, the electron emission efficiency is high. In the electron source 10 /, even if the DC voltage V p s between the surface electrode 7 and the ohmic electrode 2 is set to a low voltage of about 10 V to 20 V, electrons can be emitted. In addition, in the electron source 10 >, the dependence of the degree of vacuum of the electron emission characteristics can be reduced, and the electrons can be emitted with high emission efficiency during the electron emission without generating a hopping phenomenon. In the process of manufacturing the electron source 10, the steps of forming the drift layer 6 " (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -5- 564454 A7 ______ B7 V. Description of the Invention (3) It includes a film forming step, an anodizing step, and an oxidation step. In the film forming step, an undoped polycrystalline silicon layer is placed on one surface of the n-type silicon substrate 1 which is an electronically conductive substrate. In the anodizing step, the polycrystalline silicon layer is anodically oxidized, whereby a porous polycrystalline silicon layer including polycrystalline silicon particles and silicon nanocrystals is formed. In the oxidation step, the porous polycrystalline silicon layer is oxidized according to a rapid thermal oxidation technique, and thin oxide films are formed on the surfaces of the silicon nanocrystals and the crystal grains, respectively. In the anodizing step, a mixed solution obtained by mixing a hydrogen fluoride aqueous solvent and ethanol 1: 1 is used as an electrolytic solution for anodizing. In the oxidation step, a lamp annealing (lamp annealing) device is used. After the substrate temperature has been increased from room temperature to 900 ° C with dry oxygen for a short time, the substrate is maintained at 90 Ot-hours, and the substrate is oxidized. Then, the substrate temperature was lowered to room temperature. As shown in FIG. 2, the drift layer 6 / formed is considered to be composed of at least one cylindrical polycrystalline sand grain 5 1; a thin silicon oxide film 5 2 formed on the surface of the grain 5 1; 5 1 has a nano-sized silicon nano crystal 6 3 in between; and a film thickness formed on the surface of the silicon nano crystal 6 3 and having a smaller grain size than that of the silicon nano crystal 6 3 Silicon oxide film 6 4. That is, in the drift layer 6 >, before the anodic oxidation treatment is performed, the surface of each of the crystal grains 51 included in the polycrystalline layer is made porous and the crystalline state is maintained at the center portion of each of the crystal grains 51. Therefore, most of the electric field applied to the drift layer 6 / is thoroughly applied to the silicon oxide film 64. As a result, the injected electrons are accelerated by a strong electric field related to the silicon oxide film 64, and the direction indicated by the arrow A drifts toward the surface between the crystal grains 51. Therefore, the electron emission efficiency can be improved. Here, the size of the electronic paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). -6- (Please read the precautions on the back before filling out this page.) Printed 564454 Α7 Β7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4) Source 1 0 / Using a film that sets the size of the silicon nanocrystal 6 3 (crystal grain size) and the silicon oxide film 6 4 The thickness of the impact conduction phenomenon is equal to or less than the film thickness (the degree of the average free path of the electrons) when the electron tunneling phenomenon occurs. Electrons that reach the surface of the drift layer 6 / are considered to be hot electrons. These electrons easily tunnel through the surface electrode 7 and are emitted into a vacuum. In the electron source 10 / including the drift layer 6 /, the heat generated in the drift layer 6 / during electron emission is dissipated through the grain 51. Therefore, the heat generated in the drift layer 6 / can be efficiently dissipated, and the occurrence of the impact phenomenon can be restricted. As shown in FIG. 28, an electron source 10 having an electron conductive layer 12 formed on one surface of an insulating substrate 11 made of a glass substrate not using an n-type silicon substrate as an electronic conductive substrate is proposed. In FIG. 28, constituent elements like the electron source 10 / shown in FIG. 26 are indicated by line reference numerals. Its description is omitted here. The drift layer 6 of the electron source 10 / shown in FIG. 28 is formed based on an example similar to the electron source 10 / shown in FIG. The procedure of the electrons emitted from the electron source 10 / shown in Fig. 28 is basically similar to the example of the electron 10 / shown in Fig. 26. However, this procedure is such that the DC voltage V p s is applied between the surface electrode 7 and the electron conductive layer 12 so that the surface electrodes 7 are different from each other in the potential (positive electrode) with respect to the electron conductive layer 12 becomes high. In this way, even in the electron source 10 / shown in Fig. 28, electrons can be emitted in the same manner as the electron source 10 / shown in Fig. 26. In recent years, if it has been formed with an oxide semiconductor layer on the anode (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -7- 564454 Ministry of Economic Affairs A7 B7 printed by the Intellectual Property Cooperative Consumer Cooperative V. 5. Description of the invention (5) A device for porous semiconductor layers of some nanometer-level semiconductor nanocrystals, which proposes a memory using a new principle of operations occurring in the nanometer region Element (for example, Japanese Patent Publication No. 2000-1 2 2 8 9 2). This memory element includes a storage layer for storing information from a hermetic carrier on a nano-grade semiconductor nanocrystal having a hermetic carrier. The carrier is covered with an insulating film. However, the conventional electron source 10 / Electrons can be fixedly emitted with high electron emission efficiency, the dielectric strength is slightly lower, and the service life is slightly shorter. Therefore, a longer service life and an improvement in dielectric strength are expected. In the step of forming the above-mentioned conventional electron source 10 / drift layer 6 >, the oxidation step is performed after the anodizing step. If a fluorine component or a water component remains in the porous polycrystalline silicon layer formed in the anodizing step, the remaining components affect the silicon oxide films 5 2 and 64. Therefore, there is a danger that the electron source 10 > is damaged due to insulation damage or service life. That is, the silicon oxide films 5 2 and 64 are thermal oxide films formed according to a rapid heating technique. Therefore, if a fluorine component or a water component is left, when the silicon oxide films 52 and 64 are formed, the remaining components such as the fluorine component or the water component react with each other or are mixed. In this way, the film thicknesses of the silicon oxide films 52 and 64 become nonuniform or the film quality is degraded. As a result, there is a problem that dielectric strength failure occurs, and the yield is reduced. In addition, in the process of manufacturing the above-mentioned electron source 10 /, the anodizing process is a wet process, and therefore, the thickness of the porous region or the size of the silicon nanocrystals and its distribution become non-uniform on a plane. As a result, drifting layer 6 / Si nanometer paper size is applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling this page) -8- 564454 A7 B7 Intellectual Property of the Ministry of Economic Affairs Bureau g (printed by the Industrial and Consumer Cooperatives 5. Description of the invention (6) The size or distribution of the crystal 6 3 becomes non-uniform. Therefore, the distribution on the plane occurs due to electron emission characteristics (such as the electron emission efficiency or the current density of the emission current), and Defective areas occur. Insulation damage occurs and service life is reduced. In addition, it is difficult to obtain uniformity of distribution on a plane, and it is difficult to generate a large area. At the same time, the above-mentioned electron source 10 is formed. The drift layer 6 of / is activated by the porous polycrystalline silicon layer after the anodizing step. Therefore, if a film is exposed to the air between the anodizing step and the oxidizing step (for example, the residence period of an unfinished item) A natural oxide film is formed on the surface of the silicon nanocrystal and each of the polycrystalline silicon forms a porous polycrystalline silicon layer. As a result, there is this natural oxide film Due to the danger of the dielectric strength of the silicon oxide films 5 2 and 64, the electron source 10 / fails due to insulation breakdown or the service life is reduced. That is, the silicon oxide films 5 2 and 64 are thin as nanometers. Oxide film, and therefore, the proportion of the film thickness of the natural oxide film occupied by the entire film thickness of the silicon oxide films 5 2 and 64 is increased. Therefore, the silicon oxide films 5 2 and 6 4 having a high defect density are caused by the natural oxide film. Appeared and formed, and it has become difficult to control the film thickness of the silicon oxide films 52 and 64. As a result, a problem of dielectric strength voltage failure or the like occurs, and the yield is reduced. As shown in FIG. The size (crystal grain size) of the drifting layer 6 / electron source 10 / in which the drift layer 6 / is a semiconductor nanocrystal formed by anodizing treatment is deviated. Therefore, the coating and the surface are The silicon oxide film 63 of the insulating film 6 and the silicon nanocrystals 6 3 are deviated from each other and are formed discontinuously. Then, the paper size of the silicon nanocrystals 6 3 applies the Chinese National Standard (CNS) A4 specification (210X297) PCT) (Please read the back first Note: Please fill in this page again)-9-564454 Intellectual Property Bureau of the Ministry of Economic Affairs (printed by Industrial and Consumer Cooperatives A7 B7 V. Invention Description (7) The distribution becomes non-uniform. As a result, there is a problem that the probability of scattered electrons increases, and The electron emission efficiency is lowered. Further, there is a problem that an increase in electron dispersion occurs over time, and a service life of the electron source 10 / is reduced. In a memory element having a storage layer formed by anodization, when When the sizes of the semiconductor nanocrystals deviate from each other and are formed discontinuously, and the distribution of the semiconductor nanocrystals becomes non-uniform, the problems of controlling the writing position of the information in the storage layer and reducing the storage capacity occur. As previously explained, in the conventional electron source 10 > drift layer 6 >, the porous polycrystalline silicon layer is oxidized, whereby a thin silicon oxide film is formed on some silicon nanocrystals and some contained in the porous polycrystalline silicon layer. The grains are on individual surfaces. In order to form a silicon oxide film with good film quality on all silicon nanocrystals and grains, when the drift layer 6 / is formed, the porous polycrystalline silicon layer is composed of an aqueous solvent such as 1 mol / liter of sulfuric acid or nitric acid. The electrolyte is electrochemically oxidized. The electrolyte contains 90% or more (90 wt%) water in an amount ratio. The porous polycrystalline silicon layer is electrochemically oxidized, thereby reducing the number of examples in which the processing temperature can heat the porous polycrystalline sand layer faster, thereby forming the drift layer 6 > and, therefore, the restrictions on the base material are reduced. Therefore, a large-area electron source 10 / and cost reduction can be achieved. However, the porous polycrystalline silicon layer is electrochemically oxidized in an electron source composed of an aqueous solution such as sulfuric acid or nitric acid, thereby forming a drift layer, and there is a viewpoint that the emission current I e or the electron emission efficiency is industrially used. Small (under) problems. In addition, there is a problem that the diode current I p s gradually increases and the emission current I e gradually decreases. This problem is considered to be caused by the factors $ Paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling out this page) -10- 564454 A7 B7 Employees ’Intellectual Property Bureau Consumption The cooperative prints 5. Description of the invention (8). When the drift layer 6 / is formed, the oxidation of the porous polycrystalline silicon layer is performed in an electrolytic solution composed of an aqueous solvent such as sulfuric acid or nitric acid. That is, 90% of water or more is contained in the electrolytic solution. Therefore, a large number of water molecule-related bonds such as Si—Si, Si—H2, or Si—〇Η exist in the silicon oxide film formed in the drift layer 6 /. Therefore, it is considered that the benign weakening of the silicon oxide film, the scattering of electrons easily occurs, and the dielectric strength is reduced. SUMMARY OF THE INVENTION The present invention has been made to solve the aforementioned problems. An object of the present invention is to provide a method and a device for easily improving a dielectric strength, easily extending a service life, and easily achieving a large-area electron source. Another object of the present invention is to provide a method and apparatus for manufacturing an electron source capable of controlling the distribution or size of a semiconductor nanocrystal. A further object of the present invention is to provide a method and a device for manufacturing an electron source with high electron emission characteristics and high security over time. An electron source (field emission type electron source) manufactured according to the method of the present invention includes: an electron conductive substrate; a drift layer (a strong field drift layer) formed on one side of the electron conductive substrate; and a layer formed on the drift layer Electronic conductive film. In this electron source, the voltage is applied so that the electronically conductive film becomes positive with respect to the polarity associated with the electronically conductive substrate. In this way, the electrons injected into the drift layer from the electronically conductive substrate drift inside the drift layer and are emitted through the electron conductive film. The method of manufacturing this electron source includes: when the drift layer is formed, the semiconductor nanocrystals are formed according to anodization (please read the precautions on the back before filling this page)

本紙張尺度適用中國國家標準（CNS ) A4規格（210X：297公釐） -11 - 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（9 ) 多孔半導體層的陽極氧化處理步驟；以及形成絕緣膜於各 半導體奈米晶體的表面上的絕緣膜形成步驟。在陽極氧化 處理步驟中，陽極氧化處理被實行同時發射基本上包含半 導體層有關之可見光區域的波長之光。根據製造此電子源 的方法，包含在多孔半導體層之半導體奈米晶體的分佈或 大小可被控制。以此方式，一些被連續地分佈之半導體奈 米晶體之多孔半導體層可被形成。 在製造此電子源的方法中，發射至半導體層之光的波 長最好係由光學濾光器限制。此例中，射至半導體層之光 的波長可被輕易地調整。 在此，光學濾光器最好是由至少紅外線切除濾光器與 紫外線切除濾光器的其中之一構成的。由如此做，由無助 於多孔膜之紅外線引起之溫度上升可被限制。此外，由於 紫外線之孔產生的量增加，且半導體奈米晶體的分佈或大 小之偏離可被限制。因此，半導體奈米晶體的分佈或大小 可被輕易地控制。 在製造根據本發明之電子源的方法中，最好是以半導 體奈米晶體係彼此連續地連接之波長而設被發射在半導體 層之光的波長。此例中，一些具有奈米級之半導體奈米晶 體係連續地彼此連接之多孔半導體層可被形成而不需使用 光學零件如光學濾光器。 在製造根據本發明之電子源的方法中，最好是使用單 色光的光源。此例中，相同大小的半導體奈米晶體係連續 地彼此連接之多孔半導體層可被安全地形成。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -12- 564454 A7 B7 經濟部智慧財產局8工消費合作社印製 五、發明説明（10) 在製造根據本發明之電子源的方法中，最好是在陽極 氧化已開始後根據時間的經過改變於半導體層被發射之光 的波長。此例中，半導體奈米晶體的大小可關於多孔半導 體層的厚度方向而控制。即，半導體奈米晶體的大小可關 於多孔半導體層的厚度方向而區分。 在製造根據本發明之電子源的方法中，最好是在陽極 氧化已開始後根據時間的經過改變光學濾光器的傳送波長 。此例中，半導體奈米晶體的大小可關於多孔半導體層的 厚度方向而控制。 即，半導體奈米晶體的大小可關於多孔半導體層的厚 度方向而區分。 在製造根據本發明之電子源的方法中，最好是間歇地 於半導體層發光。此例中，半導體層的溫度上升可被限制 。以此方式，多孔半導體層之半導體奈米晶體的分佈或大 小可被輕易地控制。 在製造根據本發明之電子源的方法中，最好是自半導 體層的表面的對側發光至半導體層。此例中，孔可被有效 地自對側供應至表面和半導體層的表面側。在此，自半導 體層的厚度方向之兩側發射之光的波長也許同時被改變。 由如此做，孔可在半導體層的厚度方向之兩側被供應。因 此，甚至在半導體層的厚度稍微厚之例子中，此處理可被 輕易地實現。當半導體層是更多孔時，帶隙增加。因此， 較大的能量被需要以確保該層是更多孔的。通常，當波長 被減少時，光入侵深度變淺。然而，半導體層可由因此自 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐） -13- 564454 Α7 Β7 經濟部智懇財產局員工消費合作社印製 五、發明説明（Μ) 半導體層的厚度方向之兩側發射光而被輕易地做成更多孔 。此外，在多孔半導體層中形成之半導體奈米晶體的大小 可在多孔半導體層的厚度方向是均勻的。 在製造根據本發明之電子源的方法中，最好是使用控 制陽極氧化處理容器之電解液的濃度以致於以相同的速率 促進多孔半導體層的形成之控制機構。此例中，在形成多 孔半導體層中，電解液的濃度被控制以致於產生更多孔半 導體層的速率在導體層的平面中彼此是一致的。因此，陽 極氧化之處理是穩定的，且包含在多孔半導體層之半導體 奈米晶體的分佈或大小的再生與均勻度可被改進。結果， 漂流層之半導體奈米晶體的分佈或大小的再生與均勻度可 被改進。所以，電介質強度可被改進，且服務壽命可被展 延。此外，在具有電子發射特徵與大面積之平面中可提供 具有高均勻度之電子源。 在此，最好是利用引導具有經調整溫度與濃度之電解 液進入陽極氧化處理容器之控制容器。此例中，產生更多 孔層之速率的控制能力被改進。以此方式，多孔半導體層 的平面中之再生與均勻度可被改進。此外，最好是控制機 構被提供以好好地移動包含下電極與半導體層之目標。此 例中，包含在多孔半導體層之半導體奈米晶體的分佈與大 小的再生與均勻度可被更顯著地改進。 在製造根據本發明之電子源的方法中，最好是由使用 至少一氫有機溶劑移除殘留在多孔半導體層之電解液的沖 洗步驟被包括在陽極氧化處理步驟與絕緣膜形成步驟之間 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -14 - 564454 A 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（12) 。此例中，殘留在根據陽極氧化處理步驟形成之多孔半導 體層之電解液或其類似可在絕緣膜形成步驟之前被移除。 因此，在絕緣膜形成步驟於半導體奈米晶體的表面上形成 之絕緣膜的品質可被改進。所以，電子源的電介質強度可 被改進，且服務壽命可被展延。 在製造根據本發明之電子源的方法中，最好是由使用 至少一非可溶解有機溶劑移除殘留在多孔半導體層之電解 液的沖洗步驟被包括在陽極氧化處理步驟與絕緣膜形成步 驟之間。此例中，殘留在根據陽極氧化處理步驟形成之多 孔半導體層之電解液或其類似可在絕緣膜形成步驟之前被 移除。因此，在絕緣膜形成步驟於半導體奈米晶體的表面 上形成之絕緣膜的品質可被改進。所以，電子源的電介質 強度可被改進，且服務壽命可被展延。 在製造根據本發明之電子源的方法中，在於陽極氧化 處理步驟與氧化處理步驟間特定之時段期間，最好是避免 自然氧化膜被形成於半導體奈米晶體的表面上而不曝露多 孔半導體層至空氣中。此例中，在上述特定時段期間，自 然氧化膜可避免被形成於半導體奈米晶體的表面上。因此 根據氧化處理步驟於半導體奈米晶體的表面上形成之氧化 膜的品質可被改進。所以，電子源的電介質強度可被改進 ，且服務壽命可被展延。 在上述特定時段期間，最好是以非氧化液覆蓋多孔半 導體層的表面。由如此做，在根據陽極氧化處理步驟此非 氧化液被用作提升之例子中，例如，自然氧化膜由利用此 (請先閲讀背面之注意事項再填寫本頁) 『裝·This paper size applies Chinese National Standard (CNS) A4 specification (210X: 297 mm) -11-564454 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (9) Anodizing step of porous semiconductor layer And an insulating film forming step of forming an insulating film on the surface of each semiconductor nanocrystal. In the anodizing treatment step, the anodizing treatment is performed while emitting light having a wavelength substantially including a visible light region related to the semiconductor layer. According to the method of manufacturing this electron source, the distribution or size of semiconductor nanocrystals contained in the porous semiconductor layer can be controlled. In this manner, porous semiconductor layers of semiconductor nanocrystals which are continuously distributed can be formed. In the method of manufacturing this electron source, the wavelength of light emitted to the semiconductor layer is preferably limited by an optical filter. In this example, the wavelength of light incident on the semiconductor layer can be easily adjusted. Here, the optical filter is preferably constituted by at least one of an infrared cut filter and an ultraviolet cut filter. By doing so, the temperature rise caused by infrared rays not contributing to the porous membrane can be limited. In addition, the amount of holes due to ultraviolet rays is increased, and the distribution or size deviation of semiconductor nanocrystals can be limited. Therefore, the distribution or size of semiconductor nanocrystals can be easily controlled. In the method of manufacturing the electron source according to the present invention, it is preferable to set the wavelength of light emitted in the semiconductor layer at a wavelength at which semiconductor nanocrystal systems are continuously connected to each other. In this example, a plurality of porous semiconductor layers having semiconductor nanocrystal systems having nanometer grades continuously connected to each other can be formed without using optical parts such as optical filters. In the method of manufacturing the electron source according to the present invention, it is preferable to use a light source of monochromatic light. In this example, porous semiconductor layers in which semiconductor nanocrystal systems of the same size are continuously connected to each other can be safely formed. (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -12- 564454 A7 B7 Printed by the 8th Industrial Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation (10) In the method of manufacturing the electron source according to the present invention, it is preferable to change the wavelength of light emitted from the semiconductor layer according to the passage of time after anodization has started. In this example, the size of the semiconductor nanocrystal can be controlled with respect to the thickness direction of the porous semiconductor layer. That is, the size of the semiconductor nanocrystal can be distinguished with respect to the thickness direction of the porous semiconductor layer. In the method of manufacturing the electron source according to the present invention, it is preferable to change the transmission wavelength of the optical filter according to the passage of time after anodization has started. In this example, the size of the semiconductor nanocrystal can be controlled with respect to the thickness direction of the porous semiconductor layer. That is, the size of the semiconductor nanocrystal can be distinguished with respect to the thickness direction of the porous semiconductor layer. In the method of manufacturing the electron source according to the present invention, it is preferable to emit light on the semiconductor layer intermittently. In this example, the temperature rise of the semiconductor layer can be limited. In this manner, the distribution or size of semiconductor nanocrystals of the porous semiconductor layer can be easily controlled. In the method of manufacturing the electron source according to the present invention, it is preferable that light is emitted from the opposite side of the surface of the semiconductor layer to the semiconductor layer. In this example, the holes can be efficiently supplied from the opposite side to the surface and the surface side of the semiconductor layer. Here, the wavelength of light emitted from both sides in the thickness direction of the semiconductor layer may be changed at the same time. By doing so, the holes can be supplied on both sides in the thickness direction of the semiconductor layer. Therefore, even in the case where the thickness of the semiconductor layer is slightly thick, this process can be easily realized. When the semiconductor layer is more porous, the band gap increases. Therefore, greater energy is needed to ensure that the layer is more porous. Generally, when the wavelength is reduced, the depth of light intrusion becomes shallower. However, the semiconductor layer can be read by yourself (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 specification (210X29 * 7 mm) -13- 564454 Α7 Β7 Intellectual property of the Ministry of Economy Printed by the Bureau's Consumer Cooperative. V. Invention Description (M) The semiconductor layer emits light on both sides in the thickness direction and is easily made into more holes. In addition, the size of the semiconductor nanocrystals formed in the porous semiconductor layer may be uniform in the thickness direction of the porous semiconductor layer. In the method of manufacturing the electron source according to the present invention, it is preferable to use a control mechanism that controls the concentration of the electrolytic solution of the anodizing treatment vessel so as to promote the formation of the porous semiconductor layer at the same rate. In this example, in forming the porous semiconductor layer, the concentration of the electrolytic solution is controlled so that the rate at which more porous semiconductor layers are generated is consistent with each other in the plane of the conductive layer. Therefore, the treatment of the anode oxidation is stable, and the distribution and size of the semiconductor nanocrystals contained in the porous semiconductor layer can be improved and the uniformity can be improved. As a result, the regeneration or uniformity of the distribution or size of the semiconductor nanocrystals in the drift layer can be improved. Therefore, the dielectric strength can be improved, and the service life can be extended. In addition, an electron source having a high uniformity can be provided in a plane having electron emission characteristics and a large area. Here, it is preferable to use a control container that guides the electrolytic solution having the adjusted temperature and concentration into the anodizing container. In this example, the ability to control the rate at which more layers are produced is improved. In this way, regeneration and uniformity in the plane of the porous semiconductor layer can be improved. Further, it is preferable that a control mechanism is provided to properly move the target including the lower electrode and the semiconductor layer. In this example, the distribution and size regeneration and uniformity of the semiconductor nanocrystals contained in the porous semiconductor layer can be more significantly improved. In the method of manufacturing an electron source according to the present invention, it is preferable that a washing step of removing the electrolytic solution remaining in the porous semiconductor layer by using at least one hydrogen organic solvent is included between the anodizing step and the insulating film forming step ( Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standards (CNS) Α4 specifications (210X297 mm) -14-564454 A 7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (12). In this example, the electrolytic solution or the like remaining in the porous semiconductor layer formed according to the anodizing step may be removed before the insulating film forming step. Therefore, the quality of the insulating film formed on the surface of the semiconductor nanocrystal in the insulating film forming step can be improved. Therefore, the dielectric strength of the electron source can be improved, and the service life can be extended. In the method of manufacturing an electron source according to the present invention, it is preferable that the rinsing step of removing the electrolytic solution remaining in the porous semiconductor layer by using at least one non-soluble organic solvent is included in the anodizing step and the insulating film forming step. between. In this example, the electrolytic solution or the like remaining in the porous semiconductor layer formed according to the anodizing step may be removed before the insulating film forming step. Therefore, the quality of the insulating film formed on the surface of the semiconductor nanocrystal in the insulating film forming step can be improved. Therefore, the dielectric strength of the electron source can be improved, and the service life can be extended. In the method of manufacturing the electron source according to the present invention, it is preferable to prevent a natural oxide film from being formed on the surface of the semiconductor nanocrystal without exposing the porous semiconductor layer during a specific period between the anodizing step and the oxidizing step. Into the air. In this example, the natural oxide film can be prevented from being formed on the surface of the semiconductor nanocrystal during the specific period described above. Therefore, the quality of the oxide film formed on the surface of the semiconductor nanocrystal according to the oxidation treatment step can be improved. Therefore, the dielectric strength of the electron source can be improved, and the service life can be extended. During the above-mentioned specific period, it is preferable to cover the surface of the porous semiconductor layer with a non-oxidizing liquid. By doing so, in the example where the non-oxidizing liquid is used as a lift according to the anodizing step, for example, the natural oxide film is used by this (please read the precautions on the back before filling this page)

’1T 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 564454 A7 B7 — __— _ -- 五、發明説明（13) (請先閱讀背面之注意事項再填寫本頁) 非氧化液可避免被形成。此外，在上述特定時段，大氣也 許被使用作鈍性氣體。由如此做，多孔半導體層的濃度可 被限制。在上述特定時段，至少該多孔半導體層也許在保 持在真空中。由如此做，對多孔半導體層之雜質的黏附可 被限制。 經濟部智慧財產局Μ工消費合作社印製 在製造根據本發明之電子源的方法中，最好是絕緣膜 形成步驟包括在具有在有機溶劑溶解之溶劑之電解液中電 化地氧化多孔半導體層的主要氧化處理步驟。此例中，如 與先前技藝比較，發射電流或電子發射效率或其類似增加 ’且隨著時間的經過電子源的電子發射特徵的穩定性可被 改進。發射電流與電子發射效率可因此被改進，且隨著時 間的經過電子源的電子發射特徵的穩定性被改進之理由的 其中之一陳述如下。也就是，這是因爲氧化膜的密度增加 ，且如比較在由水溶劑如硫酸或氮酸構成之電解液中電化 地氧化多孔多晶矽層之習知技術氧化膜的電介質強度被改 進，藉此形成漂流層。此外，如比較多孔半導體層被快速 地熱氧化，藉此形成漂流層之例子中，處理溫度可被減少 ，電子源之面積可被增加，且成本減少可被達成。 在製造包含主要氧化處理步驟之電子源的方法中，最 好是加水至電解液。由如此做，在使用對作爲溶質之有機 溶劑具有小可溶解度且對水具有大可溶解度之物質之例子 中，電解液之溶質的濃度可由加水而增加。因此，氧化膜 的膜品質被改進。此外，如溶質的濃度增加，電解液的導 電率增加。所以，氧化膜的膜厚度的平面之偏離可被限制 本紙張尺度適用中國國家標準（CNS ) A4規格（2H)X297公釐） 一 -16- 564454 經濟部智慧財產局K工消費合作社印製 A7 B7五、發明説明（14) 〇 在製造包括主要氧化處理步驟之電子源的方法中，最 好是根據熱氧化技術氧化多孔半導體層的輔助氧化處理步 驟被包括至少在主要氧化處理步驟之前或後。由如此做， 氧化膜的密度可更顯著地改進。 在製造包含主要氧化處理步驟之電子源的方法中，主 要氧化處理步驟前氧化多孔半導體層的預先氧化處理步驟 也許被包括。此例中，氧化膜的密度可更顯著地被改進。 進一步’在漂流層的厚度方向，存於稍微接近電子導電薄 膜之區域之氧化膜的膜厚度可被限制免於大於存於距電子 導電薄膜稍微遠之區域之氧化膜的膜厚度。此例中，隨著 時間的經過電子發射效率與穩定度可被改進。此外，主要 氧化處理步驟與輔助氧化處理步驟前氧化多孔半導體層的 預先氧化處理步驟也許被包括。同樣在此例中，在漂流層 的厚度方向，存於稍微接近電子導電薄膜之區域之氧化膜 的膜厚度可被限制免於大於存於距電子導電薄膜稍微遠之 區域之氧化膜的膜厚度，且以此方式，隨著時間的經過電 子發射效率與穩定度可被改進。 在製造包含主要氧化處理步驟之電子源的方法中，沖 洗多孔半導體層的沖洗步驟也許在主要氧化處理步驟後被 包括。此例中，即使雜質如鹼金屬或重金屬進入多孔半導 體層，此雜質可在沖洗步驟中移除。結果，電子源的電子 發射特徵可被穩定且長期可靠度可被改進。 此外，根據本發明製造上述電子源之裝置包括··當漂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)'1T This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -15- 564454 A7 B7 — __ — _-V. Description of the invention (13) (Please read the precautions on the back before filling this page ) Non-oxidizing liquid can be prevented from being formed. In addition, the atmosphere may be used as a passive gas during the above-mentioned specific periods. By doing so, the concentration of the porous semiconductor layer can be limited. At least the porous semiconductor layer may be kept in a vacuum during the above specific period. By doing so, adhesion of impurities to the porous semiconductor layer can be restricted. In the method for manufacturing an electron source according to the present invention, it is preferable that the insulating film forming step includes the step of electrochemically oxidizing the porous semiconductor layer in an electrolytic solution having a solvent in which an organic solvent is dissolved. The main oxidation treatment steps. In this example, if compared with the prior art, the emission current or the electron emission efficiency or the like increases' and the stability of the electron emission characteristics of the electron source over time can be improved. One of the reasons why the emission current and the electron emission efficiency can be improved as a result, and the stability of the electron emission characteristics of the electron source over time is improved is stated below. That is, this is because the density of the oxide film is increased, and the dielectric strength of the oxide film is improved as compared with the conventional technique of electrochemically oxidizing the porous polycrystalline silicon layer in an electrolytic solution composed of a water solvent such as sulfuric acid or nitric acid, thereby forming Rafting layer. In addition, if the comparative porous semiconductor layer is rapidly thermally oxidized to form a drift layer, the processing temperature can be reduced, the area of the electron source can be increased, and cost reduction can be achieved. In the method of manufacturing the electron source including the main oxidation treatment step, it is preferable to add water to the electrolytic solution. By doing so, in the case where a substance having a small solubility in an organic solvent as a solute and a large solubility in water is used, the concentration of the solute in the electrolytic solution can be increased by adding water. Therefore, the film quality of the oxide film is improved. In addition, as the concentration of the solute increases, the conductivity of the electrolytic solution increases. Therefore, the deviation of the plane of the film thickness of the oxide film can be limited. The paper size applies the Chinese National Standard (CNS) A4 (2H) X297 mm. -16- 564454 Printed by A. K. Co., Ltd., Intellectual Property Bureau, Ministry of Economic Affairs B7 V. Description of the invention (14) In the method of manufacturing the electron source including the main oxidation treatment step, it is preferable that the auxiliary oxidation treatment step of oxidizing the porous semiconductor layer according to the thermal oxidation technique is included at least before or after the main oxidation treatment step. . By doing so, the density of the oxide film can be improved more significantly. In the method of manufacturing an electron source including a main oxidation treatment step, a preliminary oxidation treatment step of oxidizing the porous semiconductor layer before the main oxidation treatment step may be included. In this case, the density of the oxide film can be improved more significantly. Further, in the thickness direction of the drift layer, the film thickness of the oxide film existing in a region slightly close to the electronically conductive film can be restricted from being larger than the film thickness of the oxide film existing in a region slightly away from the electronically conductive film. In this example, the electron emission efficiency and stability can be improved over time. In addition, a preliminary oxidation treatment step for oxidizing the porous semiconductor layer before the main oxidation treatment step and the auxiliary oxidation treatment step may be included. Also in this example, in the thickness direction of the drift layer, the film thickness of the oxide film existing in a region slightly close to the electronically conductive film can be limited to be larger than the film thickness of the oxide film existing in a region slightly away from the electronically conductive film. And, in this way, the electron emission efficiency and stability can be improved over time. In the method of manufacturing an electron source including a main oxidation treatment step, a rinse step for rinsing the porous semiconductor layer may be included after the main oxidation treatment step. In this example, even if an impurity such as an alkali metal or a heavy metal enters the porous semiconductor layer, the impurity can be removed in the washing step. As a result, the electron emission characteristics of the electron source can be stabilized and long-term reliability can be improved. In addition, the device for manufacturing the above-mentioned electron source according to the present invention includes: ··················································································

-17- 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（15) 流層被形成時，根據陽極氧化形成包括半導體奈米晶體之 多孔半導體層之陽極氧化處理設備；以及形成絕緣膜於各 半導體奈米晶體的表面上之絕緣膜形成設備。在此，陽極 氧化處理設備被設計以實行陽極氧化處理同時發射基本上 包含半導體層有關之可見光區域之波長之光。根據此電子 源製造裝置，包含在多孔半導體層之半導體奈米晶體的分 佈或大小可被控制。以此方式，可形成一些半導體奈米晶 體被分佈成彼此連續地連接之多孔半導體層。 圖形的簡要說明 本發明將由附圖與發明的詳細說明而被完全地了解。 圖形中共同的類似元件係由類似參考數字表示。 圖1是描述根據第一實施例用作製造電子源之陽極氧 化設備的一般建構之槪圖； 圖2 A至圖2 D是各顯示製造電子源之處理的主要步 驟中之電子源或它的材料之截面圖； 圖3是示例電子源的操作之圖； 圖4是顯示電子源的電子發射操作之圖； 圖5是描述製造電子源之處理的陽極氧化處理步驟之 時間的經過與光波長間之關係之圖； 圖6是顯示製造電子源的方法的範例之圖； 圖7是顯示製造電子源的方法的範例之圖； 圖8是描述製造電子源之處理的陽極氧化處理步驟之 時間的經過與切除波長間之關係之圖； (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -18- 564454 A7 B7 經濟部智慧財產局8工消費合作钍印t 五、發明説明（16) 圖9是描述製造電子源之處理的陽極氧化處理步驟之 時間的經過與光波長間之關係之圖； 圖1 0是顯示製造電子源的方法的範例之圖； 圖1 1是顯示根據第二實施例之電子源的操作之圖； 圖1 2A至圖1 2D是各顯示製造電子源之處理的主 要步驟中之電子源或它的材料之截面圖； 圖1 3是顯示用作製造電子源之陽極氧化設備的一般 建構之槪圖； 圖1 4是顯示根據第三實施例之記憶體元件的一般建 構之圖； 圖1 5是記憶體元件的帶狀圖； 圖1 6是顯示記憶體元件的另一示範建構之圖； 圖1 7是顯示記憶體元件的應用範例之圖； 圖18是描述根據第四實施例用作製造電子源之陽極 氧化設備的一般建構之槪圖； 圖1 9是顯示根據第十實施例之電子發射特徵之圖； 圖2 0是顯示根據第十一實施例之電子發射特徵之圖 9 圖2 1是顯示根據第十二實施例之電子發射特徵之圖 圖2 2是顯示根據第十三實施例之電子發射特徵之圖 圖2 3是顯示根據第十至第十三實施例之電子發射特 徵的比較之圖； (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（2】OX297公釐） -19- 564454 A7 B7 經濟部智慧財產局g(工消費合作社印製 五、發明説明（17) 圖2 4是顯示根據第十四實施例之電子發射特徵之圖 圖2 5是顯示比較範例的電子源的電子發射特徵之圖 j 圖2 6是顯示習知電子源的操作之圖； 圖2 7是顯示習知電子的電子發射操作之圖； 圖2 8是另一習知電子源的操作之圖； 圖2 9是圖2 6所示之電子源的基本部分的一般建構 之 圖； 主要元件對照表 1 〇 / 電子源 6 漂流層 1 η型矽基底 7 表面電極 2 歐姆電極 3 半導體層 2 1 集極電極 5 1 圓柱多晶矽粒 5 2 薄氧化矽膜 6 3 矽奈米晶體 6 4 氧化矽膜 1 1 絕緣基底 1 2 導電層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -20- 564454 A7 B7 五、發明説明（18) 經濟部智慧財產局員工消費合作社印製 1 〇 電 子 源 6 漂 流 層 4 多 孔 多 晶 矽 層 4 1 處 理 容 器 4 2 陰 極 B 電 解 液 C 標 4 3 電 壓 源 4 4 光 源 4 5 濾 光 設 備 4 6 波 長 控 制 設 備 4 7 光 源 4 8 濾 光 設 備 1 〇 0 基 底 1 0 0 a 電 子 導 電 層 1 〇 Ob 絕 緣 層 1 〇 1 儲 存 層 1 5 探 針 1 0 0 c 矽 層 D 汲 極 S 源 極 6 0 氧 化 鬧 膜 7 0 聞 電 極 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -21 - 564454A7B7 經濟部智慧財產局8工消費合作社印製 五、發明説明（19) 較佳實施例的詳細說明 (第一實施例） 第一實施例中，電子源係由利用陽極氧化處理製造。 根據第一實施例之電子源中，電阻係數是稍微接近導體的 電阻係數（例如，具有大約0 .. 0 1 Ω / c m至〇 . 0 2 Ω / c m的電阻係數之（1 0 0 )基底）之單晶n型矽基 底被用作電子導電基底。 如圖3所示，根據第一實施例之電子源1 〇，由經氧 化的多孔多晶矽層構成之漂流層6被形成於爲導電基底之 η型矽基底1的主要表面上。表面電極7被形成於漂流層 6上。歐姆電極2被形成於η型矽基底1的背面。第一實 施例中，下電極係由η型矽基底1與歐姆電極2構成的。 所以，表面電極7是相對於下電極，且漂流層6係介於下 電極與表面電極7之間。多孔多晶矽層使多孔半導體層成 形。 具有小逸功之材料被用作表面電極7的材料。表面電 極7的厚度被設成1 0 n m。然而，此厚度也許如此厚 以致於通過漂流層6之電子可被隧穿不必被限制成1 〇 n m。表面電極7的厚度也許被設成大約1 〇 n m至 15 n m 〇 表面電極7的構成·有：由於漂流層6上形成之金屬膜 (例如，C r膜）構成之第一薄膜層；以及於第一薄膜層 上沈澱之金屬膜（例如，A u膜）構成之第二薄膜層。例 如，使用具有與漂流層6高親密關係之材料如鉻，鎳，鉑 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -22- 564454 A7 B7___ 五、發明説明（20) (讀先閱讀背面之注意事項再填寫本頁) ，鈦，或銦當作漂流層6上之第一薄膜層之材料’該材料 能夠避免第二薄膜層與漂流層6間之擴散。使用隨著時間 的經過具有低阻抗與高穩定度之金或其類似當作第二薄膜 層之材料。實施例中，C r被用作第一薄膜層之材料。第 一薄膜層的厚度被設成2 n m。A u被用作第二薄膜層 之材料。第二薄膜層的厚度被設成8 n m。第一實施例 中，表面電極7係由兩層金屬膜構成的。然而，電極也許 係由一層或三或更多層金屬膜構成的。 經濟部智慧財產局員工消費合作社印製 圖3所示之電子源1 0中，表面電極7係在真空中沈 澱，且集極電極2 1係在表面電極7的對側沈澱。接著， 直流電壓Vp s被採用以致於表面電極7在η型矽基底1 (歐姆電極2 )有關之極性上是正的。進一步，直流電壓 V c被採用以致於集極電極2 1在表面電極7有關之極性 上是正的。以此方式，自η型矽基底1注入之電子漂移於 漂流層6，且係經由表面電極7 (圖3所示之單點線鏈表 示經由表面電極7發射之電子、e - 〃）發射。如已先前 說明’流於表面電極7與η型矽基底（歐姆電極2 )間之 電流被稱爲二極體電流I p s，且流於集極電極2 1與表 面電極7間之電流被稱爲發射電流（發射電子流）I e。 如發射電流I e對二極體電流I p s的比率增加，電子發 射效率增加。 如圖4所示，第一實施例之漂流層6的構成有：至少 一圓柱多晶矽粒5 1 ;於晶粒5 1的表面上形成之薄氧化 砂膜5 2 ;介於晶粒5 1之間一些具有奈米級之矽奈米晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） - --- -23- 564454 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（21) 體6 3 ;以及爲於各矽奈米晶體6 3的表面上形成之絕緣 膜之一些氧化矽膜6 4，該膜具有較小於矽奈米晶體6 3 的晶粒大小的膜厚度。簡言之，在漂流層6中，各晶粒 5 1的表面被做成多孔，且結晶狀態被維持在各晶粒5 1 的中心部分。於矽奈米晶體6 3的表面上形成之氧化矽膜 6 4的厚度被設成電子平均自由徑的程度（S i〇2之電 子的平均自由徑已知是3 n m )，且要求設成大約1 n m至3 n m。矽奈米晶體6 3的晶粒大小小於平均自 由徑的程度。 根據第一實施例之電子源1 0中，電子發射在下列模 式中發生。也就是，直流電壓V p s被採用以致於表面電 極7在曝露於真空中之表面電極7與η型矽基底1 (歐姆 電極2 )間之極性是正的。此外，直流電壓V c被採用以 致於集極電極2 1在集極電極2 1與表面電極7間之極性 是正的。當直流電壓V p s到達預定値（決定値），電子 > e "係由熱激發自作爲下電極之η型矽基底1注入漂流 層6。另一方面，應用至漂流層6之大部分的電場被應用 至氧化矽膜6 4。因此，經注的電子> e 〃係由應用至氧 化矽膜6 4之強電場加速。接著，電子於漂流層6之晶粒 5 1間之區域的內側漂向圖4之箭頭A指示之方向之表面 ，且在經由表面電極7隧穿後在真空中被發射。因此，漂 流層6中，自η型矽基底1注入之電子被加速且漂至應用 至氧化矽膜6 4之強電場的內側而幾乎不被矽奈米晶體 6 3分散。接著，電子係經由表面電極7發射（衝擊電子 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -24 - 564454 A7 B7 五、發明説明（22) (請先閲讀背面之注意事項再填寫本頁) 發射現象）。此外，漂流層6產生之熱係經由晶粒5 1而 發散。因此，跳躍現象在電子發射期間不會發生，且電子 可被固定地發射。到達漂流層6的表面之電子被認爲是熱 電子，但係經由表面電極7輕易地隧穿，且在真空中被發 射。 之後，根據第一實施例製造電子源1 0的方法將參考 圖2A至圖2D而說明。 首先，歐姆電極2被形成於η型矽基底1的背面。非 經摻雜的多晶矽層3被形成於η型矽基底1的主要表面上 作爲半導體層。以此方式，圖2 Α所示之結構被獲得。例 如，使用C V D技術（如L P C V D技術，電漿C V D技 術，或催化C V D技術，例如）；噴濺技術或C G S (連 續晶粒矽）技術與其類似當作形成多晶矽層3之膜的方法 〇 經濟部智1財產局8工消費合作社印製 非經摻雜的多晶矽層3已被形成後，多晶矽層3係根 據陽極氧化處理步驟形成。以此方式，爲多孔半導體層之 多孔多晶矽層4被形成，且圖2 B所示之結構被獲得。在 第一實施例中，雖然所有多晶矽層3被製成多孔，但也許 僅一部分的層被製成多孔。 陽極氧化處理步驟中，圖1所示之陽極氧化設備被使 用。圖1所示之陽極氧化設備包括：具有包含氟化氫水溶 液之電解液B之處理容器4 1 ;以及由可溶解於電解液B 之鉑構成之陰極4 2。接著，當爲半導體層之多晶矽層3 被形成於下電極（在第一實施例中，下電極係由η型矽基 本紙張尺度適用中國國家榡準（CNS ) Α4規格（210X297公釐） -25- ^564454 經濟部智慈財產局P貝工消費合作社印製 A7 _B7___五、發明説明（23) 底1與歐姆電極2構成的）時獲得之目標C被放在處理容 器4 1以致於僅一部分多晶砂層3的表面與電解液B接觸 。此陽極氧化設備包括：係用爲陽極之下電極充電於陽極 與陰極間之電壓源4 3 ;發射光至目標C (多晶矽層3的 表面側）的主要表面側之光源4 4 ;置於光源4 4與目標 C間之濾光設備4 5，該濾光設備是能夠改變光傳送波長 :能夠控制濾光設備4 5的傳送波長之波長控制設備4 6 。當陽極氧化被實行同時電源係用爲陽極之下電極而供應 於陽極與陰極之間，光源4 4的光係透過濾光設備4 5發 射至目標C的主要表面側。 第一實施例中，鎢燈被使用作光源4 4。接著，一些 矽晶6 3的一邊係透過濾光設備4 5由調整射至目標C之 光的波長而控制。以此方式，同大小的矽奈米晶體6 3被 形成以連續地彼此連接。使用：由利用光干擾改變傳送波 長之波長可變濾光器；或由利用由於電場之液晶的反射係 數之改變而改變傳送波長之波長可變濾光器或其類似當作 濾光設備4 5。然而，想要傳送波長可被連續地改變。由 實質上1 : 1使用由混合5 5 w t %氟化氫水溶液與乙 醇獲得之混合液當作電解液B。多孔多晶矽層4包含一些 多晶矽晶粒與一些矽奈米晶體。第一實施例中，濾光設備 4 5與波長控制設備4 6安裝調整自光源射至爲半導體層 之多晶矽層3之光的波長以致於相鄰的矽奈米晶體被形成 以連續地彼此連接之調整機構。 陽極氧化處理步驟已終止後，多孔多晶矽層4係根據 本紙張尺度適用中國國家標準（CNS )八4規格（210X297公釐1 (請先閱讀背面之注意事項再填寫本頁) -26- 564454 A7 B7 五、發明説明（24) (請先閲讀背面之注意事項再填寫本頁) 氧化步驟而氧化。以此方式，由經氧化的多孔多晶矽層構 成之漂流層6被形成，且圖2 C所示之結構被獲得。在氧 化步驟中，多孔多晶矽層4係根據快速加熱技術而氧化， 且包含晶粒5 1 ’矽奈米晶體6 3及氧化矽膜5 2與6 4 之漂流層6被形成。在使用快速加熱技術之氧化步驟中， 燈退火設備被使用。接著，◦ 2氣體在爐的內部被產生。 基底溫度係由預定溫度提升速率（例如，8 0 °C / s e c )自室溫提升至預定的氧化溫度（例如，9 Ο 0 °C )。此 外，基底溫度被維持一預定的氧化時間（例如，一小時） 。快速加熱氧化（R T〇）已因此被實行後，基底溫度被 降至室溫。在第一實施例中，溫度提升速率被設成8 0 °C / s e c。然而，溫度提升速率也許被設成8 0 °C / s e c或更高，且速率最好被設成1 6 Ot/s e c或更 高。 經濟部智慈財產局員工消費合作社印製 漂流層6已被形成後，由金屬膜（第一實施例之C r 膜）構成之第一薄膜層係根據電子光束氣相沈積技術而沈 澱於漂流層6上。進一步，由金屬膜（第一實施例之A u 膜）構成之第二薄膜層係根據電子光束氣相沈積技術而沈 澱於第一薄膜層上。以此方式，由第一薄膜層與第二薄膜 層構成之表面電極7被形成，且圖2D所示之表面電極7 被獲得。第一實施例中，表面電極7係根據電子光束氣相 沈積技術而形成。然而，例如，噴濺技術也許被使用不必 限於電子光束氣相沈積技術當作形成表面電極7的方法。 在此製造方法中，使用了 ：調整自光源射至爲半導體 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -27- 564454 經濟部智慧財產局S(工消費合作社印製 A7 ____B7______ 五、發明説明（25) 層之多晶矽層3之光的波長以致於相鄰的矽奈米晶體被形 成以連續地彼此連接之調整機構。因此，包含在爲多孔半 導體層之多孔多晶矽層4之矽奈米晶體的分佈或大小可被 控制。以此方式，包含在多孔多晶矽層4之矽奈米晶體被 形成以連續地彼此連接。此外，包含在漂流層6之矽奈米 晶體6 3的分佈或大小可被控制。 如圖4所不，砂奈米晶體6 3的分佈或大小可在根據 此製造方法製造之電子源1 〇的漂流層6中是均勻的。此 外’一些各具有爲絕緣膜之氧化矽膜6 4之矽奈米晶體 6 3被形成以分別連續地彼此連接於表面上。結果，根據 第一實施例之電子源1 0中，分散在漂流層6之電子可較 先前技藝的減少。因此，電介質強度與電子發射效率被改 進，且服務壽命被展延。進一步，電子發射特徵的平面中 均勻度可被改進，且較大面積可被獲得。 同時，在此製造方法中，射至爲半導體層之多晶矽層 3之光的波長被適當地控制，藉此在漂流層6的厚度方向 使均勻化矽奈米晶體6 3的大小變可能，如圖4所示。 然而，如圖5所示，光的波長在氧化已開始後根據時 間的經過也許係自長波長邊變成短波長邊。 此例中，如圖6所示，矽奈米晶體6 3的大小可在厚 度方向（圖6的垂直方向）被改變。（圖6中，當多孔多 晶矽層4在自該層的表面之深度方向是較深時，矽奈米晶 體6 3的大小被減少）。 結果，如圖7所示，漂流層6之矽奈米晶體6 3的大 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -28 - 564454 經濟部智慈財產局S工消費合作社印製 A7 B7_五、發明説明（26) 小可在厚度方向被改變。圖7所示之範例中，當漂流層6 自它的表面是較深時，矽奈米晶體6 3的大小（晶粒大小 )被減少。另一方面，當晶粒大小被增加時’矽奈米晶體 6 3間之帶溝被減少。因此，用至氧化矽膜6 4之電場在 漂流層6的表面側稍微大。所以，由於強電場的效應之電 子發射特徵的改進可被預期。圖7中，電子被向上發射。 此外，如圖8之P與Q表示，濾光設備4 5之長波長 側之切除波長與短波長側之切隔波長也許分別在開始陽極 氧化後根據時間的經過被改變。同樣在此例中，如圖6所 示，矽奈米晶體6 3的大小可在厚度方向被改變。結果， 漂流層6之矽奈米晶體6 3的大小可在如圖7所示之厚度 方向被改變。 此外，如圖9所示，在調整射至爲半導體層之多晶矽 層3之光的波長中，射至多晶矽層3之光的波長也許係在 開始陽極氧化後根據時間之改變而改變以致於矽奈米晶體 6 3的晶粒大小在多晶矽層3的厚度方向連續地改變。 由如此做，如圖1 0所示，砂奈米晶體6 3的大小可 在多孔多晶矽層4的厚度方向以良好的控制能力而控制。 以上說明的濾光設備4 5被使用以便改變傳送波長。 然而，由紅外線切除濾光器與紫外線切除濾光器（長帶通 濾光器）構成之光學濾光器也許被使用。由使用此光學濾 光器，由於由無助於使多晶矽層3多孔之紅外線造成之溫 度上升陽極氧化的速率之增加可被限制（僅具有能量大於 矽帶通空隙之光有助於一對電子與電洞的產生，且因此’ ^氏^尺度適用中國國家標準（〇奶）六4規格（210/ 297公釐） (請先閲讀背面之注意事項再填寫本頁) -29- 564454 A7 _B7__ 五、發明説明（27) (請先閲讀背面之注意事項再填寫本頁) 具有能量小於矽帶通空隙之光如紅外線無助於一對電子與 電洞的產生）。此外，自由於紫外線增加之電洞產生量是 可能的，電解拋光發生，且砂奈米晶體6 3的分佈與大小 的偏離發生。因此，包含在多孔多晶矽層4之矽奈米晶體 6 3的分佈與大小被輕易地控制。也就是，在低能量成分 如紅外線被包括在射至多晶矽層3之光之例子中，此成分 無助於使該層多孔，且造成電解液B或目標C之溫度上升 。因此，多晶矽層3的晶粒場之蝕刻速率增加，且多孔多 晶矽層4的多孔結構被做的非均勻。此外，在高能量成分 如紫外線被包括之例子中，蝕刻速率增加，控制多孔多晶 矽層4的多孔結構變困難。爲克服此困難，紅外線與紫外 線被切除以致於僅有助於使該層多孔之光被發射，藉此多 孔多晶矽層4的多孔結構可被固定地獲得。此外，濾光設 備4 5也許在紅外線切除濾光器與紫外線切除濾光器的其 中之一被建構。 經濟部智慈財產局員工消費合作社印製 上述範例中，鎢燈被用作光源4 4。然而單色光（例 如，雷射）的光源可被用作光源4 4，藉此大小的矽奈米 晶體6 3係連續地彼此連接之多孔多晶矽層4可被固定地 形成。接著，光的波長係在陽極氧化已開始後根據時間的 經過而改變，藉此矽奈米晶體6 3的大小可在多孔多晶矽 層4的厚度方向被改變。此外，光係間歇地自光源4 4射 至多晶矽層3，藉此目標C或電解液B的溫度上升可被限 制。在此例中，多孔多晶矽層4之矽奈米晶體6 3的分佈 與大小被輕易地控制。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29<7公釐） -30- 564454 A 7 B7 五、發明説明（28) (第二實施例） 以下，本發明的第二實施例將於下說明。同樣在第二 實施例中，電子源係由利用陽極氧化處理而製造。然而在 第二實施例中，使用由I τ〇膜構成之電子導電層被提供 在由坡璃基底（例如，石英玻璃基底）構成之絕緣基底的 一表面上之基底當作電子導電基底。 如圖1 1所示，根據二實施例之電子源1 〇，由氧化 多孔多晶矽層構成之漂流層6被形成於絕緣基底1 1之電 子導電層1 2上。表面電極7被形成於漂流層6上。在第 二實施例中，電子導電層1 2使下電極成形。所以，同樣 在第二實施例中，表面電極7係相對於下電極，且漂流層 6係介於下電極與表面電極7之間。表面電極7的建構類 似於根據第一實施例的。 自根據第二實施例之電子源1〇發射電子之程序基本 上是類似於第一實施例的。然而，直流電壓V p s被應用 於表面電極7與電子導電層1 2間以致於表面電極7在電 子導電層1 2有關之極性（高電位）上變成正的。同樣在 根據第二實施例之電子源1 0中，電子可以與第一實施例 的相同的方式發射。此外，根據第二實施例之電子源1 0 的漂流層6的電子發射機制與結構是類似於根據第一實施 例的（參考圖4 )。 在根據第二實施例之電子源1 〇被利用作顯示器的電 子源之例子中，下電極或表面電極7與其類似也許被型樣 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 、言 經濟部智慧財產局肖工消費合作社印製 -31 - 564454 A7 B7 經濟部智恁財產局員工消費合作社印製 五、發明説明（29) 〇 以下’將參考圖1 2 A至1 2 D說明製造根據第二實 施例之電子源1 〇的方法。 首先，絕緣基底1 1的一表面上，由I T ◦膜構成之 電子導電層1 2係根據噴濺技術形成，且電子導電基底被 製造。接著，在電子導電基底的主要表面側（在電子導電 層1 2上），非經摻雜的多晶矽層3被形成作半導體層， 且圖1 2 A所示之結構被獲得。例如，可使用c V D技術 ’噴濺技術，或C G S技術或其類似當作形成多晶矽層3 的方法。 在非經摻雜的多晶矽層3已被形成後，多晶矽層3係 根據陽極氧化處理步驟做成多孔。以此方式，爲多孔半導 體層之多孔多晶矽層4被形成，且圖1 2所示之結構被獲 得。 圖1 3所示之陽極氧化設備係在陽極氧化處理步驟中 使用。圖1 3所示之陽極氧化設備的基本建構實質上是一 致於根據第一實施例之陽極氧化設備（參考圖1 )。然而 下列重點是不同的。也就是，光源4 7被裝在目標C的背 面。此外，能夠改變光的波長之濾光設備4 8被裝在光源 4 7與目標C的背面之間。 然而，光源4 7是類似於裝在目標C的表面側上之光 源4 4。此外，濾光設備4 8是類似於裝在目標C的表面 側上之濾光設備4 5。即，第二實施例的陽極氧化步驟中 ，光係自目標C的厚度方向之兩側發射。此外，波長控制 本紙張尺度適用中.國國家標準（cns ) A4規格（2丨〇'〆297公釐） (請先閱讀背面之注意事項再填寫本頁) 一裝· 訂 -32 - 564454 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（30) 設備4 6各控制濾光設備4 5與4 8以致於濾光設備4 5 與4 8的傳送波長彼此一致。 所以，如已在第一實施例中說明，在濾光設備4 5的 傳送波長已在陽極氧化已開始後根據時間的經過而改變之 例子中，濾光設備4 8的傳送波長同樣地在陽極氧化已開 始後根據時間的經過而改變。第二實施例中，鉑電極4 2 被用作陰極，爲下電極之電子導電層1 2被用作陽極，且 電源被供應於陽極與陰極間，藉此多孔多晶矽層4被形成 〇 同時，上述第一實施例中，自多晶矽層3的多晶面的 表面側之光係自光源4 4射至爲半導體層之多晶矽層3， 且因此，電洞可在多晶矽層3的表面側上被有效地供應。 然而，當多晶矽層3被做成更多孔時，帶通空隙增加。因 此，較大的能量被要求該層做成更多孔。也就是，需要減 少光的波長。當光的波長被減少，光害被減少。 然而，在第二實施例的陽極氧化設備中，光分別係自 多晶矽層3的厚度方向之兩側發射，因此輕易地使多晶矽 層3多孔。也就是，第二實施例的陽極氧化設備中，電洞 可在多晶矽層3的表面側上（多晶矽層的表面與相對於該 表面之表面）被有效地供應。因此甚至在多晶矽層3的厚 度稍微大的例子中，這可輕易地被處理。當分別自多晶矽 層3的厚度方向之兩側發射之光的波長同時被改變，包含 在多孔多晶矽層4之矽奈米晶體6 3的大小在多孔多晶矽 層4的厚度方向中可是均勻的。 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） (請先閲讀背面之注意事項再填寫本頁) -33- 564454 A7 B7 五、發明説明（31) (請先閲讀背面之注意事項再填寫本頁) 在此陽極氧化處理步驟已被終止後，多孔多晶矽層4 係根據氧化步驟而氧化。以此方式，由經氧化的多孔多晶 矽層構成之漂流層6被形成，且圖1 2 C所示之結構被獲 得。在氧化步驟中，多孔多晶矽層4係根據快速加熱技術 氧化，且由上述晶粒5 1，矽奈米晶體6 3，及氧化矽膜 5 2與6 4構成之漂流層6被形成。在使用快速加熱技術 之氧化步驟中，如第一實施例的例子，燈退火設備被使用 。此氧化步驟中之操作條件如大氣或溫度是類似於第一實 施例的。 經濟部智慧財產局B(工消費合作社印製 漂流層6已被形成後，由金屬膜（第二實施例之C r 膜）構成之第一薄膜層係根據電子光束氣相沈積技術而沈 澱於漂流層6上。進一步，由金屬膜（第二實施例之A u 膜）構成之第二薄膜層係根據電子光束氣相沈積技術而沈 澱於第一薄膜層上。以此方式，由第一薄膜層與第二薄膜 層構成之表面電極7被形成，且圖1 2 D所示之電子源 1 0被獲得。第二實施例中，表面電極7係根據電子光束 氣相沈積技術形成。然而，例如，噴濺技術也許被使用作 形成表面電極7的方法不需限於電子光束氣相沈積技術。 以此方式，由於製造根據第二實施例之電子源1 0的 方法，如第一實施例的例子，包含在爲多孔半導體層之多 孔多晶矽層4之矽奈米晶體的分佈與大小可被控制。此外 ，矽奈米晶體被分佈以彼此連續地連接之多孔多晶矽層4 可被形成。以此方式，包含在漂流層6之矽奈米晶體6 3 的分佈或大小可被控制。結果，同樣地根據第二實施例之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -34- 564454 Α7 Β7 經濟部智慈財產局員工消費合作社印製 五、發明説明（32) 電子源1 0中，如在第一實施例’漂流層6之電子分散可 較先前技藝減少。此外，電介質強度與電子發射效率被改 進。進一步，電子源1 〇的服務壽命被展延，且電子發射 特徵的平面中均勻度被改進，藉此較大面積可被獲得。 同時，第一與第二實施例中，漂流層6係經氧化的多 孔多晶矽層構成的。然而，漂流層6也許係由氮多孔多晶 矽層與氮氧多孔多晶矽層構成的。另外，以另一技術，漂 流層也許係由經氧化的，氮或氮氧多孔半導體層構成。 在漂流層6是氮化多孔多晶矽層之例子中，例如，由 利用，例如，N Η 3氣體如第一與第二實施例中根據設定 溫度上升速率之快速加熱技術實行氮化的氮化步驟取代利 用〇2氣體根據快速加熱技術氧化多孔多晶矽層4的氧化 步驟。此例中，圖4說明之氧化矽膜5 2與6 4的其中之 一被獲得作氮化矽膜。在漂流層6是氮氧化多孔多晶矽層 之例子中，由利用Ν Η 3氣體與〇2氣體的混合氣體或另 一 Ν 2 ◦氣體也許被使用如第一與第二實施例中根據設定 溫度上升速率之快速加熱技術氮氧化的氮氧化步驟取代根 據快速加熱技術氧化多孔多晶矽層4的步驟。此例中，關 於圖4說明之氧化矽膜5 2與6 4都被獲得作氮氧化矽膜 〇 此外，在根據第一與第二實施例製造電子源的方法中 ，爲絕緣膜之氧化矽膜6 4係由利用快速加熱技術形成。 然而，氧化矽膜6 4也許係根據電化法形成。在此例中， 例如，包含電解液（如1莫耳的Η 2 S〇4，1莫耳的 / (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -35- 564454 A7 B7 五、發明説明（33) (請先閱讀背面之注意事項再填寫本頁) Η N〇3，或王水，例如）之氧化處理容器被運用。接著 ，鉑電極（未顯示）被用作負極，且下電極被作用正極（ 在第一實施例中具有在η型矽基底上形成之歐姆電極2之 η型矽基底與第二實施例中之電子導電層1 2 )，且多孔 多晶矽層4係由供應固定電流而氧化，藉此包含晶粒5 1 ，矽奈米晶體6 3及氧化矽膜5 2與6 4之漂流層6被形 成。根據電化法形成之絕緣膜也許被用作氮化膜如氮化矽 膜。 此外，第一與第二實施例中，一對電極係由表面電極 7與下電極構成的，且漂流層6係介於該對電極之間，藉 此使電子經過之電子經遊層（electron travel layer )成形 ο (第三實施例） 經濟部智慧財產局員工消費合作社印製 以下，將說明本發明的第三實施例。第三實施例中， 利用陽極氧化處理形成之記憶體元件將被說明。根據第三 實施例之記憶體元件有如圖1 4所示之基本建構。也就是 ，儲存層1 0 1被形成於形成絕緣層1 〇 〇 b於電子導電 層1 00 a上之基底1 00上。儲存層1 0 1係由使用於 第一與第二實施例說明之陽極氧化設備形成。儲存層 1 〇 1中，有連續地連接爲一些具有能夠密閉載體之奈米 級半導體奈.米晶體之矽奈米晶體6 3，結晶係覆蓋爲絕緣 膜之氧化砂膜6 4。儲存層1 0 1之一些砂奈米晶體6 3 的晶粒大小是彼此一致的。氧化矽膜6 4的膜厚度小於矽 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -36- 564454 A7 B7 五、發明説明（34) 奈米晶體6 3的晶粒大小。 (請先閲讀背面之注意事項再填寫本頁) 儲存層101有如圖15所示之帶通結構。也就是， 儲存層1 0 1有大量夾於S i〇X (氧化矽膜6 4 )間之 S i之井結構。氧化矽膜6 4間之帶通空隙大約是5 e V至1 〇 e V。矽奈米晶體6 3間之帶通空隙大約是 2 e V至3 e V。已知表體間之帶通空隙大約是 1.1 e V且奈米晶體間之帶通空隙展延大約2 e V 至 3 e V。 第三實施例中，儲存層1 〇 1中，矽奈米晶體6 3係 夾於氧化砂膜6 4的阻障（barrier )間。因此，儲存資訊 之記憶功能可由密閉載體於矽奈米晶體6 3 (由儲存電荷 )而達成。如先前已說明，矽奈米晶體6 3間之帶通空隙 比表體大。因此，例如，在薄膜長晶期間形成之矽奈米晶 體的例子中，矽奈米晶體於表體中被分離地存在，因此使 密閉載體於矽奈米晶體變困難。反之，在第三實施例中’ 覆與氧化矽膜6 4之矽奈米晶體6 3係彼此連續地連接而 形成，因此使密閉載體於矽奈米晶體6 3變可能。 經濟部智慈財產局員工消費合作社印製 根據第三實施例之記憶體元件包括由密閉載體於覆與 爲絕緣膜之氧化矽膜6 4之奈米級矽奈米晶體6 3而儲存 資訊之儲存層1 0 1，該結晶係能夠密閉載體（由儲存電 荷）。電荷係儲存於奈米級矽奈米晶體6 3，且因此’較 利用習知半導體積體電路技術之半導體記憶體之小尺寸且 低成本且大容量的記憶體元件可被達成。 儲存層1 0 1中，寫入係由寫入機構（未顯不）實行 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -37- 564454 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（35) 。在儲存層1 0 1的單位區域中，載體可被密閉在多個矽 奈米晶體6 3中，藉此該載體可由寫入機構被密閉於多個 矽奈米晶體6 3中。另一方面，儲存層1 0. 1根據密閉於 載體之矽奈米晶體6 3的數目儲存多重値之資訊，藉此多 重値之資訊可被儲存於儲存層1 0 1中。 也許使用由，例如，發光而實行寫入儲存層1 0 1之 機構當作寫入機構。如果該寫入機構被設計以由改變光的 波長而控制大量儲存於儲存層1 0 1之電荷，射至儲存層 1 0 1之光的波長被改變，藉此光#進入儲存層1 0 1的 深度可被控制。如光的波長增加，載體可被密閉於儲存層 1 0 1更深區域之矽奈米晶體6 3中。此外，載體可被密 閉於較大晶粒大小之矽晶。如光的波長被減少，載體可被 密閉於儲存層1 0 1更淺區域之矽奈米晶體6 3中。此外 ，載體可被密閉於較小晶粒大小之矽晶。因此，密閉於載 體之矽奈米晶體6 3的數目可被控制，且大量儲存於儲存 層1 0 1之電荷可被控制。此外，如果寫入機構被設計以 由改變光的強度控制儲存於儲存層1 0 1之電荷的量，密 閉載體之矽奈米晶體6 3的數目可由改變射至儲存層 1 0 1之光的強度所控制，且儲存於儲存層1 0 1之電荷 的數目可被控制。 也許使用電子實行寫入儲存層101之機構當作寫入 機構。在此例中，如果儲存於儲存層1 0 1之電荷的數量 係由改變應用至儲存層1 0 1之電壓所控制，多重値之資 訊可被電子寫入儲存層1 0 1。 本纸張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐) ~ -38- (請先閲讀背面之注意事項再填寫本頁)-17- 564454 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (15) Anodizing equipment for forming a porous semiconductor layer including semiconductor nanocrystals according to anodization when the fluid layer is formed; and An insulating film forming device having an insulating film on the surface of each semiconductor nanocrystal. Here, the anodizing apparatus is designed to perform anodizing while emitting light having a wavelength substantially including a visible light region related to the semiconductor layer. According to this electron source manufacturing apparatus, the distribution or size of semiconductor nanocrystals contained in the porous semiconductor layer can be controlled. In this manner, a porous semiconductor layer in which some semiconductor nanocrystals are distributed to be continuously connected to each other can be formed. Brief Description of the Drawings The present invention will be fully understood from the accompanying drawings and detailed description of the invention. Similar elements that are common in the figures are indicated by similar reference numbers. FIG. 1 is a diagram describing a general configuration of an anodizing apparatus used as a manufacturing electron source according to the first embodiment; FIGS. 2A to 2D are each showing an electron source or its main steps in a process of manufacturing an electron source; Sectional view of the material; Figure 3 is a diagram illustrating the operation of an electron source; Figure 4 is a diagram illustrating the electron emission operation of the electron source; Figure 5 is a graph showing the elapsed time and light wavelength of the anodizing process step for manufacturing the electron source Fig. 6 is a diagram showing an example of a method of manufacturing an electron source; Fig. 7 is a diagram showing an example of a method of manufacturing an electron source; and Fig. 8 is a time describing an anodizing process step of a process of manufacturing an electron source The relationship between the process and the cut-off wavelength; (Please read the precautions on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -18- 564454 A7 B7 Ministry of Economic Affairs wisdom Property Bureau 8 Industrial and Consumer Cooperative Seals 5. V. INTRODUCTION TO THE INVENTION (16) FIG. 9 is a graph describing the relationship between the elapse of time and the wavelength of the light in the anodizing step of the process of manufacturing an electron source; FIG. 1 0 is a diagram showing an example of a method of manufacturing an electron source; FIG. 11 is a diagram showing an operation of an electron source according to a second embodiment; FIGS. 12A to 12D are main steps in each process of manufacturing an electron source. A cross-sectional view of an electron source or its material; FIG. 13 is a diagram showing a general construction of an anodizing apparatus used for manufacturing an electron source; FIG. 14 is a view showing a general construction of a memory element according to a third embodiment FIG. 15 is a band diagram of a memory element; FIG. 16 is a diagram showing another exemplary structure of the memory element; FIG. 17 is a diagram showing an application example of the memory element; The fourth embodiment is a schematic diagram of the general construction of an anodizing device for manufacturing an electron source; FIG. 19 is a diagram showing the electron emission characteristics according to the tenth embodiment; FIG. 20 is a diagram showing the electron emission according to the eleventh embodiment Fig. 9 of characteristics Fig. 21 is a diagram showing the electron emission characteristics according to the twelfth embodiment Fig. 2 is a diagram showing the electron emission characteristics according to the thirteenth embodiment Fig. 2 is a diagram showing the electron emission characteristics according to the tenth to thirteenth Electron emission characteristics of the embodiment (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 specifications (2) OX297 mm -19- 564454 A7 B7 Intellectual Property Bureau of the Ministry of Economic Affairsg (Printed by the Industrial and Consumer Cooperatives. 5. Description of the invention (17). FIG. 24 is a diagram showing the electron emission characteristics according to the fourteenth embodiment. FIG. 25 is a diagram showing the electron emission characteristics of an electron source according to a comparative example. Is a diagram showing the operation of a conventional electron source; FIG. 27 is a diagram showing the operation of a conventional electron emission device; FIG. 28 is a diagram showing the operation of another conventional electron source; FIG. 29 is shown in FIG. 26 Diagram of the general construction of the basic part of the electron source; Comparison table of main components 1 〇 / electron source 6 drift layer 1 η-type silicon substrate 7 surface electrode 2 ohmic electrode 3 semiconductor layer 2 1 collector electrode 5 1 cylindrical polycrystalline silicon particles 5 2 Thin silicon oxide film 6 3 Silicon nanocrystals 6 4 Silicon oxide film 1 1 Insulating substrate 1 2 Conductive layer This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling in this ) -20- 564454 A7 B7 V. Description of the invention (18) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 1 〇 Electron source 6 Drift layer 4 Porous polycrystalline silicon layer 4 1 Processing container 4 2 Cathode B Electrolyte C Standard 4 3 Voltage Source 4 4 Light source 4 5 Filtering device 4 6 Wavelength control device 4 7 Light source 4 8 Filtering device 1 〇0 Substrate 1 0 0 a Electronic conductive layer 1 〇Ob Insulation layer 1 〇1 Storage layer 1 5 Probe 1 0 0 c Silicon layer D Drain S Source 6 Oxidation film 7 0 Smell electrode (please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X 297 mm)- 21-564454A7B7 Printed by the 8th Industrial Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (19) Detailed description of the preferred embodiment (first embodiment) In the first embodiment, the electron source is manufactured by anodizing. In the electron source according to the first embodiment, the resistivity is slightly closer to that of the conductor (for example, a (1 0 0) substrate having a resistivity of about 0 .. 0 1 Ω / cm to 0.02 Ω / cm ) A single crystal n-type silicon substrate is used as the electronic conductive substrate. As shown in FIG. 3, according to the electron source 10 of the first embodiment, a drift layer 6 composed of an oxidized porous polycrystalline silicon layer is formed on a main surface of an n-type silicon substrate 1 which is a conductive substrate. A surface electrode 7 is formed on the drift layer 6. The ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. In the first embodiment, the lower electrode is composed of an n-type silicon substrate 1 and an ohmic electrode 2. Therefore, the surface electrode 7 is opposite to the lower electrode, and the drift layer 6 is interposed between the lower electrode and the surface electrode 7. The porous polycrystalline silicon layer forms a porous semiconductor layer. A material having a small work function is used as a material of the surface electrode 7. The thickness of the surface electrode 7 is set to 10 nm. However, this thickness may be so thick that the electrons that can pass through the drift layer 6 can be tunneled without being limited to 100 nm. The thickness of the surface electrode 7 may be set to approximately 10 nm to 15 nm. The composition of the surface electrode 7 includes: a first thin film layer formed of a metal film (for example, a Cr film) formed on the drift layer 6; and A second thin film layer composed of a metal film (for example, an Au film) deposited on the first thin film layer. For example, use materials with high intimacy with the drift layer 6 such as chromium, nickel, and platinum (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)- 22- 564454 A7 B7___ V. Description of the invention (20) (Read the precautions on the back before filling this page), titanium or indium as the material of the first thin film layer on the drift layer 6 'This material can avoid the second Diffusion between the thin film layer and the drift layer 6. As the second thin film layer, gold having a low resistance and a high stability over time is used. In the embodiment, C r is used as the material of the first thin film layer. The thickness of the first thin film layer was set to 2 nm. Au is used as the material of the second thin film layer. The thickness of the second thin film layer was set to 8 n m. In the first embodiment, the surface electrode 7 is composed of two metal films. However, the electrode may be composed of one or three or more metal films. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the electron source 10 shown in FIG. 3, the surface electrode 7 is deposited in a vacuum, and the collector electrode 21 is deposited on the opposite side of the surface electrode 7. Next, the DC voltage Vp s is adopted so that the surface electrode 7 is positive in polarity with respect to the n-type silicon substrate 1 (ohmic electrode 2). Further, the DC voltage V c is adopted so that the collector electrode 21 is positive in polarity with respect to the surface electrode 7. In this way, the electrons injected from the n-type silicon substrate 1 drift in the drift layer 6 and are emitted through the surface electrode 7 (the single-dot chain shown in FIG. 3 indicates the electrons emitted through the surface electrode 7, e-〃). As explained earlier, the current flowing between the surface electrode 7 and the n-type silicon substrate (ohmic electrode 2) is called the diode current I ps, and the current flowing between the collector electrode 21 and the surface electrode 7 is called Is the emission current (emission electron flow) I e. As the ratio of the emission current I e to the diode current I p s increases, the electron emission efficiency increases. As shown in FIG. 4, the drift layer 6 of the first embodiment is composed of at least one cylindrical polycrystalline silicon particle 5 1; a thin oxide sand film 5 2 formed on the surface of the crystal grain 51; Some of the nano-sized silicon nanocrystalline paper sizes are applicable to the Chinese National Standard (CNS) A4 specifications (210X297 mm)---- -23- 564454 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. DESCRIPTION OF THE INVENTION (21) a body 6 3; and some silicon oxide films 64, which are insulating films formed on the surface of each silicon nanocrystal 63, which have a grain size smaller than that of the silicon nanocrystal 63. Film thickness. In short, in the drift layer 6, the surface of each crystal grain 51 is made porous, and the crystalline state is maintained at the center portion of each crystal grain 51. The thickness of the silicon oxide film 64 formed on the surface of the silicon nanocrystal 6 3 is set to the extent of the average free diameter of the electrons (the average free diameter of the electrons of Si 102 is known to be 3 nm), and it is required to be set to Approximately 1 nm to 3 nm. The grain size of the silicon nanocrystal 63 is smaller than the average free diameter. In the electron source 10 according to the first embodiment, electron emission occurs in the following modes. That is, the DC voltage V p s is adopted so that the polarity of the surface electrode 7 between the surface electrode 7 exposed to the vacuum and the n-type silicon substrate 1 (ohmic electrode 2) is positive. In addition, the DC voltage V c is adopted so that the polarity of the collector electrode 21 between the collector electrode 21 and the surface electrode 7 is positive. When the DC voltage V p s reaches a predetermined value (determined value), the electrons > e " are thermally excited from the n-type silicon substrate 1 serving as the lower electrode and injected into the drift layer 6. On the other hand, most of the electric field applied to the drift layer 6 is applied to the silicon oxide film 64. Therefore, the injected electrons > e 〃 are accelerated by a strong electric field applied to the silicon oxide film 64. Next, the electrons drift inside the region between the grains 51 of the drift layer 6 toward the surface in the direction indicated by the arrow A in FIG. 4, and are emitted in a vacuum after being tunneled through the surface electrode 7. Therefore, in the drift layer 6, electrons injected from the n-type silicon substrate 1 are accelerated and drift to the inside of the strong electric field applied to the silicon oxide film 64, and are hardly dispersed by the silicon nanocrystals 63. Then, the electrons are emitted through the surface electrode 7 (impact electrons (please read the precautions on the back before filling this page). This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -24-564454 A7 B7 V. Invention Description (22) (Please read the precautions on the back before filling this page) Emission phenomenon). In addition, the heat generated by the drift layer 6 is dissipated through the crystal grains 51. Therefore, the jumping phenomenon does not occur during the electron emission, and the electrons can be fixedly emitted. The electrons that reach the surface of the drift layer 6 are considered to be hot electrons, but are easily tunneled through the surface electrode 7 and are emitted in a vacuum. Hereinafter, a method of manufacturing the electron source 10 according to the first embodiment will be described with reference to Figs. 2A to 2D. First, the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. An undoped polycrystalline silicon layer 3 is formed on the main surface of the n-type silicon substrate 1 as a semiconductor layer. In this way, the structure shown in FIG. 2A is obtained. For example, using CVD technology (such as LPCVD technology, plasma CVD technology, or catalytic CVD technology, for example); sputtering technology or CGS (Continuous Grain Silicon) technology is similar to the method for forming a film of polycrystalline silicon layer 3 Ministry of Economic Affairs After the printed non-doped polycrystalline silicon layer 3 has been formed by the Chi 1 Property Bureau and the 8th Industrial Cooperative, the polycrystalline silicon layer 3 is formed according to the anodizing step. In this manner, a porous polycrystalline silicon layer 4 which is a porous semiconductor layer is formed, and the structure shown in FIG. 2B is obtained. In the first embodiment, although all the polycrystalline silicon layers 3 are made porous, only a part of the layers may be made porous. In the anodizing step, the anodizing apparatus shown in Fig. 1 is used. The anodizing apparatus shown in FIG. 1 includes: a processing container 41 having an electrolytic solution B containing an aqueous hydrogen fluoride solution; and a cathode 42 made of platinum soluble in the electrolytic solution B. Next, when the polycrystalline silicon layer 3 which is a semiconductor layer is formed on the lower electrode (in the first embodiment, the lower electrode is made of η-type silicon basic paper size and applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -25 -^ 564454 A7 _B7___ printed by P Bayong Consumer Cooperative, Intellectual Property Bureau of the Ministry of Economic Affairs, V. Description of the invention (23) The bottom 1 and the ohmic electrode 2) were placed in the processing container 4 1 so that only A part of the surface of the polycrystalline sand layer 3 is in contact with the electrolytic solution B. This anodizing device includes: a voltage source 4 3 for charging the electrode below the anode between the anode and the cathode; a light source 4 4 that emits light to the main surface side of the target C (the surface side of the polycrystalline silicon layer 3); 4 4 and the target C, a filtering device 45, which is a wavelength control device 4 6 capable of changing the light transmission wavelength: a wavelength control device capable of controlling the transmission wavelength of the filtering device 4 5. When anodization is performed and the power supply system is used as the lower electrode of the anode and is supplied between the anode and the cathode, the light of the light source 44 is transmitted through the filtering device 45 to the main surface side of the target C. In the first embodiment, a tungsten lamp is used as the light source 44. Next, one side of some of the silicon crystals 6 3 is a transparent filtering device 45, which is controlled by adjusting the wavelength of the light irradiated to the target C. In this manner, silicon nanocrystals 63 of the same size are formed to be continuously connected to each other. Use: Variable wavelength filter that changes transmission wavelength by using light interference; or variable wavelength filter that changes transmission wavelength by changing reflection coefficient of liquid crystal due to electric field . However, the desired transmission wavelength can be continuously changed. As the electrolytic solution B, a mixed solution obtained by mixing a 55 wt% hydrogen fluoride aqueous solution and ethanol substantially 1: 1 was used. The porous polycrystalline silicon layer 4 includes some polycrystalline silicon grains and some silicon nanocrystals. In the first embodiment, the filter device 45 and the wavelength control device 46 are installed to adjust the wavelength of light emitted from the light source to the polycrystalline silicon layer 3 which is a semiconductor layer so that adjacent silicon nanocrystals are formed to be continuously connected to each other. Adjustment mechanism. After the anodizing step has been terminated, the porous polycrystalline silicon layer 4 is based on the Chinese paper standard (CNS) 8-4 specifications (210X297 mm1) (please read the precautions on the back before filling this page) -26- 564454 A7 B7 V. Description of the invention (24) (Please read the precautions on the back before filling this page) Oxidation step. In this way, the drift layer 6 composed of the oxidized porous polycrystalline silicon layer is formed, as shown in Figure 2C The structure shown is obtained. In the oxidation step, the porous polycrystalline silicon layer 4 is oxidized according to the rapid heating technology, and the drift layer 6 containing the grains 5 1 ′ silicon nanocrystals 6 3 and the silicon oxide films 5 2 and 6 4 is Formation. In the oxidation step using the rapid heating technique, a lamp annealing device is used. Then, 2 gas is generated inside the furnace. The substrate temperature is raised from a predetermined temperature (for example, 80 ° C / sec) from room temperature Raise to a predetermined oxidation temperature (for example, 900 ° C). In addition, the substrate temperature is maintained for a predetermined oxidation time (for example, one hour). After the rapid thermal oxidation (RT0) has been implemented, the substrate The bottom temperature is lowered to room temperature. In the first embodiment, the temperature increase rate is set to 80 ° C / sec. However, the temperature increase rate may be set to 80 ° C / sec or higher, and the rate is the most It can be set to 1 6 Ot / sec or higher. After the drift layer 6 printed by the employee consumer cooperative of the Intellectual Property Office of the Ministry of Economy has been formed, the first thin film composed of a metal film (Cr film of the first embodiment) The layer is deposited on the drift layer 6 according to the electron beam vapor deposition technology. Further, the second thin film layer composed of a metal film (the Au film of the first embodiment) is deposited on the first layer according to the electron beam vapor deposition technology. On a thin film layer. In this way, the surface electrode 7 composed of the first thin film layer and the second thin film layer is formed, and the surface electrode 7 shown in FIG. 2D is obtained. In the first embodiment, the surface electrode 7 is based on It is formed by the electron beam vapor deposition technique. However, for example, the sputtering technique may not be limited to the electron beam vapor deposition technique as a method of forming the surface electrode 7. In this manufacturing method, the adjustment from the light source to Semiconductor The scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -27- 564454 Intellectual Property Bureau of the Ministry of Economic Affairs S (printed by Industrial and Consumer Cooperatives A7 ____B7______ V. Description of the invention (25) Polycrystalline silicon layer 3 light An adjustment mechanism having a wavelength such that adjacent silicon nanocrystals are formed to be continuously connected to each other. Therefore, the distribution or size of the silicon nanocrystals included in the porous polycrystalline silicon layer 4 which is a porous semiconductor layer can be controlled. In this way The silicon nanocrystals included in the porous polycrystalline silicon layer 4 are formed to be continuously connected to each other. In addition, the distribution or size of the silicon nanocrystals 6 3 included in the drift layer 6 can be controlled. As shown in FIG. 4, the distribution or size of the sand nanocrystals 63 can be uniform in the drift layer 6 of the electron source 10 manufactured according to this manufacturing method. In addition, some silicon nanocrystals 63 each having a silicon oxide film 64 as an insulating film are formed so as to be continuously connected to each other on the surface, respectively. As a result, in the electron source 10 according to the first embodiment, the number of electrons dispersed in the drift layer 6 can be reduced as compared with the prior art. As a result, dielectric strength and electron emission efficiency are improved, and service life is extended. Further, the uniformity in the plane of the electron emission feature can be improved, and a larger area can be obtained. At the same time, in this manufacturing method, the wavelength of light emitted to the polycrystalline silicon layer 3 which is a semiconductor layer is appropriately controlled, thereby making it possible to uniformize the size of the silicon nanocrystals 63 in the thickness direction of the drift layer 6, such as Shown in Figure 4. However, as shown in Fig. 5, the wavelength of light may change from a long wavelength side to a short wavelength side according to the passage of time after oxidation has started. In this example, as shown in FIG. 6, the size of the silicon nanocrystal 63 can be changed in the thickness direction (the vertical direction in FIG. 6). (In Fig. 6, when the porous polycrystalline silicon layer 4 is deeper in the depth direction from the surface of the layer, the size of the silicon nanocrystals 63 is reduced). As a result, as shown in FIG. 7, the large paper size of the silicon nanocrystal 6 3 of the drift layer 6 is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) -28-564454 A7 B7 printed by S Industrial Consumer Cooperatives, Intellectual Property Office of the Ministry of Economic Affairs V. Description of Invention (26) Small can be changed in thickness direction. In the example shown in FIG. 7, when the drift layer 6 is deeper from its surface, the size (grain size) of the silicon nanocrystals 63 is reduced. On the other hand, when the grain size is increased, the band gap between the ' silicon nanocrystals 63 is reduced. Therefore, the electric field applied to the silicon oxide film 64 is slightly larger on the surface side of the drift layer 6. Therefore, improvements in electron emission characteristics due to the effect of strong electric fields can be expected. In Figure 7, electrons are emitted upward. In addition, as shown by P and Q in FIG. 8, the cut-off wavelength on the long wavelength side and the cut-off wavelength on the short wavelength side of the filtering device 45 may be changed according to the passage of time after the anodization is started, respectively. Also in this example, as shown in FIG. 6, the size of the silicon nanocrystal 63 can be changed in the thickness direction. As a result, the size of the silicon nanocrystal 63 of the drift layer 6 can be changed in the thickness direction as shown in FIG. In addition, as shown in FIG. 9, in adjusting the wavelength of light emitted to the polycrystalline silicon layer 3 which is a semiconductor layer, the wavelength of the light incident to the polycrystalline silicon layer 3 may be changed according to time after the anodization is started so that the silicon The grain size of the nanocrystal 63 is continuously changed in the thickness direction of the polycrystalline silicon layer 3. By doing so, as shown in FIG. 10, the size of the sand nanocrystals 63 can be controlled in the thickness direction of the porous polycrystalline silicon layer 4 with good control ability. The filter device 45 described above is used in order to change the transmission wavelength. However, an optical filter composed of an infrared cut filter and an ultraviolet cut filter (long-band pass filter) may be used. By using this optical filter, the increase in the rate of anodization due to the temperature rise caused by infrared rays that do not help to make the polycrystalline silicon layer 3 porous can be limited (only light with energy greater than the silicon band-pass gap helps a pair of electrons And the generation of holes, and therefore the '^' ^ standard applies to the Chinese National Standard (〇 奶) 6 4 specifications (210/297 mm) (Please read the precautions on the back before filling this page) -29- 564454 A7 _B7__ V. Description of the invention (27) (Please read the precautions on the back before filling out this page) Light with energy less than the silicon band-pass gap, such as infrared, does not help the generation of a pair of electrons and holes). In addition, it is possible to generate the amount of holes free from the increase in ultraviolet rays, electrolytic polishing occurs, and deviations in the distribution and size of the sand nanocrystals 63 occur. Therefore, the distribution and size of the silicon nanocrystals 63 included in the porous polycrystalline silicon layer 4 can be easily controlled. That is, in the case where a low-energy component such as infrared rays is included in the light irradiated to the polycrystalline silicon layer 3, this component does not help make the layer porous, and causes the temperature of the electrolytic solution B or the target C to rise. Therefore, the etching rate of the grain field of the polycrystalline silicon layer 3 is increased, and the porous structure of the porous polycrystalline silicon layer 4 is made non-uniform. Further, in the case where high-energy components such as ultraviolet rays are included, the etching rate is increased, and it becomes difficult to control the porous structure of the porous polycrystalline silicon layer 4. To overcome this difficulty, the infrared and ultraviolet rays are cut off so that only the light that makes the layer porous is emitted, whereby the porous structure of the porous polycrystalline silicon layer 4 can be fixedly obtained. In addition, the filtering device 45 may be constructed in one of an infrared cut filter and an ultraviolet cut filter. Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs In the above example, tungsten lamps were used as the light source 4 4. However, a light source of monochromatic light (e.g., laser) can be used as the light source 4 4, whereby the silicon nanocrystals 6 3 of the size are porous polycrystalline silicon layers 4 continuously connected to each other and can be fixedly formed. Next, the wavelength of light is changed according to the passage of time after anodization has started, whereby the size of the silicon nanocrystals 63 can be changed in the thickness direction of the porous polycrystalline silicon layer 4. In addition, the light is intermittently emitted from the light source 44 to the polycrystalline silicon layer 3, whereby the temperature rise of the target C or the electrolytic solution B can be restricted. In this example, the distribution and size of the silicon nanocrystals 63 of the porous polycrystalline silicon layer 4 are easily controlled. This paper size applies to China National Standard (CNS) A4 (210X29 < 7 mm) -30- 564454 A 7 B7 V. Description of the Invention (28) (Second Embodiment) Hereinafter, a second embodiment of the present invention will be described below. Also in the second embodiment, the electron source is manufactured by using an anodizing treatment. However, in the second embodiment, a substrate provided on one surface of an insulating substrate composed of a sloped glass substrate (for example, a quartz glass substrate) using an electronic conductive layer composed of an I τ film is used as the electronic conductive substrate. As shown in FIG. 11, according to the electron source 10 of the second embodiment, a drift layer 6 composed of an oxidized porous polycrystalline silicon layer is formed on the electronic conductive layer 12 of the insulating substrate 11. A surface electrode 7 is formed on the drift layer 6. In the second embodiment, the electron conductive layer 12 shapes the lower electrode. Therefore, also in the second embodiment, the surface electrode 7 is opposite to the lower electrode, and the drift layer 6 is interposed between the lower electrode and the surface electrode 7. The construction of the surface electrode 7 is similar to that according to the first embodiment. The procedure for emitting electrons from the electron source 10 according to the second embodiment is basically similar to that of the first embodiment. However, the DC voltage V p s is applied between the surface electrode 7 and the electronic conductive layer 12 so that the surface electrode 7 becomes positive on the polarity (high potential) related to the electronic conductive layer 12. Also in the electron source 10 according to the second embodiment, electrons can be emitted in the same manner as in the first embodiment. In addition, the electron emission mechanism and structure of the drift layer 6 of the electron source 10 according to the second embodiment is similar to that according to the first embodiment (refer to FIG. 4). In the example in which the electron source 10 according to the second embodiment is used as the electron source of the display, the lower electrode or the surface electrode 7 is similar to that of the sample paper, and the size of the paper may be in accordance with the Chinese National Standard (CNS) A4 (210X297 mm). (Please read the precautions on the back before filling out this page.) Printed by Xiao Gong Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy-31-564454 A7 B7 Printed by Consumer Cooperative of Employees of Intellectual Property Bureau of Ministry of Economy 〇 Hereinafter, a method of manufacturing the electron source 10 according to the second embodiment will be described with reference to FIGS. 12A to 12D. First, on one surface of the insulating substrate 11, an electronic conductive layer 12 made of an IT film is formed according to a sputtering technique, and an electronic conductive substrate is manufactured. Next, on the main surface side of the electronically conductive substrate (on the electronically conductive layer 12), an undoped polycrystalline silicon layer 3 is formed as a semiconductor layer, and the structure shown in FIG. 12A is obtained. For example, c V D technology 'sputtering technology, or C G S technology or the like can be used as a method for forming the polycrystalline silicon layer 3. After the undoped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous according to the anodizing step. In this manner, a porous polycrystalline silicon layer 4 which is a porous semiconductor layer is formed, and the structure shown in Fig. 12 is obtained. The anodizing equipment shown in Fig. 13 is used in the anodizing step. The basic configuration of the anodizing apparatus shown in Fig. 13 is substantially the same as that of the anodizing apparatus according to the first embodiment (refer to Fig. 1). However, the following points are different. That is, the light source 47 is mounted on the back of the target C. In addition, a filter device 48 capable of changing the wavelength of light is installed between the light source 47 and the back surface of the target C. However, the light source 47 is similar to the light source 4 4 mounted on the surface side of the target C. In addition, the filter device 48 is similar to the filter device 45 installed on the surface side of the target C. That is, in the anodizing step of the second embodiment, light is emitted from both sides in the thickness direction of the target C. In addition, the wavelength control of this paper is applicable in China. National Standard (cns) A4 specification (2 丨 〇'〆297mm) (Please read the precautions on the back before filling this page) One Pack · Order -32-564454 Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau A7 B7 V. Invention Description (30) Equipment 4 6 Controls filter equipment 4 5 and 4 8 so that the transmission wavelengths of filter equipment 4 5 and 4 8 are consistent with each other. Therefore, as described in the first embodiment, in the example where the transmission wavelength of the filter device 45 has changed according to the passage of time after the anodization has started, the transmission wavelength of the filter device 48 is also at the anode. After oxidation has started, it changes according to the passage of time. In the second embodiment, a platinum electrode 4 2 is used as a cathode, an electronic conductive layer 12 as a lower electrode is used as an anode, and a power source is supplied between the anode and the cathode, whereby a porous polycrystalline silicon layer 4 is formed. At the same time, In the above-mentioned first embodiment, the light from the surface side of the polycrystalline silicon layer 3 of the polycrystalline silicon layer 3 is emitted from the light source 44 to the polycrystalline silicon layer 3 which is a semiconductor layer, and therefore, holes can be formed on the surface side of the polycrystalline silicon layer 3 Supply effectively. However, when the polycrystalline silicon layer 3 is made more holes, the band-pass gap increases. Therefore, greater energy is required to make the layer more porous. That is, it is necessary to reduce the wavelength of light. When the wavelength of light is reduced, light damage is reduced. However, in the anodizing apparatus of the second embodiment, light is emitted from both sides in the thickness direction of the polycrystalline silicon layer 3, so that the polycrystalline silicon layer 3 is easily made porous. That is, in the anodizing apparatus of the second embodiment, holes can be efficiently supplied on the surface side of the polycrystalline silicon layer 3 (the surface of the polycrystalline silicon layer and the surface opposite to the surface). Therefore, even in the case where the thickness of the polycrystalline silicon layer 3 is slightly larger, this can be easily handled. When the wavelengths of the light emitted from both sides of the polycrystalline silicon layer 3 in the thickness direction are simultaneously changed, the size of the silicon nanocrystals 6 3 contained in the porous polycrystalline silicon layer 4 may be uniform in the thickness direction of the porous polycrystalline silicon layer 4. This paper size applies to Chinese National Standard (CNS) A4 specifications (2 丨 0X297 mm) (Please read the precautions on the back before filling this page) -33- 564454 A7 B7 V. Description of the invention (31) (Please read the back first (Notes on this page, please fill in this page)) After this anodizing step has been terminated, the porous polycrystalline silicon layer 4 is oxidized according to the oxidation step. In this way, a drift layer 6 composed of an oxidized porous polycrystalline silicon layer is formed, and the structure shown in Fig. 12C is obtained. In the oxidation step, the porous polycrystalline silicon layer 4 is oxidized according to a rapid heating technique, and a drift layer 6 composed of the above-mentioned grains 51, silicon nanocrystals 6 3, and silicon oxide films 5 2 and 64 is formed. In the oxidation step using the rapid heating technique, as in the example of the first embodiment, a lamp annealing apparatus is used. Operating conditions such as atmosphere or temperature in this oxidation step are similar to those of the first embodiment. After the intellectual property bureau B of the Ministry of Economy B (industrial and consumer cooperative printing drift layer 6 has been formed, the first thin film layer composed of a metal film (the Cr film of the second embodiment) is deposited on the basis of the electron beam vapor deposition technology On the drift layer 6. Further, a second thin film layer composed of a metal film (Au film of the second embodiment) is deposited on the first thin film layer according to an electron beam vapor deposition technique. In this way, the first thin film layer A surface electrode 7 composed of a thin film layer and a second thin film layer is formed, and an electron source 10 shown in FIG. 12D is obtained. In the second embodiment, the surface electrode 7 is formed according to an electron beam vapor deposition technique. However, For example, the sputtering technique may be used as the method of forming the surface electrode 7 without being limited to the electron beam vapor deposition technique. In this way, since the method of manufacturing the electron source 10 according to the second embodiment is as in the first embodiment For example, the distribution and size of the silicon nanocrystals included in the porous polycrystalline silicon layer 4 which is a porous semiconductor layer can be controlled. In addition, the porous polycrystalline silicon layer 4 in which the silicon nanocrystals are distributed to be continuously connected to each other can be controlled. Formation. In this way, the distribution or size of the silicon nanocrystals 6 3 contained in the drift layer 6 can be controlled. As a result, the Chinese National Standard (CNS) A4 specification (210X) is also applied according to the paper size of the second embodiment (297 mm) -34- 564454 Α7 Β7 Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs. 5. Description of the invention (32) In the electron source 10, as in the first embodiment, the electron dispersion of the drift layer 6 can be more than before Skills are reduced. In addition, dielectric strength and electron emission efficiency are improved. Further, the service life of the electron source 10 is extended, and the uniformity in the plane of the electron emission characteristics is improved, whereby a larger area can be obtained. At the same time, In the first and second embodiments, the drift layer 6 is composed of an oxidized porous polycrystalline silicon layer. However, the drift layer 6 may be composed of a nitrogen porous polycrystalline silicon layer and a nitrogen oxygen porous polycrystalline silicon layer. In addition, with another technique, The drift layer may be composed of an oxidized, nitrogen or nitrogen-oxygen porous semiconductor layer. In the case where the drift layer 6 is a nitrided porous polycrystalline silicon layer, for example, by using, for example, NΗ3 gas In the first and second embodiments, the rapid heating technique based on the set temperature rising rate is used to perform the nitriding nitriding step instead of the oxidizing step of oxidizing the porous polycrystalline silicon layer 4 using the 02 heating gas according to the rapid heating technique. One of the silicon oxide films 5 2 and 6 4 is obtained as a silicon nitride film. In the case where the drift layer 6 is an oxynitride porous polycrystalline silicon layer, a mixed gas using N 3 gas and 0 2 gas or the other Ν 2 ◦ The gas may be replaced by a nitrogen oxidation step using a rapid heating technique based on a set temperature rise rate in the first and second embodiments instead of a step of oxidizing the porous polycrystalline silicon layer 4 according to the rapid heating technique. In this example, regarding FIG. The silicon oxide films 5 2 and 64 explained in 4 are both obtained as silicon oxynitride films. In addition, in the method of manufacturing an electron source according to the first and second embodiments, the silicon oxide film 6 which is an insulating film is used. Rapid heating technology is formed. However, the silicon oxide film 64 may be formed by an electrochemical method. In this example, for example, containing electrolyte (such as 1 mole of Η 2 S〇4, 1 mole / (Please read the precautions on the back before filling out this page) This paper size applies Chinese National Standard (CNS) Α4 specifications (210X297 mm) -35- 564454 A7 B7 V. Description of the invention (33) (Please read the precautions on the back before filling this page) Η No. 3, or aqua regia, for example) oxidation treatment container is used . Next, a platinum electrode (not shown) is used as the negative electrode, and the lower electrode is used as the positive electrode (the n-type silicon substrate having the ohmic electrode 2 formed on the n-type silicon substrate in the first embodiment and the n-type silicon substrate in the second embodiment). The electronic conductive layer 1 2), and the porous polycrystalline silicon layer 4 is oxidized by supplying a fixed current, whereby the drift layer 6 including the crystal grains 5 1, the silicon nanocrystals 6 3 and the silicon oxide films 5 2 and 64 is formed. An insulating film formed according to an electrochemical method may be used as a nitride film such as a silicon nitride film. In addition, in the first and second embodiments, a pair of electrodes is composed of a surface electrode 7 and a lower electrode, and a drift layer 6 is interposed between the pair of electrodes, so that the electrons passing through the electron transit layer (electron) The travel layer is formed. (Third embodiment) The third embodiment of the present invention will be described below by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the third embodiment, a memory element formed by an anodizing process will be described. The memory element according to the third embodiment has a basic structure as shown in FIG. 14. That is, the storage layer 101 is formed on the substrate 100 forming the insulating layer 100b on the electronic conductive layer 100a. The storage layer 100 is formed by the anodizing apparatus used in the first and second embodiments. In the storage layer 101, there are silicon nanocrystals 6 3 which are continuously connected to nanometer-level semiconductor nanometers and crystals capable of sealing the carrier, and the crystalline oxide film 6 4 is covered with an insulating film. The grain sizes of some sand nanocrystals 6 3 of the storage layer 1 0 1 are consistent with each other. The thickness of the silicon oxide film 6 4 is smaller than the size of the silicon paper. The Chinese national standard (CNS) A4 specification (210X297 mm) -36- 564454 A7 B7 V. Description of the invention (34) The grain size of the nano crystal 6 3 . (Please read the precautions on the back before filling this page) The storage layer 101 has a band-pass structure as shown in FIG. 15. That is, the storage layer 101 has a large number of well structures of S i sandwiched between S iOX (silicon oxide film 6 4). The band-pass gap between the silicon oxide films 64 and 5 is approximately 5 e V to 10 e V. The band-pass gap between the silicon nanocrystals 6 and 3 is approximately 2 e V to 3 e V. It is known that the band-pass gap between the body is about 1.1 e V and the band-pass gap between the nanocrystals extends about 2 e V to 3 e V. In the third embodiment, in the storage layer 101, the silicon nanocrystal 6 3 series is sandwiched between the barriers of the oxide sand film 64. Therefore, the memory function of storing information can be achieved by sealing the carrier on the silicon nanocrystal 6 3 (by storing the charge). As explained earlier, the band-pass gap between the silicon nanocrystals 63 is larger than that of the watch body. Therefore, for example, in the case of the silicon nanocrystals formed during the growth of the thin film, the silicon nanocrystals are separately present in the surface body, thereby making it difficult to seal the carrier on the silicon nanocrystals. On the other hand, in the third embodiment, the silicon nanocrystals 6 3 coated with the silicon oxide film 64 are formed by being continuously connected to each other, thereby making it possible to seal the carrier on the silicon nanocrystals 63. The memory device according to the third embodiment printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes a sealed carrier coated with a silicon oxide film 6 4 which is an insulating film and a nano-grade silicon nano-crystal 6 6 which stores information. With a storage layer of 101, the crystal system can seal the carrier (by storing charge). The electric charge is stored in the nano-scale silicon nano-crystal 6 3, and therefore, it is possible to achieve a small-sized, low-cost, large-capacity memory element that is smaller than a semiconductor memory using a conventional semiconductor integrated circuit technology. In the storage layer 101, the writing is implemented by the writing organization (not shown). The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -37- 564454 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs System A7 B7 V. Description of Invention (35). In the unit area of the storage layer 101, the carrier can be enclosed in a plurality of silicon nanocrystals 63, whereby the carrier can be enclosed in a plurality of silicon nanocrystals 63 by a writing mechanism. On the other hand, the storage layer 10.1 stores information of multiple chirps according to the number of silicon nanocrystals 6 3 enclosed in the carrier, whereby the multiple chirped information can be stored in the storage layer 101. As the writing mechanism, a mechanism that performs writing into the storage layer 101 by, for example, emitting light may be used. If the writing mechanism is designed to control a large amount of charges stored in the storage layer 1 0 1 by changing the wavelength of the light, the wavelength of the light incident on the storage layer 1 0 1 is changed, whereby the light # enters the storage layer 1 0 1 The depth can be controlled. If the wavelength of light increases, the carrier can be sealed in the silicon nanocrystals 63 in the deeper regions of the storage layer 101. In addition, the carrier can be enclosed in silicon crystals of a larger grain size. If the wavelength of light is reduced, the carrier can be hermetically sealed in the silicon nanocrystals 63 in the shallower region of the storage layer 101. In addition, the carrier can be enclosed in silicon crystals of smaller grain size. Therefore, the number of silicon nanocrystals 6 3 enclosed in the carrier can be controlled, and a large amount of electric charges stored in the storage layer 101 can be controlled. In addition, if the writing mechanism is designed to control the amount of electric charges stored in the storage layer 101 by changing the intensity of light, the number of silicon nanocrystals 6 3 in the closed carrier can be changed by changing the amount of light incident on the storage layer 101. The intensity is controlled, and the number of charges stored in the storage layer 101 can be controlled. It is possible to use a mechanism for writing into the storage layer 101 using electrons as a writing mechanism. In this example, if the amount of charge stored in the storage layer 101 is controlled by changing the voltage applied to the storage layer 101, multiple tritium information can be electronically written into the storage layer 101. This paper size is applicable. National National Standard (CNS) A4 specification (210X297 mm) ~ -38- (Please read the precautions on the back before filling this page)

564454 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（36) 此外，如果儲存層1 0 1被設計以儲存根據密閉於載 體之矽奈米晶體6 3的位置之資訊’儲存容量可被顯著地 增加。所以，如’果寫入機構被設計以由改變光的波長而控 制儲存電荷於儲存層1 0 1之位置’光害進入儲存層 101的深度可由改變射至儲存層101之光的波長而控 制。如光的波長增加，載體可被密閉於儲存層1 0 1可被 密閉之較深區域之矽奈米晶體6 3中，且載體可被密閉於 較大晶粒大小之矽奈米晶體6 3。如光的波長減少，載體 可被密閉於儲存層1 0 1可被密閉之較淺區域之矽奈米晶 體6 3中。此外，載體可被密閉於較小晶粒大小之矽奈米 晶體6 3。因此，密閉載體之矽奈米晶體6 3的位置可被 控制。 在此，由使用第一實施例之陽極氧化設備，如果儲存 層1 0 1被設計以致於矽奈米晶體6 3的晶粒大小被減少 如該結果在厚度方向距η型矽基底1遠’例如’矽奈米晶 體6 3間之光學空隙在儲存層1 〇 1的深度方向改變。因 此，儲存層1 0 1的深度方向之寫入精確性可被改進。 根據第三實施例之記憶體元件，例如，假設覆蓋氧化 矽膜6 4之晶粒大小之5 n m的矽奈米晶體被建構於 2.54 c m X 2 · 5 4 c m (即，1 吋□)的 η 型 矽基底上，下列關係被建立。 (2 · 54χ10_2/5χ10 一 9) 2^2 ·58χ1〇 1 3 > 1 X 1 0 1 2 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -39- 564454 經濟部智慧財產局a(工消費合作社印製 A7 B7__ 五、發明説明（37) 所以，1位元資訊被儲存於一矽奈米晶體6 3中，藉此 0.155 T位元/公分2 (1T/吋2)的大容量記 憶體可被達成。 如圖1 6所示，應用電場至儲存層1 〇 1之探針1 5 也許被提供。此例中，電子導電層1 〇 〇 a係連接至直流 電源E的負極，且探針1 5係連接至直流電源E的正極。 接著，探針1 5的頂端是接近於儲存層1 0 1，且電場係 由探針1 5應用至儲存層1 0 1。由如此做，矽奈米晶體 6 3產生之一對電子與電洞可被分開。結果，靠近矽奈米 晶體6 3之載體的服務壽命可被展延，且儲存時間可被展 延。 圖16之電子導電層100a，絕緣層l〇〇b，與 矽層1 0 0 c可分別由，例如，S I Μ〇X (由經植入的 氧分開）基底上之矽基底，矽基底上之S i〇2膜，以及 S i〇2上之矽基底構成。然而，當然，電子導電層 1 0 0 a也許係由金屬層或另一具有電子導電不用 SIMOX基底之材料構成。 儲存於儲存層1 〇 1之資訊可由發出具有不同於，例 如’當資訊係由發光寫入儲存層1 〇 1之適當波長或適當 強度之光而抹除或讀出。 上述記憶體元件之儲存層1 〇 1係根據下列程序形成 。也就是’多晶矽層被形成於根據，例如，C v D技術之 基底1 0 0的一表面上。此多晶矽層係根據陽極氧化處理 (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 線 本紙張尺度適用中.國國家標準（CNS ) A4規格（210X297公釐） -40- 564454 A7 ___B7___ 五、發明説明（38) 做成多孔，藉此出現量子圍阻效應之具有奈米級之矽奈米 晶體6 3被形成。接著，氧化矽膜6 4係根據，例如，氧 化處理如R T〇技術形成於矽奈米晶體6 3。以此方式， 一些覆與氧化矽膜6 4具有奈米級之矽奈米晶體6 3可被 提供以三維方式彼此靠近。因此，具有圖1 5所示之多量 子井結構之儲存層1 0 1可被形成。所以，可提供小尺寸 與低成本且大容量之記憶體元件。 在電子導電層1 0 0 a被形成當作玻璃基底上之電子 導電薄膜之例子中，製造驅動一般使用玻璃基底當作基底 之液晶顯示器之T F T之處理可被轉移。此外，T F T製 造裝置可被轉移。 儲存層1 0 1可被使用作新記憶體代替現有的半導體 記憶體如快閃記憶體。 例如，如圖1 7所示，覆與爲絕緣膜之氧化矽膜6 4 之奈米級矽奈米晶體6 3被設於多晶矽的圓柱晶粒（半導 體結晶）5 1之間。在此，一對晶粒5 1，5 1分別被提 供作汲極D與源極S。由介於一對晶粒5 1，5 1間且覆 與氧化矽膜6 4之奈米級矽奈米晶體6 3構成之部分被提 供作氧化閘膜6 0。（儲存層1 0 1 )。於閘氧化膜6 0 上形成之電子導電膜被提供作閘電極7 0。因此，Μ〇S 電晶體結構可被獲得，且多重値可被儲存。此Μ〇S電晶 體結構可根據下列程序以自我校準方式製造。也就是，基 底1 0 0的一表面側，例如，多晶矽層係根據C V D技術 形成。多晶矽層係根據陽極氧化處理做成多孔，且形成包 本紙張尺度適用中國國家標準（CNS ) Α4規格(2】0Χ297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -41 - 564454 A7 _ _B7___ 五、發明説明（39) (請先閱讀背面之注意事項再填寫本頁) 含圓柱半導體結晶與量子的效應出現之奈米級矽奈米晶體 6 3，該結晶由多晶矽晶粒5 1構成。接著，例如，氧化 矽膜6 4係根據氧化處理如R T ◦技術形成作矽奈米晶體 6 3的表面上之絕緣膜。 第三實施例中，於矽奈米晶體6 3的表面上形成之絕 緣膜被提供作氧化矽膜6 4。然而，氮化矽膜或氮氧化矽 膜也許被形成代替氧化矽膜6 4。 以下，將說明本發明的第四實施例。然而，根據第四 實施例電子源與其製造方法在基本建構與功能方面是一致 於根據第一實施例的。第四實施例將參考圖2 A至圖2 D 及圖3與圖4說明。 第四實施例中，如在第一實施例中，電阻率稍微接近 導體的電阻率（例如，電阻率實質上是〇 . 〇 1 Ω / c m 至0 · 02Q/cm之（100)基底）之單晶n型矽基 底被用作電子導電基底。 經濟部智慧財產局Ρ貝工消費合作社印製 如圖3所示，根據第四實施例之電子源1 〇，如在第 一實施例中，形成了 η型矽基底1，歐姆電極2，漂流層 6，與表面電極7。這些元件的結構與功能類似於根據第 一實施例之電子源1 0的那些。其說明在此省略。 此外，同樣地根據第四實施例之電子源1 〇，電子以 類似於第一實施例的例子之機制與模式發射。 以下，根據第四實施例製造電子源1 0的方法將參考 圖2Α至圖2D說明。 首先，歐姆電極2被形成於η型矽基底1的背面。接 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐1 一 -42- 564454 A7 B7 五、發明説明（40) (請先閱讀背面之注意事項再填寫本頁} 著，非經摻雜的多晶矽層3被形成作η型矽基底1的主要 表面上之半導體層，且圖2 Α所示之結構被獲得。例如， 可使用C V D技術，噴濺技術，或c G S技術與其類似當 作形成多晶矽層3之膜的方法。 非經摻雜的多晶矽層3已被形成後，多晶矽層3係根 據陽極氧化處理步驟做成多孔，且爲多孔半導體層之多孔 多晶矽層4被形成。以此方式，圖2 B所示之結構被獲得 〇 經濟部智葸財產局8工消費合作社印製 陽極氧化設備在陽極氧化處理步驟中被使用。圖1 8 所示之陽極氧化設備中，包含下電極與多晶矽層3之目標 C浸沒於包含在處理容器4 1之電解液B中（另外，僅目 標C之多晶矽層3係與電解液B接觸）。接著，當鉑電極 (未顯示）被用作負極，且目標C之η型矽基底1(歐姆 電極2 )被用作正極，陽極氧化係以固定電流實行同時光 係自光源射至多晶矽層3 (未顯示）。以此方式，多孔多 晶矽層4被形成。利用由以1 : 1混合5 5 w t %的氟 化氫水溶液與乙醇獲得之混合液當作電解液B。電解液B 基本上是氟酸構成，且在一般半導體製造處理使用之液體 可被使用作電解液B。處理容器4 1之電解液B的溫度與 濃度係由電解液管理設備4 6管理。電解液管理設備4 6 包牯管理容器（未顯示）。處理容器4 1的電解液係透過 電解液導管4 4導入管理容器。在管理容器中，電解液B 的溫度與濃度被控制以致於被維持在各別的設定。管理容 器的電解液B係透過電解液遞送導管4 5遞送至處理容器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -43- 564454 A7 _ _B7____ 五、發明説明（41) (請先閱讀背面之注意事項再填寫本頁) 4 1。即，電解液B係循環於處理容器4 1與管理容器之 間。旋轉翼4 2 (攪拌）被設在處理容器4 1中。旋轉翼 4 2係由驅動設備4 3驅動且旋動且攪拌處理容器4 1之 電解液B。 第四實施例中，由旋轉翼4 2與驅動設備4 3構成之 攪拌設備；及電解液管理設備4 6裝設管理處理容器4 1 之電解液B的濃度之管理機構以致於爲多孔半導體層之多 晶矽層3的平面中以相同的速率被做成多孔。因此形成的 多孔多晶矽層4包含多晶矽晶粒與矽奈米晶體。第四實施 例中，雖然所有多晶矽層3被做成多孔，但也許該層的部 分被做成多孔。管理機構包括攪拌設備與電解液管理設備 。進一步，好好地移動包含爲下電極與半導體層之多晶矽 層3之目標C之設備也許被加至管理機構。該管理機構也 許包括至少一攪拌設備。進一步，想要管理機構包括電解 液管理設備4 6與好好地移動目標C之設備。 經濟部智慈財產局S工消費合作社印製 陽極氧化處理步驟已被終止後，多孔多晶矽層4在氧 化步驟被氧化。以此方式，構成經氧化的多孔多晶矽層之 漂流層6被形成，且圖2 C所示之結構被獲得。在氧化步 驟中，多孔多晶矽層4係由快速加熱技術氧化，且包含晶 粒5 1 ，矽奈米晶體6 3，及氧化矽膜5 2與6 4之漂流 層被形成。在使用快速加熱技術之氧化步驟中燈退火設備 被使用。基底溫度係以預定溫度上升速率（例如，8 0 °C / s e c )自室溫提升至預定氧化溫度（例如，9 0 0 °C )，且被維持預定的氧化時間（例如，一小時）。接著， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公一 -44 - 564454 A7 ____B7_ 五、發明説明（42) 快速加熱氧化（R T〇）被實行。接著，基底溫度被降至 室溫。第四實施例中，預定上升速率被設成8 〇 t / s e c或更高。然而，溫度提升速率也許被設成8〇t/ sec ’且該速率最好被設成160t/sec或更高。 漂流層6已被形成後，由金屬膜（第四實施例之c r 膜）構成之第一薄膜層係根據電子光束氣相沈積技術而沈 澱於漂流層6上。進一步，由金屬膜（第四實施例之A u 膜）構成之第二薄膜層係根據電子光束氣相沈積技術而沈 澱於第一薄膜層上。以此方式，由第一與第二薄膜層構成 之表面電極7被形成，且圖2D所示之電子源1 0被獲得 。第四實施例中，表面電極7係根據電子光束氣相沈積技 術而形成。然而，例如，形成表面電極7的方法不限於電 子光束氣相沈積技術，，例如，噴濺技術也許被使用。 由此製造方法形成之電子源1 0中，電介質強度被改 進，且服務壽命係較先前技藝展延。此外，電子發射特徵 (如電子發射效率或發射電流的電流密度）的平面中均勻 度被改進。這是因爲，陽極氧化處理步驟中，漂流層6之 矽奈米晶體6 3的分佈良好與大小由使用管理機構變完全 地均勻。 爲半導體層（矽層）之多晶矽層3的陽極氧化中’已 知多孔膜或電解拋光發生因爲F離子的供應量與電洞的供 應量間之交換。在F離子的供應量超過電洞的供應量之例 子中，多孔膜發生，且矽奈米晶體6 3被形成。另一方面 ，在電洞的供應量超過F離子的供應量之例子中，電解拋 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝·564454 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (36) In addition, if the storage layer 1 0 1 is designed to store the information based on the position of the silicon nanocrystal 6 3 enclosed in the carrier 'storage capacity Can be significantly increased. Therefore, if the 'fruit writing mechanism is designed to control the position of the stored charge at the storage layer 1 0 by changing the wavelength of light', the depth of light damage entering the storage layer 101 can be controlled by changing the wavelength of the light incident on the storage layer 101. . If the wavelength of light increases, the carrier can be sealed in the silicon nanocrystal 6 3 in the deeper region where the storage layer 1 01 can be sealed, and the carrier can be sealed in the silicon nanocrystal 6 3 with a larger grain size. . If the wavelength of light is reduced, the carrier can be sealed in the silicon nanocrystal 6 3 in the shallower region where the storage layer 101 can be sealed. In addition, the carrier can be enclosed in silicon nanocrystals 63 with smaller grain sizes. Therefore, the position of the silicon nanocrystal 63 in the closed carrier can be controlled. Here, by using the anodizing apparatus of the first embodiment, if the storage layer 1 01 is designed so that the grain size of the silicon nanocrystal 6 3 is reduced, the result is far from the n-type silicon substrate 1 in the thickness direction. For example, the optical gap between the silicon nanocrystals 63 and 3 changes in the depth direction of the storage layer 101. Therefore, the writing accuracy in the depth direction of the storage layer 101 can be improved. According to the memory element of the third embodiment, for example, it is assumed that a 5 nm silicon nanocrystal covering the silicon oxide film 6 4 with a grain size is constructed at 2.54 cm X 2 · 5 4 cm (ie, 1 inch). On the η-type silicon substrate, the following relationships are established. (2 · 54χ10_2 / 5χ10 -1 9) 2 ^ 2 · 58χ1〇1 3 > 1 X 1 0 1 2 (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) Α4 specifications (210X 297 mm) -39- 564454 Intellectual Property Bureau of the Ministry of Economic Affairs a (printed by Industrial and Consumer Cooperatives A7 B7__ V. Invention Description (37) Therefore, 1-bit information is stored in a silicon nanocrystal 6 3, borrowed This mass memory of 0.155 Tbit / cm 2 (1T / inch 2) can be achieved. As shown in FIG. 16, a probe 15 that applies an electric field to the storage layer 1 〇1 may be provided. In this example The electronic conductive layer 100a is connected to the negative electrode of the DC power supply E, and the probe 15 is connected to the positive electrode of the DC power supply E. Next, the top of the probe 15 is close to the storage layer 101 and the electric field is It is applied by the probe 15 to the storage layer 101. By doing so, a pair of electrons and holes generated by the silicon nanocrystal 6 3 can be separated. As a result, the service life of the carrier near the silicon nanocrystal 6 3 Can be extended, and storage time can be extended. The electronic conductive layer 100a, insulating layer 100b, and silicon layer 100c of FIG. 16 can be separated, respectively. For example, the silicon substrate on the SI MOS (separated by implanted oxygen) substrate, the Si substrate on the silicon substrate, and the silicon substrate on Si substrate. However, of course, the electronic conductive layer 1 0 0 a may be composed of a metal layer or another material having electronic conductivity without a SIMOX substrate. Information stored in the storage layer 1 may be issued with a difference such as' when the information is written into the storage layer 1 by light emission. The light of appropriate wavelength or intensity of 1 is erased or read. The storage layer 1 of the above-mentioned memory element is formed according to the following procedure. That is, a 'polycrystalline silicon layer is formed on the basis of, for example, the C v D technology 1 0 0 on one surface. This polycrystalline silicon layer is treated according to anodizing (please read the precautions on the back before filling out this page)-binding and binding. The paper size is applicable. National Standard (CNS) A4 specification (210X297 (Mm) -40- 564454 A7 ___B7___ 5. Description of the invention (38) The nano-sized silicon nanocrystals 6 3 with nanometer-level confinement effect are formed. Then, the silicon oxide film 6 4 series According to, for example, oxidation Ricoh technology is formed on the silicon nanocrystals 63. In this way, some silicon nanocrystals 63 coated with the silicon oxide film 64 having nanometer grades can be provided to approach each other in a three-dimensional manner. A storage layer 101 with a multiple quantum well structure as shown in FIG. 15 can be formed. Therefore, a small-sized, low-cost and large-capacity memory element can be provided. The electronic conductive layer 100a is formed as a glass substrate In the above example of an electronic conductive film, the process of manufacturing a TFT that drives a liquid crystal display that generally uses a glass substrate as a substrate can be transferred. In addition, TF manufacturing equipment can be transferred. The storage layer 101 can be used as a new memory instead of an existing semiconductor memory such as a flash memory. For example, as shown in FIG. 17, a nano-grade silicon nanocrystal 6 3 coated with a silicon oxide film 6 4 which is an insulating film is provided between cylindrical crystal grains (semiconductor crystals) 51 of polycrystalline silicon. Here, a pair of dies 5 1 and 5 1 are provided as a drain D and a source S, respectively. A portion composed of a nano-grade silicon nanocrystal 6 3 interposed between a pair of crystal grains 51, 51 and covered with a silicon oxide film 64 is provided as the oxide gate film 60. (Storage layer 1 0 1). An electronic conductive film formed on the gate oxide film 60 is provided as the gate electrode 70. Therefore, the MOS transistor structure can be obtained, and multiple fluorenes can be stored. This MOS electrical crystal structure can be manufactured in a self-calibrating manner according to the following procedure. That is, one surface side of the substrate 100, for example, a polycrystalline silicon layer is formed according to the CVD technology. The polycrystalline silicon layer is made porous according to anodizing treatment, and the size of the coated paper is applicable to China National Standard (CNS) A4 specification (2) 0 × 297 mm. (Please read the precautions on the back before filling this page) Printed by the Consumer Affairs Cooperative of the Property Bureau -41-564454 A7 _ _B7___ V. Description of the invention (39) (Please read the precautions on the back before filling this page) Nano-level silicon nanometers containing cylindrical semiconductor crystals and quantum effects Crystal 63, which is composed of polycrystalline silicon crystal grains 51. Next, for example, the silicon oxide film 64 is formed as an insulating film on the surface of the silicon nanocrystal 6 3 according to an oxidation process such as R T ◦ technology. In the third embodiment, an insulating film formed on the surface of the silicon nanocrystal 63 is provided as the silicon oxide film 64. However, a silicon nitride film or a silicon oxynitride film may be formed instead of the silicon oxide film 64. Hereinafter, a fourth embodiment of the present invention will be described. However, the electron source and its manufacturing method according to the fourth embodiment are consistent with the first embodiment in terms of basic construction and function. The fourth embodiment will be described with reference to FIGS. 2A to 2D and FIGS. 3 and 4. In the fourth embodiment, as in the first embodiment, the resistivity is slightly close to the resistivity of the conductor (for example, the resistivity is substantially between (0.1) Ω / cm and (100) substrate of 0. 02Q / cm). A single crystal n-type silicon substrate is used as an electronic conductive substrate. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, the Pui Gong Consumer Cooperative, as shown in FIG. 3, according to the fourth embodiment of the electron source 10, as in the first embodiment, an n-type silicon substrate 1, an ohmic electrode 2, and a drift Layer 6, and surface electrode 7. The structure and function of these elements are similar to those of the electron source 10 according to the first embodiment. Its description is omitted here. In addition, also according to the electron source 10 of the fourth embodiment, electrons are emitted in a mechanism and mode similar to the example of the first embodiment. Hereinafter, a method of manufacturing the electron source 10 according to the fourth embodiment will be described with reference to FIGS. 2A to 2D. First, the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. The dimensions of this paper are in accordance with the Chinese National Standard (CNS) A4 specifications (210 × 297 mm 1-42- 564454 A7 B7 V. Description of the invention (40) (Please read the precautions on the back before filling this page}) The doped polycrystalline silicon layer 3 is formed as a semiconductor layer on the main surface of the n-type silicon substrate 1, and the structure shown in FIG. 2A is obtained. For example, CVD technology, sputtering technology, or c GS technology can be used similarly. As a method for forming a film of the polycrystalline silicon layer 3. After the non-doped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous according to the anodizing step, and a porous polycrystalline silicon layer 4 which is a porous semiconductor layer is formed. In this way, the structure shown in Fig. 2B was obtained. The anodizing equipment printed by the 8th Industrial Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs was used in the anodizing step. The anodizing equipment shown in Fig. 18 contains The target C of the lower electrode and the polycrystalline silicon layer 3 is immersed in the electrolytic solution B contained in the processing container 41 (in addition, only the polycrystalline silicon layer 3 of the target C is in contact with the electrolytic solution B.) Then, when the platinum electrode (not shown) use The negative electrode, and the η-type silicon substrate 1 (ohmic electrode 2) of the target C is used as the positive electrode. The anodization is performed at a fixed current while the optical system is emitted from the light source to the polycrystalline silicon layer 3 (not shown). 4 is formed. A mixed solution obtained by mixing a 55 wt% aqueous solution of hydrogen fluoride and ethanol 1: 1 is used as the electrolytic solution B. The electrolytic solution B is basically composed of hydrofluoric acid, and the liquid used in general semiconductor manufacturing processes may be It is used as electrolyte B. The temperature and concentration of electrolyte B in the processing container 41 are managed by the electrolyte management device 46. The electrolyte management device 4 6 includes a management container (not shown). The electrolysis of the processing container 41 The liquid system is introduced into the management container through the electrolyte conduit 44. In the management container, the temperature and concentration of the electrolyte B are controlled so as to be maintained at respective settings. The electrolyte B of the management container is passed through the electrolyte delivery conduit 4 5 Delivery to the processing container This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -43- 564454 A7 _ _B7____ V. Description of the invention (41) (Please read the precautions on the back before filling (This page) 4 1. That is, the electrolyte B is circulated between the processing container 41 and the management container. The rotary wing 4 2 (stirring) is provided in the processing container 41. The rotary wing 4 2 is driven by the driving device 4 3 The electrolytic solution B of the processing container 41 is driven and rotated and stirred. In the fourth embodiment, a stirring device composed of a rotary wing 42 and a driving device 43 is installed; and an electrolytic solution management device 4 6 is provided with a management processing container 41. The management mechanism of the concentration of the electrolytic solution B is such that the plane of the polycrystalline silicon layer 3 which is a porous semiconductor layer is made porous at the same rate. The porous polycrystalline silicon layer 4 thus formed contains polycrystalline silicon grains and silicon nanocrystals. In the fourth embodiment, although all the polycrystalline silicon layer 3 is made porous, a part of the layer may be made porous. Management agencies include stirring equipment and electrolyte management equipment. Further, a device for moving the target C containing the polycrystalline silicon layer 3 which is the lower electrode and the semiconductor layer well may be added to the management body. The regulatory body may include at least one mixing device. Further, it is desirable that the management mechanism includes an electrolytic solution management device 46 and a device that moves the target C well. Printed by the Industrial and Commercial Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs After the anodizing step has been terminated, the porous polycrystalline silicon layer 4 is oxidized in the oxidation step. In this manner, the drift layer 6 constituting the oxidized porous polycrystalline silicon layer is formed, and the structure shown in Fig. 2C is obtained. In the oxidation step, the porous polycrystalline silicon layer 4 is oxidized by a rapid heating technique, and a drift layer including crystal grains 51, silicon nanocrystals 63, and silicon oxide films 52 and 64 is formed. Lamp annealing equipment is used in the oxidation step using rapid heating technology. The substrate temperature is increased from a room temperature to a predetermined oxidation temperature (for example, 900 ° C) at a predetermined temperature rising rate (for example, 80 ° C / sec), and is maintained for a predetermined oxidation time (for example, one hour). Next, this paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 Gongyi-44-564454 A7 ____B7_ V. Description of the invention (42) Rapid heating oxidation (RT0) is implemented. Then, the substrate temperature is reduced to room temperature In the fourth embodiment, the predetermined rising rate is set to 80 t / sec or higher. However, the temperature rising rate may be set to 80 t / sec 'and the rate is preferably set to 160 t / sec or more. After the drift layer 6 has been formed, a first thin film layer composed of a metal film (cr film of the fourth embodiment) is deposited on the drift layer 6 according to an electron beam vapor deposition technique. Further, a metal film ( The second thin film layer composed of the Au film of the fourth embodiment is deposited on the first thin film layer according to the electron beam vapor deposition technique. In this way, the surface electrode 7 composed of the first and second thin film layers is Is formed, and the electron source 10 shown in FIG. 2D is obtained. In the fourth embodiment, the surface electrode 7 is formed according to an electron beam vapor deposition technique. However, for example, the method of forming the surface electrode 7 is not limited to the electron beam gas Facies deposition For example, sputtering technology may be used. In the electron source 10 formed by this manufacturing method, the dielectric strength is improved, and the service life is extended from previous techniques. In addition, electron emission characteristics such as electron emission efficiency or emission current The uniformity in the plane of the current density is improved. This is because during the anodizing step, the distribution and size of the silicon nanocrystals 63 of the drift layer 6 are good and the size becomes completely uniform by the use of a management mechanism. For the semiconductor layer ( In the anodization of polycrystalline silicon layer 3), it is known that the porous membrane or electrolytic polishing occurs because the supply of F ions is exchanged with the supply of holes. Example where the supply of F ions exceeds the supply of holes In this case, a porous membrane occurs and silicon nanocrystals 6 3 are formed. On the other hand, in the case where the supply of holes exceeds the supply of F ions, the paper size of electrolytic paper is subject to the Chinese National Standard (CNS) A4 specification (210X297mm) (Please read the notes on the back before filling this page)

*1T 經濟部智慈財產局員工消費合作社印製 -45- 564454 A7 B7 _ 五、發明説明（43) 光發生，且矽奈米晶體6 3不被形成。然而’第四實施例 中，陽極氧化設備包括攪拌設備。因此，F離子的供應量 至多晶矽層3可自平面中脫離而被限制。並且，供應至使 多晶矽層3多孔需要之反應幣之F離子的多晶矽層3可被 加速。因此，F離子的供應量可避免是小於電洞的供應量 。結果，電解拋光可避免多晶矽層3的區域性部分地發生 。以此方式，多孔成膜係以實質上相同的速率在多晶矽層 3的平面中加速。所以，多孔多晶矽層4之矽奈米晶體 6 3的分佈密度與大小係完全均勻的。結果，漂流層6之 矽奈米晶體6 3的分佈密度與大小係完全均勻的。此外， 陽極氧化設備包括電解液管理設備4 6，且因此，多晶矽 層3的多孔成膜的速率的控制力被改進。以此方式，多孔 多晶矽層4的平面中均勻度可被改進，且再生力可被改進 〇 由根據第四實施例製造電子源1 0之方法，當多孔多 晶砂層4係在陽極氧化處理步驟中形成，電解液B的濃度 被管理以致於多晶矽層3的多孔成膜的速率在多晶砂層3 的平面中是彼此一致的。因此，陽極氧化之處理係穩定的 ，且包含在多孔多晶矽層4之矽奈米晶體6 3的分佈與大 小的再生力可被改進。結果，漂流層6之矽奈米晶體6 3 的分佈與大小的再生力可被改進。以此方式，漂流層6之 矽奈米晶體6 3的分佈與大小是均勻的，且漂流層6之電 子分散可被減少。所以，電介質強度可被改進，且服務壽 命可被展延。進一步，電子發射效率可被改進。更進一步 本紙張尺度適用中國國家標準(CNS ) A4規格（210X 297公釐） '~-- -46- (請先閲讀背面之注意事項再填寫本頁) -裝.* 1T Printed by the Consumer Cooperatives of the Intellectual Property Office of the Ministry of Economic Affairs -45- 564454 A7 B7 _ V. Description of the invention (43) Light is generated and the silicon nanocrystal 6 3 is not formed. However, in the 'fourth embodiment, the anodizing apparatus includes a stirring apparatus. Therefore, the supply amount of F ions to the polycrystalline silicon layer 3 can be restricted from being detached from the plane. Also, the polycrystalline silicon layer 3 supplied to the F ions of the reaction coin required to make the polycrystalline silicon layer 3 porous can be accelerated. Therefore, the supply of F ions can be avoided to be smaller than the supply of holes. As a result, the electrolytic polishing can prevent the localization of the polycrystalline silicon layer 3 from partially occurring. In this way, the porous film-forming system is accelerated in the plane of the polycrystalline silicon layer 3 at substantially the same rate. Therefore, the distribution density and size of the silicon nanocrystals 6 3 of the porous polycrystalline silicon layer 4 are completely uniform. As a result, the distribution density and size of the silicon nanocrystals 63 in the drift layer 6 are completely uniform. In addition, the anodizing apparatus includes an electrolytic solution management apparatus 46, and therefore, the control force of the rate of porous film formation of the polycrystalline silicon layer 3 is improved. In this way, the uniformity in the plane of the porous polycrystalline silicon layer 4 can be improved, and the regenerative force can be improved. By the method of manufacturing the electron source 10 according to the fourth embodiment, when the porous polycrystalline sand layer 4 is subjected to the anodizing step, In the formation, the concentration of the electrolytic solution B is managed so that the rate of porous film formation of the polycrystalline silicon layer 3 is consistent with each other in the plane of the polycrystalline sand layer 3. Therefore, the anodizing treatment is stable, and the distribution and the regenerative force of the silicon nanocrystals 63 included in the porous polycrystalline silicon layer 4 can be improved. As a result, the distribution and size of the silicon nanocrystals 6 3 of the drift layer 6 can be improved. In this way, the distribution and size of the silicon nanocrystals 63 of the drift layer 6 are uniform, and the electron dispersion of the drift layer 6 can be reduced. Therefore, the dielectric strength can be improved and the service life can be extended. Further, the electron emission efficiency can be improved. Further, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) '~--46- (Please read the precautions on the back before filling this page) -pack.

、1T 經濟部智慈財產局員工消費合作社印製 564454 A7 B7 經濟部智態財產局g(工消費合作社印製 五、發明説明（44) ’電子發射特徵的平面中均勻度可被改進，且電子源之面 積可被增加。 (第五實施例） 以下，將說明本發明的第五實施例。然而，根據第五 實施例電子源與製造電子源的方法在基本架構與功能是與 根據第二實施例的那些一致的。第五實施例將參考圖1 1 與圖1 2A至圖1 2D說明。電子源與製造它的方法對根 據第四實施例的那些有許多共通點。 第五實施例中，使用由金屬層（例如，鎢膜）構成之 電子導電層被提供於由玻璃基底（例如，石英玻璃基底） 構成之絕緣基底的一表面上之基底當作電子基底。 如圖1 1所示，同樣地根據第五實施例之電子源1 0 中，實質上是類似於第二實施例，絕緣基底1 1，電子導 電層1 2，漂流層6，與表面電極7被形成。這些元件的 結構與功能是類似於根據第二實施例之電子源1 0的那些 。其說明在此被省略。 同樣根據第五實施例之電子源1 0中，電子係在類似 於第二實施例的例子之機制與模式發射。 在根據第五實施例電子源1 0被利用作顯示器的電子 源之例子中，下電極與表面電極7或其類似也許被適當地 型樣。 以下，根據第五實施例製造電子源1 0的方法將參考 圖1 2A至圖1 2D說明。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -47- 564454 A7 B7 五、發明説明（45) 首先，在絕緣基底1 1的一表面上，由金屬膜（例如 ’鎢膜）構成之電子導電層1 2係根據噴濺技術形成，且 電子導電基底被製造。接著，在電子導電基底（電子導電 層1 2上）的主要表面側上，經非摻雜的多晶矽層3被形 成作半導體層，且圖1 2 A所示之結構被獲得。例如，使 用C V D技術，噴濺技術或C G S技術與其類似當作形成 多晶矽層3之膜的方法。 非經摻雜的多晶矽層3已被形成後，多晶矽層3在陽 極氧化處理步驟中被做成多孔。以此方式，爲多孔半導體 層之多孔多晶矽層4被形成，且圖1 2 B所示之結構被獲 得。陽極氧化處理步驟中，使用包含第四實施例中說明之 管理機構之陽極氧化設備（參考圖1 8 )。也就是，如在 第四實施例中，使用了包含由實質上1 : 1混合5 5 w t %氟化氫水溶液與乙醇獲得之混合液構成之電解液b 之處理容器4 1。接著，由鉑電極爲負極且電子導電層 1 2爲正極，同時光發射對於多晶矽層3實行，陽極氧化 處理係以固定電流實行。以此方式，多孔多晶矽層4被形 成。因此形成的多孔多晶矽層4包含多晶矽晶粒與矽奈米 晶體。第五實施例中，雖然所有多晶矽層3被做成多孔， 但也許僅該層的部分被做成多孔。 陽極氧化處理步驟已終止後，多孔多晶矽層4在氧化 步驟中被氧化。以此方式，由經氧化的多孔多晶矽層構成 之漂流層6被形成，且圖1 2 C所示之結構被獲得。氧化 步驟中，多孔多晶矽層4係根據快速加熱技術氧化。以此 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 批衣-- (請先閱讀背面之注意事項再填寫本頁) 訂 線 經濟部智慈財產局員工消費合作社印製 -48- 564454 A7 B7 五、發明説明（46) 方式，包含晶粒5 1，矽奈米晶體6 3及氧化矽膜5 2與 6 4之漂流層6被形成。在使用快速加熱技術之氧化步驟 中，燈退火設備被使用如第四實施例。0 2氣體在爐中被 產生。基底溫度係以預定溫度提升速率（例如，8 0 t / s e c )自室溫提升至預定氧化溫度（例如，9 0 0 t ) ’且被維持預定的氧化時間（例如，一小時）。接著，快 速加熱氧化（R T〇）被實行。接著，基底溫度被降至室 溫。第五實施例中，預定上升速率被設成8 0 t / s e c 。然而，如在第四實施例中，溫度提升速率也許被設成 8 〇°C/s e c或更高，且該速率最好被設成1 6 0°C/ s e c或更高。 漂流層6已被形成後，由金屬膜（第五實施例之C r 膜）構成之第一薄膜層係根據電子光束氣相沈積技術而沈 澱於漂流層6上。進一步，由金屬膜（第五實施例之A u 膜）構成之第二薄膜層係根據電子光束氣相沈積技術而沈 澱於第一薄膜層上。以此方式，由第一薄膜層與第二薄膜 層構成之表面電極7被形成，且圖1 2 D所示之電子源 1 0被獲得。第五實施例中，表面電極7係根據電子光束 氣相沈積技術而形成。然而，例如，形成表面電極7的方 法不限於電子光束氣相沈積技術，，例如，噴濺技術也許 被使用。 以此方式，由於製造根據第五實施例之電子源1 〇的 方法，漂流層6之矽奈米晶體6 3的分佈密度與大小完全 變均勻。所以漂流層6的電子分散可被減少。結果，電介 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 -49- 564454 經濟部智慧財產局員工消费合作社印製 A7 _________B7_ 五、發明説明（47) 質強度可被改進，且服務壽命可被展延。進一步，電子發 射效率可被改進，且電子發射特徵的平面中均勻度可被改 進。此外，電子源之面積可被增加。 第五實施例中，漂流層6係由經氧化的多孔多晶矽層 構成的。然而，漂流層6也許係氮化多孔多晶矽層或氮氧 化多孔多晶矽層構成的。另外，此層也許係由其它氧化， 氮化，或氮氧化多孔半導體層構成的。 在漂流層6是氮化多孔多晶矽層之例子中，也許使用 了根據快速加熱技術氮化由使用，例如，N Η 3氣體如第 四與第五實施例中根據設定氮化溫度上升速率的氮化步驟 取代使用〇2氣體根據快速加熱技術氧化多孔多晶矽層4 的氧化步驟。此例中，氧化矽膜5 2與6 4 (參考圖4 ) 都被獲得作氮化矽膜。在漂流層6是氮氧化多孔多晶矽層 之例子中，由使用ΝΗ3氣體與〇2氣體的混合氣體氮氧 化根據如第四與第五實施例中設定快速加熱技術之溫度上 升速率的氮氧化步驟取代根據快速加熱技術氧化多孔多晶 矽層4的步驟。此例中，氧化矽膜5 2與6 4 (參考圖4 )都被獲得作氮氧化矽膜。 在根據第四與第五實施例製造電子源的方法中，爲絕 緣膜之氧化矽膜6 4係由利用快速加熱技術形成。然而， 氧化矽膜6 4也許係根據電化法形成。在此例中’例如， 包含電解液（如1莫耳的H2S〇4’ 1莫耳的ΗΝ〇3’ 或王水，例如）之氧化處理容器被使用。接著’鉑電極（ 未顯示）爲負極且下電極爲正極，固定電流被供應’且多 張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閱讀背面之注意事項再填寫本頁}1T printed by the Intellectual Property Office of the Ministry of Economic Affairs and the Consumer Cooperatives 564454 A7 B7 printed by the Intellectual Property Office of the Ministry of Economic Affairs (printed by the Industrial and Consumer Cooperatives V. Description of the invention (44) 'The uniformity in the plane of the electron emission characteristics can be improved, The area of the electron source can be increased. (Fifth embodiment) Hereinafter, a fifth embodiment of the present invention will be described. However, the basic structure and function of the electron source and the method of manufacturing the electron source according to the fifth embodiment are the same as those according to the fifth embodiment. Those of the second embodiment are consistent. The fifth embodiment will be described with reference to FIGS. 11 and 12A to 12D. The electron source and the method of manufacturing it have many points in common with those according to the fourth embodiment. Fifth implementation In the example, an electronic conductive layer made of a metal layer (for example, a tungsten film) is used as an electronic substrate provided on a surface of an insulating substrate made of a glass substrate (for example, a quartz glass substrate). See FIG. 1 1 As shown, the electron source 10 according to the fifth embodiment is also substantially similar to the second embodiment, in which an insulating substrate 11, an electronic conductive layer 12, a drift layer 6, and a surface electrode 7 are formed. The structures and functions of these elements are similar to those of the electron source 10 according to the second embodiment. The description is omitted here. Also in the electron source 10 according to the fifth embodiment, the electrons are similar to those of the second embodiment. Mechanism and mode emission of the example. In the example where the electron source 10 according to the fifth embodiment is used as the electron source of the display, the lower electrode and the surface electrode 7 or the like may be appropriately shaped. Hereinafter, according to the first The method of manufacturing the electron source 10 according to the fifth embodiment will be described with reference to FIGS. 12A to 12D. (Please read the precautions on the back before filling this page.) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). ) -47- 564454 A7 B7 V. Description of the invention (45) First, on one surface of the insulating substrate 1 1, the electronic conductive layer 12 made of a metal film (such as a 'tungsten film') is formed according to the sputtering technology, and An electronically conductive substrate is manufactured. Next, on the main surface side of the electronically conductive substrate (on the electronically conductive layer 12), an undoped polycrystalline silicon layer 3 is formed as a semiconductor layer, and the structure shown in FIG. obtain For example, CVD technology, sputtering technology, or CGS technology is used similarly as a method for forming the polycrystalline silicon layer 3. After the undoped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is formed in an anodizing step Porous. In this way, a porous polycrystalline silicon layer 4 that is a porous semiconductor layer is formed, and the structure shown in FIG. 12B is obtained. In the anodizing step, anodizing including the management mechanism described in the fourth embodiment is used. Equipment (refer to FIG. 18). That is, as in the fourth embodiment, a processing vessel 4 containing an electrolytic solution b composed of a mixed solution obtained by mixing a 1: 1 substantially 55 wt% hydrogen fluoride aqueous solution and ethanol is used. 1. Next, the platinum electrode is used as the negative electrode and the electronic conductive layer 12 is used as the positive electrode. At the same time, light emission is performed on the polycrystalline silicon layer 3, and the anodizing treatment is performed at a fixed current. In this manner, the porous polycrystalline silicon layer 4 is formed. The porous polycrystalline silicon layer 4 thus formed includes polycrystalline silicon grains and silicon nanocrystals. In the fifth embodiment, although all the polycrystalline silicon layer 3 is made porous, only a part of the layer may be made porous. After the anodizing step has been terminated, the porous polycrystalline silicon layer 4 is oxidized in the oxidizing step. In this manner, the drift layer 6 composed of the oxidized porous polycrystalline silicon layer is formed, and the structure shown in Fig. 12C is obtained. In the oxidation step, the porous polycrystalline silicon layer 4 is oxidized according to a rapid heating technique. Based on this paper size, the Chinese National Standard (CNS) A4 specification (210X297 mm) is approved.-(Please read the precautions on the back before filling out this page.) Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economy- 48- 564454 A7 B7 V. Description of the invention (46) The method includes a grain layer 51, a silicon nanocrystal 6 3, and a drift layer 6 of silicon oxide films 5 2 and 64. In the oxidation step using the rapid heating technique, a lamp annealing apparatus is used as in the fourth embodiment. 0 2 gas is generated in the furnace. The substrate temperature is raised from room temperature to a predetermined oxidation temperature (for example, 900 t) at a predetermined temperature increase rate (for example, 80 t / s e c) and maintained for a predetermined oxidation time (for example, one hour). Next, rapid thermal oxidation (RT0) was performed. Then, the substrate temperature was lowered to room temperature. In the fifth embodiment, the predetermined rising rate is set to 80 t / s e c. However, as in the fourth embodiment, the temperature increase rate may be set to 80 ° C / s e c or higher, and the rate is preferably set to 160 ° C / s e c or higher. After the drift layer 6 has been formed, a first thin film layer composed of a metal film (the Cr film of the fifth embodiment) is deposited on the drift layer 6 according to an electron beam vapor deposition technique. Further, a second thin film layer composed of a metal film (the Au film of the fifth embodiment) is deposited on the first thin film layer according to an electron beam vapor deposition technique. In this manner, the surface electrode 7 composed of the first thin film layer and the second thin film layer is formed, and the electron source 10 shown in Fig. 12D is obtained. In the fifth embodiment, the surface electrode 7 is formed according to an electron beam vapor deposition technique. However, for example, the method of forming the surface electrode 7 is not limited to the electron beam vapor deposition technique, and for example, a sputtering technique may be used. In this way, due to the method of manufacturing the electron source 10 according to the fifth embodiment, the distribution density and size of the silicon nanocrystals 63 of the drift layer 6 become completely uniform. Therefore, the electron dispersion of the drift layer 6 can be reduced. As a result, the paper size of the dielectric is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the precautions on the back before filling out this page) -49- 564454 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _________B7_ V. Description of Invention (47) The quality and strength can be improved and the service life can be extended. Further, the electron emission efficiency can be improved, and the uniformity in the plane of the electron emission characteristics can be improved. In addition, the area of the electron source can be increased. In the fifth embodiment, the drift layer 6 is composed of an oxidized porous polycrystalline silicon layer. However, the drift layer 6 may be composed of a nitrided porous polycrystalline silicon layer or a nitrided porous polycrystalline silicon layer. In addition, this layer may be composed of other oxidized, nitrided, or oxynitride porous semiconductor layers. In the case where the drift layer 6 is a nitrided polycrystalline silicon layer, nitridation may be used according to a rapid heating technique, for example, NN3 gas such as nitrogen in the fourth and fifth embodiments according to a set rate of increase in nitriding temperature. The oxidizing step replaces the oxidizing step of oxidizing the porous polycrystalline silicon layer 4 using a 02 gas according to a rapid heating technique. In this example, both silicon oxide films 5 2 and 6 4 (refer to FIG. 4) are obtained as silicon nitride films. In the case where the drift layer 6 is an oxynitride porous polycrystalline silicon layer, it is replaced by an oxynitridation step using a mixed gas of ΝΗ3 gas and 〇2 gas according to the temperature rise rate set by the rapid heating technology in the fourth and fifth embodiments A step of oxidizing the porous polycrystalline silicon layer 4 according to a rapid heating technique. In this example, silicon oxide films 5 2 and 6 4 (refer to FIG. 4) are obtained as silicon oxynitride films. In the method of manufacturing an electron source according to the fourth and fifth embodiments, the silicon oxide film 64, which is an insulating film, is formed by using a rapid heating technique. However, the silicon oxide film 64 may be formed by an electrochemical method. In this case, for example, an oxidation treatment container containing an electrolytic solution (such as 1 mole of H2S04, 1 mole of NONO3 'or aqua regia, for example) is used. Then "platinum electrode (not shown) is the negative electrode and the lower electrode is the positive electrode, and the fixed current is supplied" and multiple dimensions are applicable to China National Standard (CNS) A4 specifications (210 × 297 mm) (Please read the precautions on the back before filling in this page}

-50- 564454 Α7 Β7 五、發明説明（48) 孔多晶矽層4被氧化，藉此包含晶粒5 1 ，矽奈米晶體 6 3及氧化矽膜5 2與6 4之漂流層6被形成。當然，根 據電化法形成之絕緣膜也許被用作氮化膜如氮化矽膜。 (第六實施例） 以下，將說明本發明的第六實施例。然而，根據第六 實施例電子源與製造電子源的方法在基本架構與功能是與 根據第一實施例的那些一致的。第六實施例將參考圖2 A 至圖2D及圖3與圖4說明。 第六實施例中，如在第一實施例中，使用了電阻率稍 微接近導體的電阻率（例如，電阻率實質上是0 . 0 1 Ω /cm至〇 · 〇2Q/cm之（100)基底）之單晶η 型矽基底當作電子導電基底。 如圖3所示，同樣根據第六實施例之電子源1 〇，如 在第一實施例中，η型矽基底1 ，歐姆電極2，漂流層6 ，與表面電極7被形成。這些元件的結構與功能類似於根 據第一實施例之電子源1 0的那些。其說明在此省略。 此外，如圖4所示，同樣地根據第六實施例之電子源 1 0，電子係以類似於第一實施例的例子之機制與模式發 射。 以下，根據第六實施例製造電子源1 〇的方法將參考 圖2Α至圖2D說明。 首先，歐姆電極2被形成於η型矽基底1的背面。接 著’在η型矽基底1的主要表面上，非經摻雜的多晶矽層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 一裝· 訂 經濟部智慧財產局g(工消f合作社印製 -51 - 564454 Α7 Β7 五、發明説明（49) 3被形成作半導體層，且圖2 A所示之結構被獲得。例如 ，可使用C V D技術，噴濺技術，或C G S技術與其類似 當作形成多晶矽層3之膜的方法。 非經摻雜的多晶矽層3已被形成後，多晶矽層3係根 據陽極氧化處理步驟做成多孔，以此方式，爲多孔半導體 層之多孔多晶矽層4被形成，且圖2 B所示之結構被獲得 。陽極氧化處理步驟中，使用了包含由實質上1:1混合 5 5 w t %氟化氫水溶液與乙醇獲得之混合液構成之電 解液之處理容器。接著，由鉑電極（未顯示）爲負極且η 型矽基底1 (歐姆電極2 )爲正極，同時對於多晶矽層3 光發射被實行，陽極氧化係以固定電流實行。以此方式， 多孔多晶矽層4被形成。因此形成的多孔多晶矽層4有分 別是矽奈米晶體6 3與晶粒5 1的源極之矽奈米晶體與晶 粒。第六實施例中，雖然所有多晶矽層3被做成多孔，但 也許僅該層的部分被做成多孔。 陽極氧化處理步驟已終止後，移除在多孔多晶矽層4 剩下之電解液的沖洗S Τ Ρ被實行。接著，多孔多晶矽層 4係在爲絕緣膜形成步驟之氧化步驟中氧化。以此方式， 由經氧化的多孔多晶矽層構成之漂流層6被形成，且圖2 C所示之結構被獲得。 沖洗步驟中，首先，沖洗係以純水實行第一預定時間 (例如，大約數分鐘至1 〇分鐘）。接著，爲了換掉純水 ，浸入爲水溶性有機溶劑（親水有機溶劑）之甲基乙醇第 二預定時間（例如，大約1分鐘至5分鐘）被實行大約3 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 經濟部智慈財產局員工消贽合作社印製 -52- 564454 Α7 Β7 五、發明説明（50) (請先閱讀背面之注意事項再填寫本頁) 至5分鐘。隨後，浸入非水溶性有機溶劑第三預定時間（ 例如，大約1分鐘至5分鐘）被實行大約3至5分鐘。也 許使用乙基乙醇（濃度9 5%或更高）或異丙基乙醇（濃 度9 9 %或更高）與其類似取代使用甲基乙醇（濃度9 9 %或更高）當作水溶性有機溶劑。苯（濃度9 9 · 5 %或 更高）也許被使用取代使用己烷（濃度9 6%或更高）當 作非水溶性有機溶劑。 氧化步驟中，氧化處理容器包含電解液（如經稀釋的 硫酸，經稀釋的氮酸，或王水，例如）。由鉑電極（未顯 示）爲負極且η型矽基底1 (歐姆電極2 )爲正極’固定 電流被供應，藉此多孔多晶矽層4被電化地氧化。以此方 式，包含晶粒5 1，矽奈米晶體6 3及氧化矽膜5 2與 6 4之漂流層6被形成。在氧化步驟中，多孔多晶矽層4 被電化地氧化。然而，多孔多晶矽層4也許係由使用燈退 火設備之快速加熱技術（快速加熱氧化技術）氧化。 經濟部智慈財產局員工消费合作社印製 漂流層6已被形成後，由金薄膜構成之表面電極7被 形成於漂流層6上，且圖2 D所示之電子源1 0被獲得。 第六實施例中，表面電極7係根據電子氣相沈積技術形成 。然而，形成表面電極7的方法不限於電子氣相沈積技術 ，且例如，噴濺技術也許被使用。 根據第六實施例製造電子源1 0的方法中，形成漂流 層6的步驟包括：根據使用電解液之陽極氧化形成多孔多 晶矽層4的陽極氧化處理步驟；移除留在多孔多晶矽層4 之電解液的沖洗步驟；以及氧化多孔多晶矽層4的絕緣膜 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -53- 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（51) 形成步驟，藉此分別形成絕緣膜（氧化矽膜5 2與6 4 ) 於政奈米晶體6 3與晶粒5 1的表面上。因此，留在陽極 氧化處理步驟中形成之多孔多晶矽層4之電解液或其類似. 可在絕緣膜形成步驟前移除。此外，於矽奈米晶體6 3與 晶粒5 1的各表面上形成之絕緣膜（氧化矽膜5 2與6 4 )的品質可在絕緣膜形成步驟中被改進。結果，電子源 1 0的電介質強度可被改進，且服務壽命可較先前技術延 長。 沖洗步驟中，使用純水之沖洗後，使用非水溶性有機 溶劑之沖洗被實行。也就是，在以非水溶性溶液沖洗之前 ，沖洗係以純水實行，且因此，剩下的雜質如氟可在短時 間內移除。並且，在以非水溶性溶液沖洗之前，沖洗係以 純水實行，且進一步，純水被換成水溶性有機溶劑。因此 ，由使用水溶性有機溶劑之沖洗，留在多孔多晶矽層4之 水含量可自多孔多晶矽層4移除。結果，水含量可自留在 多孔多晶矽層4中留下。 第六實施例中，使用了較低乙醇如甲基乙醇，乙基乙 醇，或異丙基乙醇當作水溶性有機溶劑。這些乙醇溶劑有 少數的碳在分子中，且在分子比重中稍微小。因爲如此， 這些溶劑輕易地滲入好的結構（好的多孔結構）如多孔多 晶矽層4。因此，留在多孔多晶矽層4之水含量可在稍微 短的時間內移除。甲基乙醇在小分子比重方面較佳，但在 毒性方面較不佳。所以，由使用乙基乙醇取代甲基乙醇， 帶（banding )可被簡化，且安全可被改進。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -54- 564454 A7 _ B7___ 五、發明説明（52) (請先閲讀背面之注意事項再填寫本頁) 使用了沸點不超過1 〇 〇且溶點不超過2 0之有機溶 劑如己烷或苯當作非水溶性有機溶劑。此非水溶性有機溶 劑是高揮發，且易於蒸發。因此，該非水溶性有機溶劑可 避免留在多孔多晶矽層4中。此外，在沖洗步驟中不需要 準備特定的環境或裝備。因此，由設施投資造成之製造成 本之增加可被避免。 (第七實施例） 以下，將說明本發明的第七實施例。然而，根據第六 實施例之電子源與製造電子源的方法在基本架構與功能是 與根據第二實施例的那些一致的。第七實施例將參考圖 1 1與圖1 2 A至圖1 2 D說明。根據第七實施例之電子 源與製造方法對根據第六實施例的那些有許多共通點。 經濟部智慧財產局員工消費合作社印製 第七實施例中，使用了於由金屬膜（例如，鎢層）構 成之電子導電層被提供於由玻璃基底構成之絕緣基底的一 表面上之基底當作電子導電基底。在電子導電層被因此形 成於絕緣基底的表面側上之例子中，電子源的成本減少與 較大面積較如第六實施例用作電子導電基底之半導體基底 之例子可能。 如圖1 1所示，同樣地根據第七實施例之電子源1 0 中，實質上是類似於第二實施例，形成了絕緣基底1 1， 電子導電層1 2，漂流層6，與表面電極7。這些元件的 結構與功能是類似於根據第二實施例之電子源1 0的那些 。其說明在此被省略。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -55- 564454 A7 B7 五、發明説明（53) 同樣根據第七實施例之電子源1 〇中，電子係在類似 於第二實施例的例子之機制與模式發射。 在根據第七實施例電子源1 〇被利用作顯示器的電子 源之例子中，下電極與表面電極7或其類似也許被適當地 型樣。 以下，根據第七實施例製造電子源1 〇的方法將參考 圖1 2A至圖1 2D說明。 首先，在絕緣基底1 1的一表面上，由金屬膜（例如 ’鎢膜）構成之電子導電層1 2係根據噴濺技術形成，且 電子導電基底被製造。接著，在電子導電基底（電子導電 層1 2上）的主要表面側上，經非摻雜的多晶矽層3被形 成作半導體層，且圖1 2 A所示之結構被獲得。例如，使 用C V D技術，噴濺技術或C G S技術與其類似當作形成 多晶砂層3之膜的方法。 非經摻雜的多晶矽層3已被形成後，多晶矽層3在陽 極氧化處理步驟中被做成多孔。以此方式，爲多孔半導體 層之多孔多晶砂層4被形成，且圖1 2 B所示之結構被獲 得。陽極氧化處理步驟中，使用了包含由實質上1:1混 合5 5 w t %氟化氫水溶液與乙醇獲得之混合液構成之 電解液B之處理容器。由鉑電極（未顯示）爲負極且電子 導電層1 2爲正極，同時光發射對於多晶矽層3實行，陽 極氧化處理係以固定電流實行，藉此多孔多晶矽層4被形 成。因此形成的多孔多晶矽層4有分別爲晶粒5 1與矽奈 米晶體6 3的源極之晶粒與矽奈米晶體。第七實施例中， 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） t衣-- (請先閲讀背面之注意事項再填寫本頁) 訂 線 經濟部智慧財產局Μ工消費合作社印製 -56- 564454 A7 B7 五、發明説明（54) 雖然所有多晶矽層3被做成多孔，但也許僅該層的部分被 做成多孔。 (請先閱讀背面之注意事項再填寫本頁) 陽極氧化處理步驟已終止後，沖洗步驟被實行如第六 實施例的例子。接著，多孔多晶矽層4係在爲絕緣膜形成 步驟之氧化步驟中氧化，且由經氧化的多孔多晶矽層構成 之漂流層6被形成，且圖1 2 C所示之結構被獲得。 氧化步驟中，包含電解液（如經稀釋的硫酸，經稀釋 的氮酸，或王水，例如）之氧化處理容器被使用。接著， 由鉑電極（未顯示）爲負極且電子導電層1 2爲正極，固 定電流被供應，且多孔多晶矽層4被氧化，藉此，形成了 包含晶粒5 1 ，矽奈米晶體6 3及氧化矽膜5 2與6 4之 漂流層6。 漂流層6已被形成後，由金薄膜構成之表面電極7被 形成於漂流層6上，且圖1 2 D所示之電子源1 〇被獲得 。第七實施例中，表面電極7係根據電子氣相沈積技術形 成。然而，形成表面電極7的方法不限於電子氣相沈積技 術，且例如，噴濺技術也許被使用。 經濟部智慧財產局貞工消費合作社印製 以此方式，同樣根據第七實施例製造電子源1 0的方 法中，如第六實施例的例子，形成漂流層6的步驟包括陽 極氧化處理步驟，沖洗步驟，以及絕緣膜形成步驟。因此 ，留在於陽極氧化處理步驟中形成之多孔多晶矽層4之電 解液可在絕緣膜形成步驟前被減少。此外，於矽奈米晶體 6 3與晶粒5 1的各表面上形成之絕緣膜（氧化矽膜5 2 與6 4 )的品質可在絕緣膜形成步驟中被改進。結果，電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -57- 564454 A7 B7 五、發明説明（55) 子源1 0的電介質強度可被改進，且服務壽命可較先前技 術延長。 (請先閱讀背面之注意事項再填寫本頁) 第六與第七實施例中，漂流層6係由多孔多晶矽層構 成的。然而，該層也許係由其它經氧化的多孔半導體層或 氮化或氮氧化多孔半導體層構成的。也就是，第六與第七 實施例中，雖然於絕緣膜形成步驟形成之絕緣膜是氧化矽 膜，絕緣膜也許係除氧化矽膜外之氧化膜，氮化膜如氮化 矽膜，或氮氧化膜如氮氧化矽膜構成的。氮化矽膜或氮氧 化矽膜被使用，藉此電介質強度電壓可較氧化矽膜的例子 被改進。氮化矽膜或氮氧化矽膜與其類似也許係根據快速 加熱氧化形成。 經濟部智慧財產局員工消費合作社印製 第六與第七實施例中，金被使用成表面電極7之材料 。然而，鋁，鉻，鎢，鎳，或鉑也許被使用。此外，表面 電極7也許係由至少以厚度方向沈澱之兩層的薄膜層構成 的。在表面電極7係由兩層的薄膜層構成的例子中，例如 ，金或其類似被用作上薄膜層之材料。此外，例如，鉻， 鎳，鉑，鈦，或銦被用作下薄膜層之材料（在漂流層6側 之薄膜層）。 (第八實施例） 以下，將說明本發明的第八實施例。然而，根據第八 實施例電子源與製造電子源的方法在基本架構與功能是與 根據第一實施例的那些一致的。第八實施例將參考圖2 A 至圖2D及圖3與圖4說明。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -58- 經濟部智祛財產局貨工消費合作社印製 564454 A7 ____B7_ 五、發明説明（56) 第八實施例中，如在第一實施例中，使用了電阻率稍 微接近導體的電阻率（例如，電阻率實質上是〇 . 〇 1 Ω / c m至〇 · 〇 2 Ω / c m之（1 0 〇 )基底）之單晶η 型矽基底當作電子導電基底。 如圖3所示，同樣根據第八實施例之電子源1 〇，如 在第一實施例中，形成了 η型矽基底1，歐姆電極2，漂 流層6，與表面電極7。這些元件的結構與功能類似於根 據第一實施例之電子源1 〇的那些。其說明在此省略。 此外，如圖4所示，同樣地根據第八實施例之電子源 1 0，電子係以類似於第一實施例的例子之機制與模式發 射。 以下，根據第八實施例製造電子源1 0的方法將參考 圖2Α至圖2D說明。 首先，歐姆電極2被形成於η型矽基底1的背面。接 著’在η型矽基底1的主要表面上，非經摻雜的多晶矽層 3被形成作半導體層，且圖2 Α所示之結構被獲得。例如 ’可使用C V D技術，噴濺技術，或C G S技術與其類似 當作形成多晶矽層3之膜的方法。 非經摻雜的多晶矽層3已被形成後，多晶矽層3係根 • 據陽極氧化處理步驟做成多孔，以此方式，爲多孔半導體 層之多孔多晶矽層4被形成，且圖2 B所示之結構被獲得 。陽極氧化處理步驟中，使用了包含由實質上1 : 1混合 5 5 w t %氟化氫水溶液與乙醇獲得之混合液構成之電 解液之處理容器。接著，由鉑電極（未顯示）爲負極且η 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ~ -59- (請先閲讀背面之注意事項再填寫本頁)-50- 564454 Α7 Β7 V. Description of the Invention (48) The porous polycrystalline silicon layer 4 is oxidized, thereby forming the drift layer 6 including the crystal grains 5 1, the silicon nanocrystals 6 3 and the silicon oxide films 5 2 and 64. Of course, an insulating film formed according to an electrochemical method may be used as a nitride film such as a silicon nitride film. (Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described. However, the basic structure and functions of the electron source and the method of manufacturing the electron source according to the sixth embodiment are consistent with those according to the first embodiment. The sixth embodiment will be described with reference to FIGS. 2A to 2D and FIGS. 3 and 4. In the sixth embodiment, as in the first embodiment, the resistivity that is slightly close to that of the conductor is used (for example, the resistivity is substantially (100) from 0.01 Ω / cm to 〇 · 〇2Q / cm. Substrate) The single crystal η-type silicon substrate is used as the electronic conductive substrate. As shown in FIG. 3, the electron source 10 according to the sixth embodiment is also formed. As in the first embodiment, an n-type silicon substrate 1, an ohmic electrode 2, a drift layer 6, and a surface electrode 7 are formed. The structure and function of these elements are similar to those of the electron source 10 according to the first embodiment. Its description is omitted here. In addition, as shown in Fig. 4, the electrons are emitted in a mechanism and mode similar to the example of the first embodiment according to the electron source 10 of the sixth embodiment. Hereinafter, a method of manufacturing the electron source 10 according to the sixth embodiment will be described with reference to FIGS. 2A to 2D. First, the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. Then 'on the main surface of the η-type silicon substrate 1, the non-doped polycrystalline silicon layer is used for this paper. The size of the paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) One pack · Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs (printed by Industrial Consumers Cooperatives -51-564454 A7 B7) 5. Invention Description (49) 3 is formed as a semiconductor layer, and the structure shown in Figure 2A is obtained. For example, CVD technology, sputtering technology, or CGS technology can be used as a method for forming the polycrystalline silicon layer 3. After the undoped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous according to the anodizing step. In this way, a porous polycrystalline silicon layer 4 that is a porous semiconductor layer is formed, and the structure shown in Fig. 2B is obtained. In the anodizing step, an aqueous solution containing 5 5 wt% hydrogen fluoride by substantially 1: 1 mixing is used. A processing container for an electrolytic solution composed of a mixed solution obtained with ethanol. Next, a platinum electrode (not shown) is used as a negative electrode and an η-type silicon substrate 1 (ohmic electrode 2) is used as a positive electrode. The anodic oxidation is performed at a fixed current. In this way, the porous polycrystalline silicon layer 4 is formed. Therefore, the formed porous polycrystalline silicon layer 4 has the silicon nanocrystals of the source of silicon nanocrystals 6 3 and crystal grains 51 respectively. In the sixth embodiment, although all the polycrystalline silicon layer 3 is made porous, only part of the layer may be made porous. After the anodizing step has been terminated, the porous polycrystalline silicon layer 4 is removed and left The washing of the electrolyte STP is performed. Next, the porous polycrystalline silicon layer 4 is oxidized in the oxidation step of the insulating film forming step. In this way, the drift layer 6 composed of the oxidized porous polycrystalline silicon layer is formed, and The structure shown in 2C is obtained. In the rinsing step, first, the rinsing is performed with pure water for a first predetermined time (for example, about several minutes to 10 minutes). Then, in order to replace the pure water, the immersion is water-soluble organic The second predetermined time (for example, about 1 minute to 5 minutes) of methyl alcohol of the solvent (hydrophilic organic solvent) is implemented for about 3 paper standards applicable to the Chinese National Standard (CNS) A4 specification (210X297) ) (Please read the precautions on the back before filling this page) Binding and printing Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-52- 564454 Α7 Β7 V. Description of the invention (50) (Please read the precautions on the back first Fill out this page again) to 5 minutes. Then, a third predetermined time (for example, about 1 to 5 minutes) of immersion in a non-water-soluble organic solvent is performed for about 3 to 5 minutes. Ethyl ethanol (concentration of 9 5% or Or higher) or isopropyl alcohol (99% or higher) instead of methyl alcohol (99% or higher) as a water-soluble organic solvent. Benzene (99.5% or higher) High) may be used instead of using hexane (9 6% or higher) as a water-insoluble organic solvent. In the oxidation step, the oxidation treatment container contains an electrolytic solution (such as diluted sulfuric acid, diluted nitric acid, or aqua regia, for example). A fixed current is supplied from a platinum electrode (not shown) as a negative electrode and an n-type silicon substrate 1 (ohmic electrode 2) as a positive electrode, whereby the porous polycrystalline silicon layer 4 is electrochemically oxidized. In this manner, the drift layer 6 including the crystal grains 51, the silicon nanocrystals 63, and the silicon oxide films 52 and 64 is formed. In the oxidation step, the porous polycrystalline silicon layer 4 is electrochemically oxidized. However, the porous polycrystalline silicon layer 4 may be oxidized by a rapid heating technique (rapid heating oxidation technique) using a lamp annealing apparatus. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs After the drift layer 6 has been formed, a surface electrode 7 composed of a thin gold film is formed on the drift layer 6 and an electron source 10 shown in FIG. 2D is obtained. In the sixth embodiment, the surface electrode 7 is formed according to an electronic vapor deposition technique. However, the method of forming the surface electrode 7 is not limited to the electron vapor deposition technique, and, for example, a sputtering technique may be used. In the method of manufacturing the electron source 10 according to the sixth embodiment, the step of forming the drift layer 6 includes: an anodizing step of forming the porous polycrystalline silicon layer 4 according to anodization using an electrolytic solution; and removing the electrolysis remaining in the porous polycrystalline silicon layer 4 Liquid washing steps; and the insulating film oxidizing the porous polycrystalline silicon layer 4. The paper size is applicable to Chinese National Standard (CNS) A4 specifications (210 × 297 mm) -53- 564454 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (51) A forming step, whereby insulating films (silicon oxide films 5 2 and 6 4) are formed on the surfaces of the crystals 6 3 and 5 1 respectively. Therefore, the electrolytic solution of the porous polycrystalline silicon layer 4 remaining in the anodizing step or the like can be removed before the insulating film forming step. In addition, the quality of the insulating films (silicon oxide films 5 2 and 6 4) formed on the surfaces of the silicon nanocrystals 6 3 and the crystal grains 51 can be improved in the insulating film forming step. As a result, the dielectric strength of the electron source 10 can be improved, and the service life can be extended compared to the prior art. In the rinsing step, rinsing with pure water is followed by rinsing with a water-insoluble organic solvent. That is, before rinsing with a water-insoluble solution, rinsing is performed with pure water, and therefore, remaining impurities such as fluorine can be removed in a short time. In addition, before rinsing with a water-insoluble solution, rinsing is performed with pure water, and further, pure water is replaced with a water-soluble organic solvent. Therefore, the water content remaining in the porous polycrystalline silicon layer 4 can be removed from the porous polycrystalline silicon layer 4 by rinsing with a water-soluble organic solvent. As a result, the water content can remain in the porous polycrystalline silicon layer 4 by itself. In the sixth embodiment, a lower ethanol such as methyl ethanol, ethyl ethanol, or isopropyl ethanol is used as the water-soluble organic solvent. These ethanol solvents have a small amount of carbon in the molecule and are slightly smaller in the specific gravity of the molecule. Because of this, these solvents easily penetrate good structures (good porous structures) such as the porous polycrystalline silicon layer 4. Therefore, the water content remaining in the porous polycrystalline silicon layer 4 can be removed in a slightly shorter time. Methyl ethanol is better in terms of small-molecule specific gravity, but less effective in terms of toxicity. Therefore, by using methyl ethanol instead of methyl ethanol, banding can be simplified, and safety can be improved. (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -54- 564454 A7 _ B7___ V. Description of the invention (52) (Please read the first Note: Please fill in this page again.) An organic solvent such as hexane or benzene with a boiling point not exceeding 100 and a melting point not exceeding 20 is used as a water-insoluble organic solvent. This water-insoluble organic solvent is highly volatile and easily evaporates. Therefore, the water-insoluble organic solvent can be prevented from remaining in the porous polycrystalline silicon layer 4. In addition, no special environment or equipment needs to be prepared during the flushing step. Therefore, the increase in manufacturing costs caused by the investment in facilities can be avoided. (Seventh Embodiment) Hereinafter, a seventh embodiment of the present invention will be described. However, the basic structure and functions of the electron source and the method of manufacturing the electron source according to the sixth embodiment are consistent with those according to the second embodiment. The seventh embodiment will be described with reference to FIGS. 11 and 12A to 12D. The electron source and manufacturing method according to the seventh embodiment have many points in common with those according to the sixth embodiment. In the seventh embodiment printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a substrate using an electronic conductive layer composed of a metal film (for example, a tungsten layer) provided on a surface of an insulating substrate composed of a glass substrate As an electronically conductive substrate. In the example where the electronic conductive layer is thus formed on the surface side of the insulating substrate, the cost reduction and larger area of the electron source are possible as compared with the example of the semiconductor substrate used as the electronic conductive substrate in the sixth embodiment. As shown in FIG. 11, the electron source 10 according to the seventh embodiment is similar to the second embodiment, and an insulating substrate 11, an electronic conductive layer 12, a drift layer 6, and a surface are formed. Electrode 7. The structure and function of these elements are similar to those of the electron source 10 according to the second embodiment. Its description is omitted here. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -55- 564454 A7 B7 V. Description of the invention (53) Also according to the electron source 10 of the seventh embodiment, the electron system is similar to the second one The mechanism and mode of the example of the embodiment are transmitted. In the example where the electron source 10 according to the seventh embodiment is used as the electron source of the display, the lower electrode and the surface electrode 7 or the like may be appropriately shaped. Hereinafter, a method of manufacturing the electron source 10 according to the seventh embodiment will be described with reference to FIGS. 12A to 12D. First, on one surface of the insulating substrate 11, an electronic conductive layer 12 made of a metal film (for example, a 'tungsten film) is formed according to a sputtering technique, and an electronic conductive substrate is manufactured. Next, on the main surface side of the electronic conductive substrate (on the electronic conductive layer 12), an undoped polycrystalline silicon layer 3 is formed as a semiconductor layer, and the structure shown in FIG. 12A is obtained. For example, C V D technology, sputtering technology, or C G S technology is used as a method for forming a film of the polycrystalline sand layer 3 similarly. After the undoped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous in the anode oxidation treatment step. In this way, a porous polycrystalline sand layer 4 which is a porous semiconductor layer is formed, and the structure shown in Fig. 12B is obtained. In the anodizing step, a processing container containing an electrolytic solution B consisting of a mixed solution obtained by mixing a 55 wt% hydrogen fluoride aqueous solution and ethanol substantially 1: 1 was used. A platinum electrode (not shown) is used as the negative electrode and the electronic conductive layer 12 is used as the positive electrode. At the same time, light emission is performed on the polycrystalline silicon layer 3. The anode oxidation treatment is performed with a fixed current, whereby the porous polycrystalline silicon layer 4 is formed. The porous polycrystalline silicon layer 4 thus formed has crystal grains and silicon nanocrystals as the source of the crystal grains 51 and the silicon nanocrystals 6 3, respectively. In the seventh embodiment, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) t-shirt-(Please read the precautions on the back before filling this page) Thread consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative-56- 564454 A7 B7 V. Description of the invention (54) Although all the polycrystalline silicon layer 3 is made porous, only part of the layer may be made porous. (Please read the notes on the back before filling this page.) After the anodizing step has been terminated, the rinse step is performed as in the example of the sixth embodiment. Next, the porous polycrystalline silicon layer 4 is oxidized in the oxidation step for the insulating film formation step, and a drift layer 6 composed of the oxidized porous polycrystalline silicon layer is formed, and the structure shown in FIG. 12C is obtained. In the oxidation step, an oxidation treatment container containing an electrolytic solution (such as diluted sulfuric acid, diluted nitric acid, or aqua regia, for example) is used. Next, a platinum electrode (not shown) is used as the negative electrode and the electronic conductive layer 12 is used as the positive electrode, a fixed current is supplied, and the porous polycrystalline silicon layer 4 is oxidized, thereby forming the crystal grains 5 1 and the silicon nanocrystalline 6 3. And the drift layer 6 of the silicon oxide film 5 2 and 64. After the drift layer 6 has been formed, a surface electrode 7 composed of a gold thin film is formed on the drift layer 6, and an electron source 10 shown in FIG. 12D is obtained. In the seventh embodiment, the surface electrode 7 is formed according to an electron vapor deposition technique. However, the method of forming the surface electrode 7 is not limited to the electron vapor deposition technique, and, for example, a sputtering technique may be used. In this way, in the method for manufacturing the electron source 10 according to the seventh embodiment, as in the example of the sixth embodiment, the step of forming the drift layer 6 includes the anodizing step. A rinsing step, and an insulating film forming step. Therefore, the electrolytic solution remaining in the porous polycrystalline silicon layer 4 formed in the anodizing step can be reduced before the insulating film forming step. In addition, the quality of the insulating films (silicon oxide films 5 2 and 6 4) formed on the surfaces of the silicon nanocrystals 6 3 and the crystal grains 51 can be improved in the insulating film forming step. As a result, the paper size of the electric paper is in accordance with the Chinese National Standard (CNS) A4 (210X297 mm) -57- 564454 A7 B7 V. Description of the invention (55) The dielectric strength of the sub-source 10 can be improved, and the service life can be longer than before Technology extension. (Please read the notes on the back before filling this page.) In the sixth and seventh embodiments, the drift layer 6 is composed of a porous polycrystalline silicon layer. However, this layer may be composed of another oxidized porous semiconductor layer or a nitrided or oxynitride porous semiconductor layer. That is, in the sixth and seventh embodiments, although the insulating film formed in the insulating film forming step is a silicon oxide film, the insulating film may be an oxide film other than a silicon oxide film, a nitride film such as a silicon nitride film, or The oxynitride film is composed of a silicon oxynitride film. A silicon nitride film or a silicon nitride oxide film is used, whereby the dielectric strength voltage can be improved compared to the example of a silicon oxide film. A silicon nitride film or a silicon oxynitride film may be formed by rapid thermal oxidation. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In the sixth and seventh embodiments, gold is used as the material of the surface electrode 7. However, aluminum, chromium, tungsten, nickel, or platinum may be used. Further, the surface electrode 7 may be composed of two thin film layers which are deposited at least in the thickness direction. In the case where the surface electrode 7 is composed of two thin film layers, for example, gold or the like is used as the material of the upper thin film layer. In addition, for example, chromium, nickel, platinum, titanium, or indium is used as the material of the lower film layer (the film layer on the drift layer 6 side). (Eighth Embodiment) Hereinafter, an eighth embodiment of the present invention will be described. However, the electron source and the method of manufacturing the electron source according to the eighth embodiment are identical in basic structure and function to those according to the first embodiment. The eighth embodiment will be described with reference to FIGS. 2A to 2D and FIGS. 3 and 4. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -58- Printed by the Consumer Goods Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs 564454 A7 ____B7_ V. Description of the invention (56) In the eighth embodiment, as in In the first embodiment, a single crystal having a resistivity slightly close to that of a conductor (for example, a resistivity which is substantially (0.10 Ω / cm to 〇2 Ω / cm (1 0 〇) substrate) is used. The η-type silicon substrate is used as the electronic conductive substrate. As shown in FIG. 3, the electron source 10 according to the eighth embodiment is also formed. As in the first embodiment, an n-type silicon substrate 1, an ohmic electrode 2, a drift layer 6, and a surface electrode 7 are formed. The structure and function of these elements are similar to those of the electron source 10 according to the first embodiment. Its description is omitted here. In addition, as shown in Fig. 4, also according to the electron source 10 of the eighth embodiment, the electrons are emitted in a mechanism and mode similar to the example of the first embodiment. Hereinafter, a method of manufacturing the electron source 10 according to the eighth embodiment will be described with reference to FIGS. 2A to 2D. First, the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. Next, on the main surface of the n-type silicon substrate 1, an undoped polycrystalline silicon layer 3 is formed as a semiconductor layer, and the structure shown in FIG. 2A is obtained. For example, a C V D technology, a sputtering technology, or a C G S technology can be used as a method for forming the film of the polycrystalline silicon layer 3. After the non-doped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous according to the anodizing step. In this way, the porous polycrystalline silicon layer 4 which is a porous semiconductor layer is formed, as shown in FIG. 2B The structure is obtained. In the anodizing treatment step, a processing vessel containing an electrolytic solution composed of a mixed solution obtained by mixing a 55: 1 aqueous solution of hydrogen fluoride and ethanol substantially 1: 1 was used. Next, a platinum electrode (not shown) is used as the negative electrode and η This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) ~ -59- (Please read the precautions on the back before filling this page)

564454 Α7 Β7 五、發明説明（57) 型矽基底1 (歐姆電極2 )爲正極，同時對於多晶矽層3 光發射被實行，陽極氧化係以固定電流實行。以此方式， 多孔多晶矽層4被形成。因此形成的多孔多晶矽層4有分 別是矽奈米晶體6 3與晶粒5 1的源極之矽奈米晶體與晶 粒。第八實施例中，雖然所有多晶矽層3被做成多孔，但 也許僅該層的部分被做成多孔。 氧化步驟中，包含電解液（如經稀釋的硫酸，經稀釋 的氮酸，或王水，例如）之氧化處理容器被使用。接著， 由鉑電極（未顯示）爲負極且η型矽基底1 (歐姆電極2 )爲正極，固定電流被供應，且多孔多晶矽層4被氧化， 藉此形成了包含晶粒5 1，矽奈米晶體6 3及氧化矽膜 5 2與6 4之漂流層6。 根據第八實施例之製造方法中，在陽極氧化處理步驟 與氧化步驟間之特定時期期間，自然氧化膜避免被形成於 爲半導體奈米晶體之矽奈米晶體的表面上以便不曝露多孔 多晶矽層4於空氣中。第八實施例中，爲了避免自然氧化 膜係在特定時期形成，多晶矽層3在陽極氧化處理步驟中 被做成多孔，且接著，沖洗係由使用乙醇（例如，如乙醇 ，異丙基乙醇，或甲基乙醇）實行。沖洗後，多孔多晶矽 層4立即被溶於氧化處理容器的電解液中同時它的表面被 覆與乙醇。所以，自然氧化膜可避免被形成於多孔多晶矽 層4上，且污染可被限制。 第八實施例中，乙醇使非氧化液成形。鈍性氣體也許 在特定時期期間被使用作大氣當作避免多孔多晶矽層在特 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I 裝-- (請先閱讀背面之注意事項再填寫本頁) ,ιτ 線 經濟部智慧財產局g(工消費合作社印製 -60- 564454 經濟部智慧財產局R工消費合作社印製 A7 _ B7五、發明説明（58 ) 定時期期間被曝露於空氣中之機構。另外，至少多孔多晶 矽層4也許在特定時期期間被維持在真空中。鈍性氣體在 特定時期期間被使用作大氣，藉此自然氧化膜可避免被形 成，且多孔多晶矽層4的污染可被限制。此外，如果多孔 多晶矽層4被維持在真空中，自然氧化膜可避免被形成， 且雜質可被限制免於附著於多孔多晶矽層4。 漂流層6已被形成後，由金屬薄膜構成之表面電極7 被形成於漂流層6上，且圖2 D所示之電子源1 〇被獲得 。第八實施例中，表面電極7係根據電子氣相沈積技術形 成。然而，形成表面電極7的方法不限於電子氣相沈積技 術，且例如，噴濺技術也許被使用。 以此方式，根據第八實施例製造電子源1 〇的方法中 ，形成漂流層6的步驟包括：根據陽極氧化形成多孔多晶 石夕層4的陽極氧化處理步驟；以及氧化多孔多晶砂層4的 氧化步驟，藉此分別形成氧化矽膜5 2與6 4於晶粒5 1 與矽奈米晶體6 3的表面上。在陽極氧化處理步驟與氧化 步驟間之特定時期期間，自然氧化膜避免被形成於爲半導 體奈米晶體之矽奈米晶體的表面上以便不曝露多孔多晶矽 層4於空氣中。因此，在陽極氧化處理步驟與氧化步驟間 之特定時期期間，自然氧化膜避免被形成於矽奈米晶體 6 3的表面上。結果，於矽奈米晶體的表面上形成之氧化 矽膜的品質可在氧化步驟中被改進。以此方式，電子源 1 0的電介質強度可被改進，且服務壽命可較先前技術延 長。 本紙張尺度適用中國國家標準（CMS) A4規格（210X 297公釐） 一 -61 - (請先閲讀背面之注意事項再填寫本頁) 564454 A7 ___ B7 五、發明説明（59 ) (請先閲讀背面之注意事項再填寫本頁) 根據第八實施例之製造方法製造之電子源i 〇，電子 發射效率係較根據習知製造方法製造之電子源1 〇改進。 此改進的原因如下。也就是，自然氧化膜避免被形成。因 此，漂流層6之氧化砂膜5 2與6 4的各膜厚度的誤差， 氧化矽膜5 2與6 4的缺陷密度，或氧化矽膜6 4與矽奈 米晶體6 3間之臨界表面的缺陷密度及其類似係較習知的 漂流層6 /減少。因此，氧化矽膜6 4的分散或然率可較 先前技藝更顯著地減少，且由於分散之失誤被減少。 (第九實施例） 以下，將說明本發明的第九實施例。然而，根據第九 實施例之電子源與製造電子源的方法在基本架構與功能是 與根據第二實施例的那些一致的。第九實施例將參考圖 1 1與圖1 2A至圖1 2D說明。根據第九實施例之電子 源與製造方法對根據第八實施例的那些有許多共通點。 經濟部智慧財產局員工消費合作社印製 第九實施例中，使用了於由金屬膜（例如，鎢層）構 成之電子導電層被提供於由玻璃基底構成之絕緣基底的一 表面上之基底當作電子導電基底。在電子導電層被形成於 絕緣基底的表面側上之基底因此被使用之例子中，電子源 的成本減少與較大面積較如第八實施例用作電子導電基底 之半導體基底之例子可能。 如圖1 1所示，同樣地根據第九實施例之電子源1 〇 中，實質上是類似於第二實施例，有絕緣基底1 1 ，電子 導電層1 2，漂流層6，與表面電極7。這些元件的結構 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -62- 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（60 ) 與功能是類似於根據第二實施例之電子源1 0的那些。其 說明在此被省略。 同樣根據第九實施例之電子源1 0中，電子係在類似 於第二實施例的例子之機制與模式發射。 在根據第九實施例電子源1 0被利用作顯示器的電子 源之例子中，下電極與表面電極7或其類似也許被適當地 型樣。 以下，根據第九實施例製造電子源1 0的方法將參考 圖1 2A至圖1 2D說明。 首先，在絕緣基底1 1的一表面上，由金屬膜（例如 ，鎢膜）構成之電子導電層1 2係根據噴濺技術形成，且 電子導電基底被製造。接著，在電子導電基底（電子導電 層1 2上）的主要表面側上，經非摻雜的多晶矽層3被形 成作半導體層，且圖1 2 A所示之結構被獲得。例如，使 用C V D技術，噴濺技術或C G S技術與其類似當作形成 多晶矽層3之膜的方法。 非經摻雜的多晶矽層3已被形成後，多晶矽層3在陽 極氧化處理步驟中被做成多孔。以此方式，爲多孔半導體 層之多孔多晶矽層4被形成，且圖1 2 B所示之結構被獲 得。陽極氧化處理步驟中，使用了包含由實質上1 : 1混 合5 5 w t %氟化氫水溶液與乙醇獲得之混合液構成之 電解液之處理容器。由鉑電極（未顯示）爲負極且電子導 電層1 2爲正極，同時光發射對於多晶矽層3實行，陽極 氧化處理係以固定電流實行，藉此多孔多晶矽層4被形成 (請先閱讀背面之注意事項再填寫本頁) 、11 本紙張尺度適用中國國家標準（GNS ) A4規格（210X29*7公釐） -63- 564454 A7 B7 五、發明説明（61) (請先閱讀背面之注意事項再填寫本頁) 。因此形成的多孔多晶矽層4有分別爲晶粒5 1與矽奈米 晶體6 3的源極之晶粒與矽奈米晶體。第九實施例中，雖 然所有多晶矽層3被做成多孔，但也許僅該層的部分被做 成多孔。 陽極氧化處理步驟已終止後，多孔多晶矽層4係在爲 氧化步驟中氧化。以此方式，由經氧化的多孔多晶矽層構 成之漂流層6被形成，且圖1 2 C所示之結構被獲得。 氧化步驟中，包含電解液（如經稀釋的硫酸，經稀釋 的氮酸，或王水，例如）之氧化處理容器被使用。接著， 由鉑電極（未顯示）爲負極且電子導電層1 2爲正極，固 定電流被供應，且多孔多晶矽層4被氧化，藉此，包含晶 粒5 1 ，矽奈米晶體6 3及氧化矽膜5 2與6 4之漂流層 6被形成。在根據第九實施例之製造方法中，如在第八實 施例的例子，自然氧化膜係避免被形成於爲半導體奈米晶 體之矽奈米晶體的表面上以便不在陽極氧化處理步驟與氧 化步驟間之特定時期期間曝露爲多孔半導體層之多孔多晶 石夕層4至空氣中。 經濟部智惡財產局員工消費合作社印製 漂流層6已被形成後，由金薄膜構成之表面電極7被 形成於漂流層6上，且圖1 2 D所示之電子源1 〇被獲得 。第九實施例中，表面電極7係根據電子氣相沈積技術形 成。然而，形成表面電極7的方法不限於電子氣相沈積技 術，且例如，噴濺技術也許被使用。 以此方式，根據第九實施例製造電子源1 〇的方法中 ，形成漂流層6的步驟包括：由陽極氧化處理形成多孔多 本紙張尺度適用中國國家標準（ CNS ) A4規格（210X 297公慶） -64- 564454 A7 B7 五、發明説明（62 ) (請先閲讀背面之注意事項再填寫本頁) 晶矽層4的陽極氧化處理步驟以及氧化多孔多晶矽層4的 氧化步驟，藉此分別形成氧化矽膜5 2與6 4於晶粒5 1 與矽奈米晶體6 3的表面上。接著，在陽極氧化處理步驟 與氧化步驟間之特定時期期間，自然氧化膜避免被形成於 矽奈米晶體6 3的表面上以便不曝露多孔多晶矽層4於空 氣中。因此，在陽極氧化處理步驟與氧化步驟間之特定時 期期間，自然氧化膜避免被形成於矽奈米晶體6 3的表面 上。此外，氧化步驟中於矽奈米晶體的表面上形成之氧化 矽膜的品質可被改進。結果，電子源1 0的電介質強度可 被改進，且服務壽命可較先前技術延長。 根據第九實施例之製造方法製造之電子源1 0，電子 發射效率係較根據習知製造方法製造之電子源1 〇 /改進 。此改進的原因類似於第八實施例的例子。 第八與第九實施例中，漂流層6係由多孔多晶矽層構 成的，此層也許係由其它經氧化的多孔半導體層構成的。 經濟部智慧財產局員工消費合作社印製 第八與第九實施例中，金被使用成表面電極7之材料 。然而，表面電極7的材料不限於金，且例如，鋁，鉻， 鎢，鎳，或鉑與其類似也許被使用。此外，表面電極7也 許係由至少以厚度方向沈澱之兩層的薄膜層構成的。在表 面電極7係由兩層的薄膜層構成的例子中，例如，金或其 類似被用作上薄膜層之材料。此外，例如，鉻，鎳，鉑， 鈦’或銦與其類似被用作下薄膜層之材料（在漂流層6側 之薄膜層）。 本紙張尺度適用巾酬家辟（CNS ) A4規格（2Κ)Χ 297公f ) -65- 564454 Α7 _ Β7 五、發明説明（63 ) (第十實施例） (請先閲讀背面之注意事項再填寫本頁) 以下，將說明本發明的第十實施例。根據第十實施例 電子源與製造電子源的方法在基本架構與功能是與根據第 一實施例的那些一致的。第十實施例將參考圖2 A至圖2 D及圖3與圖4說明。 第十實施例中，如在第一實施例中，使用了電阻率稍 微接近導體的電阻率（例如，電阻率實質上是〇 . 0 1 Ω / c m至〇 . 〇 2 Ω / c m之（1 〇 〇 )基底）之單晶η 型矽基底當作電子導電基底。 如圖3所示，同樣根據第十實施例之電子源1 0，如 在第一實施例中，形成了 η型矽基底1 ，歐姆電極2，漂 流層6，與表面電極7。這些元件的結構與功能類似於根 據第一實施例之電子源1 〇的那些。其說明在此省略。 此外，如圖4所示，同樣地根據第十實施例之電子源 1 0，電子係以類似於第一實施例的例子之機制與模式發 射。 經濟部智慧財產局3工消費合作社印製 以下，根據第十實施例製造電子源1 〇的方法將參考 圖2Α至圖2D說明。 首先，歐姆電極2被形成於η型矽基底1的背面。接 著，η型矽基底1的主要表面上，預定膜厚度（例如， 1 · 5 // m )的非經摻雜的多晶矽層3係根據，例如， L P C V D技術形成，且圖2 A所示之結構被獲得。形成 多晶矽層3之膜之條件如下。真空的程度是2 0 Pa。 基底溫度是6 4 〇 °C。單矽烷氣體的流率在標準狀態是 本紙張ϋ適用中國國家標準（CNS ) A4規格（210X297公釐） " -66 - 564454 Α7 Β7 五、發明説明（64) (請先閱讀背面之注意事項再填寫本頁) 0.6 L / m i η ( 6 0 0 s c c m )。形成多晶石夕 層3之膜的方法，例如，使用了 C V D技術，噴濺技術， 或C G S技術與其類似。 非經摻雜的多晶矽層3已被形成後，多晶矽層3在陽 極氧化處理步驟中被做成多孔。以此方式，爲多孔半導體 層之多孔多晶矽層4被形成，且圖2 B所示之結構被獲得 。陽極氧化處理步驟中，使用了包含由實質上1:1混合 5 5 w t %氟化氫水溶液與乙醇獲得之混合液構成之電 解液之處理容器。接著，由鉑電極（未顯示）爲負極且由 η型矽基底1與歐姆電極2構成之下電極爲正極，同時光 發射對於多晶矽層3實行，陽極氧化處理係以固定電流實 行，藉此多孔多晶矽層4被形成。因此形成的多孔多晶矽 層4包含多晶矽晶粒與矽奈米晶體。第十實施例中，陽極 氧化處理之條件如下。電流密度爲固定之3 0 m A / c m 2。陽極氧化時間是1 0秒。陽極氧化處理期間，光 發射係由5 0 0 W燈實行於多晶矽層3的表面上。 經濟部智慧財產局8工消費合作社印製 陽極氧化處理步驟已終止後，多孔多晶矽層4係在爲 氧化步驟中氧化。以此方式，由經氧化的多孔多晶矽層構 成之漂流層6被形成，且圖2 C所示之結構被獲得。 氧化步驟中，例如，使用了包含由溶解0 · 0 4莫耳 /公升（以下， ''莫耳/公升〃被稱爲％ Μ 〃 ）的硝酸鉀 (溶質）於電解液（有機溶劑）之處理容器。接著，由鉑 電極（未顯示）爲負極（陰極）且由η型矽基底1與歐姆 電極2構成之下電極爲正極（陽極）’固定電流被供應’ 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨〇 X 297公釐） -67- 564454 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（65) 且多孔多晶矽層4被電化地氧化，藉此由晶粒5 1 ，矽奈 米晶體6 3，及氧化矽膜5 2與6 4構成之漂流層6被形 成。也就是，第十實施例中，多孔多晶矽層4係由使用不 包含水之電解液電化地氧化。 第十實施例的氧化步驟中，0 · 1 m A / c m 2的 固定電流被供應直到正極與負極間之電壓上升至2 Ο V ，藉此多孔多晶矽層4被氧化。然而，此條件如需要也許 被改變。例如，氧化已以固定電流實行直到正極與負極間 之電壓上升至預定電壓（例如，20 V)後，正極與負 極間之電壓被維持在以上預定電壓。接著，當化學合成電 流密度降低至預定値（例如，0 . 0 1 m A / c m 2 ) ，電源供應也許被停止。由如此做，在漂流層6中，接近 η型矽基底1之區域之氧化矽膜5 2與6 4的精細度可被 改進。 漂流層6已被形成後，由金屬薄膜構成之表面電極7 係根據，例如，氣相沈積技術形成於漂流層6上，且圖2 D所示之電子源1 〇被獲得。 根據製造以上電子源1 0的方法，當漂流層6被形成 時，爲多孔半導體層之多孔多晶矽層4係在由溶解溶質於 有機溶劑（主要氧化處理步驟）獲得之電解液中電化地氧 化。因此，發射電流或電子發射效率與其類似被改進，且 對於電子源1 0的電子發射特徵隨時間的經過之穩定性被 改進。（所以，電子源1 〇的服務壽命可被延長）。如較 先前技藝，電子發射特徵被改進及隨時間的經過之穩定性 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -68- 564454 A7 B7 五、發明説明（66) (請先閱讀背面之注意事項再填寫本頁) 被改進，因爲無水存於氧化步驟中使用之電解液，且氧化 矽膜5 2與6 4的精細度被增加，藉此氧化矽膜5 2與 6 4的電介質強度被改進。此外，電子發射效率係較先前 技藝改進。這是因爲由於漂流層6之氧化矽膜5 2之電子 分散之能量損失被減少。 此外，多孔多晶矽層4係在氧化步驟中快速地熱氧化 ，藉此處理溫度可較形成漂流層之處理減少，且較大面積 與成本減少可被輕易地達成。即，由於經降低的處理溫度 ，基底材料之限制被減少。這使使用大面積，不貴的玻璃 基底（例如，如無鹼玻璃基底，低鹼玻璃基底，或納石灰 玻璃基底）變可能。在此玻璃基底被使用之例子中，由電 子導電材料構成之下電極也許被形成於玻璃基底的一表面 上。 經濟部智慈財產局員工消費合作社印製 根據上述製造方法製造之電子源1 0中，漂流層6係 在由溶解溶質於有機溶劑中獲得之電解液中根據包含電化 地氧化爲多孔半導體層之多孔多晶矽層4的氧化步驟之處 理形成。因此，不像先前技藝，發射電流或電子發射效率 與其類似可較在由水溶液如硫酸或氮酸構成之電解液中由 電化地氧化多孔多晶矽層形成之漂流層之電子源改進。進 一步，對於電子發射特徵隨時間的經過之穩定性可被改進 〇 上述氧化步驟使用之電解液之有機溶劑不限於乙燒乙 二醇。例如，也許使用了一或兩種有機溶劑如乙烯乙二醇 ，甲醇，乙醇，丙醇，丁醇，二乙烯乙二醇，甲氧基乙醇 本紙張尺度適用中國國家標準（CNS ) A4規格(210X297公釐） '" -69- 564454 A7 B7 五、發明説明（67) ’甘油，聚乙烯乙二醇，二甲基甲醛，丙烯乙二醇，2 -乙氧基乙醇’丁基內酯，戊內酯，乙烯碳酸鹽，丙烯碳酸 鹽’甲基乙醯胺，二甲基乙醯胺，氫糠基醇的混合液體。 電解液的溶質不限於硝酸鉀。也許使用了一或兩種酸如氫 氧化物，氯化物，碳酸，硫酸，硝酸，磷酸，鉻酸，酒石 酸，氫氯酸，溴酸，丙二酸，己二酸，羊脂酸，壬酸，棕 櫚酸，油酸，walitilic酸，羧酸，安息香酸，間苯二酚酸 ’枯酸，檸檬酸，蘋果酸，琥珀酸，庚二酸，辛二酸，壬 二酸，癸二酸，順丁烯二酸，反丁烯二酸，檸檬酸，硼酸 ’鎢酸，鉬酸，或釩酸的混合。此外，也許使用了 一或兩 種鹽如碳酸鹽，硫酸鹽，硝酸鹽，磷酸鹽，鉻酸鹽，酒石 酸鹽，氫氯酸鹽，溴酸鹽，丙二酸鹽，己二酸鹽，羊脂酸 鹽，壬酸鹽，棕櫚酸鹽，油酸鹽，walitilic酸鹽，羧酸鹽 ，安息香酸鹽，間苯二酚酸鹽，枯酸鹽，檸檬酸鹽，蘋果 酸鹽，琥珀酸鹽，庚二酸鹽，辛二酸鹽，壬二酸鹽，癸二 酸鹽，順丁烯二酸鹽，反丁烯二酸鹽，檸檬酸鹽，硼酸鹽 ，鎢酸鹽，鉬酸鹽，或釩酸鹽的混合。也許使用了 一或兩 種鹽如氫氧化鈉，氫化鉀，氫化鋰，氫化鈣，氯化鈉，氯 化鉀，氯化鎂，氯化鋁，硫酸鈉，硫酸鎂，硝酸鋰，硝酸 鉀，硝酸鈉，硝酸鈣，或酒石酸銨的混合。 同時，如在第十實施例中，在多孔多晶矽層4係由使 用包含鹼金屬如硝酸鉀在主要氧化處理步驟中電化地氧化 之例子中，有雜質如驗金屬被混合在多孔多晶砂層4之危 險。因此，想要淸洗多孔多晶矽層4之淸洗處理被實行。 本紙張尺度適用中國國家標準（CNS ) Α4規格（21 ο X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝.564454 Α7 Β7 V. Description of the invention (57) Silicon substrate 1 (ohmic electrode 2) is the positive electrode, and at the same time, light emission is performed for polycrystalline silicon layer 3, and anodization is performed at a fixed current. In this manner, a porous polycrystalline silicon layer 4 is formed. The porous polycrystalline silicon layer 4 thus formed is the silicon nanocrystals and crystal grains of the source of the silicon nanocrystals 6 3 and the crystal grains 51. In the eighth embodiment, although all the polycrystalline silicon layer 3 is made porous, only a part of the layer may be made porous. In the oxidation step, an oxidation treatment container containing an electrolytic solution (such as diluted sulfuric acid, diluted nitric acid, or aqua regia, for example) is used. Next, a platinum electrode (not shown) is used as the negative electrode and the n-type silicon substrate 1 (the ohmic electrode 2) is used as the positive electrode. A fixed current is supplied and the porous polycrystalline silicon layer 4 is oxidized, thereby forming a silicon-containing polycrystalline silicon 51. Rice crystal 6 3 and drift layer 6 of silicon oxide films 5 2 and 64. In the manufacturing method according to the eighth embodiment, during a specific period between the anodizing treatment step and the oxidation step, the natural oxide film is prevented from being formed on the surface of the silicon nanocrystal which is a semiconductor nanocrystal so as not to expose the porous polycrystalline silicon layer. 4 in the air. In the eighth embodiment, in order to avoid the formation of a natural oxide film at a specific period, the polycrystalline silicon layer 3 is made porous in the anodizing step, and then, the washing system is made of ethanol (for example, ethanol, isopropyl alcohol, etc.). Or methyl alcohol). Immediately after the rinsing, the porous polycrystalline silicon layer 4 was dissolved in the electrolytic solution of the oxidation treatment container while its surface was covered with ethanol. Therefore, the natural oxide film can be prevented from being formed on the porous polycrystalline silicon layer 4, and pollution can be restricted. In the eighth embodiment, ethanol is used to form a non-oxidizing liquid. The inert gas may be used as the atmosphere during certain periods to avoid porous polycrystalline silicon layers. In the special paper size, the Chinese National Standard (CNS) A4 specification (210X297 mm) is installed. I installed-(Please read the precautions on the back first. (Fill in this page), ιτ line Intellectual Property Bureau of the Ministry of Economic Affairs (printed by the Industrial and Consumer Cooperatives-60- 564454 printed by the Intellectual Property Bureau of the Ministry of Economics and printed by R Industrial Consumer Cooperatives A7 _ B7 V. Description of the invention (58) was exposed during a certain period of time Mechanisms in the air. In addition, at least the porous polycrystalline silicon layer 4 may be maintained in a vacuum during a specific period of time. A passive gas is used as the atmosphere during a specific period of time, thereby preventing the formation of a natural oxide film, and the porous polycrystalline silicon layer 4 Pollution can be limited. In addition, if the porous polycrystalline silicon layer 4 is maintained in a vacuum, a natural oxide film can be prevented from being formed, and impurities can be restricted from being attached to the porous polycrystalline silicon layer 4. After the drift layer 6 has been formed, the A surface electrode 7 made of a metal thin film is formed on the drift layer 6, and an electron source 10 shown in FIG. 2D is obtained. In the eighth embodiment, the surface electrode 7 is a root The electron vapor deposition technique is formed. However, the method of forming the surface electrode 7 is not limited to the electron vapor deposition technique, and for example, a sputtering technique may be used. In this manner, in the method of manufacturing the electron source 10 according to the eighth embodiment The step of forming the drift layer 6 includes: an anodizing step of forming the porous polycrystalline stone layer 4 according to anodization; and an oxidation step of oxidizing the porous polycrystalline sand layer 4 to form silicon oxide films 5 2 and 64 respectively. The surfaces of the grains 5 1 and the silicon nanocrystals 6 3. During a certain period between the anodizing step and the oxidation step, a natural oxide film is prevented from being formed on the surface of the silicon nanocrystals that are semiconductor nanocrystals so that The porous polycrystalline silicon layer 4 is not exposed to the air. Therefore, during a specific period between the anodizing step and the oxidation step, a natural oxide film is prevented from being formed on the surface of the silicon nanocrystal 6 3. The quality of the silicon oxide film formed on the surface can be improved in the oxidation step. In this way, the dielectric strength of the electron source 10 can be improved, and the service can be improved. The service life can be extended compared with the previous technology. This paper size applies the Chinese National Standard (CMS) A4 specification (210X 297 mm) I-61-(Please read the precautions on the back before filling this page) 564454 A7 ___ B7 V. Description of the invention (59) (Please read the precautions on the back before filling in this page.) The electron source i 〇 manufactured according to the manufacturing method of the eighth embodiment has improved electron emission efficiency compared to the electron source 1 〇 manufactured according to the conventional manufacturing method. The reason for the improvement is as follows. That is, the natural oxide film is prevented from being formed. Therefore, the error in the thickness of each of the oxide sand films 5 2 and 64 of the drift layer 6, the defect density of the silicon oxide films 5 2 and 64, or the oxidation The defect density at the critical surface between the silicon film 64 and the silicon nanocrystal 63 is similar to that of the conventional drift layer 6 / reduction. Therefore, the dispersion probability of the silicon oxide film 64 can be reduced more significantly than in the prior art, and errors due to dispersion are reduced. (Ninth Embodiment) Hereinafter, a ninth embodiment of the present invention will be described. However, the electron source and the method of manufacturing the electron source according to the ninth embodiment are identical in basic structure and function to those according to the second embodiment. The ninth embodiment will be described with reference to FIGS. 11 and 12A to 12D. The electron source and manufacturing method according to the ninth embodiment have many points in common with those according to the eighth embodiment. In the ninth embodiment printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a substrate using an electronic conductive layer composed of a metal film (for example, a tungsten layer) provided on a surface of an insulating substrate composed of a glass substrate is used. As an electronically conductive substrate. In the example in which the electronically conductive layer is formed on the surface side of the insulating substrate and therefore the cost of the electron source is reduced and the area is larger than that of the semiconductor substrate used as the electronically conductive substrate of the eighth embodiment, it is possible. As shown in FIG. 11, the electron source 10 according to the ninth embodiment is also similar to the second embodiment, and has an insulating substrate 1 1, an electronic conductive layer 12, a drift layer 6, and a surface electrode. 7. The structure of these components is based on the Chinese national standard (CNS) A4 specification (210X 297 mm) -62- 564454 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (60) and the function are similar Those of the electron source 10 according to the second embodiment. Its description is omitted here. Also in the electron source 10 according to the ninth embodiment, the electrons are emitted in a mechanism and mode similar to the example of the second embodiment. In the example where the electron source 10 according to the ninth embodiment is used as the electron source of the display, the lower electrode and the surface electrode 7 or the like may be appropriately shaped. Hereinafter, a method of manufacturing the electron source 10 according to the ninth embodiment will be described with reference to FIGS. 12A to 12D. First, on one surface of the insulating substrate 11, an electronic conductive layer 12 made of a metal film (for example, a tungsten film) is formed according to a sputtering technique, and an electronic conductive substrate is manufactured. Next, on the main surface side of the electronic conductive substrate (on the electronic conductive layer 12), an undoped polycrystalline silicon layer 3 is formed as a semiconductor layer, and the structure shown in FIG. 12A is obtained. For example, a method of forming a film of the polycrystalline silicon layer 3 using CVD technology, sputtering technology, or CGS technology is similar thereto. After the undoped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous in the anode oxidation treatment step. In this way, a porous polycrystalline silicon layer 4 which is a porous semiconductor layer is formed, and the structure shown in Fig. 12B is obtained. In the anodizing step, a processing container containing an electrolytic solution composed of a mixed liquid obtained by mixing a 1: 1 substantially 5% wt% hydrogen fluoride aqueous solution and ethanol was used. A platinum electrode (not shown) is used as the negative electrode and the electronic conductive layer 12 is used as the positive electrode. At the same time, the light emission is performed on the polycrystalline silicon layer 3, and the anodizing treatment is performed with a fixed current. Note: Please fill in this page again), 11 This paper size applies Chinese National Standard (GNS) A4 specification (210X29 * 7mm) -63- 564454 A7 B7 V. Description of invention (61) (Please read the precautions on the back before Fill out this page). The porous polycrystalline silicon layer 4 thus formed has crystal grains of silicon 51 and source of silicon nanocrystals 6 3 and silicon nanocrystals, respectively. In the ninth embodiment, although all the polycrystalline silicon layer 3 is made porous, only a part of the layer may be made porous. After the anodizing step has been terminated, the porous polycrystalline silicon layer 4 is oxidized in the oxidation step. In this manner, the drift layer 6 composed of the oxidized porous polycrystalline silicon layer is formed, and the structure shown in Fig. 12C is obtained. In the oxidation step, an oxidation treatment container containing an electrolytic solution (such as diluted sulfuric acid, diluted nitric acid, or aqua regia, for example) is used. Next, a platinum electrode (not shown) is used as the negative electrode and the electronic conductive layer 12 is used as the positive electrode, a fixed current is supplied, and the porous polycrystalline silicon layer 4 is oxidized, thereby including the crystal grain 5 1, the silicon nanocrystal 6 3, and the oxidation. The drift layers 6 of the silicon films 52 and 64 are formed. In the manufacturing method according to the ninth embodiment, as in the example of the eighth embodiment, the natural oxide film is prevented from being formed on the surface of the silicon nanocrystal which is a semiconductor nanocrystal so as not to be anodized and oxidized. During a certain period of time, the porous polycrystalline stone layer 4 which is a porous semiconductor layer is exposed to the air. Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs After the drift layer 6 has been formed, a surface electrode 7 composed of a thin gold film is formed on the drift layer 6 and an electron source 10 shown in FIG. 12D is obtained. In the ninth embodiment, the surface electrode 7 is formed according to an electron vapor deposition technique. However, the method of forming the surface electrode 7 is not limited to the electron vapor deposition technique, and, for example, a sputtering technique may be used. In this way, in the method of manufacturing the electron source 10 according to the ninth embodiment, the step of forming the drift layer 6 includes: forming a porous multi-sheet by anodizing treatment, and applying the Chinese National Standard (CNS) A4 specification (210X 297) ) -64- 564454 A7 B7 V. Description of the invention (62) (Please read the precautions on the back before filling this page) Anodizing step of crystalline silicon layer 4 and oxidation step of oxidizing porous polycrystalline silicon layer 4, respectively, to form separately Silicon oxide films 5 2 and 6 4 are on the surfaces of the crystal grains 5 1 and the silicon nanocrystals 6 3. Next, during a specific period between the anodizing step and the oxidizing step, a natural oxide film is prevented from being formed on the surface of the silicon nanocrystals 63 so that the porous polycrystalline silicon layer 4 is not exposed to the air. Therefore, the natural oxide film is prevented from being formed on the surface of the silicon nanocrystal 63 during a specific period between the anodizing step and the oxidizing step. In addition, the quality of the silicon oxide film formed on the surface of the silicon nanocrystal in the oxidation step can be improved. As a result, the dielectric strength of the electron source 10 can be improved, and the service life can be extended compared to the prior art. The electron emission efficiency of the electron source 10 manufactured by the manufacturing method of the ninth embodiment is 10 / improved over that of the electron source manufactured by the conventional manufacturing method. The reason for this improvement is similar to the example of the eighth embodiment. In the eighth and ninth embodiments, the drift layer 6 is composed of a porous polycrystalline silicon layer, and this layer may be composed of other oxidized porous semiconductor layers. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In the eighth and ninth embodiments, gold is used as the material of the surface electrode 7. However, the material of the surface electrode 7 is not limited to gold, and, for example, aluminum, chromium, tungsten, nickel, or platinum similar thereto may be used. In addition, the surface electrode 7 may be composed of two thin film layers that are deposited at least in the thickness direction. In the case where the surface electrode 7 is composed of two thin film layers, for example, gold or the like is used as the material of the upper thin film layer. Further, for example, chromium, nickel, platinum, titanium 'or indium and the like are used as the material of the lower film layer (thin film layer on the drift layer 6 side). This paper size applies to towels (CNS) A4 size (2K) X 297 male f) -65- 564454 Α7 _ Β7 V. Description of the invention (63) (Tenth embodiment) (Please read the precautions on the back before (Fill in this page) Hereinafter, a tenth embodiment of the present invention will be described. According to the tenth embodiment, the basic structure and functions of the electron source and the method of manufacturing the electron source are consistent with those according to the first embodiment. The tenth embodiment will be described with reference to FIGS. 2A to 2D and FIGS. 3 and 4. In the tenth embodiment, as in the first embodiment, a resistivity slightly close to that of the conductor is used (for example, the resistivity is substantially from 0.01 Ω / cm to 0.02 Ω / cm (1 〇〇) substrate) single crystal n-type silicon substrate as an electronically conductive substrate. As shown in FIG. 3, the electron source 10 according to the tenth embodiment is also formed. As in the first embodiment, an n-type silicon substrate 1, an ohmic electrode 2, a drift layer 6, and a surface electrode 7 are formed. The structure and function of these elements are similar to those of the electron source 10 according to the first embodiment. Its description is omitted here. In addition, as shown in FIG. 4, similarly, according to the electron source 10 of the tenth embodiment, electrons are emitted in a mechanism and mode similar to the example of the first embodiment. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Industrial Cooperative Cooperative, the method of manufacturing the electron source 10 according to the tenth embodiment will be described with reference to FIGS. 2A to 2D. First, the ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. Next, on the main surface of the n-type silicon substrate 1, an undoped polycrystalline silicon layer 3 having a predetermined film thickness (for example, 1 · 5 // m) is formed according to, for example, LPCVD technology, and shown in FIG. 2A The structure is obtained. The conditions for forming the film of the polycrystalline silicon layer 3 are as follows. The degree of vacuum is 20 Pa. The substrate temperature was 64 ° C. The flow rate of monosilane gas is standard in this paper. Applicable to China National Standard (CNS) A4 specification (210X297 mm) " -66-564454 Α7 Β7 V. Description of the invention (64) (Please read the notes on the back first Fill out this page again) 0.6 L / mi η (6 0 0 sccm). The method of forming the polycrystalline layer 3 film, for example, uses a CVD technique, a sputtering technique, or a CGS technique similar thereto. After the undoped polycrystalline silicon layer 3 has been formed, the polycrystalline silicon layer 3 is made porous in the anode oxidation treatment step. In this way, a porous polycrystalline silicon layer 4 which is a porous semiconductor layer is formed, and the structure shown in FIG. 2B is obtained. In the anodizing step, a processing vessel containing an electrolytic solution composed of a mixed solution obtained by mixing a 55 wt% aqueous solution of hydrogen fluoride and ethanol substantially 1: 1 was used. Next, a platinum electrode (not shown) is used as the negative electrode and the lower electrode is composed of the η-type silicon substrate 1 and the ohmic electrode 2 as the positive electrode. At the same time, light emission is performed on the polycrystalline silicon layer 3. The anodizing treatment is performed at a fixed current to thereby make the porous A polycrystalline silicon layer 4 is formed. The porous polycrystalline silicon layer 4 thus formed includes polycrystalline silicon grains and silicon nanocrystals. In the tenth embodiment, the conditions of the anodizing treatment are as follows. The current density is fixed at 30 m A / c m 2. The anodizing time is 10 seconds. During the anodizing process, a light emitting system was performed on the surface of the polycrystalline silicon layer 3 by a 500 W lamp. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Industrial Cooperative Cooperative. After the anodizing step has been terminated, the porous polycrystalline silicon layer 4 is oxidized in the oxidation step. In this manner, the drift layer 6 composed of the oxidized porous polycrystalline silicon layer is formed, and the structure shown in Fig. 2C is obtained. In the oxidation step, for example, potassium nitrate (a solute) containing 0.44 mol / liter (hereinafter referred to as “mol / liter” is referred to as “% Μ”) is used in an electrolytic solution (organic solvent). Handle the container. Next, the platinum electrode (not shown) is the negative electrode (cathode) and the η-type silicon substrate 1 and the ohmic electrode 2 are used. The lower electrode is the positive electrode (anode). 'Fixed current is supplied.' This paper applies Chinese national standards (CNS) Α4 specifications (2 丨 〇X 297 mm) -67- 564454 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (65) And the porous polycrystalline silicon layer 4 is electrochemically oxidized, whereby the crystal grains 5 1, a silicon nanocrystal 6 3, and a drift layer 6 composed of silicon oxide films 5 2 and 64 are formed. That is, in the tenth embodiment, the porous polycrystalline silicon layer 4 is electrochemically oxidized by using an electrolytic solution containing no water. In the oxidation step of the tenth embodiment, a fixed current of 0 · 1 m A / cm 2 is supplied until the voltage between the positive electrode and the negative electrode rises to 20 V, whereby the porous polycrystalline silicon layer 4 is oxidized. However, this condition may be changed if necessary. For example, oxidation has been performed at a fixed current until the voltage between the positive and negative electrodes rises to a predetermined voltage (for example, 20 V), and then the voltage between the positive and negative electrodes is maintained at the above predetermined voltage. Then, when the current density of the chemical synthesis is reduced to a predetermined value (for example, 0.01 m A / c m 2), the power supply may be stopped. By doing so, in the drift layer 6, the fineness of the silicon oxide films 5 2 and 64 in a region close to the n-type silicon substrate 1 can be improved. After the drift layer 6 has been formed, the surface electrode 7 composed of a metal thin film is formed on the drift layer 6 according to, for example, a vapor deposition technique, and the electron source 10 shown in FIG. 2D is obtained. According to the method of manufacturing the above electron source 10, when the drift layer 6 is formed, the porous polycrystalline silicon layer 4 which is a porous semiconductor layer is electrochemically oxidized in an electrolytic solution obtained by dissolving a solute in an organic solvent (the main oxidation treatment step). Therefore, the emission current or the electron emission efficiency is improved similarly, and the stability of the electron emission characteristics of the electron source 10 over time is improved. (So, the service life of the electron source 10 can be extended). If compared with the previous technology, the electron emission characteristics have been improved and the stability over time. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) -68 -564454 A7 B7 V. Description of the invention (66) (Please read the precautions on the back before filling in this page) It has been improved because no water exists in the electrolyte used in the oxidation step, and the fineness of the silicon oxide films 5 2 and 6 4 The degree is increased, whereby the dielectric strength of the silicon oxide films 52 and 64 is improved. In addition, the electron emission efficiency is improved compared to the prior art. This is because the energy loss due to the electron dispersion of the silicon oxide film 52 of the drift layer 6 is reduced. In addition, the porous polycrystalline silicon layer 4 is rapidly thermally oxidized in the oxidation step, whereby the processing temperature can be reduced compared to the processing for forming the drift layer, and a larger area and cost reduction can be easily achieved. That is, restrictions on the base material are reduced due to the reduced processing temperature. This makes it possible to use large-area, inexpensive glass substrates (for example, alkali-free glass substrates, low-alkali glass substrates, or soda-lime glass substrates). In this example where a glass substrate is used, a lower electrode composed of an electrically conductive material may be formed on one surface of the glass substrate. In the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the electron source 10 manufactured according to the above-mentioned manufacturing method is used. The process of the oxidation step of the porous polycrystalline silicon layer 4 is formed. Therefore, unlike the prior art, the emission current or electron emission efficiency is similar to that of the electron source of the drift layer formed by electrochemically oxidizing the porous polycrystalline silicon layer in an electrolytic solution composed of an aqueous solution such as sulfuric acid or nitric acid. Further, the stability of the electron emission characteristics over time can be improved. The organic solvent of the electrolytic solution used in the above oxidation step is not limited to ethylene glycol. For example, one or two organic solvents such as ethylene glycol, methanol, ethanol, propanol, butanol, diethylene glycol, and methoxyethanol may be used. This paper is sized for the Chinese National Standard (CNS) A4 ( 210X297 mm) '" -69- 564454 A7 B7 V. Description of the invention (67)' Glycerin, polyethylene glycol, dimethyl formaldehyde, propylene glycol, 2-ethoxyethanol 'butyl lactone , Valprolactone, ethylene carbonate, propylene carbonate 'methylacetamide, dimethylacetamide, a mixed liquid of hydrogen furfuryl alcohol. The solute of the electrolytic solution is not limited to potassium nitrate. May use one or two acids such as hydroxide, chloride, carbonic acid, sulfuric acid, nitric acid, phosphoric acid, chromic acid, tartaric acid, hydrochloric acid, bromic acid, malonic acid, adipic acid, capric acid, nonanoic acid , Palmitic acid, oleic acid, walitilic acid, carboxylic acid, benzoic acid, resorcinol 'cumic acid, citric acid, malic acid, succinic acid, pimelic acid, suberic acid, azelaic acid, sebacic acid, A blend of maleic acid, fumaric acid, citric acid, boric acid'tungstic acid, molybdic acid, or vanadic acid. In addition, one or two salts such as carbonate, sulfate, nitrate, phosphate, chromate, tartrate, hydrochloride, bromate, malonate, adipate, sheep may be used Fatty acid salt, nonanoate salt, palmitate salt, oleate salt, walitilic acid salt, carboxylate salt, benzoate salt, resorcinolate salt, citrate salt, citrate salt, malate salt, succinate salt , Pimelate, suberate, azelate, sebacate, maleate, fumarate, citrate, borate, tungstate, molybdate, Or a blend of vanadates. Maybe use one or two salts like sodium hydroxide, potassium hydride, lithium hydride, calcium hydride, sodium chloride, potassium chloride, magnesium chloride, aluminum chloride, sodium sulfate, magnesium sulfate, lithium nitrate, potassium nitrate, sodium nitrate , Calcium nitrate, or ammonium tartrate. Meanwhile, as in the tenth embodiment, in the example in which the porous polycrystalline silicon layer 4 is electrochemically oxidized by using an alkali metal such as potassium nitrate in the main oxidation treatment step, impurities such as test metals are mixed in the porous polycrystalline sand layer 4 Of danger. Therefore, a cleaning process for cleaning the porous polycrystalline silicon layer 4 is performed. This paper size applies to Chinese National Standard (CNS) Α4 specification (21 ο X 297 mm) (Please read the precautions on the back before filling this page)

、1T 經濟部智慧財產局員工消費合作社印製 -70- 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（68 ) 由實行此淸洗處理，即使雜質如鹼金屬或重金屬被混在多 孔多晶矽層4中，雜質可在淸洗處理中被移除。結果，電 子源1 0的電子發射特徵可被穩定，且長期可靠度可被改 進。 在淸洗處理中，例如，硫酸與過氧化氫的混合液，氫 氯酸與過氧化氫的混合液，或王水與其類似也許被用作混 合液。由使用任何這些混合液的淸洗液，在淸洗處理使用 之淸洗液可以稍微低的成本獲得。結果，電子源1 0的製 造成本可被減少。 (第十一實施例） 以下，將說明本發明的第十一實施例。第十一實施例 的基本架構與第十實施例的一致。爲了避免重複說明，將 主要說明與第十實施例之差異。 根據第十一實施例製造電子源1 0的方法包括在氧化 利用電解液根據陽極氧化處理形成之多孔多晶矽層之主要 氧化處理之前根據使用燈退火設備快速加熱技術（熱氧化 技術）實行稍微短時間快速加熱氧化之輔助氧化處理過程 。這是唯一不同於第十實施例。根據快速加熱技術之快速 加熱地氧化多孔多晶矽層4如下。氧化溫度是9 0 0 °C， 氧化時間是5分鐘。當僅根據快速加熱氧化形成漂流層時 之氧化時間稍微長，其大約是1小時。 根據第十一實施例之製造方法製造電子源1 0中，隨 電子發射特徵的時間的經過之穩定性係較第十實施例的例 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X 297公釐） -71 - 564454 A7 B7 五、發明説明（69) 子更顯著地改進。這是因爲氧化矽膜5 2與6 4的精細度 係較第十實施例的例子更顯著地改進。 (請先閱讀背面之注意事項再填寫本頁) 第十一實施例中，雖然輔助氧化處理過程係在主要氧 化處理過程之前實行，前者也許係在後者之後實行。 (第十二實施例） 以下，將說明本發明的第十二實施例。第十二實施例 的基本架構與第十實施例的一致。爲了避免重複·說明，將 主要說明與第十實施例之差異。 根據第十二實施例之製造電子源1 〇，漂流層6係由 利用電解液電化地氧化根據陽極氧化處理形成之多孔多晶 矽層4而形成。然而，在陽極氧化處理中，氟化氫水溶液 與乙醇間之混合液被使用，且因此，多孔多晶矽層4之矽 奈米晶體的表面係由氫終止。因此，有漂流層6之氫的含 量在數量上稍微高之危險。 經濟部智慧財產局員工消費合作社印製 反之，第十二實施例中，多孔多晶矽層4係在根據陽 極氧化處理形成之多孔多晶矽層4係由使用電解液（預先 氧化處理過程）氧化之主要氧化處理過程之前由氧化液氧 化。也就是，第十二實施例中，在主要氧化處理過程之前 ，矽奈米晶體與晶粒係由某一程度之時間間隔溶於氧化液 中以致於該表面被氧化，且終止矽原子之氫原子係以氧原 子取代。 預先氧化處理過程之處理條件如下。使用了以1 1 5 °C (濃度7 0 % )加熱之硝酸當作氧化液。氧化時間1 〇 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -72- 564454 A7 B7 五、發明説明（7〇 ) (請先閲讀背面之注意事項再填寫本頁) 分鐘。當氧化液被加熱時，氧化速率增加，因此使減少當 氧化液被使用時之處理時間變可能。可使用一或超過一種 選自硝酸，硫酸，氫氯酸，或過氧化氫水構成之群之氧化 劑當作氧化液。 經濟部智慧財產局S工消費合作杜印製 根據第十二實施例之製造方法製造之電子源1 0中， 隨電子發射特徵的時間的經過之穩定性係較第十實施例的 例子更顯著地改進。這是因爲氧化矽膜5 2與6 4的精細 度係較第十實施例的例子更顯著地改進。根據陽極氧化處 理形成之多孔多晶矽層4有奈米級的良好結構。因此，在 由利用電解液電化地氧化多孔多晶矽層4之主要氧化處理 過程被實行之例子中，新電解液被供應至多孔多晶砂層4 的表面。另一方面，在多孔多晶矽層4的厚度方向，電解 液幾乎不侵入距該表面稍微遠之區域，且電解液的取代幾 乎不會發生。因此，在多孔多晶矽層4的厚度方向中，氧 化矽膜6 4的膜厚度在稍微接近該表面之區域是大的，同 時氧化矽膜6 4的膜厚度在距該表面稍微遠之區域是小的 。結果，在漂流層6的厚度方向稍微接近表面電極7之區 域中，氧化矽膜6 4的膜厚度是如此大以致於電子分散很 可能發生。以此方式，電子發射效率被降低。另一方面， 在漂流層6的厚度方向距表面電極7稍微遠之區域中，氧 化矽膜6 4的膜厚度是如此小以致於電介質強度被降低， 且隨時間的經過之特徵被削弱。 反之，第十二實施例中，預先氧化處理過程係在電化 地氧化多孔多晶矽層4之主要氧化處理過程之前實行。（ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -73- 564454 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（71) 即，主要氧化處理過程係在預先氧化處理過程之後實行） 。因此，在開始主要氧化處理過程之前，多孔多晶矽層4 的表面側已被氧化。所以，在主要氧化處理過程中，在多 孔多晶砂層4的厚度方向，電流幾乎不在接近該表面之區 域流動，且氧化反應不進行。另一方面，氧化在距該表面 稍微遠之區域進行。因此，存於漂流層6的厚度方向中稍 微接近表面電極7之區域之氧化矽膜5 2與6 4的厚度方 向可被限制免於大於存於距表面電極7稍微遠之區域之氧 化矽膜5 2與6 4的厚度方向。簡言之，一些氧化矽膜 6 4的膜厚度的誤差可被減少。結果，漂流層6之電子分 散可限制，且電介質強度被限制免於被降低。 第十二實施例中，多孔多晶矽層4的氧化係在預先氧 化處理過程中由使用電解液而實行。然而，在預先氧化處 理過程中，多孔多晶矽層4也許係由使用氧化氣體，例如 ，如氧或臭氧取代氧化溶液而氧化。此外，氧化也許係由 僅曝露多孔多晶砂層4的表面於空氣中而實行。然而，在 此例中’有被形成之氧化膜的膜品質被損害之可能性。所 以’退火處理最好被實行如稍後說明之第十四實施例的例 子。 此外，在輔助氧化處理過程係在主要氧化處理過程之 前實行之例子如第十一實施例的例子中，預先氧化處理過 程係在輔助氧化處理過程之前實行，藉此隨時間的經過之 穩定性對於電子發射特徵可更顯著地改進。 (請先閱讀背面之注意事項再填寫本百〇 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -74- 564454 Α7 Β7 五、發明説明（72) (第十三實施例） (請先閱讀背面之注意事項再填寫本頁) 以下，將說明本發明的第十三實施例。第十三實施例 1 3的基本架構與第十實施例的一致。爲了避免重複說明 ，將主要於一說明與第十實施例之差異。 第十三實施例中，根據第十實施例製造電子源1 0的 方法特徵在於水被加至電化地氧化多孔多晶矽層4之主要 氧化處理過程使用之電解液中。第十三實施例中，乙烯乙 二醇被用作電解液之有機溶劑，且0 . 0 4 Μ的硝酸鉀被 用作溶質。6 w t %的水被包含在電解液中。 根據第十三實施例，如第十實施例的例子，發射電流 與電子發射效率可較多孔多晶矽層在由水溶液如硫酸或硝 酸構成之電解液中電化地氧化之習知電子源改進，藉此漂 流層被形成，且隨時間的經過之穩定性對於電子發射特徵 可被改進。 經濟部智慧財產局S工消費合作社印髮 此外，水被加至電解液。因此，在對有機溶劑之溶解 度與對水之溶解度之物質被使用用溶質，電解液之溶質的 濃度可由加水而增加。所以，氧化矽膜5 2與6 4的膜品 質被改進。此外，當溶質的濃度增加時，電解液的電子導 電率增加。所以，氧化矽膜5 2與6 4的膜厚度之平面中 誤差可被限制。 可使用第十實施例所示範的當作有機溶劑與溶質。此 外，包含在電解液中之水的比例最好是1 〇 w t %或更 少。然而，即使以上比例是2 0 w t % ’發射電流與電 子發射效率可較先前技藝改進。即使比例是5 0 w t % 本紙張尺度適用中國國家標準（CNS ) A4規格（2]OX 297公釐） -75- 564454 A7 B7 五、發明説明（73) ’發射電流與電子發射效率可較先前技藝改進。 (請先閱讀背面之注意事項再填寫本頁) (第十四實施例） 以下，將說明本發明的第十四實施例。第十四實施例 的基本架構與第十實施例的一致。爲了避免重複說明，將 主要於一說明與第十實施例之差異。 在氧化矽膜5 2與6 4在主要氧化處理過程後被曝露 於空氣中之例子中，有其溶質被損害之危險。第十四實施 例包括由利用第十實施例之電解液電化地氧化多孔多晶矽 層4之主要氧化處理過程後實行退火處理之退火處理過程 。這是唯一不同於第十實施例的。 經濟部智慧財產局8工消費合作社印製 退火處理係由預定的退火時間（例如，1小時）在氧 氣體大氣中（即，含氧化硬幣之大氣）由維持預定的退火 溫度（例如，5 0 0 °C )而實行。退火溫度要求設在 6 0 0 °C或更少。由設定退火溫度至6 0 0 °C或更少，例 如，在形成下電極於玻璃基底上的例子中，低熱阻抗溫度 與適度價格之玻璃基底可被用作玻璃基底。因此，電子源 1 0的成本可被減少，且退火時間可被稍微地增加。結果 ，氧化矽膜5 2與6 4的精細度被改進。 根據第十四實施例之製造方法製造之電子源10中， 隨發射電流與電子發射效率係較第十實施例的例子更顯著 地改進。這是因爲氧化矽膜5 2與6 4的精細度係較第十 實施例的例子更顯著地改進。如已先前說明，退火處理係 在含氧化硬幣之大氣中實行，藉此使避免雜質被導入氧化 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） -76- 564454 A7 _____B7_ 五、發明説明（74 ) 矽膜5 2與6 4變可能。 (.讀先閱讀背面之注意事項再填寫本頁) 退火處理也許係在真空或鈍性氣體大氣中實行。退火 處理係在鈍性氣體大氣中實行，藉此使稍微減少退火溫度 變可能。另一方面，退火處理係在鈍性氣體大氣中實行， 藉此使避免雜質被導入氧化矽膜5 2與6 4或另一膜被形 成於氧化矽膜5 2與6 4的表面上變可能。此外，不需使 用真空設備以實行退火處理。因此，經簡化的設備可較真 空設備被使用之例子被使用。結果，實行退火處理之設備 之生產能力可被改進，且製造成本可被減少。 (範例） 以下，由各種改變根據第十實施例製造電子源1 0的 方法之氧化步驟之條件獲得之結果，藉此製造電子源1 〇 ’且接著，製造電子發射特徵將參考圖1 9至2 5而說明 〇 首先，製造各電子源1 0的方法之共同的條件將被說 明。 經濟部智慧財產局員工消費合作社印製 使用了電阻率0 . OlQcm至〇· 〇2Qcm與厚 度5 2 5 // m的（1 0 〇 )基底當作η型矽基底。多晶矽 層3的膜厚度（參考圖2Α)是1 · 5#m。多晶矽層3 的膜形成係根據L P C V D實行。在膜形成步驟中，真空 的程度是20 Pa，基底溫度是640 °C。單矽烷氣體 的流率在標準狀態是0 · 6 L /m i η (600 seem)。在陽極氧化處理步驟中，使用了由以實質上 本紙張尺度用中國國家標準（CNS ) A4規格（210XM7公釐） 〜 -77- 564454 Μ __ _Β7_ 五、發明説明（75) (請先閱讀背面之注意事項再填寫本頁) 1 : 1混合5 5 w t %的氟化氫水溶液與乙醇獲得之電 解液當作電解液。在陽極氧化期間，5 0 0 W燈被用作 光源。同時光發射係在多晶矽層3的主要表面上實行， 12.5 m A的固定電流係由爲陽極之下電極1 2與鉑 電極構成之陰極間之預定時間自電源供應。表面電極7係 根據真空沈積技術形成之膜厚度1 〇 # m的金薄膜。 圖1 9顯示當對於根據第十實施例之製造方法之乙烯 乙二醇（有機溶劑）由溶解〇 · 0 4 Μ硝酸鉀（溶質）獲 得之電解液被使用時電子源的測量結果（以下，稱爲〜第 一範例的電子源〃）。 圖2 0顯示當電解液被使用時，電子源的測量結果（ 以下，稱爲 > 第二範例的電子源〃），該電解液係由對於 根據第十實施例之製造方法之由溶解〇 · 〇 4 Μ硝酸鉀（ 溶質）於乙烯乙二醇（有機溶劑）獲得，且進一步，根據 第十實施例之製造方法，加3 w t %的水到那裏（即， 第十三實施例的製造方法）。 經濟部智葸財產局員工消費合作社印繁 圖2 1顯示當電解液被使用時，電子源的測量結果（ 以下’稱爲、、第三範例的電子源〃），該電解液係由對於 根據第十實施例之製造方法之由溶解〇 · 〇 4 Μ硝酸鉀（ 谷質）於乙嫌乙一醇（有機溶劑）獲得，且進一步，根據 第十實施例之製造方法，加6 w t %的水到那裏（即， 第十三實施例的製造方法）。 圖2 2顯示當電解液被使用時，電子源的測量結果（ 以下，稱爲、、第四範例的電子源〃），該電解液係由對於 *~ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297么ϋ — 一 -78- 564454 A7 --- B7 五、發明説明（76) (請先閱讀背面之注意事項再填寫本頁) 根據第十實施例之製造方法之由溶解〇 · 〇 4 Μ硝酸鉀（ ί谷質）於乙烯乙一醇（有機溶劑）獲得，且進一步，根據 第十實施例之製造方法，加1 0 w t %的水到那裏（即 ’第十三實施例的製造方法）。 圖2 4顯示當，在根據第十實施例之製造方法中，電 化地氧化係由使用對乙烯乙二醇（有機溶劑）溶解 〇 · 0 4 Μ硝酸鉀（溶質）獲得之電解液實行時之電子源 的測量結果（以下，稱爲、、第五範例的電子源〃）。 圖2 5顯示當1 Μ的硫酸水溶液被使用作電解液時之 電子源的測量結果（以下，稱爲、、比較範例的電子源〃） 0 圖2 3比較圖1 9至圖2 2的測量結果。 經濟部智慧財產局8工消費合作社印製 各電子源的電子發射特徵係根據下列程序測量。也就 是，電子源被導入真空室中（未顯示）。如圖3所示，集 極電極2 1被沈澱於表面電極7的對側。直流電壓V p s 係採用以致於表面電極7在下電極相關之電位高。更進一 步，直流電壓V c被採用以致於集極電極2 1在表面電極 7相關之電位高。Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-70- 564454 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (68) This washing process is performed even if impurities such as alkali metals or heavy metals are Mixed in the porous polycrystalline silicon layer 4, impurities can be removed during the cleaning process. As a result, the electron emission characteristics of the electron source 10 can be stabilized, and the long-term reliability can be improved. In the decanting treatment, for example, a mixed solution of sulfuric acid and hydrogen peroxide, a mixed solution of hydrochloric acid and hydrogen peroxide, or aqua regia similar thereto may be used as the mixed solution. From the cleaning solution using any of these mixed solutions, the cleaning solution used in the cleaning process can be obtained at a slightly lower cost. As a result, the manufacturing cost of the electron source 10 can be reduced. (Eleventh Embodiment) Hereinafter, an eleventh embodiment of the present invention will be described. The basic structure of the eleventh embodiment is the same as that of the tenth embodiment. In order to avoid repetitive description, differences from the tenth embodiment will be mainly explained. The method of manufacturing the electron source 10 according to the eleventh embodiment includes performing a slightly shorter period of time according to a rapid heating technique (thermal oxidation technique) using a lamp annealing apparatus before oxidizing the porous polycrystalline silicon layer formed using an electrolytic solution according to an anodic oxidation process. Rapid heating oxidation assisted oxidation process. This is the only difference from the tenth embodiment. The rapid heating oxidation of the porous polycrystalline silicon layer 4 according to the rapid heating technique is as follows. The oxidation temperature is 9 0 ° C and the oxidation time is 5 minutes. The oxidation time is slightly longer when the drift layer is formed only by rapid heating oxidation, which is about 1 hour. In the manufacture of the electron source 10 according to the manufacturing method of the eleventh embodiment, the stability with the passage of time of the electron emission characteristics is more stable than that of the tenth embodiment (please read the precautions on the back before filling this page). The standard applies to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) -71-564454 A7 B7 5. The invention description (69) is significantly improved. This is because the fineness of the silicon oxide films 5 2 and 64 is significantly improved compared with the example of the tenth embodiment. (Please read the notes on the back before filling this page.) In the eleventh embodiment, although the auxiliary oxidation process is performed before the main oxidation process, the former may be performed after the latter. (Twelfth Embodiment) Hereinafter, a twelfth embodiment of the present invention will be described. The basic structure of the twelfth embodiment is the same as that of the tenth embodiment. In order to avoid repetition and explanation, differences from the tenth embodiment will be mainly described. According to the manufacturing electron source 10 according to the twelfth embodiment, the drift layer 6 is formed by electrochemically oxidizing the porous polycrystalline silicon layer 4 formed by an anodizing treatment using an electrolytic solution. However, in the anodizing treatment, a mixed solution between an aqueous hydrogen fluoride solution and ethanol is used, and therefore, the surface of the silicon nanocrystals of the porous polycrystalline silicon layer 4 is terminated by hydrogen. Therefore, there is a danger that the hydrogen content of the drift layer 6 is slightly higher in quantity. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the twelfth embodiment, the porous polycrystalline silicon layer 4 is mainly oxidized by using an electrolytic solution (pre-oxidation treatment process). It is oxidized by an oxidizing solution before the process. That is, in the twelfth embodiment, before the main oxidation treatment process, the silicon nanocrystals and crystal grains are dissolved in the oxidation solution at a certain time interval so that the surface is oxidized, and the hydrogen of the silicon atoms is terminated. Atoms are replaced with oxygen atoms. The processing conditions of the pre-oxidation process are as follows. Nitric acid heated at 115 ° C (concentration 70%) was used as the oxidation solution. Oxidation time 1 〇 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -72- 564454 A7 B7 V. Description of the invention (70) (Please read the precautions on the back before filling this page) minutes. When the oxidizing liquid is heated, the oxidation rate increases, thereby making it possible to reduce the processing time when the oxidizing liquid is used. As the oxidizing liquid, one or more than one oxidizing agent selected from the group consisting of nitric acid, sulfuric acid, hydrochloric acid, or hydrogen peroxide water can be used. The Intellectual Property Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperation Du printed the electronic source 10 manufactured according to the manufacturing method of the twelfth embodiment. The stability with the passage of time of the electron emission characteristics is more significant than the example of the tenth embodiment. To improve. This is because the fineness of the silicon oxide films 5 2 and 64 is more significantly improved than the example of the tenth embodiment. The porous polycrystalline silicon layer 4 formed by the anodizing treatment has a good structure on the order of nanometers. Therefore, in an example in which the main oxidation treatment process of electrochemically oxidizing the porous polycrystalline silicon layer 4 by using the electrolytic solution is carried out, a new electrolytic solution is supplied to the surface of the porous polycrystalline sand layer 4. On the other hand, in the thickness direction of the porous polycrystalline silicon layer 4, the electrolytic solution hardly penetrates into a region slightly away from the surface, and replacement of the electrolytic solution hardly occurs. Therefore, in the thickness direction of the porous polycrystalline silicon layer 4, the film thickness of the silicon oxide film 64 is large in a region slightly close to the surface, and the film thickness of the silicon oxide film 64 is small in a region slightly away from the surface. of. As a result, in a region where the thickness direction of the drift layer 6 is slightly close to the surface electrode 7, the film thickness of the silicon oxide film 64 is so large that electron dispersion is likely to occur. In this way, the electron emission efficiency is reduced. On the other hand, in a region where the thickness direction of the drift layer 6 is slightly far from the surface electrode 7, the film thickness of the silicon oxide film 64 is so small that the dielectric strength is reduced, and the characteristics over time are weakened. In contrast, in the twelfth embodiment, the pre-oxidation process is performed before the main oxidation process of electrochemically oxidizing the porous polycrystalline silicon layer 4. (This paper size applies to Chinese National Standard (CNS) A4 specifications (210X297 mm) -73- 564454 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. V. Invention Description (71)) That is, the main oxidation treatment process is in advance After the oxidation process). Therefore, before starting the main oxidation treatment process, the surface side of the porous polycrystalline silicon layer 4 has been oxidized. Therefore, during the main oxidation treatment, in the thickness direction of the porous polycrystalline sand layer 4, an electric current hardly flows in a region close to the surface, and the oxidation reaction does not proceed. On the other hand, oxidation proceeds in a region slightly away from the surface. Therefore, the thickness direction of the silicon oxide films 5 2 and 64 located in a region slightly close to the surface electrode 7 in the thickness direction of the drift layer 6 can be restricted from being larger than the silicon oxide film existing in a region slightly away from the surface electrode 7. 5 2 and 6 4 thickness direction. In short, some errors in the film thickness of some silicon oxide films 64 can be reduced. As a result, the electron dispersion of the drift layer 6 can be restricted, and the dielectric strength can be restricted from being reduced. In the twelfth embodiment, the oxidation system of the porous polycrystalline silicon layer 4 is performed by using an electrolytic solution during the prior oxidation treatment. However, during the pre-oxidation process, the porous polycrystalline silicon layer 4 may be oxidized by using an oxidizing gas such as, for example, oxygen or ozone instead of the oxidizing solution. In addition, oxidation may be performed by exposing only the surface of the porous polycrystalline sand layer 4 to the air. However, in this example, there is a possibility that the film quality of the formed oxide film is impaired. Therefore, the 'annealing process is preferably performed as an example of the fourteenth embodiment described later. In addition, in the case where the auxiliary oxidation treatment process is performed before the main oxidation treatment process, such as in the example of the eleventh embodiment, the pre-oxidation treatment process is performed before the auxiliary oxidation treatment process, whereby the stability over time is Electron emission characteristics can be improved more significantly. (Please read the notes on the back before filling in this paper. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -74- 564454 Α7 B7. V. Description of the invention (72) (Thirteenth embodiment ) (Please read the notes on the back before filling out this page) The following describes the thirteenth embodiment of the present invention. The basic structure of the thirteenth embodiment 13 is the same as that of the tenth embodiment. In order to avoid repetitive description, The difference from the tenth embodiment will be mainly explained in the first embodiment. In the thirteenth embodiment, the method of manufacturing the electron source 10 according to the tenth embodiment is characterized in that water is added to the main oxidation treatment process of electrochemically oxidizing the porous polycrystalline silicon layer 4 In the electrolytic solution used. In the thirteenth embodiment, ethylene glycol was used as an organic solvent for the electrolytic solution, and 0.4 M potassium nitrate was used as a solute. 6 wt% of water was contained in the electrolytic solution. According to the thirteenth embodiment, as in the example of the tenth embodiment, the emission current and the electron emission efficiency can be improved compared to the conventional electron source in which a porous polycrystalline silicon layer is electrochemically oxidized in an electrolytic solution composed of an aqueous solution such as sulfuric acid or nitric acid. As a result, the drift layer is formed, and the stability over time can be improved for the characteristics of electron emission. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Industrial Cooperatives, in addition, water is added to the electrolyte. Therefore, in organic solvents Solutes with solubility and solubility in water are used as solutes. The concentration of the solute in the electrolyte can be increased by adding water. Therefore, the film quality of the silicon oxide films 5 2 and 64 is improved. In addition, when the concentration of the solute is increased, The electronic conductivity of the electrolytic solution is increased. Therefore, the errors in the planes of the film thicknesses of the silicon oxide films 52 and 64 can be limited. The organic solvent and solute as exemplified in the tenth embodiment can be used. In addition, The proportion of water in the liquid is preferably 10 wt% or less. However, even if the above proportion is 20 wt%, the emission current and electron emission efficiency can be improved compared to previous techniques. Even if the proportion is 50 wt%, this paper scale Applicable to Chinese National Standard (CNS) A4 specification (2) OX 297 mm) -75- 564454 A7 B7 V. Description of the invention (73) 'The emission current and electron emission efficiency can be improved compared to previous techniques. (Read the precautions on the back before filling this page) (Fourteenth Embodiment) Hereinafter, the fourteenth embodiment of the present invention will be described. The basic structure of the fourteenth embodiment is the same as that of the tenth embodiment. In order to avoid repetition The explanation will mainly focus on the differences from the tenth embodiment. In the case where the silicon oxide films 52 and 64 are exposed to the air after the main oxidation treatment process, there is a danger that the solute is damaged. Fourteenth The embodiment includes an annealing process in which an annealing treatment is performed after the main oxidation treatment process of the porous polycrystalline silicon layer 4 is electrochemically oxidized with the electrolyte of the tenth embodiment. This is the only difference from the tenth embodiment. The Bureau of Intellectual Property, Ministry of Economic Affairs 8 Industrial and consumer cooperative printing annealing process is carried out by a predetermined annealing time (for example, 1 hour) in an oxygen gas atmosphere (that is, an atmosphere containing oxidized coins) and by maintaining a predetermined annealing temperature (for example, 500 ° C) . The annealing temperature needs to be set at 600 ° C or less. From setting the annealing temperature to 600 ° C or less, for example, in the case where a lower electrode is formed on a glass substrate, a glass substrate having a low thermal resistance temperature and a moderate price can be used as the glass substrate. Therefore, the cost of the electron source 10 can be reduced, and the annealing time can be slightly increased. As a result, the fineness of the silicon oxide films 52 and 64 is improved. In the electron source 10 manufactured according to the manufacturing method of the fourteenth embodiment, the emission current and electron emission efficiency are more significantly improved than those of the tenth embodiment. This is because the fineness of the silicon oxide films 5 2 and 64 is improved more significantly than the example of the tenth embodiment. As already explained, the annealing process is carried out in the atmosphere containing oxidized coins, so as to prevent impurities from being introduced into the oxidized paper. The size of the paper applies the Chinese National Standard (CNS) Λ4 specification (210X297 mm) -76- 564454 A7 _____B7_ V. Description of the invention (74) Silicon films 5 2 and 6 4 become possible. (Please read the notes on the back before filling in this page.) Annealing may be performed in a vacuum or inert gas atmosphere. The annealing treatment is performed in an inert gas atmosphere, thereby making it possible to slightly reduce the annealing temperature. On the other hand, the annealing treatment is performed in an inert gas atmosphere, thereby making it possible to prevent impurities from being introduced into the silicon oxide films 5 2 and 64 or to form another film on the surfaces of the silicon oxide films 5 2 and 64. . In addition, no vacuum equipment is required to perform the annealing process. Therefore, the simplified device can be used more than the example where a vacuum device is used. As a result, the productivity of the equipment for performing the annealing treatment can be improved, and the manufacturing cost can be reduced. (Example) Hereinafter, results obtained by variously changing the conditions of the oxidation step of the method of manufacturing the electron source 10 according to the tenth embodiment, thereby manufacturing the electron source 10 ′ and then, manufacturing electron emission characteristics will be described with reference to FIGS. 25. First, the conditions common to the method of manufacturing each electron source 10 will be explained. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A (100) substrate with a resistivity of 0.1 OlQcm to 0.02Qcm and a thickness of 5 2 5 // m was used as the n-type silicon substrate. The film thickness of the polycrystalline silicon layer 3 (refer to FIG. 2A) is 1.5 m. The film formation of the polycrystalline silicon layer 3 is performed according to L P C V D. During the film formation step, the degree of vacuum was 20 Pa, and the substrate temperature was 640 ° C. The flow rate of monosilane gas is 0 · 6 L / m i η (600 seem) in a standard state. In the anodizing process step, the Chinese National Standard (CNS) A4 specification (210XM7 mm) in the paper size is used to -77- 564454 Μ __ _Β7_ V. Description of the invention (75) (Please read the back first Note: Please fill in this page again.) 1: 1 An electrolyte obtained by mixing a 55 wt% aqueous solution of hydrogen fluoride and ethanol as the electrolyte. A 500 W lamp was used as the light source during anodizing. At the same time, light emission is performed on the main surface of the polycrystalline silicon layer 3, and a fixed current of 12.5 m A is supplied from a power source at a predetermined time between a cathode composed of an electrode 12 below the anode and a platinum electrode. The surface electrode 7 is a gold thin film with a thickness of 10 m formed by a vacuum deposition technique. FIG. 19 shows measurement results of an electron source when an ethylene glycol (organic solvent) obtained by dissolving 0.4 M potassium nitrate (a solute) for an ethylene glycol (organic solvent) according to the manufacturing method according to the tenth embodiment is used (hereinafter, Called ~ the first example of the electron source 〃). FIG. 20 shows a measurement result of an electron source (hereinafter, referred to as > an electron source of the second example) when an electrolytic solution is used, and the electrolytic solution is dissolved by the manufacturing method according to the tenth embodiment. · 〇4 M potassium nitrate (solute) was obtained from ethylene glycol (organic solvent), and further, according to the manufacturing method of the tenth embodiment, 3 wt% of water was added thereto (ie, the manufacture of the thirteenth embodiment) method). Figure 2 1 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs shows the measurement results of the electron source when the electrolyte is used (hereinafter referred to as “the third example of the electron source”). The manufacturing method of the tenth embodiment is obtained by dissolving potassium nitrate (gluten) in ethylene glycol (organic solvent) at a concentration of 0.04 M, and further, according to the manufacturing method of the tenth embodiment, 6 wt% of water is added. Go there (ie, the manufacturing method of the thirteenth embodiment). Figure 2 2 shows the measurement results of the electron source when the electrolyte is used (hereinafter, referred to as the electron source of the fourth example). The electrolyte is based on the Chinese National Standard (CNS) for this paper size. A4 specifications (210X 297 Modal — I-78- 564454 A7 --- B7 V. Description of the invention (76) (Please read the precautions on the back before filling this page) Dissolve by the manufacturing method according to the tenth embodiment. 〇4 M potassium nitrate (gluten) was obtained from ethylene glycol (organic solvent), and further, according to the manufacturing method of the tenth embodiment, 10 wt% of water was added there (that is, the thirteenth embodiment Figure 2 4 shows that, in the manufacturing method according to the tenth embodiment, electrochemically oxidizing is obtained by dissolving 0.004 M potassium nitrate (solute) using ethylene glycol (organic solvent). Measurement results of the electron source when the electrolyte is implemented (hereinafter, referred to as the electron source of the fifth example). Fig. 25 shows the measurement results of the electron source when a 1 M sulfuric acid aqueous solution is used as the electrolyte (hereinafter , Called, comparison example Electron source 〃) 0 Figure 2 3 compares the measurement results of Figure 19 to Figure 22. The electron emission characteristics of each electron source printed by the 8th Industrial Cooperative Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs are measured according to the following procedure. Into a vacuum chamber (not shown). As shown in FIG. 3, the collector electrode 21 is deposited on the opposite side of the surface electrode 7. The DC voltage V ps is adopted so that the potential associated with the surface electrode 7 at the lower electrode is high. Further The DC voltage V c is adopted so that the potential associated with the collector electrode 21 at the surface electrode 7 is high.

圖1 9至圖2 2及圖2 4與圖2 5各顯示當直流電壓 V c固定在1 〇 〇V，且真空室之真空程度是5χ 1 0 ' 5 P a時之電子發射特徵的測量結果。各圖的水 平軸表示直流電壓V p s。左側的垂直軸表示電流密度。 右側的垂直軸表示電子發射效率。X表示二極體電流 I p s的電流密度。Y表示發射電流I e的電流密度。Z 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -79 - 564454 Μ Β7 —----------------- 五、發明説明（77 ) 表示電子發射效率。 此外，圖2 3是描繪當直流電壓Vp s在圖1 9至圖 2 2的測量結果是1 4 V時之資料之圖形。圖2 3的水平 軸質量率之水含量。.左側的垂直軸表示電流密度。右側的 垂直軸表示電子發射效率。Y表示發射電流I e的電流密 度。Z表示電子發射效率。 自圖1 9至圖2 4與圖2 5，可發現第一至第五範例 的電子源分別在發射電流I e的電子發射效率與電流密度 被改進，如與比較範例的那些比較。 本發明已結合它特定的實施例說明。對那些熟知此技 藝之人一些各種修改與改變可能發生將是明顯的。所以， 本發明應係受限於附加的申請專利範圍而不受限於此實施 例。 (請先閱讀背面之注意事項再填寫本頁) 裝 -、11 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -80-Figures 19 to 22 and Figures 2 4 and 25 each show the measurement of the electron emission characteristics when the DC voltage V c is fixed at 1000 V and the degree of vacuum in the vacuum chamber is 5χ 1 0 '5 Pa result. The horizontal axis of each figure represents a DC voltage V p s. The vertical axis on the left indicates the current density. The vertical axis on the right indicates the electron emission efficiency. X represents the current density of the diode current I p s. Y represents the current density of the emission current I e. Z This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) -79-564454 Μ B7 ------------------ 5. Description of the invention (77) Indicates the electron emission efficiency. In addition, FIG. 23 is a graph depicting data when the measurement result of the DC voltage Vp s in FIG. 19 to FIG. 22 is 14 V. Fig. 2 Water content of horizontal axis mass ratio. The vertical axis on the left indicates the current density. The vertical axis on the right indicates the electron emission efficiency. Y represents the current density of the emission current I e. Z represents the electron emission efficiency. From FIGS. 19 to 24 and FIG. 25, it can be found that the electron emission efficiency and current density of the electron sources of the first to fifth examples at the emission current I e are improved, as compared with those of the comparative example. The invention has been described in connection with its specific embodiments. It will be apparent to those skilled in the art that various modifications and changes may occur. Therefore, the present invention should be limited by the scope of additional patent applications and not by this embodiment. (Please read the precautions on the back before filling out this page) Pack-, 11 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm) -80-

Claims (1)

564454 A8 B8 C8 D8 六、申請專利範圍 1 (請先閲讀背面之注意事項再填寫本頁) 1.一種製造具有電子導電基底於電子導電基底的一 表面上形成之強力場致漂流層以及於強力場致漂流層上形 成之電子導電薄膜之場致發射式電子源的方法，其中電壓 被採用以致於電子導電薄膜在電子導電基底相關之極性上 變正的，藉此自電子導電基底注入強力場致漂流層之電子 漂移於強力場致漂流層內且係經由電子導電薄膜發射，該 方法包含： 當強力場致漂流層被形成時，由陽極氧化形成包含半 導體奈米晶體之多孔半導體層的陽極氧化處理步驟；·以及 形成絕緣膜於各半導體奈米晶體的表面上的絕緣膜形 成步驟，其中，在該陽極氧化處理步驟中，陽極氧化處理 被實行同時發射基本上包含半導體層相關之可見光區域的 波長之光。 2 ·根據申請專利範圍第1項之方法，其中射至半導· 體層之光的波長係由光學濾光器限制。 經濟部智慧財產局員工消費合作社印製 3 ·根據申請專利範圍第2項之方法，其中光學濾光 器係由紅外線切除濾光器與紫外線切除濾光器至少其中之 一構成的。 4 ·根據申請專利範圍第1項之方法，其中射至半導 體層之光的波長係設在當半導體奈米晶體係彼此連續地連 接時形成之波長。 5 .根據申請專利範圍第1項之方法，其中單色光的 光源被使用。 6 .根據申請專利範圍第1項之方法，其中射至半導 本紙張尺度適用中國國家榇準（CNS ) A4規格(210X297公釐) ' -81 - 564454 A8 B8 C8 D8 六、申請專利範圍 2 體層之光的波長係在開始陽極氧化後根據時間的經過而改 變 0 (請先閲讀背面之注意事項再填寫本頁) 7 ·根據申請專利範圍第2項之方法，其中光學濾光 器的傳送波長係在開始陽極氧化後根據時間的經過而改變 〇 8 ·根據申請專利範圍第1項之方法，其中光係間斷 地射至半導體層。 9 ·根據申請專利範圍第1項之方法，其中光係自半 導體層的該表面的對側射至半導體層。 1 0 ·根據申請專利範圍第9項之方法，其中光係在 半導體層的厚度方向自兩側發射，且係與兩光的波長同時 改變。 1 1 ·根據申請專利範圍第1項之方法，其中在陽極 氧化處理步驟中使用了控制陽極氧化處理容器中之電解液. 的濃度以便以同速率進行多孔半導體層的形成的控制機構 〇 經濟部智慧財產局員工消費合作社印製 1 2 ·根據申請專利範圍第1 1項之方法，其中控制 機構運用引導具有經調整的濃度與溫度之電解液進入陽極 氧化處理容器之控制容器。 1 3 ·根據申請專利範圍第1 1項之方法，其中控制 機構精巧地移動包含下電極與半導體層之目標。 1 4 ·根據申請專利範圍第1項之方法，其中由使用 至少一親水有機溶劑而移除留在多孔半導體層中之電解液 的沖洗步驟被包括在該陽極氧化處理步驟與該絕緣膜形成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -82 - 564454 8 888 ABCD 夂、申請專利範圍 3 步驟之間。 (請先閲讀背面之注意事項再填寫本頁) 1 5 ·根據申請專利範圍第1項之方法，其中由使用 至少一非水可溶性有機溶劑而移除留在多孔半導體層中之 電解液的沖洗步驟被包括在該陽極氧化處理步驟與該絕緣 膜形成步驟之間。 1 6 .根據申請專利範圍第1項之方法，其中，在該 陽極氧化處理步驟與該氧化處理步驟間之特定時期期間， 自然氧化膜係避免被形成於半導體奈米晶體上以便不曝靈 多孔半導體層於空氣中。 1 7 ·根據申請專利範圍第1 6項之方法，其中，在 特定時期期間，多孔半導體層的表面係覆與非氧化物液體 〇 1 8 ·根據申請專利範圍第1 6項之方法，其中，在 特定時期期間，大氣是鈍性氣體。 1 9 ·根據申請專利範圍第1 6項之方法，其中，在 特定時期期間，至少一多孔半導體層被保持在真空中。 經濟部智慧財產局員工消費合作社印製 2 0 ·根據申請專利範圍第1項之方法，其中該絕緣 膜形成步驟包含在由溶解溶質於有機溶劑獲得之電解液中 電化地氧化多孔半導體層的主要氧化處理步驟。 2 1 ·根據申請專利範圍第2 0項之方法，其中水被 加至電解液。 2 2 ·根據申請專利範圍第2 0項之方法，其中在該 主要氧化處理步驟之前或之後包括根據熱氧化技術氧化多 孔半導體層的輔助氧化處理步驟。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -83 - 564454 A8 B8 C8 D8 六、申請專利範圍 4 (請先閲讀背面之注意事項再填寫本頁) 2 3 .根據申請專利範圍第2 0項之方法，在該主要 氧化處理步驟之前包括氧化多孔半導體層的預先氧化處理 步驟。 2 4 .根據申請專利範圍第2 2項之方法，其中在該 主要氧化處理步驟與該輔助氧化處理步驟之前包括氧化多 孔半導體層的預先氧化處理步驟。 2 5 .根據申請專利範圍第2 0項之方法，其中在該 主要氧化處理步驟之後包括淸洗多孔半導體層的淸洗步驟 〇 2 6 . —種製造具有電子導電基底於電子導電基底的 一表面上形成之強力場致漂流層以及於強力場致漂流層上 形成之電子導電薄膜之場致發射式電子源的裝置，其中電 壓被採用以致於電子導電薄膜在電子導電基底相關之極性 上變正的，藉此自電子導電基底注入強力場致漂流層之電· 子漂移於強力場致漂流層內且係經由電子導電薄膜發射， 該裝置包含： 經濟部智慧財產局員工消費合作社印製 當強力場致漂流層被形成時，根據陽極氧化形成包含 半導體奈米晶體之多孔半導體層之陽極氧化處理設備；以 及 形成絕緣膜於各半導體奈米晶體的表面上的絕緣膜形 成設備，其中陽極氧化處理設備實行陽極氧化處理同時發 射基本上包含半導體層相關之可見光區域的波長之光。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -84-564454 A8 B8 C8 D8 6. Scope of patent application 1 (Please read the precautions on the back before filling out this page) 1. A kind of strong field drift layer with electronic conductive substrate formed on one surface of electronic conductive substrate and strong Method for field emission electron source of electronically conductive thin film formed on field drifting layer, in which voltage is applied so that electronically conductive thin film becomes positive on the polarity associated with electronically conductive substrate, thereby injecting a strong field from the electronically conductive substrate The electrons of the drifting layer drift in the strong field drifting layer and are emitted through the electronic conductive film. The method includes: when the strong field drifting layer is formed, an anode is formed by anodic oxidation to form a porous semiconductor layer containing semiconductor nanocrystals. An oxidation treatment step; and an insulation film formation step of forming an insulation film on the surface of each semiconductor nanocrystal, wherein, in the anodization treatment step, the anodization treatment is performed while emitting a visible light region substantially including the semiconductor layer Light of the wavelength. 2 · The method according to item 1 of the scope of patent application, wherein the wavelength of the light incident on the semiconductor layer is limited by the optical filter. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 · The method according to item 2 of the patent application scope, wherein the optical filter is composed of at least one of an infrared cut filter and an ultraviolet cut filter. 4. The method according to item 1 of the scope of patent application, wherein the wavelength of light incident on the semiconductor layer is set at a wavelength formed when semiconductor nanocrystal systems are continuously connected to each other. 5. The method according to item 1 of the scope of patent application, wherein a monochromatic light source is used. 6. The method according to item 1 of the scope of patent application, in which the paper size of the semiconducting paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) '-81-564454 A8 B8 C8 D8 The wavelength of the light in the body layer is changed according to the passage of time after the anodization is started. (Please read the precautions on the back before filling out this page.) 7 · According to the method in the scope of patent application No. 2, in which the transmission of optical filters The wavelength is changed according to the passage of time after starting the anodization. 8 According to the method of the first patent application, the light is intermittently emitted to the semiconductor layer. 9. The method according to item 1 of the scope of patent application, wherein light is emitted from the opposite side of the surface of the semiconductor layer to the semiconductor layer. 10 · The method according to item 9 of the scope of patent application, wherein the light is emitted from both sides in the thickness direction of the semiconductor layer, and the wavelength of both light is changed simultaneously. 1 1 · The method according to item 1 of the scope of patent application, wherein in the anodizing step, a control mechanism for controlling the concentration of the electrolyte in the anodizing container to perform the formation of the porous semiconductor layer at the same rate is adopted. Printed by the Intellectual Property Bureau's Consumer Cooperatives 1 2 · The method according to item 11 of the scope of patent application, in which the control mechanism guides the electrolyte with the adjusted concentration and temperature into the control container of the anodizing container. 1 3 · The method according to item 11 of the scope of patent application, wherein the control mechanism delicately moves the target including the lower electrode and the semiconductor layer. 1 4 · A method according to item 1 of the scope of patent application, wherein a washing step of removing the electrolytic solution remaining in the porous semiconductor layer by using at least one hydrophilic organic solvent is included in the anodizing step and the insulating film forming substrate. Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -82-564454 8 888 ABCD 夂, 3 steps between patent application scope. (Please read the precautions on the back before filling out this page) 1 5 · The method according to item 1 of the scope of patent application, in which the electrolyte remaining in the porous semiconductor layer is removed by using at least one non-water-soluble organic solvent A step is included between the anodizing step and the insulating film forming step. 16. The method according to item 1 of the scope of patent application, wherein during a specific period between the anodizing step and the oxidizing step, the natural oxide film is prevented from being formed on the semiconductor nanocrystal so as not to be exposed to the porous The semiconductor layer is in the air. 1 7 · A method according to item 16 of the scope of patent application, wherein the surface of the porous semiconductor layer is coated with a non-oxide liquid during a certain period of time. 1 · A method according to item 16 of the scope of patent application, wherein, During certain periods, the atmosphere is a passive gas. 19 · The method according to item 16 of the scope of patent application, wherein, during a specific period, at least one porous semiconductor layer is maintained in a vacuum. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Co-operative Society 20 · The method according to item 1 of the scope of patent application, wherein the insulating film forming step includes the main steps of electrochemically oxidizing the porous semiconductor layer in an electrolytic solution obtained by dissolving a solute in an organic solvent Oxidation treatment step. 2 1 · A method according to item 20 of the patent application, wherein water is added to the electrolyte. 2 2 A method according to item 20 of the scope of patent application, wherein a secondary oxidation treatment step of oxidizing the porous semiconductor layer according to a thermal oxidation technique is included before or after the main oxidation treatment step. This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) -83-564454 A8 B8 C8 D8 VI. Application for patent scope 4 (Please read the precautions on the back before filling this page) 2 3. The method of claim 20 of the patent application scope includes a prior oxidation treatment step of oxidizing the porous semiconductor layer before the main oxidation treatment step. 24. The method according to item 22 of the scope of patent application, wherein a preliminary oxidation treatment step of oxidizing the porous semiconductor layer is included before the main oxidation treatment step and the auxiliary oxidation treatment step. 25. The method according to item 20 of the scope of patent application, wherein after the main oxidation treatment step, a washing step of washing the porous semiconductor layer is included. 206. A method of manufacturing an electronically conductive substrate on a surface of the electronically conductive substrate The field-effect drifting layer formed on the device and the field emission type electron source of the electron-conducting thin film formed on the field-effect drifting layer, in which the voltage is adopted so that the electron-conducting film becomes positive on the polarity related to the electron-conductive substrate In this way, the electrons of the strong field drift layer are injected into the strong field drift layer from the electronic conductive substrate. The electrons drift in the strong field drift layer and are emitted through the electronic conductive film. The device includes: When the field drift layer is formed, an anodizing apparatus for forming a porous semiconductor layer containing semiconductor nanocrystals according to anodization; and an insulating film forming apparatus for forming an insulating film on the surface of each semiconductor nanocrystal, wherein the anodizing process The device performs anodizing and emits semiconductor layers The light wavelength of the visible light region. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -84-