五、發明説明（1 ) 【發明領域】 別曰：發明是在提供一種晶片除錯定位方法及其裝置，特 種可明確判斷錯誤晶片位置的晶片除錯定位方法 5【習知技藝說明】 當電子元件安裝在印刷電路板後，有鑑於IC之接腳 支曰加及封裝方法上的演進，印刷電路板面臨著元件密度 增加、接線與接線間之空間縮小等問題，特別是當使用ς ―極陣列封裝（BGAP)方法時，因為IC之“為球狀腳 端之構造，因此無法以傳統之方法目視監看印刷電路板上 iC間連線開路之問題。 為了解決上述問題，由一群電子製造業者組成了 JTAG㈤nt Test Acti〇n Gr〇up)，並發展了解決電路測試 上問題之邊界掃瞄（boundary scan)標準，而此標準在經電 15子電機工程協會（IEEE)於199〇年規格化後即成為IEEE 1149.1-1990標準測試存取埠及邊界掃瞄架構V. Description of the Invention (1) [Field of Invention] The invention is to provide a method and device for wafer debugging and positioning, and a special method for wafer positioning and positioning for determining the position of a wrong wafer. [Description of Known Skills] After the components are mounted on the printed circuit board, in view of the evolution of IC pin support and packaging methods, printed circuit boards face problems such as increased component density and reduced space between wiring and wiring, especially when using In the package-on-package (BGAP) method, because the IC is a ball-shaped pin structure, it is impossible to visually monitor the open circuit connection between iCs on a printed circuit board by conventional methods. In order to solve the above problems, a group of electronics manufacture The industry formed the JTAG㈤nt Test Actión Gr〇up), and developed a boundary scan standard that solves problems in circuit testing, and this standard was specified by the IEEE 15 Sub-Electrical Engineering Association (IEEE) in 1990. After becoming the IEEE 1149.1-1990 standard test access port and boundary scan architecture
Test Access Port and Boundary-Scan Architecture)。而遵 循此標準之測試方法即稱為JTAG測試，簡言之，JTA(J 測試係對一印刷電路板上之積體電路元件輸入測試信號， 20並在積體電路元件之外部腳端上擷取輸入/輸出測試數 據，藉以進行元件内部及元件間連線的測試方法。因此， 以此方法進行測試時，在印刷電路板上之電子元件（不需 全部）應以能支援此一 JTAG方法為前提，亦即需是邊界 測試標準元件（JTAG測試相容元件）。 第4頁 本紙張尺度適用中國國家標準（CNS) A4規格（210 X 297公釐） 558640 A7 -------B7___ 發明説^72 ) ^ " 參閱第一圖，為一習知之JTAG測試系統示意圖，該 測試系統包含一内建有控制程式之主機7，及一裝設在該 主機7上之jtAG測试裝置71，其中，jtAG測試裝置71 包含一 JTAG控制基板72,及一測試存取埠73(Test Access 〇Γί簡稱TAP)，由JTAG控制基板透過測試存取璋73 發出测δ式訊號予一待測試基板上之一第一晶片d 1 (JTAG 相谷元件）及一第二晶片D2，最後循序通過第一晶片〇ι 與第二晶片D2之測試訊號再回到主機7内，並藉由主機 7内之控制程式加以解析，即可了解線路之故障處。而所 1〇謂的測試存取埠（TAP)，係指為了進行針對測試邏輯電路 之指令、測試數據或測試結果等數據加以輸入/輸出之串 列介面，並備有TDI、TMS、TCK及TDO等信號線，可 經由外界電腦主機加以控制，以便進行JTAG測試。雖然 此種測试方法可以告訴測試人員二晶片間某一條特定線路 15 (traCe)為開路，但無法明確得知究竟是哪一個晶片的對應 接腳與基板上該線路之墊片連結產生問題，更因為所有接 腳與墊片之接點都埋藏在各晶片與印刷電路板間，完全無 法/木入觀察或檢測，測試人員以嘗試錯誤（try & error)法 來判斷，必須隨機拆卸兩晶片之一，不僅造成時間上的浪 20費，更造成測試成本的提高。因此，本發明即是針對上述 問題加以設計而得。 此外，參閱第二圖，必需一提的是，所謂的邊界測試 兀件（晶片）8即除了原來之内部邏輯電路81，以及外部之 複數接腳82外，為了相容於JTAG測試法，在内部邏輯 ____ 第5頁 本紙張尺度朝(⑽織格⑵0χ297公着> ·(請先背面之注意事項再填寫本頁) 訂丨 # 558640 A7 _____B7_ 五、發明説明（3 ) 電路與接腳間更設置有複數之邊界掃瞄暫存器83、一旁 路暫存器 84(bypass register)、一指令暫存器 85(instruction register)，及一 TAP控制器86，而邊界掃瞄暫存器83之 内部則包含了一個移位暫存器83 1 (shift register)與一個閃 5 鎖器832(latch)，藉由該等邊界掃瞄暫存器83的設置， 使得待測試之晶片8可不透過其内部邏輯電路81而可以 IEEE 1149.1之標準與主機相互溝通，即可得知問題發生 處。而在此邊界測試晶片上亦設置有一測試存取埠（Test Access Port，簡稱TAP)，係用以接收來自於JTAG測試 10 基板72之測試信號；指令暫存器85接收來自於jTaG測 試基板72之信號，並使測試信號依其測試指令而分為旁 路（BYPASS)、取樣（SAMPLE/PRELOAD)，及外部測試 (EXTEST)三種動作。 【發明概要】 15 因此，本發明之目的即在提供一種配合JTAG測試系 統進行測試，且可明確定位邊界測試標準晶片之特定接腳 與印刷電路板上對應墊片間之接點是否為開路的晶片除錯 定位方法及其裝置。 於是，本發明晶片除錯定位裝置是配合一主機及一設 20 置在該主機上之JTAG測試裝置以進行晶片除錯定位作 業，該主機包含有一用以控制該JTAG測試裝置之jTaG 控制程式，該主機與該JTAG測試裝置可對於一電路板上 之一電路及設置在該電路板上之至少一邊界測試標準晶片 發送一第一測試信號以進行測試，該邊界測試標準晶片並 第6頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 〈請先閲讀背面之注意事項再填寫本頁) 訂. 558640 發明説明（4 10 15 20 界測試標準:片=電等路接具:至複數广別用以電性連接該邊 線，片除錯定位裝置接:二^ 感測裝置是連接在該JTAG測=一疋位裝置。 JTAG測試裝置感測到誃、毐 、、置上，用以當該 、以邊界測試標準晶片盥該第二晶片 間之一第一連線為開路時，發二 一 ^ ^ J 具有不同兩低準位序列 s \”㈣第—連線至該邊界測試標準晶片或該 第二曰曰片，並接收一自該邊界測試標準晶片或該第二晶片 回傳之信號。 定位裝置是連接在該主機上，藉由該感測裝置接收來 自於該邊界測試標準晶片或該第二晶“傳之信號，並定 位該第一連線之開路處。 並依據上述裝置，因而本發明之晶片除錯定位方法係 當JTAG測試裝置感測到該邊界測試標準晶片與第二晶片 間之一第一連線為開路時，進行步驟勾電性連接該晶片 除錯裝置與該第一連線；b)由該晶片除錯裝置發送一第二 測試信號經該第一連線及該邊界測試標準晶片之第一接腳 至該邊界測試標準晶片，並接收由該邊界測試標準晶片回 傳之信號，且該第二測試信號是一包含不同高低準位之序 列信號；c)比較該回傳信號與一預定值，判斷該第一接腳 與該第一連線是否為開路。 【圖式之簡單說明】 本發明之技術内容、特徵及優點，在以下配合參考圖 式之較佳實施例的詳細說明中，將可清楚的呈現，在圖式 〈請先閲讀背面之注意事項再填窝本頁) 訂— 1 第 頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 558640Test Access Port and Boundary-Scan Architecture). The test method that complies with this standard is called JTAG test. In short, JTA (J test is to input test signals to integrated circuit components on a printed circuit board, and 20 is captured on the external pins of the integrated circuit components. Take the input / output test data to test the internal and inter-component connections. Therefore, when testing by this method, the electronic components (not all) on the printed circuit board should support this JTAG method. As a premise, it must be a boundary test standard component (JTAG test compatible component). Page 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 558640 A7 ------- B7___ Invention ^ 72) ^ " Refer to the first figure for a schematic diagram of a conventional JTAG test system. The test system includes a host 7 with a built-in control program, and a jtAG test installed on the host 7. Device 71, wherein the jtAG test device 71 includes a JTAG control substrate 72 and a test access port 73 (Test Access 〇Γί for short), and the JTAG control substrate sends a test δ signal to a waiter through the test access 璋 73. Test substrate One of the first chip d 1 (JTAG phase valley element) and a second chip D2, and finally pass the test signals of the first chip ι and the second chip D2 in order and return to the host 7 again, and pass the test signal in the host 7 The control program can be analyzed to understand the fault of the line. The so-called test access port (TAP) refers to a serial interface for inputting / outputting data such as instructions, test data, or test results of test logic circuits, and is equipped with TDI, TMS, TCK, and Signal lines such as TDO can be controlled by an external computer host for JTAG testing. Although this test method can tell the tester that a specific line 15 (traCe) between the two chips is open, it is not clear whether the corresponding pin of the chip is connected to the pad of the circuit on the substrate. Furthermore, because all the pins and pad contacts are buried between each chip and the printed circuit board, it is completely impossible to observe or detect them. The tester judges by the try & error method. One of the chips not only causes a 20-hour wave of time, but also increases the test cost. Therefore, the present invention has been designed in view of the above problems. In addition, referring to the second figure, it must be mentioned that the so-called boundary test element (chip) 8 is in addition to the original internal logic circuit 81 and the external multiple pins 82. In order to be compatible with the JTAG test method, Internal logic ____ page 5 This paper is oriented towards the paper (⑽ 格格 ⑵0χ297 公 着) · (Please note on the back before filling this page) Order # 558640 A7 _____B7_ V. Description of the invention (3) Circuits and pins There are a plurality of boundary scan registers 83, a bypass register 84 (bypass register), an instruction register 85 (instruction register), and a TAP controller 86, and the boundary scan register The inside of 83 includes a shift register 83 1 (shift register) and a flash 5 latch 832 (latch). With the setting of these boundary scan registers 83, the chip 8 to be tested can be saved. Through its internal logic circuit 81, it is possible to communicate with the host computer according to the IEEE 1149.1 standard, and you can know where the problem occurs. A test access port (TAP) is also set on this boundary test chip, which is used for To receive from JTAG Test 10 Test signal of the substrate 72; the command register 85 receives the signal from the jTaG test substrate 72, and makes the test signal divided into BYPASS, SAMPLE / PRELOAD, and EXTEST according to its test command. ) Three actions. [Summary of the invention] 15 Therefore, the object of the present invention is to provide a test that cooperates with the JTAG test system and can clearly locate the contact between the specific pin of the boundary test standard chip and the corresponding pad on the printed circuit board. Method and device for wafer debugging and positioning whether it is an open circuit. Therefore, the wafer debugging and positioning device of the present invention cooperates with a host and a JTAG test device set on the host to perform wafer debugging and positioning operation. The host includes There is a jTaG control program for controlling the JTAG test device. The host and the JTAG test device can send a first test signal to a circuit on a circuit board and at least one boundary test standard chip disposed on the circuit board. Test, the boundary test standard wafer and page 6 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm (Please read the precautions on the back before filling in this page) Order. 558640 Invention Description (4 10 15 20 test standard: slice = electrical isolator: to plural numbers to electrically connect the edge line, slice debugging Positioning device connection: Two ^ The sensing device is connected to the JTAG measurement device. The JTAG test device senses 誃, 毐, and 置, and is used to test the second chip between the second chip and the standard chip. When one of the first connections is open, send two one ^ ^ J with different two low level sequences s \ ”㈣ 第 —connect to the boundary test standard chip or the second chip, and receive one from the Boundary test signal from the standard wafer or the second wafer. The positioning device is connected to the host, and the sensing device receives signals from the boundary test standard chip or the second crystal, and locates the open circuit of the first connection. According to the above device, therefore When the JTAG test device senses that the first connection between the boundary test standard wafer and the second wafer is an open circuit, the wafer debug positioning method of the present invention performs a step to electrically connect the wafer debug device and the first wafer. A connection; b) a second test signal sent by the chip debugging device via the first connection and the first pin of the boundary test standard wafer to the boundary test standard wafer, and receiving the boundary test standard wafer The returned signal, and the second test signal is a sequence signal including different high and low levels; c) comparing the returned signal with a predetermined value to determine whether the first pin and the first connection are open. [Brief description of the drawings] The technical content, features, and advantages of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. Note nest of reloading the page) book --1 page of this paper scale applicable to Chinese National Standard (CNS) A4 size (210X297 mm) 558 640
發明説明 10 15 20 中： 第一圖是一示意圖，說明一習知之JTAG測試系統對 一待測基板進行測試的情況； 第二圖是一示意圖，說明一 JTAG相容元件之構成，· 第三圖是一示意圖，說明本創作晶片除錯定位裝置之 一較佳實施例配合一 JTAG測試裝置與一主機，對一電路 板上之晶片進行測試的情況； 第四圖是一流程圖，說明本創作之晶片除錯定位方 法；及 第五圖是一示意圖，說明該JTAG測試裝置感測到晶 片間開路的情況。 【較佳實施例之詳細說明】 參閱第三圖，本發明之晶片除錯定位裝置i之一較佳 實施例是配合一主機3及一設置在主機3上之jtag測試 裝置10來對一電路板4上之晶片b 1及B2進行測試。 JTAG測試裝置1〇是設置在該主機3上，且主機3 具有JTAG控制程式來以控制JTAG測試裝置1〇之測試 信號的發送與接收回傳，而JTAG測試裝置1〇則具有一 裝没在主機11上之JTAG測試控制基板1〇1，及一 TAp 控制器102,且TAP控制器102是以一 JTAGi連接埠（圖 未示）連接到JTAG測試基板1〇1上，並以另一 jtag之 連接埠連接到晶片除錯定位裝置i(一般習知之jtag測試 裝置可提供四個JTAG連接埠）。 電路板4上具有至少一邊界測試標準晶片（相容於 第8頁 •(請先閲讀背面之注意事項再填寫本頁) •、π— 558640Description of Invention 10 15 20: The first diagram is a schematic diagram illustrating a conventional JTAG test system for testing a substrate to be tested; the second diagram is a schematic diagram illustrating the structure of a JTAG-compatible component; The figure is a schematic diagram illustrating a preferred embodiment of the device for debugging and locating the creative chip. A JTAG test device and a host are used to test a chip on a circuit board. The fourth diagram is a flowchart illustrating the present invention. The method for debugging and positioning of the created wafer; and the fifth diagram is a schematic diagram illustrating the situation that the JTAG test device senses an open circuit between the wafers. [Detailed description of the preferred embodiment] Referring to the third figure, a preferred embodiment of the wafer debugging and positioning device i of the present invention is to cooperate with a host 3 and a jtag test device 10 provided on the host 3 to match a circuit. The wafers b 1 and B 2 on the board 4 were tested. The JTAG test device 10 is set on the host 3, and the host 3 has a JTAG control program to control the sending and receiving of test signals of the JTAG test device 10, and the JTAG test device 10 has a The JTAG test control board 101 on the host 11 and a TAp controller 102, and the TAP controller 102 is connected to the JTAG test board 101 with a JTAGi port (not shown), and another jtag The port is connected to the chip debugging and positioning device i (the conventional jtag test device can provide four JTAG ports). Circuit board 4 has at least one boundary test standard chip (compatible with page 8 • (Please read the precautions on the back before filling out this page) •, π — 558640
ίο 15 20 JTAG測試標準之晶片），在本實施例中，為便於說明起見， 圖式中僅以一邊界測試標準晶片B1，及一第二晶片B2 來作說明，邊界測試標準晶片B1具有一内部邏輯電路 4〇1、複數邊界掃瞄暫存器411、一 TAP控制器421、一 旁路暫存器431，及一指令暫存器441，且第二晶片B2 具有一内部邏輯電路402、複數邊界掃瞄暫存器412、一 TAP控制器422、一旁路暫存器432及指令暫存器442。 此外，邊界測試標準晶片B1具有複數接腳6〇且第 二晶片B2具有與該等接腳6〇相對應之接腳62，在本實 施例中’為方便說明起見，邊界測試標準晶片Bi及第二 晶片B2間之接腳係僅以電路板4上之六條連線61來作 電性連接’當然’實際上晶片間之接腳數目及連線數目並 不以圖式中為限。另一方面，雖上述之第二晶片B2亦為 相谷於邊界測試之晶片，但事實上，在下述所舉之元件互 接測試（待測元件間連接狀態之測試）中，第二晶片B2亦 可為一般之晶片，而不需一定是相容於jTAg測試之元 件。 晶片除錯裝置1具有一感測裝置u，及一定位裝置 12’該感測裝置1丨是藉由一探針u(pr〇be)來對發送/感 測測試信號，而定位裝置12則是藉由感測裝置u回傳之 測試信號來判斷晶片B1與B2間之錯誤發生處。而在感 測裝置11中，可選擇性設置另一相容於邊界掃瞄測試之 晶片（圖未示），用以接受來自主機之控制信號而對晶片間 發送測试信號’事實上，感測裝置丨丨及定位裝置12之功 第 頁 本紙張尺度適用中國國家標準（CNS) A4規格（21〇><297公爱） ·(請先閱讀背面之注意事項再填寫本頁) •訂· 558640 五、發明説明 月b亦可藉由軟體模擬的方式而包含在控制程式之中，可更 減少硬體建置的成本。 5 10 15 20 配口第四圖’因此，藉由上述裝置，步驟51是先藉 由JTAG測試裝置10來對電路板4上之晶片B1及B2進 灯凡件互接測試。由於此元件互接測試係為習 知JTAG測 試裝置10之测試步驟，且皆為熟知此項技藝人士所能輕 易了解，因而下述僅簡單描述其操作動作。 參閱第五（a)圖’主機3發送取樣（PRELOAD/SAMPLE) 指令至邊界測試標準晶片B1之指令暫存器441中，並同 時發送旁路（BYPASS)的指令至第二晶片B2之指令暫存器 442中，參閱第五（1))圖，接著邊界測試標準晶片bi中之 TAP控制器421將一第一測試信號（例如Χι、χ2、χ3、χ4、ίο 15 20 JTAG test standard wafer), in this embodiment, for convenience of explanation, the figure only uses a boundary test standard wafer B1 and a second wafer B2 for description. The boundary test standard wafer B1 has An internal logic circuit 401, a complex boundary scan register 411, a TAP controller 421, a bypass register 431, and an instruction register 441. The second chip B2 has an internal logic circuit 402, A plurality of boundary scan registers 412, a TAP controller 422, a bypass register 432, and an instruction register 442. In addition, the boundary test standard wafer B1 has a plurality of pins 60 and the second chip B2 has pins 62 corresponding to the pins 60. In this embodiment, 'for convenience of explanation, the boundary test standard wafer Bi The pins between the second chip B2 and the second chip B2 are only electrically connected by the six wires 61 on the circuit board 4. Of course, the number of pins and the number of wires between the chips are not limited in the drawing. . On the other hand, although the above-mentioned second chip B2 is also a phase-tested boundary wafer, in fact, in the component interconnection test described below (test of the connection state between the components to be tested), the second chip B2 It can also be a general chip, and does not need to be a component compatible with jTAg testing. The chip debugging device 1 has a sensing device u and a positioning device 12 ′. The sensing device 1 ′ sends / senses a test signal through a probe u (pr0be), and the positioning device 12 has The test signal returned by the sensing device u is used to determine where the error occurs between the chips B1 and B2. In the sensing device 11, another chip (not shown in the figure) compatible with the boundary scan test can be optionally provided to receive a control signal from the host and send a test signal between the chips. The measuring device 丨 丨 and the positioning device 12 The page size of this paper applies the Chinese National Standard (CNS) A4 specifications (21〇 > < 297 public love) · (Please read the precautions on the back before filling this page) • ·· 558640 V. Description of the invention Month b can also be included in the control program by means of software simulation, which can further reduce the cost of hardware installation. 5 10 15 20 The fourth picture of the port ′ Therefore, with the above-mentioned device, step 51 is to use the JTAG test device 10 to test the interconnection of the lamps B1 and B2 on the circuit board 4 with each other. Since this component interconnection test is a test procedure of the conventional JTAG test device 10, and is easily understood by those skilled in the art, the following only briefly describes its operation. Refer to the fifth (a) diagram. The host 3 sends a sample (PRELOAD / SAMPLE) instruction to the instruction register 441 of the boundary test standard chip B1, and at the same time sends a BYPASS instruction to the instruction chip of the second chip B2. In the register 442, refer to the fifth (1)) diagram, and then the TAP controller 421 in the boundary test standard chip bi sends a first test signal (for example, χ, χ2, χ3, χ4,
Xs、X6)設定在邊界測試標準晶片B1右側之邊界掃瞄暫 存器411中，而此時晶片B2則藉由旁路暫存器432跳過 測試，接著見第五（c)圖，對邊界測試標準晶片B1之指令 暫存器441下達外部測試（exteST)指令，並對第二晶片 B2之指令暫存器442下達取樣（pREL〇AD/SAMpLE)指 令，最後如第五（d)圖，將第一測試信號自邊界測試標準 晶片B1上藉由連線61傳送到第二晶片B2，亦即由邊界 測試標準晶片B1之接腳60，經由連線61，將第一測試 "ί吕滅輸送到第二晶片B2之接腳62上，以及輸送到第一 晶片Β2左侧之邊界掃瞒暫存器412上，並藉由主機3反 覆進行資料移位（shift)，將第二晶片Β2之邊界掃晦暫存 器412之内容由第二晶片B2之TDO擷取回電腦主機3 第10頁 本紙張尺度適用中國國家標準（CNS) A4規格（210 X 297公釐） ’並將來自於邊界料標準w m之第―測試信號 料^2、^^)與到達第二晶片32之輸入資 門路1 A、I、I I Μ加以比較，若部份連線發生 由電腦主機3上所得到的第_^Βι之第一測試 ::即與第二晶片Β2之輸入資料不同。為方便進行下述 ^進行，以下假設主機3已感測到第_晶片m與第二 :片幻間之-第-連線61，為開路，且對應此第一連線 片幻上之接腳62，。上之第-接腳价，及第二晶 10 15 20 參閱第三、四圖，本發明晶片除錯定位方法之特徵是 路之：52連V將晶片除錯定位裝置1之感測裝置11與開 ^第;連線61’電性連接，在本實施例中，晶片除錯裝 探斜;Γ—料13與第—連線61，相互電性連接，且此 接之功能，能對第-連“，進行一 襄置第3 τ達指令’使晶片除錯定位 而至邊界測試標準晶連線61’ ==係包含了 一序列不同高低準位之信號，亦即諸: 腳性之信號，藉以探知兩晶片之接 興電路板4上之連線電性連接的狀態。 接著在步驟54中，由探針13接 “’透過邊界測試標準晶片則所广連線 第二晶…•第—傳之 第〗1頁 本紙張尺細令國國家標準 558640 A7Xs, X6) are set in the boundary scan register 411 on the right side of the boundary test standard chip B1, and at this time, the chip B2 skips the test by bypassing the register 432, and then sees the fifth (c) diagram. The instruction test register 441 of the boundary test standard wafer B1 issues an external test (exteST) instruction, and the instruction register 442 of the second wafer B2 issues a sampling (pREL0AD / SAMpLE) instruction, as shown in Figure 5 (d). The first test signal is transmitted from the boundary test standard wafer B1 to the second chip B2 through the connection 61, that is, the pin 60 of the boundary test standard wafer B1 is connected to the first test through the connection 61. Lu Mi is transferred to the pin 62 of the second chip B2, and to the boundary sweep register 412 on the left side of the first chip B2, and the data is shifted by the host 3 repeatedly to shift the second The content of the boundary erase register 412 of the chip B2 is retrieved by the TDO of the second chip B2 and returned to the computer host 3 Page 10 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 'and Test signal material from the boundary material standard wm (^ 2, ^^) and reach the second chip 32 Compare input channels 1 A, I, I I M. If part of the connection occurs, the first test of _ ^ Βι obtained on the computer host 3 :: is different from the input data of the second chip B2. In order to facilitate the following, the following assumes that the host 3 has sensed the _th chip m and the second: the -th-connection 61 of the film magic, which is an open circuit, and corresponds to the connection on the first connection of the film magic. Feet 62 ,. The first-pin price above, and the second crystal 10 15 20 Refer to the third and fourth figures. The feature of the wafer debugging and positioning method of the present invention is the way: 52-line V. And 61; the connection 61 'is electrically connected. In this embodiment, the chip is debugged for tilt detection; Γ-material 13 and the first connection 61 are electrically connected to each other, and the function of this connection can The "-then" command is used to set the third τ reach command 'to debug the wafer to the boundary test standard crystal line 61' == contains a series of signals of different high and low levels, that is: The signal is used to detect the state of the electrical connection of the connection on the circuit board 4 of the two chips. Then, in step 54, the probe 13 is connected to the "" through the boundary test standard chip is widely connected to the second crystal ... • 第 — 传 第 第 1 页 This paper rule is detailed in National Standard 558640 A7
五、發明説明（9 ) 裝置1之定位裝置12將此回傳之信號與一預定值加以判 讀比對，而此預定值即可為該第二測試信號或主機内預設 之其它測試信號，即可判斷開路是發生於第一接腳6〇,與 第一連線61，之接點上，或此開路是發生於第二接腳62, 5 與第一連線61’之接點上，或此開路同時發生於第一連線 61’之二端的情況，因此，可明確得知此開路是發生於哪 一個晶片上，即可避免測試時間上的浪費，更可避免由於 誤拆晶片所造成的損失。此外，本發明之晶片除錯定位裝 置係僅包含一感測裝置與一定位裝置，更不需大量硬體建 10 置所需之成本即可達成本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 第12頁 本紙張尺度適用中國國家標準（〇〖S) A4規格（210X297公釐） ·(請先閱讀背面之注意事項再填寫本頁)5. Description of the invention (9) The positioning device 12 of the device 1 judges and compares the returned signal with a predetermined value, and the predetermined value can be the second test signal or other test signals preset in the host. That is, it can be determined that the open circuit occurs at the contact between the first pin 60 and the first connection 61, or the open circuit occurs at the contact between the second pin 62, 5 and the first connection 61 '. Or, this open circuit occurs at the same time at the two ends of the first connection 61 '. Therefore, it can be clearly known on which chip this open circuit occurs, which can avoid the waste of test time, and also avoid the accidental disassembly of the chip. Losses caused. In addition, the wafer debugging and positioning device of the present invention only includes a sensing device and a positioning device, and the cost required for a large amount of hardware construction can be used to achieve the purpose of the invention. However, the above are only the preferred embodiments of the present invention. When the scope of implementation of the present invention cannot be limited by this, that is, the simple equivalent changes and modifications made according to the scope of the patent application and the content of the invention specification, All should still fall within the scope of the invention patent. Page 12 This paper size applies the Chinese national standard (〇 〖S) A4 specification (210X297mm) · (Please read the precautions on the back before filling this page)
558640 A7 B7 五、發明説明（1G ) 【元件標號對照】 1 晶片除錯定位裝置 43 1 指令暫存器 10 JTAG測試裝置 432 指令暫存器 11 感測裝置 51 步驟 12 定位裝置 52 步驟 3 主機 53 步驟 4 電路板 54 步驟 401 内部邏輯電路 60 接腳 402 内部邏輯電路 61 連線 411 邊界掃瞄暫存器 62 接腳 412 邊界掃瞒暫存器 605 第一接腳 421 TAP控制器 61 5 第一連線 422 TAP控制器 625 第二接腳 431 旁路暫存器 B1 邊界測試標準晶片 432 旁路暫存器 B2 第二晶片 •(請先閱讀背面之注意事項再填寫本頁) 第13頁 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐）558640 A7 B7 V. Description of the invention (1G) [Comparison of component numbers] 1 Chip debug positioning device 43 1 Instruction register 10 JTAG test device 432 Instruction register 11 Sensing device 51 Step 12 Positioning device 52 Step 3 Host 53 Step 4 Circuit board 54 Step 401 Internal logic circuit 60 Pin 402 Internal logic circuit 61 Connection 411 Boundary scan register 62 Pin 412 Boundary concealment register 605 First pin 421 TAP controller 61 5 First Wiring 422 TAP controller 625 Second pin 431 Bypass register B1 Boundary test standard chip 432 Bypass register B2 Second chip • (Please read the precautions on the back before filling this page) Page 13 This Paper size applies to China National Standard (CNS) A4 (210X297 mm)