TW557539B - Method to form shallow trench isolation - Google Patents
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557539 五、發明說明（1) 5-1發明領域： 本發明係關於一種形成淺溝渠隔離（S h a 1 1 〇 w T r e n c h I sol at ion)的方法，特別是一種有關於形成具有保護間隙 壁淺溝渠隔離的方法，其中完全不使用氮化矽層。 5 - 2發明背景： 當積體電路之積集度不斷地增加，半導體元件中主動 區之間的隔離區的尺寸必須不斷地縮小。傳統用於隔離主 動區的區域氧化法（LOCOS)是以熱氧化法形成場氧化層， 而半導體元件中主動區之間有效的隔離長度則受限於以熱 氧化法形成之場氧化層，因此以熱氧化法形成之場氧化層 隔離區的隔離效果逐漸不敷所需。此外，傳統的區域氧化 法尚有源自於其製程本身的缺點，舉例來說，矽底材上擴 散層罩幕（Diffusion layer mask)之下主動區邊緣之氧 化造成場氧化層邊緣具有一鳥嘴（B i r d ’ s b e a k)的形狀。 為了避免上述區域氧化法的缺點，一種利用溝渠的隔 離技術被發展出來。大致上溝渠隔離的製程步驟包含蝕刻 矽底材以形成一溝渠，以化學氣相沈積法（CVD)沈積一氧 化層以填滿該溝渠，及以化學機械研磨法（CMP)平坦化該 氧化層表面，再將主動區上方的氧化層移去。557539 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a shallow trench isolation (S ha 1 1 0w Trench I sol at ion), in particular to a method for forming a protective barrier wall Shallow trench isolation method in which no silicon nitride layer is used at all. 5-2 Background of the Invention: As the integration degree of integrated circuits continues to increase, the size of the isolation region between active regions in a semiconductor device must be continuously reduced. Traditionally, the area oxidation method (LOCOS) used to isolate the active area uses thermal oxidation to form a field oxide layer. The effective isolation length between active areas in a semiconductor device is limited by the field oxide layer formed by thermal oxidation. The isolation effect of the field oxide layer isolation region formed by the thermal oxidation method is gradually insufficient. In addition, the traditional regional oxidation method still has its shortcomings derived from the process itself. For example, the oxidation of the edge of the active area under the diffusion layer mask on a silicon substrate causes the field oxide layer to have a bird's edge. The shape of the mouth (Bird'sbeak). In order to avoid the disadvantages of the above-mentioned area oxidation method, a trench isolation technique has been developed. The process steps of trench isolation generally include etching a silicon substrate to form a trench, depositing an oxide layer by chemical vapor deposition (CVD) to fill the trench, and planarizing the oxide layer by chemical mechanical polishing (CMP). Surface, remove the oxide layer above the active area.
557539 五'發明說明（2) ' 根據上述的技術，石夕麻好姑力丨 心』乂』/抵材被蝕刻至一預定的深度，並 提供良好隔離效果。此外，揚量彳卜s | %乳化層是以化學氣相沈積法 沈積，意謂著相對於以埶ft於、土；^ ^ 巧百仲』、A热虱化法形成之場氧化層，在後續 微影製程中定義出的隔離區結構可維持一貫性。上述用於 隔離元件的技術也就是著名的淺溝渠隔離（讣&11〇〜557539 Five 'Invention Explanations (2)' According to the above-mentioned technology, Shi Xima's good heart 乂 heart 乂 心 / / material is etched to a predetermined depth, and provides a good isolation effect. In addition, the lift s |% emulsified layer is deposited by chemical vapor deposition, which means that compared to the field oxide layer formed by 埶 ft and soil; The isolation zone structure defined in the subsequent lithography process can maintain consistency. The above-mentioned technology for isolating components is also known as shallow trench isolation (讣 & 11〇 ~
Trench Isolation)製程 。 儘管如_此’傳統的淺溝渠隔離製程仍然有幾項缺點。 第一 A圖顯示在一傳統的淺溝渠隔離之剖面圖。第一 a圖中 顯示一底材1 0 0、一二氧化矽層i 〇 2、一氮化矽層1 〇 4與一 線性氧化層（Linear 〇xide) 1〇6。在以加熱磷酸濕蝕刻製 程以形成罩幕氮化矽層104時，蝕刻劑（Etchant)也會同 時侵餘底下鄰近二氧化矽層1 〇 2的底材1 〇 〇之多晶矽層或是 石夕層。圖中侵姓點（p i t t i ng)的形成嚴重破壞底材1 〇 〇之 擴散區（Diffusion Regi〇n)或主動區（Active Region〕 的性負。在氮化石夕層濕蝕刻移除之後在緩衝多晶矽層中與 在多晶石夕層I虫刻後在底材中亦有侵蝕點的形成。侵蝕點的 形成可能源自於水、氨與矽在濕氧化製程中的化學反應。 其反應機構發表於 T. T. Sheng，et al.，in the paper "From White Ribbon to Black Belt: A Direct Observation of the Kooi Effect Masking Film by Transmission Electron Microscopy”，J. Electrochem· Soc·，vol. 140，p. L.163， 1 9 93·。此反應機構造成底Trench Isolation) process. Despite this, the traditional shallow trench isolation process still has several disadvantages. The first panel A shows a cross section of a conventional shallow trench isolation. In the first a, a substrate 100, a silicon dioxide layer i 0 2, a silicon nitride layer 104, and a linear oxide layer 106 are shown. During the wet etching process with heated phosphoric acid to form the mask silicon nitride layer 104, an etchant will simultaneously invade the polycrystalline silicon layer or the stone substrate of the substrate 100 which is adjacent to the silicon dioxide layer 100 Floor. The formation of pitti ng in the picture severely damages the diffusion zone (Diffusion Region) or the active region of the substrate 100. After the nitride etch layer is removed by wet etching, it is buffered There are also erosion points in the polycrystalline silicon layer and in the substrate after the polycrystalline stone layer I was etched. The formation of the erosion points may originate from the chemical reaction of water, ammonia and silicon in the wet oxidation process. Published in TT Sheng, et al., In the paper " From White Ribbon to Black Belt: A Direct Observation of the Kooi Effect Masking Film by Transmission Electron Microscopy ", J. Electrochem · Soc ·, vol. 140, p. L .163, 1 9 93 ·. This reaction mechanism caused the bottom
第5頁 557539 五、發明說明（3) 材的損壞並導致深次微米7°件的良率的損失。為了解決上 述的問題，現代半導體業界係以犧牲氧化層（Sacri f iCia Oxide Layer)來避免侵#點的問題，但這樣做需額外的製 程步驟與花費較多的時間。此外，由於氮化矽具有高達 109dyne/cm拉伸應力，因此氮化矽的使用將造成底材應 力，使得必須使用额外的製程步驟如形成犧牲氧化層以移 除受損之底材。 傳統淺溝渠隔離的另一個問題源自^氣化物敍刻製程 ，如第- B圖所示。此淺溝渠隔離2:統製程步驟包含 氧化層填人、化學機械研磨與# W二。:第-B圖所 示，淺溝渠隔離氧化廣1_轉角或上處產“一 擾的溝槽，此溝槽玎能引起電路導l ^ ^溝渠隔離失效 。這些溝槽之所以形成是因為轉角或A、’角處的蝕刻率總 是較高的緣故。 有鑑於上述傳統製程的缺點，因此有必要發展出一種 新穎進步的淺溝渠隔離結構與製程以克服傳統製程的缺點 本發明正能符合這樣的需求。 _ 5 - 3發明目的及概述： 本發明之一目的為提供一種淺溝渠隔離製程，其中未Page 5 557539 V. Description of the invention (3) Damage to materials and loss of yield of 7 ° deep sub-micron parts. In order to solve the above problems, the modern semiconductor industry avoids the problem of sacrificing oxide layers (Sacri ficia Oxide Layer), but doing so requires additional process steps and takes more time. In addition, because silicon nitride has a tensile stress of up to 109 dyne / cm, the use of silicon nitride will cause substrate stress, making it necessary to use additional process steps such as forming a sacrificial oxide layer to remove the damaged substrate. Another problem with traditional shallow trench isolation stems from the gasification process, as shown in Figure -B. This shallow trench isolation 2: the process steps include oxide layer filling, chemical mechanical polishing and #W two. : As shown in Figure -B, the shallow trench isolation oxidizes a wide angle or a disturbing trench. The trench can cause circuit isolation failure. These trenches are formed because The etch rate at corners or A, 'corners is always higher. In view of the shortcomings of the traditional process described above, it is necessary to develop a novel and improved shallow trench isolation structure and process to overcome the shortcomings of the traditional process. Meets such needs. _ 5-3 Purpose and summary of the invention: One object of the present invention is to provide a shallow trench isolation process, in which
557539 五、發明說明（4) 使用任何氮化矽層因此可預防Koo i效應及氮化矽造成之底 材應力。 本發明之另一目的為提供一種淺溝渠隔離結構，此結 構包含保護間隙壁以保護淺溝渠隔離的轉角或絕緣角。 本發明之又一目的為提供一種可靠的淺溝渠隔離結構 與製程，以確保元件主動區域之間的隔離品質。 為 離的方 材具有 層上； 導體層 、該第 :共形 電材料 三介電 該第三 刻該第 層以曝 了達成上述 法，此方法 一第一介電 形成一第二 覆蓋該第二 二介電層、 線性 生成一 以形成 層覆蓋 溝 該第 介電層與該 一導體層以 露出該底材 之目 至少 層於 介電 介電 該第 介電 渠隔 二介 第二 曝露 :及 的，本發明利用一種形成淺溝渠隔 包含下列步驟：提供一底材，該底 其上及一第 層覆蓋該第 層；形成一 一導體層、 層覆蓋該溝 離；移除該 電層與該溝 介電層以曝 一導體層於該 一導體層；形 溝渠進入該第二導體層 該第一介電層與該底材 滿該溝 體層； 第一介電 成一第二 渠以一介 形成一第 渠；填 第二導 渠隔離；非等向性蝕刻 露出該第一導體層；蝕 出該第一介電層 I虫刻該第一介電 氧化該底材 本發明避免使用任何氮化矽材料以防範Koo i效應及氮 化矽造成之底材應力並利用間隙壁保護淺溝渠隔離之轉角557539 5. Description of the invention (4) The use of any silicon nitride layer can prevent the Koo i effect and the substrate stress caused by silicon nitride. Another object of the present invention is to provide a shallow trench isolation structure, which includes a protective corner to protect the corner or insulation angle of the shallow trench isolation. Another object of the present invention is to provide a reliable shallow trench isolation structure and process to ensure the isolation quality between active areas of the components. The isolated square material has a layer; a conductor layer, the first: a conformal electrical material, three dielectrics, the third layer, and the third layer is exposed to achieve the above method. This method uses a first dielectric to form a second covering the first Twenty-two dielectric layers are linearly formed to form a layer to cover the trench. The first dielectric layer and the first conductive layer are exposed to expose the substrate. At least one layer of the dielectric is separated from the second dielectric channel and the second exposure is: And, the present invention utilizes a method of forming a shallow trench barrier to include the following steps: providing a substrate, the substrate and a first layer covering the first layer; forming a conductor layer, the layer covering the trench; removing the electrical layer And a trench dielectric layer to expose a conductor layer to the conductor layer; a trench is formed into the second conductor layer; the first dielectric layer and the substrate fill the trench body layer; the first dielectric is formed into a second channel; Forming a first channel; filling a second channel for isolation; non-isotropic etching to expose the first conductor layer; etching out the first dielectric layer I etching the first dielectric oxidation substrate; the invention avoids using any nitrogen Silicone material to prevent Koo i effect and silicon nitride The stress and the substrate using a shallow trench isolation spacers protection of the corner
第7頁 (5)557539 五、發明說明 或絕緣角 與蠢晶碎 氮化矽層 層作為犧 製程步驟 多晶秒層 電層在淺 部份。第 被用以在 。本發明 牲氧化層 。第一介 、非晶碎 溝渠隔離 一導體層如一多晶 極氧化層 維持。形 如濕式餘 形成的過 成之間隙 刻不被破 上述有關發明 並非限制。其他不 應包含在的本發明 一導 淺溝 同時 ，如 電層 層與 形成 碎層 程中 壁可 壞， 的簡 脫離 的專 體層 渠隔 利用 此就 如一 遙晶 的製 、非 一同 保護 故主 至少包 離形成 至少包 不需再 二氧化 矽之高 程中不 晶碎層 被氧化 淺溝渠 動區域 含多 的製 含墊 進行 碎層 蝕刻 會受 與磊 ，故 隔離 之間 晶碎 程中 氧化 形成 與第 選擇 到損 晶石夕 元件 在各 的隔 層、非晶碎層 取代傳統所用 層之第一介電 犧牲氧化層的 一導體層如一 得第一介 比使 壞。 會與 隔離 種製 離可 剩餘的第 底材在閘 品質可被 程步驟中 以確保。 單說明及以下的％ 本笋明之_I 細說明僅為範例 =::之‘神的等效改 利範圍之内。 ^ π q 5 -4發明的詳細說 明 在此必須說明的是以下描述之 含完整之製程。本發明可以藉各種i::驟及結構並不包 施’在此僅提及瞭解本發明所需之製心J:製程技術來實 以下將根據本發明所附圖示做詳細的說明，請注意圖Page 7 (5) 557539 V. Description of the invention or insulation angle and stupid crystal silicon nitride layer as a sacrifice process step Polycrystalline second layer The electrical layer is in the shallow part. Article is used in. The present invention is an animal oxide layer. The first dielectric and amorphous trench isolation is maintained by a conductor layer such as a polycrystalline oxide layer. Excessive gaps formed in the form of wet residues are not to be broken at the moment. The above-mentioned related inventions are not limited. Other shallow trenches of the present invention that should not be included at the same time, such as the electrical layer and the formation of broken layers in the middle wall can be broken, the simple separation of the specialized layer canal is used as a remote crystal system, not to protect the owner together In the formation of at least the height of the silicon dioxide layer, the amorphous fragmentation layer is oxidized. In the shallow trenches, the area containing a lot of pads is subjected to fragmentation etching. Therefore, the oxide formation and isolation during the crystallization fragmentation process are separated. A conductive layer of the first dielectric sacrificial oxide layer which replaces the conventional dielectric sacrificial oxide layer in each of the interlayers and amorphous broken layers of the spar crystal element is selected so that the first dielectric ratio becomes bad. The remaining substrate can be separated from the isolation seed and the quality of the gate can be ensured in the process step. The single description and the following% This detailed explanation of _I is only an example = :: of ‘God ’s equivalent improvement. ^ π q 5 -4 Detailed description of the invention What must be explained here is the complete process described below. The present invention can be borrowed from various i :: steps and structures and is not inclusive. 'Here only mentioned the centering required to understand the present invention J: process technology to achieve the following will be described in detail based on the accompanying drawings of the present invention, please Attention map
五、發明說明（6) 示均為簡單的形式且未依照比例描繪’而尺寸均被誇大以 利於瞭解本發明。 參考第二A圖所示，顯示一介電層20 2與一導體層204 依序形成於一底材2 0 0上。此底材2 0 0至少包含一具有< 1 〇 0>晶格方向的矽底材，但不限於具有< 1 〇 〇>晶格方向 的石夕底材。底材2 〇 〇亦可包含介電材料如二氧化碎與類鑽 石之碳，也可包含鍺、珅化鎵與坤化銦。介電層2 〇 2至少 包含一以熱氧化法形成之墊氧化層（Pad 〇xide Layer)， 但不限於以熱氧化法形成之氧化層。介電層2 〇 2之厚度為 約1 0 0埃至約2 0 0埃之間，而以約2 0 0埃較佳。導體層4至 少包含一多晶矽層、一非晶矽層與一磊晶矽，此多晶石夕層 、非晶石夕層與一蠢晶石夕可以傳統之方法形成，例如化學氣 相沈積法或物理氣相沈積法，其他符合本發明精神之的材 料亦不應被排除。導體層2 04之厚度為約5〇埃至約2〇〇埃之 間0 參考第二B圖所示，一介電層2〇6與一導 形成於第二A圖所示之結構豆^ z 化㈣’此二氧化…以傳統二=少包含-二氧 相沈積法或物理氣相沈積法，但不 1’例如化學氣 層2〇6之厚度為約2〇〇埃至約5〇〇埃之、。一軋化石夕層。介電 含一多晶矽層、—非曰 ―體層2 0 8至少包 曰曰 矽層與磊晶矽可 A g /、麻日日矽，此多晶矽層、非 以傳統之方法形成，例如化學氣相沈積 557539 五、發明說明（7) 法或物理乳相沈積法，而其他符合本發明精神之的材料亦 不應被排除。導體層2 0 8之厚度為約6 0 0埃至約1 2 0 0埃之間 ，而以約1 0 0 0埃較佳。 參考第二C圖所示，一溝渠（Trench)經蝕刻導體層208 、介電層206、導體層204、介電層20 2與底材20 0而形成， 而一介電層210共形生成於導體層20 8與此溝渠上。此溝渠 的深度取決於此淺溝渠隔離所隔離的元件為何種元件，舉 例來說’對於快閃記憶體（F 1 a s h M e m 〇 r y)而言，此溝渠 的深度為約4 0 0 0埃，而對於邏輯元件如金屬氧化物半導體 (MOS)電晶體而言，此溝渠的深度為約2 9 0 0埃。此溝渠 係以非等向性钱刻例如反應性離子触刻形成較佳，但其他 傳統的蝕刻法亦可使用。介電層2 1 0至少包含一以熱氧化 法形成之線性氧化物（Linear Oxide)層。介電層210之厚 度為約1 0 0埃至約5 0 0埃之間 參考第二D圖所示，第二C圖中所示之溝渠被填入一介 電層212，且此介電層21 2與介電層210位於導體層20 8上的 部份被移除。介電層2 1 2與介電層2 1 0位於導體層2 0 8上的 部份可以傳統方式移除並提供一平坦之表面，例如化學機 械研磨。介電層2 1 2至少包含一以高密度電漿化學氣相沈 積之二氧化矽層，但不限於以高密度電漿（High Density Plasma)化學氣相沈積之二氧化矽層，其他符合本發明精 神之的材料亦不應被排除。。對於現代深次微米半導體技V. Description of the invention (6) The illustrations are in simple form and are not drawn to scale 'and the dimensions are exaggerated to facilitate understanding of the present invention. Referring to FIG. 2A, a dielectric layer 202 and a conductive layer 204 are sequentially formed on a substrate 200. This substrate 2000 includes at least one silicon substrate having a < 100 > lattice direction, but is not limited to a stone substrate having a < 100 > lattice direction. The substrate 2000 may also include dielectric materials such as crushed dioxide and diamond-like carbon, and may also include germanium, gallium sulfide, and indium Kundium. The dielectric layer 202 includes at least a pad oxide layer formed by a thermal oxidation method, but is not limited to an oxide layer formed by a thermal oxidation method. The thickness of the dielectric layer 202 is between about 100 angstroms and about 200 angstroms, and preferably about 200 angstroms. The conductive layer 4 includes at least a polycrystalline silicon layer, an amorphous silicon layer, and an epitaxial silicon. The polycrystalline silicon layer, the amorphous stone layer, and a stupid crystal layer can be formed by a conventional method, such as a chemical vapor deposition method. Or physical vapor deposition, other materials that are in line with the spirit of the invention should not be excluded. The thickness of the conductor layer 204 is between about 50 angstroms and about 200 angstroms. 0 Referring to the second diagram B, a dielectric layer 206 and a conductor are formed in the structure shown in the second diagram A ^ ㈣Chemicals 'this oxidation ... The traditional two = less-containing-dioxygen phase deposition method or physical vapor deposition method, but not 1', for example, the thickness of the chemical gas layer 206 is about 200 angstroms to about 50. 〇 Egypt ,. A layer of rolled fossils. The dielectric contains a polycrystalline silicon layer, which is not a bulk layer. At least the silicon layer and epitaxial silicon can be A g /, Ma Ri silicon, this polycrystalline silicon layer is not formed by traditional methods, such as chemical vapor phase Deposition 557539 V. Description of the invention (7) method or physical milk phase deposition method, and other materials consistent with the spirit of the invention should not be excluded. The thickness of the conductive layer 208 is between about 600 Angstroms and about 12 Angstroms, and preferably about 100 Angstroms. Referring to FIG. 2C, a trench is formed by etching the conductive layer 208, the dielectric layer 206, the conductive layer 204, the dielectric layer 202 and the substrate 200, and a dielectric layer 210 is formed conformally. On the conductor layer 20 8 and this trench. The depth of this trench depends on what kind of element is isolated by this shallow trench isolation. For example, 'for flash memory (F 1 ash M em ry), the depth of this trench is about 4 0 0 0 Angstroms. For logic elements such as metal oxide semiconductor (MOS) transistors, the depth of this trench is about 2900 Angstroms. The trench is preferably formed with an anisotropic coin such as a reactive ion touch etch, but other traditional etching methods can also be used. The dielectric layer 210 includes at least a linear oxide layer formed by a thermal oxidation method. The thickness of the dielectric layer 210 is between about 100 angstroms and about 500 angstroms. Referring to the second diagram D, the trench shown in the second diagram C is filled with a dielectric layer 212, and the dielectric The portions of the layer 21 2 and the dielectric layer 210 on the conductor layer 20 8 are removed. The portions of the dielectric layer 2 12 and the dielectric layer 2 10 on the conductive layer 208 can be removed in a conventional manner and provide a flat surface, such as chemical mechanical polishing. The dielectric layer 2 1 2 includes at least a silicon dioxide layer deposited by a high-density plasma chemical vapor deposition, but is not limited to a silicon dioxide layer deposited by a high-density plasma chemical vapor deposition. Inventive materials should not be excluded. . For modern deep submicron semiconductor technology
第10頁 557539 五、發明說明（8) 術中，有鑑於元件尺寸均極微小，以高密度電漿化學氣相 沈積法較符合需求。以高密度電漿化學氣相沈積法沈積二 氧化矽層係於化學氣相沈積的同時施以直流濺鍍（DC-Bias S pu 11 e r i n g)，以含石夕、含氧與含惰性氣體之混合氣體進 行反應。高密度電漿源提供低能量而密度高於.1 0 12cnr的離 子。以高密度電漿化學氣相沈積法沈積二氧化矽層亦可以 交流濺鍵（R F S p u 11 e r i n g)進行以避免電荷蓄積。於沈積 時，施加直流偏壓以加速氬（Argon)離子以濺擊並控制沈 積薄膜的性質，沈積速率等。高密度電漿化學氣相沈積法 可形成高品質、良好熱穩定性、低濕氣吸附性與優良之機 械性質之氧化物層。高密度電漿化學氣相沈積法係以化學 氣相沈積的同時加上直流錢擊以加強溝填（G a p - F i 1 1 i n g ) 能力。 參考第二E圖所示，導體層20 8被移除且一介電層214 接著共形生成於圖中所示之結構。導體層2 0 8以乾式蝕刻 法例如反應性離子法移除較佳。其他可移除導體層2 0 8之 方法如濕式蝕刻法亦不應被排除。介電層2 1 4至少包含一 以低壓化學氣相沈積法形成之二氧化矽層，但不限於以低 壓化學氣相沈積法形成之二氧化矽層。 參考第二F圖所示，介電層214、介電層20 6與導體層 2 0 4被非等向性蝕刻以形成保護間隙壁。第二F圖中所示之 結構係以傳統之製程步驟至少包含：非等向性蝕刻介電層Page 10 557539 V. Description of the invention (8) During the operation, in view of the extremely small component sizes, the high-density plasma chemical vapor deposition method is more suitable. The high-density plasma chemical vapor deposition method is used to deposit a silicon dioxide layer during chemical vapor deposition and DC-Bias S pu 11 ering. The mixed gas is reacted. High-density plasma sources provide low-energy ions with a density higher than .10 12cnr. High-density plasma chemical vapor deposition of silicon dioxide can also be performed by AC sputtering (R F S p u 11 e r i n g) to avoid charge accumulation. During deposition, a DC bias voltage is applied to accelerate Argon ions to splash and control the properties of the deposited film, the deposition rate, and the like. The high-density plasma chemical vapor deposition method can form an oxide layer of high quality, good thermal stability, low moisture adsorption, and excellent mechanical properties. The high-density plasma chemical vapor deposition method uses chemical vapor deposition and a direct current coin to strengthen the trench filling (G a p-F i 1 1 i n g) capability. Referring to the second figure E, the conductor layer 208 is removed and a dielectric layer 214 is then conformally formed in the structure shown in the figure. The conductive layer 208 is preferably removed by a dry etching method such as a reactive ion method. Other methods of removing the conductive layer 208, such as wet etching, should not be excluded. The dielectric layer 2 1 4 includes at least a silicon dioxide layer formed by a low pressure chemical vapor deposition method, but is not limited to a silicon dioxide layer formed by a low pressure chemical vapor deposition method. Referring to the second F diagram, the dielectric layer 214, the dielectric layer 206, and the conductor layer 204 are anisotropically etched to form a protective spacer. The structure shown in Figure 2F is a traditional process step including at least: anisotropic etching of the dielectric layer
557539 五、發明說明（9) 2 1 4以乾式餘刻法如反應性離子触刻法，非等向性姓刻介 電層2 0 6以乾式#刻法如反應性離子敍刻法與非等向性|虫 刻導體層2 0 4以乾式姓刻法如反應性離子姓刻法。介電層 2 1 4與介電層2 0 6亦可同時被姓刻，且由於介電層2 〇 6如一 二氧化石夕層與導體層20 4如一多晶石夕層之高|虫刻選擇比（ Selectivity Ratio)，導體層2 04被用作為蝕刻終止（ Etching-Stop)層以保護底下之介電層202。由於導體層557539 V. Description of the invention (9) 2 1 4 The dry-type post-etching method such as the reactive ion touch-engraving method, the non-isotropic surname engraving the dielectric layer 2 0 6 The dry-type # -engraving method such as the reactive ion engraving method and the non- Isotropic | Insect engraved conductor layer 2 0 4 is engraved with a dry name such as reactive ion. The dielectric layer 2 1 4 and the dielectric layer 2 06 can also be engraved at the same time, and because the dielectric layer 2 06 is as high as a dioxide layer and the conductive layer 20 4 is as high as a polycrystalline layer | Selectivity ratio, the conductive layer 204 is used as an Etching-Stop layer to protect the underlying dielectric layer 202. As the conductor layer
2 0 4對介電層2 0 2之高敍刻選擇比，使得餘刻導體層2 〇 4時 不會使介電層20 2被姓刻。介電層2 0 2如墊氧化層被用作為 犧牲氧化層（Sacrificial 〇xide Layer)，如此就不需再 進行形成犧牲氧化層的製程步驟。接著為了形成主動區域 ，η型佈植離子如磷離子或是p型佈植離子如硼離子佈植進 200 \ G圖所示，介電層202被蝕刻以暴露出底材The high etch ratio of 204 to the dielectric layer 202 is such that the conductor layer 204 will not be engraved with the surname when the conductor layer 204 is etched. The dielectric layer 202, such as a pad oxide layer, is used as a sacrificial oxide layer, so there is no need to perform a process step of forming the sacrificial oxide layer. Next, in order to form an active region, n-type implanted ions such as phosphorus ions or p-type implanted ions such as boron ions are implanted in the 200 \ G diagram, and the dielectric layer 202 is etched to expose the substrate.
以傳統之%I2 0 0如—矽底材與導體層2 04如一多晶矽層被 Layer〇21 人氧化以形成一閘極氧化層（Gate 0xide 法或濕式姓W電層2 0 2被蝕刻以傳統之方法例如乾式蝕亥 時同:夺被氧;二Ϊ體ί 204如一多晶矽層在底材2°°氧W 層2 04如—多曰矽;；：電層216如一二氧化矽層。導體 氧化速率，故阳莫辦、有大約二倍於底材2〇〇如一矽底材戈 如一二氢外 豆曰2 0 4如一多晶矽層將轉變成介電層2 1 " 羊L彳t*句7層。The traditional% I2 0 0 such as silicon substrate and conductive layer 2 04 such as a polycrystalline silicon layer is oxidized by Layer 021 to form a gate oxide layer (Gate 0xide method or wet type W electric layer 2 0 2 is etched to The traditional method, such as dry etching, is the same as the following: capture of oxygen; a dibasic body 204 such as a polycrystalline silicon layer on the substrate 2 ° oxygen W layer 20 04 such as polysilicon; an electrical layer 216 such as a silicon dioxide layer The oxidation rate of the conductor is not as high as that of the substrate, which is about twice as high as that of the substrate, such as a silicon substrate, such as a dihydrogen outer bean, and a polycrystalline silicon layer that will turn into a dielectric layer. 2 1 " Sheep L 彳t * sentence 7 layers.
第12頁 557539Page 12 557539
五、發明說明（ίο) 本發明避充，〜，Ν Ί工門紙iu七 、 化石夕造成之底材應力並利用間=防範Kooi效應及氮 或絕緣角部份。導體層204至少護淺溝渠隔離之轉角 被用以在淺溝渠隔離形成的製程中否夕曰曰石夕層或非晶矽層 牲氧化層，如此就不需再進行形成‘：電層2〇2作。為犧 。介電層2 0 6如-二氧化矽，#導體層2:: f ”程步驟 非晶石夕層之高触刻選擇比使得介電/ 〇夕Ba石夕層或 f的製程中不會受到損土裏。剩餘的導體層2〇4如一多晶石夕 曰或非晶矽層會與底材2 0 0在閘極氧化層218形成的過程中 一，被氧化，故元件隔離品質可被維持。形成之間隙壁可 保護淺溝渠隔離在各種製程步驟中如濕式蝕刻不被破壞， 故主動區域之間的隔離可以確保。 工延有關 ^ , ...... 〜叮州谷儿口月惶 业非限制。其他不脫離本發明之精神的等效改變或 應包含在的本發明的專利範圍之内。V. Description of the invention (ίο) The present invention avoids filling, ~, Ί 门 工 门 纸 iu VII, substrate stress caused by the fossil eve and the use of time = to prevent Kooi effect and nitrogen or insulation corners. The conductor layer 204 protects at least the corners of the shallow trench isolation. It is used in the process of forming the shallow trench isolation. It is said that the Xixi layer or the amorphous silicon layer is an oxide layer, so there is no need to form it again. 2 works. For the sacrifice. Dielectric layer 206 such as-silicon dioxide, #conductor layer 2 :: f ”process step, the high contact selectivity ratio of the amorphous stone layer makes the dielectric / 〇ba Ba stone layer or f process will not In the damaged soil, the remaining conductor layer 204, such as a polycrystalline stone or an amorphous silicon layer, will be oxidized with the substrate 200 during the formation of the gate oxide layer 218, so the component isolation quality Can be maintained. The formed barrier wall can protect shallow trench isolation in various process steps such as wet etching from being damaged, so the isolation between active areas can be ensured. Work delay related ^, ...... ~ Dingzhou Guerkou Yueye is not limited. Other equivalent changes that do not depart from the spirit of the present invention or should be included in the patent scope of the present invention.
第13頁 557539 圖式簡單說明 為了能讓本發明上述之其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 第一 A圖顯示一傳統的淺溝渠隔離之剖面圖； 第一 B圖顯示一傳統的淺溝渠隔離之剖面圖，此淺溝 渠隔離在其轉角處有溝槽； 第二A圖顯示一介電層與一導體層依序形成於一底材 上的結果， 第二B圖顯示依序形成一介電層與一導體層於第二A圖 中所示的結構之結果； 第二C圖顯示形成一溝渠進入第二B圖中所示的結構與 共形生成一介電層於其上的結果； 第二D圖顯示填滿溝渠以形成淺溝渠隔離並將淺溝渠 隔離平坦化的結果； 第二E圖顯示移除第二D圖中所示的頂部導體層並接著 形成一介電層於其上之結果；Page 557539 Brief description of the drawings In order to make the other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Figure A shows a section view of a conventional shallow trench isolation. Figure B shows a section view of a conventional shallow trench isolation. The shallow trench isolation has trenches at its corners. Figure A shows a dielectric layer. And a conductor layer sequentially formed on a substrate, the second diagram B shows the result of sequentially forming a dielectric layer and a conductor layer in the structure shown in the second diagram A; the second diagram C shows formation The result of a trench entering the structure shown in Figure 2B and conformal formation of a dielectric layer on it; Figure 2D shows the result of filling the trench to form shallow trench isolation and flattening the shallow trench isolation; Figure 2E shows the result of removing the top conductor layer shown in Figure 2D and then forming a dielectric layer on it;
第14頁 557539 圖式簡單說明 第二F圖顯示非等向性蝕刻第二E圖中所示的結構並形 成淺溝渠隔離間隙壁的結果；及 第二G圖顯示完成本發明之淺溝渠隔離並氧化底材之 結果。 主要部分之代表符號： 1 0 0底材 1 0 2二氧化矽層 1 0 4氮化矽層 1 0 6線性氧化層 1 0 8淺溝渠隔離氧化層 2 0 0底材 2 0 2介電層 2 0 4導體層 2 0 6介電層 2 0 8導體層 2 1 0介電層 2 1 2介電層 2 1 4介電層 2 1 6介電層 2 18閘極氧化層Page 14 557539 Schematic illustration of the second F diagram showing the results of anisotropic etching of the structure shown in the second E diagram and the formation of a shallow trench isolation barrier; and the second G diagram shows the completion of the shallow trench isolation of the present invention And the result of oxidizing the substrate. Representative symbols of main parts: 1 0 0 substrate 1 0 2 silicon dioxide layer 1 0 4 silicon nitride layer 1 0 6 linear oxide layer 1 0 8 shallow trench isolation oxide layer 2 0 0 substrate 2 0 2 dielectric layer 2 0 4 conductor layer 2 0 6 dielectric layer 2 0 8 conductor layer 2 1 0 dielectric layer 2 1 2 dielectric layer 2 1 4 dielectric layer 2 1 6 dielectric layer 2 18 gate oxide layer
第15頁Page 15
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