TW557528B

TW557528B - Automatic grading system of wafer product and method thereof

Info

Publication number: TW557528B
Application number: TW91109020A
Authority: TW
Inventors: Yu-Chih Chen; Remaerd Hsieh
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-04-30
Filing date: 2002-04-30
Publication date: 2003-10-11

Abstract

An automatic grading system of wafer product is disclosed, which comprises at least a testing unit and a grading unit. The testing unit proceeds test to plural chip units of the wafer for multiple testing items, and obtains a tested result corresponding to each testing item respectively for each chip unit. The grading unit determines the error value of each chip unit corresponding to each testing item according to the tested result of each testing item corresponding to each chip unit and the specification limitation of each corresponding testing item, and sums up the error value of each corresponding testing item for each chip unit, so as to obtain a corresponding total error value for each chip unit, and then proceeds grading for each chip unit according to a predetermined grading scale and the total error value of each corresponding chip unit.

Description

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本毛明係有關於一種自動分級糸雄；5古、土 _ 關於-種日in rw f 徑曰勒刀級糸統及方法’且特別有 ^日。日固（Wafer)產品之自動分級系統及方法。之f程i Ξ代工製造廠中’# 一晶圓都必須經過大量精密中:方可得到最後的產品。在生產晶圓的過程产等%境因子、工程師的操作行為以及製程技術程度寺4都可能影響到整體晶圓之生產良率。以動恶隨機存取記憶體（Dynamic Random Access en^ory)為例，在每一個晶圓中的每一個晶片之中都包括置相同結構之記憶體單元（Mem〇ry Cel丨）。在製造過程中:由於製程技術的限制或是其他人為操作失當的情況，往Ϊ會造成一個晶片中某些記憶體單元會有所損壞。然而，由=動態隨機存取記憶體特別的設計，這些具有損壞憶體f元之動態隨機存取記憶體仍然可以使用。舉例來說，最而品質（具有很少損壞之記憶體單元）的動態隨機記憶體用於高階處理器之用，而較低品質的動記憶體用於繪圖卡之用。或仔取在動態隨機存取記憶體製造廠中，晶圓中晶片的情形必須由測試人員將每一晶圓經過測試機台來進行檢測。然而，由於大量的晶圓與缺乏有效自動結合測試工與晶圓分級的機制，也大幅增加製造廠大量的人力需求，以及喪失次級產品再利用的好處。 2鑑於此，本發明之主要目的為提供一種晶圓產品之自動为級糸統及方法，本發明可以結合測試機台斑自八級單元，將測試完成的晶圓直接進行分級。 *、刀The Maoming Department is about an automatic grading of males; 5 ancient, soil _ about-seed day in rw f diameter said Ledao-level system and method 'and especially ^ day. Automatic grading system and method for Wafer products. In order to obtain the final product, a wafer must be subjected to a large amount of precision in the foundry manufacturing plant. Environmental factors such as the production of wafers, the operating behavior of engineers, and the degree of process technology may affect the overall yield of wafers. Taking Dynamic Random Access Memory (Dynamic Random Access Encryption) as an example, each wafer in each wafer includes a memory unit (Memory Cel) with the same structure. During the manufacturing process: due to process technology limitations or other human mishandling, some memory cells in a chip will be damaged. However, due to the special design of dynamic random access memory, these dynamic random access memories with corrupted memory f-elements can still be used. For example, the highest quality (with less damaged memory cells) dynamic random access memory is used for high-end processors, and lower quality dynamic memory is used for graphics cards. Or, in a dynamic random access memory manufacturing factory, the condition of the wafers in the wafer must be tested by a tester by passing each wafer through a test machine. However, due to the large number of wafers and the lack of a mechanism to effectively automatically combine testers and wafer grading, it has also greatly increased the manpower requirements of manufacturing plants and lost the benefits of secondary product reuse. 2 In view of this, the main purpose of the present invention is to provide an automatic level system and method for wafer products. The present invention can directly classify the wafers that have been tested in combination with the test machine from the eight-level unit. *, Knife

立、發明說明（2) 為了達成上述目的，u — 之自動分級系統及方法、拿可藉由本發明所提供之晶圓產品品之自動分級系統包括至，二依據本發明實施例之晶圓產1 元。 y測试單元與一分級處理單測4單元將晶圓之目進行測試，從而I B调曰曰片早疋分別針對多個測試頌到-測試結果。：：；晶片單元相應每-測試項目分别每-測試項目之测；、:；虚依據每-晶片單元相應決定晶片單元相應每一，母一測試項目之規格限制一晶片單元，加_ :二項目之錯誤值。之後，對於每 ?片單元得到相應之之錯誤值’從而每- 級。以⑭應之總錯誤值，將每一晶片#元進行分” 晶片二卜為ΓίΓΓ實施例：若晶圓中具有同-級別之別。分級單時’則》級早70將此晶®分級為此級别之批貨。具有此級別之多個晶圓合併為具有此級其中，規格限制包.括相應測試項目之規格上限横格下限值與規格容錯值。眼值残實施例第1圖係顯示依據本發明實施例之晶圓產品之自動分級出^系統之系統架構。第2圖係顯示依據本發明實施例之晶圓產品之自動分級出貨方法之操作流程。依據本發明實施例之自動分級出貨系統包括多個測鉍(2) In order to achieve the above-mentioned object, the automatic classification system and method for u — and the automatic classification system for wafer products provided by the present invention include the following: 1 Yuan. The y test unit and a grading processing unit test 4 units test the purpose of the wafer, so that the IB tuning is based on the test results for multiple tests. ：:; each unit of test unit corresponding to the test unit of each wafer test item;;:; virtual basis on the basis of each unit of the wafer unit to determine the corresponding unit of each wafer unit, the specifications of the parent one test item limit one wafer unit, plus _: two The error value of the item. After that, a corresponding error value ′ is obtained for each slice unit and thus each stage. The total error value corresponding to each wafer is used to divide each wafer. The wafer is classified as ΓΓΓΓ Example: If the wafers have the same-level difference. When grading a single order, then the crystal is graded as early as 70. This level is a batch of goods. Multiple wafers with this level are combined to have this level. Among them, the specification limit includes the upper limit of the upper limit of the corresponding test item and the lower limit of the specification and the tolerance value of the specification. The figure shows the system architecture of the automatic grading system for wafer products according to the embodiment of the present invention. The second figure shows the operation flow of the method for automatic grading and shipping of wafer products according to the embodiment of the present invention. Example automated grading shipping system includes multiple bismuth measurements

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=10與—分級單元12。測試單元1G可以是具有檢測晶圓中晶片單元損壞情形或電路檢測之檢測機台。首先，如步驟S2 0，測試單元丨0將晶圓之多個晶片單元分別針對多個測試項目進行測試，從而每一晶片單元相應每一測試分別得到一測試結果。、之後，如步驟S22，分級單元丨2依據每一晶片單元相應每一測試項目之測試結果與相應每一測試項目之規格限制決定晶片單元相應每一測試項目之錯誤值。其中，規格限制包括相應測試項目之規格上限值、規格下限值與規格之後，如步驟S24，對於每一晶片單元，加總相應每 -測試項目之錯誤值，&而每一晶片單元得到相應之總錯誤值。最後，如步驟S26，依據一既定級距與每一晶片單元相應之總錯誤值’將每一晶片單元進行分級。注意的卜測試單元10可以依據不同的產品類型而有不同的測試項目，且同一種產品類型也可以，。舉繼’測試項目可以是晶片單元之接觸測^ 是電性測試。當晶圓中具有同一級別之晶片單元為最多數時，則分級單元1 2將此晶圓分級為此一級別。另夕卜，分級單元i 2亦可將具有此-級別之多個晶圓合併為具有此級別之批貨，用以提供予出貨單位來依據不同等級之批貨進行出貨。接下來，舉實例進行說明。第3圖係顯示晶圓中晶片單元相應每一測試項目之錯誤值與加總之總錯誤值例子。= 10 与 —grading unit 12. The test unit 1G may be a test machine having a wafer unit damage condition or a circuit inspection in the wafer. First, as in step S20, the test unit 丨 0 tests a plurality of wafer units of a wafer separately for a plurality of test items, so that each wafer unit obtains a test result corresponding to each test. Then, according to step S22, the grading unit 2 determines the error value of each test item of the wafer unit according to the test result of each test item of each wafer unit and the specification limit of each test item. Among them, the specification limit includes the specification upper limit value, the specification lower limit value, and the specification of the corresponding test item. In step S24, for each wafer unit, the corresponding per-test item error value is added up, and each wafer unit Get the corresponding total error value. Finally, in step S26, each wafer unit is classified according to a predetermined step distance corresponding to the total error value of each wafer unit. Note that the test unit 10 may have different test items according to different product types, and the same product type may also be used. The following test item may be a contact test of a chip unit. It is an electrical test. When the number of wafer units with the same level in the wafer is the largest, the classification unit 12 classifies the wafer to this level. In addition, the grading unit i 2 can also combine multiple wafers with this level into batches with this level, and provide them to the shipping unit to ship according to different levels of batches. Next, an example will be used for explanation. Figure 3 shows an example of the error value and the total error value of each test item corresponding to the wafer unit in the wafer.

557528 五、發明說明（4)557528 V. Description of Invention (4)

在此例子中，等級A的總錯誤值設為1 — 5之間；等級B 的總錯誤值設為6-49之間；等級C的總錯誤值設為5〇-95之間；等級D的總錯誤值設為95-9 9之間；以及等級e的總奸誤值設為99以上。、心a 以晶片單元1為例，其相應測試項目丨至8之錯爷八別為 '、〇/, 、、、2" 、、、5„ 、、、1 厂/ 、、、3"、、、曰〇:、、刀與、、〇"，則晶片單元1相應之總錯誤值為、、21,,' ，則晶片單元1被分級為等級B。以晶片單元2為例，立相應測試項目1至8之錯誤值分別為、、丨-、、、0 „ VN〇 ,7 w 、、、(Τ 、Μ" 、與、0" ’則晶、片單元2相應之總錯誤值為1，，，則晶片單元2被分級為等級Α。注意的當晶片單元的測試結果在判斷限制之規上限值與規格下限值之間時，則其錯誤值為、、0„ 。而告測試結果大於規格上限值時，則錯誤值可以下列方程式"表示：錯誤值=((測試結果-規格上限值）/規格上限值）—規格值。而測試結果小於規格下限值時，則錯誤值可以下列方錯誤值=(I (測試結果-規格下格容錯值。限值）| /規格下限值）—規曰曰In this example, the total error value of level A is set between 1-5; the total error value of level B is set between 6-49; the total error value of level C is set between 50-95; level D And the total error value of level e is set to 99 or more. 、 Heart a Take chip unit 1 as an example. The corresponding test items 丨 to 8 are the same as', 〇 /,,,, 2 ",,, 5 „,,, 1 factory /, ,, 3 ", ,, said 〇: ,, knife and, 〇 ", the corresponding total error value of wafer unit 1 is ,, 21 ,, ', then wafer unit 1 is classified as level B. Take wafer unit 2 as an example, The corresponding error values of the corresponding test items 1 to 8 are ,, 丨-,,, 0 „VN〇, 7 w 、, ((T, M ", and, 0 " 'The total error value corresponding to the chip, chip unit 2' 1 ,, then the wafer unit 2 is classified as a grade A. Note that when the test result of the wafer unit is between the upper limit value of the judgment limit and the lower limit value of the specification, the error value is ,, 0.. When the test result is greater than the upper limit of the specification, the error value can be expressed by the following equation " Value, the error value can be the following error value = (I (test result-grid tolerance value under specifications. Limit value) | / under specifications Value) - Yue Yue Regulation

A 以晶圓1為例，其圓1被分級為等級於等級B，因此第4圖係顯示晶圓進行分級的例子。片單元之大部分屬於等級A，因此，晶以晶圓2為例’其晶片單元之大部分屬A Take wafer 1 as an example, and circle 1 is classified into grade B, so Figure 4 shows an example of wafer classification. Most of the wafer units belong to grade A. Therefore, the wafer takes wafer 2 as an example.

557528 五、發明說明（5) ，晶圓2被分級為等級B。第5 a、5 b、5 c圖為示意圖係分別顯示不同等級之晶圓例子。如圖所示，第5a圖之晶圓為一等級A之晶圓，其中晶片單元的總錯誤值大部分皆在1 -5之間；第5b圖之晶圓為一等級B之晶圓，其中晶片單元的總錯誤值大部分皆在6-49之間；第5c圖之晶圓為一等級C之晶圓，其中晶片單元的總錯誤值大部分皆在5 0 - 9 5之間。第6圖係顯示相同等級晶圓進行合併的例子。如圖所示，當相同等級的晶圓合併之後，批貨1中包含大部分都是等級A之晶圓，也具有最多等級A之晶片單元。相反地，批貨5中包含大部分都是等級D之晶圓，也具有最多等級D 之晶片單元。因此，藉由本發明所提出之晶圓產品之自動分級出貨系統及方法，可以結合測試機台與自動分級單元，將測試完成的晶圓直接進行分級，從而節省大量進行測試與分級的人力，進一步創造次級產品的產值。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍内，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。557528 5. Description of the invention (5), wafer 2 is classified as grade B. Figures 5a, 5b, and 5c are schematic diagrams showing examples of wafers of different grades, respectively. As shown in the figure, the wafer in Figure 5a is a grade A wafer, and the total error value of the wafer unit is mostly between 1-5. The wafer in Figure 5b is a grade B wafer. The total error value of the wafer unit is mostly between 6 and 49; the wafer in Figure 5c is a grade C wafer, and the total error value of the wafer unit is mostly between 50 and 95. Figure 6 shows an example of merging wafers of the same grade. As shown in the figure, after the wafers of the same grade are merged, Lot 1 contains most of the wafers of grade A and also has the most wafer units of grade A. Conversely, lot 5 contains wafers that are mostly grade D and also has the most wafer units of grade D. Therefore, with the automatic grading and shipping system and method for wafer products proposed by the present invention, the testing machine and the automatic grading unit can be combined to directly grade the wafers that have been tested, thereby saving a lot of manpower for testing and grading. Further create the output value of secondary products. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

0503-6973TWF(N) ； TSMC2000-0553 ； yianhou.ptd 第8頁 557528 圖式簡單說明為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一實施例，並配合所附圖示，作詳細說明如下：第1圖係顯示依據本發明實施例之晶圓產品之自動分級系統之系統架構。第2圖係顯示依據本發明實施例之晶圓產品之自動分級方法之操作流程。第3圖係顯示晶圓中晶片單元相應每一測試項目之錯誤值與加總之總錯誤值例子。第4圖係顯示晶圓進行分級的例子。第5a、5b、5c圖為不意圖係分別顯不不同等級之晶圓例子。第6圖係顯示相同等級晶圓進行合併的例子。符號說明 1 0〜測試單元； 1 2〜分級單元； S20、S22.....S2、6〜操作步驟。0503-6973TWF (N); TSMC2000-0553; yianhou.ptd page 8 557528 The diagram briefly illustrates that in order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, an example is given below, in conjunction with the attached The diagram is described in detail as follows: FIG. 1 shows a system architecture of an automatic grading system for a wafer product according to an embodiment of the present invention. FIG. 2 shows the operation flow of an automatic grading method for a wafer product according to an embodiment of the present invention. Figure 3 shows an example of the error value and the total error value of each test item of the wafer unit in the wafer. Figure 4 shows an example of wafer grading. Figures 5a, 5b, and 5c are examples of wafers that are not intended to show different grades. Figure 6 shows an example of merging wafers of the same grade. Explanation of symbols 1 0 ~ test unit; 12 ~ grading unit; S20, S22 ..... S2, 6 ~ operation steps.

0503-6973TWF(N) ； TSMC2000-0553 ； yianhou.ptd 第9頁0503-6973TWF (N); TSMC2000-0553; yianhou.ptd page 9

Claims

557528 修正辛補充 _案號91109020 年呤月六、申請專利範圍 _ 1. 一種晶圓產品之自動分級系統，包括：至少一測試單元，用以將一晶圓之複數晶片單元分別針對複數測試項目進行測試，從而每一該等晶片單元相應每一該等測試項目分別得到一測試結果；以及一分級單元，依據每一該等晶片單元相應每一該等測試項目之該測試結果與相應每一該等測試項目之一規格限制決定該晶片單元相應每一該等測試項目之一錯誤值，並對於每一該等晶片單元，加總相應每一該等測試項目之該等錯誤值，從而每一該等晶片單元得到相應之一總錯誤值，且依據一既定級距與每一該等晶片單元相應之該總錯誤值，將每一該等晶片單元進行分級。 2. 如申請專利範圍第1項所述之晶圓產品之自動分級系統，更包括若該晶圓中具有一級別之該等晶片單元為最多數，則該分級單元將該晶圓分級為該級別。 3. 如申請專利範圍第1項所述之晶圓產品之自動分級系統，更包括該分級單元將具有該級別之複數晶圓合併為具有該級別之批貨。 4. 如申請專利範圍第1項所述之晶圓產品之自動分級系統，其中該規格限制包括相應該測試項目之規格上限值。 5. 如申請專利範圍第1項所述之晶圓產品之自動分級系統，其中該規格限制包括相應該測試項目之規格下限值。 6. 如申請專利範圍第1項所述之晶圓產品之自動分級557528 Amendment Xin_Case No. 91109020 June 6, Patent Application Scope_ 1. An automatic grading system for wafer products, including: at least one test unit, which is used to target multiple wafer units of a wafer to multiple test items respectively Testing, so that each of the wafer units obtains a test result corresponding to each of the test items; and a classification unit, according to the test results of each of the wafer units and each of the test items and each of the corresponding test items A specification limitation of one of the test items determines an error value corresponding to each of the test items of the chip unit, and for each of the chip units, the error values corresponding to each of the test items are added up, so that each One such wafer unit obtains a corresponding total error value, and each of the wafer units is classified according to a predetermined step distance corresponding to the total error value of each of the wafer units. 2. The automatic grading system for wafer products as described in item 1 of the scope of the patent application, further comprising, if the wafer unit having a level in the wafer is the largest number, the grading unit grades the wafer into the level. 3. The automatic grading system for wafer products as described in item 1 of the scope of the patent application, further including the grading unit that merges multiple wafers with this level into batches with that level. 4. The automatic classification system for wafer products as described in item 1 of the scope of patent application, wherein the specification limit includes the upper limit value of the corresponding specifications of the test item. 5. The automatic grading system for wafer products as described in item 1 of the patent application scope, wherein the specification limit includes the lower specification value of the corresponding test item. 6. Automatic grading of wafer products as described in item 1 of the scope of patent application

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0503-6973TWF1(N);TSMC2000-0553;Yi anhou.ptc 第10頁 5575280503-6973TWF1 (N); TSMC2000-0553; Yi anhou.ptc Page 10 557528

包括相應該測試項目之規格容錯銮號 91109020 _ _ 六、申請專利範圍 /系統，其中該規格限制值。 7. 如申請專利範圍系統’其中違測试項目 8. 如申請專利範圍系統，其中該測試項目 9. 一種晶圓產品之將一晶圓之複數晶測試，從而每一該等晶得到一測試結果，依據每一該等晶片試結果與相應每一該等單元相應每一該等測試對於母一遠專晶片之該等錯誤值，從而每誤值；以及第1項所述之晶圓產品之自動分級為接觸測試。第1項所述之晶圓產品之自動分級為電性測試。自動分級方法，包括下列步驟：片單元分別針對複數測試項目進行片單元相應每一該等測試項目分別單元相應每一該等測試項目之該測測試項目之一規格限制決定該晶片項目之一錯誤值；單元，加總相應每一該等測試項目一該等晶片單元得到相應之一總錯依據一既定級距與每一該等晶片單元相應之該總錯誤值，將每一該等晶片單元進行分級。 1 0 ·如申請專利範圍第9項所述之晶圓產品之自動分級方法’更包括若該晶圓中具有一級別之該等晶片單元為最多數，則將該晶圓分級為該級別。 11 ·如申請專利範圍第9項所述之晶圓產品之自動分級方法，更包括將具有該級別之複數晶圓合併為具有該級別之批貨。Including the fault tolerance specification of the corresponding test item No. 91109020 _ _ VI. Patent application scope / system, where the specification limit value. 7. If the patent scope system is applied, where the test items are violated. 8. If the patent scope system is applied, the test item is 9. The wafer product is a multiple crystal test of a wafer, so that each of the crystals receives a test. As a result, according to each of these wafer test results and each of these units, each of these tests corresponds to the error values of the mother-distance wafer, and thus each error value; and the wafer product described in item 1 It is automatically classified as a contact test. The automatic classification of the wafer products described in item 1 is electrical testing. The automatic grading method includes the following steps: The slice unit performs a slice unit for a plurality of test items, and each of the test items corresponds to one of the test items. The specification limit of one of the test items determines an error of the wafer item. Unit, add up each of these test items, one of these wafer units, and get a corresponding one of the total errors. Based on a predetermined step distance, the total error value corresponding to each of these wafer units is Grading. 10 · The method for automatically grading a wafer product as described in item 9 of the scope of the patent application 'further includes grading the wafer to that level if the wafer unit having a level in the wafer is the majority. 11 · The automatic grading method for wafer products as described in item 9 of the scope of patent application, further comprising merging a plurality of wafers with this level into a batch with this level.

〇503-6973TWFl(N);TSMC200〇.〇553;Yianhou.ptc 第 11 頁 557528 _案號91109020_年月曰修正_ 六、申請專利範圍 1 2 ·如申請專利範圍第9項所述之晶圓產品之自動分級方法，其中該規格限制包括相應該測試項目之規格上限值。 1 3.如申請專利範圍第9項所述之晶圓產品之自動分級方法，其中該規格限制包括相應該測試項目之規格下限值。 1 4.如申請專利範圍第9項所述之晶圓產品之自動分級方法，其中該規格限制包括相應該測試項目之規格容錯值。 1 5.如申請專利範圍第9項所述之晶圓產品之自動分級方法，其中該測試項目為接觸測試。 1 6.如申請專利範圍第9項所述之晶圓產品之自動分級方法’其中該測試項目為電性測試。〇503-6973TWFl (N); TSMC200〇.〇553; Yianhou.ptc Page 11 557528 _ Case No. 91109020 _ year month month amendment _ 6, the scope of patent application 1 2 · as described in the scope of the patent application No. 9 The automatic classification method for round products, wherein the specification limit includes the upper specification limit of the corresponding test item. 1 3. The automatic grading method for a wafer product as described in item 9 of the scope of patent application, wherein the specification limit includes the lower specification value of the corresponding test item. 1 4. The automatic grading method for wafer products as described in item 9 of the scope of patent application, wherein the specification limit includes the specification tolerance value of the corresponding test item. 1 5. The automatic grading method for wafer products as described in item 9 of the scope of patent application, wherein the test item is a contact test. 1 6. The automatic grading method for wafer products as described in item 9 of the scope of patent application, wherein the test item is an electrical test.

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