TW557487B - Method for producing dielectric isolated silicon (DIS) - Google Patents

Abstract

A method for producing a dielectric isolated silicon (DIS) comprises: conformally forming a first dielectric layer in the opening of a substrate having an opening; using an ion implantation method to form a boron doped layer having a doping concentration of 10<19> to 10<21> atom/cm<3> on the interface between the surface of the substrate and the first dielectric layer; anisotropically etching the first dielectric layer to form a dielectric spacer on the inner wall of the opening; using a selective epitaxial method to form a single crystal silicon layer in the opening; sequentially performing an anodic treatment and a thermal oxidation treatment to convert the doping layer on the periphery of the single crystal silicon layer into a second dielectric layer as a dielectric isolation layer; and polishing off the second dielectric layer until exposing the surface of the silicon layer, thereby completing the production of the dielectric isolated silicon structure.

Description

/487/ 487

發明領域： 本發明係有關於一種半 種介電隔離石夕晶之製造方 構並可降低熱預算進而簡化 相關技術說明： 導體製程技術，特別是有關於 法，無需額外形成溝槽隔離結 製程步驟及降低製造成本。 幾π 5I製造的半導體凡件中，尸、有應用到矽晶圓表面約 成1奈米（_)厚度作為元件主動區Uctive are〇 ，Field of the Invention: The present invention relates to a manufacturing structure for a half-type dielectric isolation stone and can reduce the thermal budget and thereby simplify the related technical description: Conductor process technology, especially related to the method, without the need to form an additional trench isolation junction process Steps and reduce manufacturing costs. Among the semiconductor products manufactured by several π 5I, the thickness of the semiconductor wafer applied to the surface of the silicon wafer is about 1 nm (_) as the active area Uctive are.

成原件與石夕基底產生寄生效應（parasitic effect 日閉鎖效應（latch-up effect )及增加基底漏電流等 二j發生。然而，隨著積體電路製程技術日新發展，於是 ^出-種將絕緣薄膜設置於單㈠下方以隔離元件層與石夕 土底層之…構來解決上述之問題。此種結構即為絕緣層上 矽晶（silicon on insulat〇r，s〇I )結構，而其中所使 用之絕緣層通常為氧化矽層，主要是因利用矽熱生長之氧 化矽層對於矽晶圓的製程整合性較高。The original and the parasitic effect of the Shixi substrate produce a latch-up effect and increase the leakage current of the substrate. However, with the development of the integrated circuit process technology, new technologies have been developed, so it will come out The insulating film is arranged under the single layer to isolate the element layer and the bottom layer of the stone to solve the above problems. This structure is a silicon on insulator (soi) structure, and among them The insulating layer used is usually a silicon oxide layer, which is mainly due to the high integration of the silicon wafer process by silicon thermal growth.

為了進一步說明本發明背景，以下配合第“及。圖說 明習知形成絕緣層上矽晶（s〇I )結構之方法。首先，請 參照第ia圖，提供-基底m，例如—石夕晶圓，對高溫的 基底100，例如600 t，進行氧離子高能佈值。接著，請參 照第lb圖，實施兩階段退火處理，例如分別在125(rc及 1 35 0 °C，以消除佈值時對基底100的損害，並形成埋藏氧 化層（buried oxide layer，B0X) 1〇〇&amp;而隔離出矽元件 層100b。此即所謂的氧離子佈值隔離矽晶（separat i〇nIn order to further illustrate the background of the present invention, the following steps are described with reference to "." The conventional method for forming a silicon crystal (soi) structure on an insulating layer is described below. First, please refer to the ia diagram, providing-substrate m, for example-Shi Xijing Round, for high-temperature substrate 100, such as 600 t, the oxygen ion high-energy distribution value. Next, refer to Figure lb, and implement two-stage annealing treatment, such as 125 (rc and 1 35 0 ° C, to eliminate the distribution value Damages the substrate 100, and forms a buried oxide layer (B0X) 1 00 &amp; and isolates the silicon element layer 100b. This is the so-called oxygen ion cloth isolation silicon crystal (separat i〇n

557487 五、發明說明（2) 〜 by implanted oxygen，SIMOX )製程技術。然而，此種製 程方法需在局溫下進行、熱預算（dermal budget)大以 及埋藏氧化層應力高等問題。 為了解決上述問題，美國專利第5, 950, 〇94號揭示— 種介電隔離矽層（DIS)製造方法，其藉由在具有埋藏摻 雜層的基底上形成溝槽，並接著進行陽極處理及熱氧化步 驟而將埋藏摻雜層轉成埋藏氧化層。最後，在溝槽内填入 介電層而完成介電隔離矽層結構。然而，此種方法係運用 兩種隔離結構。亦即以埋藏氧化層作縱向元件隔離且以溝 槽隔離結構作橫向元件隔離，製程較為複雜。 有鑑於此，本發明提供一種介電隔離矽晶之製造方法 ，包括下列步驟：在具有溝槽的矽基底的溝槽外圍形成摻 雜層。接著，在溝槽内形成單晶矽層。然後，經由陽極^ f及氧化處理而使摻雜層快速轉成介電隔離層並包圍住單 曰曰石夕層。最後’磨除單晶矽層上方之介電層。因此，無需 再形成橫向元件隔離結構且有效降低熱預算。 發明概述： 、本發明之目的在於提供一種介電隔離矽晶之製造方 法，其無需額外再形成溝槽來製作隔離結構而簡化製程 驟。 少 本發明之另一目的在於提供一種介電隔離矽晶之 少Ξ預ί藉由氧化多孔隙矽層以快速形成介電隔離層而減 根據上述之目的，本發明提供一種介電隔離矽晶之製557487 V. Description of the invention (2) ~ by implanted oxygen (SIMOX) process technology. However, this process method needs to be performed at local temperature, large dermal budget, and high buried oxide stress. In order to solve the above problems, U.S. Patent No. 5,950, 〇94 discloses a method for manufacturing a dielectric isolation silicon layer (DIS) by forming a trench on a substrate having a buried doped layer and then performing anodization. And thermal oxidation step to convert the buried doped layer into a buried oxide layer. Finally, a dielectric layer is filled in the trench to complete the dielectric isolation silicon layer structure. However, this method uses two isolation structures. That is, the buried oxide layer is used for vertical element isolation and the trench isolation structure is used for lateral element isolation. The manufacturing process is more complicated. In view of this, the present invention provides a method for manufacturing a dielectrically isolated silicon crystal, including the following steps: forming a doping layer on the periphery of a trench of a silicon substrate having a trench. Next, a single crystal silicon layer is formed in the trench. Then, the anode layer and the oxidation process are used to quickly convert the doped layer into a dielectric isolation layer and surround the monolithic layer. Finally, the dielectric layer above the single crystal silicon layer is abraded. Therefore, it is no longer necessary to form a lateral element isolation structure and effectively reduces the thermal budget. SUMMARY OF THE INVENTION: The object of the present invention is to provide a method for manufacturing a dielectric isolation silicon crystal, which does not require additional trenches to form an isolation structure and simplifies the manufacturing process. Another object of the present invention is to provide a dielectric isolating silicon crystal. According to the above object, the present invention provides a dielectric isolating silicon crystal by oxidizing a porous silicon layer to quickly form a dielectric isolating layer. System

557487 五、發明說明（3)557487 V. Description of the invention (3)

造方法’包括下列步驟··提供一基底，此基底上形成有一 開口；在該開口内表面順應性形成一第一介電層；在基底 之表面及與第一介電層相鄰之界面形成一摻雜層；非等向 性蝕刻第一介電層，以在開口底部露出摻雜層表面並在開 口内側壁形成一介電間隔層；在内側壁形成有介電間隔層 之開口内填滿一矽層；在介電間隔層及矽層上方形成一保 護層；將基底浸入一反應溶液以實施陽極處理；去除保護 層；實施一氧化處理，以在矽層外圍形成一第二介電層， 以作為介電隔離層；以及研磨去除第二介電層直至露出石夕 層表面。其中，藉由離子植入法形成硼摻雜層且摻雜濃度 在1019到1021 atom/cm3的範圍。再者，藉由選擇性磊晶法 形成單晶矽層。 ％ / 較佳實施例之詳細說明： 以下配合第2到1 〇圖說明本發明實施例之介電隔離矽 晶之製造方法。 一基底2 0 0，例如一石夕晶 塾氧化層202及一氮化矽層 首先，請參照第2圖，提供 圓，此基底200上依序形成有一 204。 接下來，請參照第3圖，藉由f知微影製程並以氣化The manufacturing method includes the following steps: a substrate is provided, an opening is formed on the substrate; a first dielectric layer is conformably formed on the inner surface of the opening; and a surface of the substrate and an interface adjacent to the first dielectric layer are formed A doped layer; anisotropically etch the first dielectric layer to expose the surface of the doped layer at the bottom of the opening and form a dielectric spacer layer on the inner side wall of the opening; Full silicon layer; forming a protective layer over the dielectric spacer layer and the silicon layer; immersing the substrate in a reaction solution to perform anodizing; removing the protective layer; performing an oxidation treatment to form a second dielectric around the silicon layer Layer as a dielectric isolation layer; and grinding and removing the second dielectric layer until the surface of the Shi Xi layer is exposed. Among them, a boron-doped layer is formed by an ion implantation method with a doping concentration in a range of 1019 to 1021 atom / cm3. Furthermore, a single crystal silicon layer is formed by a selective epitaxy method. % / Detailed description of the preferred embodiment: The manufacturing method of the dielectric isolation silicon crystal according to the embodiment of the present invention will be described below with reference to Figs. 2 to 10. A substrate 200, such as a stone crystalline silicon hafnium oxide layer 202 and a silicon nitride layer. First, please refer to FIG. 2 to provide a circle. A 204 is sequentially formed on the substrate 200. Next, please refer to Figure 3 to understand the lithography process and f

石夕層204及墊氧化層2〇2作為硬弋罢苴麻工各# &amp;一 Μ ^乍為硬式罩幕層而在基底200上形 成-開200a，其冰度約6〇〇〇埃以）。隨後，請參照 4圖’在此開口 20 0a的内表面順應 ，例如藉由熱氧化法所开m ^ a # ’丨電層 子植入步驟時，作為開口2〇〇a處之罩幕層。The Shixi layer 204 and the pad oxide layer 002 are used as hard slabs. Each of them is formed on the substrate 200 as a hard cover layer-200a, and the ice degree is about 6,000 angstroms. To). Subsequently, please refer to FIG. 4 to conform to the inner surface of the opening 20 0a. For example, when the m ^ a # '丨 electric layer implantation step opened by the thermal oxidation method is used as a mask layer at the opening 200 a .

557487 五、發明說明（4) 接下來，請參gg笫5阁 · 200表面區域形成含，P第之5松圖施思貫9施一離子植入，以在基底 之4多雜層2 0 1且摻雜@j Λ19不丨】〇21 at⑽/cm3的範圍。此 夂雜/辰度在10丨9到1021 。另外，在之作用將於本文猶後說明 發明並未受限；：：：；=元素為侧（β)，然而本 (Ga)。 此亦可摻雜其他的三價元素，例如鎵 接下來，請參照第6圖，蕻由韭 第一 +猎由非4向性活性離子蝕刻 二。丄22 在開口 200a底部露出含ρ+之掺 2::ίϊί:開口2〇〇a内側壁形成由第-介電層 206所構成之介電間隔層⑽，亦即氧化 spacer )。隨後，藉由選擇 yt &amp; JU ^ η, 悍注磊日日成長法以在内側壁形成 有乳化間隔層206a之開口 200a内填滿 單晶矽層208係作為元件層。期門仫4, :: 7層·此 十从祕…丄 ^期間係利用氧化間隔層206a 來維4形成單晶矽層2 〇 8之品質。 接下纟’請參照第7 _，去除罩幕層2〇4及2〇2，以露 出έΡ+之摻雜層201表面。接著’在氧化間隔層2〇6a及單 晶矽層208上方形成一保護層21〇，例如光阻層，用以在後 續步驟中，保護單晶矽層208不受到損害。 接下來，請參照第8圖，冑完成上：步驟之基底2〇〇浸 入一反應溶液（未繪示），例如氫氟酸（HF )溶液及硝酸 溶液之混合液，以實施陽極處理。如此一來，摻雜層2〇1 繪轉變成具有多孔隙之矽層2 0 1 a。 接下來，凊參照第9圖，在去除光阻層2 1 〇之後，對多 孔隙之矽層201a實施一熱氧化處理，以在單晶矽層2〇8外 0503-7158TWF(N) ； TSMC2001-0999 ； spin.ptd 第7頁 557487 五、發明說明（5) 圍形成第二介電層2〇lb。此第二介電層2〇lb係作 離層以隔離單晶矽層2〇8 (元件層）與矽基底2〇〇。由， 孔隙之矽層201a可快速被熱氡化’因此可大幅降低埶預： 。另外，形成第二介電層201b之後，無需像習知之氧 佈值隔離矽晶法（SIM0X)，進行高溫退火。再者， =電隔離層2〇lb完全包圍住作為元件層之單晶了 另外！成橫向元件隔離結構，如先前所述。如此 了有效地間化製程步驟。 ，後，請參照第10圖，藉由化學機械研磨法 ΐϊΐ:隔離層2〇lb直至露出單晶石夕層208表面。如 此便完成介電隔離矽晶（DIS )纟 本發明之介電隔離矽晶（DIS):製作。因此’根據 緣層上矽晶（SOI )結構之低電 / 、，不但具有絕 作速度快的優點，而Η又/士 /W耗、電流損失少及操 雖然本發明已以較佳實施 、 限定本發明，任何熟習此項技蓺者$ σ ，然其並非用以 神和範圍内，當可作更動與^者阳在不脫離本發明之精 當視後附之申請專利範圍^界定者為g本發明之保護範圍 第8頁 〇503-7158TW(N) ； TSMC2001-0999 ； spin.ptd 557487 圖式簡單說明 為讓本發明之上述目的、特徵和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如 下： 第1 a到1 b圖係繪示出習知之形成絕緣層上矽晶結構之 剖面示意圖。 第2到1 0圖係繪示出根據本發明實施例之介電隔離矽 晶之製造方法剖面示意圖。 [符號說明] 100、200〜基底； 1 0 0 a〜元件層； 1 0 0 b〜埋藏氧化層； 20 0a〜開口； 2 0 1〜摻雜層； 2 0 1 a〜多孔隙之矽層； 201b〜第二介電層； 2 0 2〜墊氧化層； 2 0 4〜氮化矽層； 206〜第一介電層； 206a〜介電間隔層； 2 0 8〜單晶矽層； 2 1 0〜保護層。557487 V. Description of the invention (4) Next, please refer to gg 笫 5 阁 · 200 surface area formation, including P 5th, Song Tu, Shi Si Guan 9 and ion implantation, in order to have 4 heterogeneous layers 2 0 1 and Doping @j Λ19 不 丨】 〇21 at⑽ / cm3. The doping / chen degree ranges from 10 to 9 to 1021. In addition, the role will be explained later in this article. The invention is not limited; :::; = element is side (β), but this (Ga). This can also be doped with other trivalent elements, such as gallium. Next, please refer to Figure 6, 蕻 by chill first + hunting by non-quadritic active ion etch II.丄 22 A dopant containing ρ + is exposed at the bottom of the opening 200a 2 :: ίϊί: A dielectric spacer ⑽ formed by the first dielectric layer 206 is formed on the inner side wall of the opening 2000a, that is, an oxide spacer). Subsequently, by selecting yt &amp; JU ^ η, the daily growth method is used to fill the opening 200a with the emulsified spacer layer 206a on the inner side wall and fill the single crystal silicon layer 208 as the element layer. The gate 仫 4, :: 7 layers · These ten steps are used to form the single-crystal silicon layer 208 with the oxide spacer layer 206a. Next, please refer to No. 7_ to remove the mask layer 204 and 202 to expose the surface of the doped layer 201 of P +. Next, a protective layer 21, such as a photoresist layer, is formed over the oxidation spacer layer 206a and the single crystal silicon layer 208 to protect the single crystal silicon layer 208 from damage in subsequent steps. Next, please refer to FIG. 8 to complete the above step: the substrate 200 is immersed in a reaction solution (not shown), such as a mixed solution of a hydrofluoric acid (HF) solution and a nitric acid solution, to perform anodizing. In this way, the doped layer 201 is transformed into a porous silicon layer 210a. Next, referring to FIG. 9, after removing the photoresist layer 210, a thermal oxidation treatment is performed on the porous silicon layer 201a so as to be 0503-7158TWF (N) outside the single crystal silicon layer 208; TSMC2001 -0999; spin.ptd page 7 557487 V. Description of the invention (5) A second dielectric layer 20 lb is formed around. The second dielectric layer 20 lb serves as an isolation layer to isolate the single crystal silicon layer 208 (element layer) from the silicon substrate 2000. Because the porous silicon layer 201a can be rapidly thermally thermally cured ', it can greatly reduce the temperature: In addition, after the second dielectric layer 201b is formed, it is not necessary to perform high-temperature annealing as in the conventional silicon oxide silicon isolation method (SIM0X). Moreover, = 20 lb of the electrical isolation layer completely surrounds the single crystal as the element layer. In addition! Into a lateral element isolation structure, as previously described. This effectively interleaves process steps. After that, please refer to FIG. 10 by chemical mechanical polishing method ΐϊΐ: the isolation layer is 20 lb until the surface of the single crystal evening layer 208 is exposed. This completes the dielectric isolation silicon (DIS). The dielectric isolation silicon (DIS) of the present invention: fabrication. Therefore, according to the low power of the silicon-on-silicon (SOI) structure on the edge layer, it not only has the advantage of fast operation speed, but also has the advantage of / ± / W consumption, less current loss, and operation. Although the present invention has been implemented in a preferred manner, To limit the present invention, anyone who is familiar with this technique $ σ, but it is not used within the scope of the gods, and can be changed, and those who do not depart from the essence of the present invention should be attached to the scope of the patent application ^ defined For the scope of protection of the present invention, page 8 503-7158TW (N); TSMC2001-0999; spin.ptd 557487 The diagram is briefly explained. In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the following is enumerated The preferred embodiment and the accompanying drawings are described in detail as follows: Figures 1a to 1b are schematic cross-sectional views showing a conventional formation of a silicon crystal structure on an insulating layer. Figures 2 to 10 are schematic cross-sectional views showing a method for manufacturing a dielectric isolation silicon crystal according to an embodiment of the present invention. [Explanation of symbols] 100, 200 ~ substrate; 100a ~ element layer; 100b ~ buried oxide layer; 200a ~ opening; 2101 ~ doped layer; 2101a ~ porous silicon layer 201b ~ second dielectric layer; 202 ~ pad oxide layer; 204 ~ silicon nitride layer; 206 ~ first dielectric layer; 206a ~ dielectric spacer layer; 208 ~ single crystal silicon layer; 2 1 0 ~ protective layer.

0503-7158TWF(N) ； TSMC2001-0999 ； spin.ptd 第9頁0503-7158TWF (N); TSMC2001-0999; spin.ptd page 9

Claims (1)

557487 六 申請專利範圍 1 · 一種介電隔離矽晶之製造方法，包括 、 提供一基底，該基底上形成有一開^ ^列步驟： 在該開口内表面順應性形成一第一介電展 在邊基底之表面及與該第一介電層相鄰 摻雜層； &lt;界面形成— 非等向性刻該第一介電層，以在該開口 摻雜層表面並在該開口内側壁形成一介電間隔底。卩露出該 在内側壁形成有該介電間隔層之該開口 Z f ’ 層； π填滿一矽 在該介電間隔層及該矽層上方形成一保護層. 將該基底浸入一反應溶液以實施陽極處理丨曰’ 去除該保護層； ’ 實施一氧化處理，以在該矽層外圍形成一第-八 層’以作為介電隔離層；以及 一；丨電 研磨去除該第二介電層直至露出該石夕層表面。 2 ·如申請專利範圍第1項所述之介電隔離矽晶之穿』i 方法，其中該第一及第二介電層為氧化矽層。 3·如申請專利範圍第1項所述之介電隔離矽晶之製&amp; 方法，其中藉由離子植入法形成該摻雜層。 义 4 ·如申請專利範圍第1項所述之介電隔離矽晶之製、皮 =法，其中藉由選擇性磊晶法形成該矽層且該矽層係一&amp; cm kr7 ο ' 、如申請專利範圍第1項所述之介電隔離矽晶之製 法’其中該保護層係一光阻層557487 Six applications for patent scope1. A method for manufacturing dielectrically isolated silicon crystals, comprising, providing a substrate, an opening formed on the substrate, and forming a first dielectric array on the inner surface of the opening; The surface of the substrate and the doped layer adjacent to the first dielectric layer; &lt; Interface formation—the first dielectric layer is anisotropically etched to form a surface of the opening doped layer and an inner sidewall of the opening. Dielectric interval bottom. (1) Exposing the opening Z f 'layer having the dielectric spacer layer formed on the inner side wall; π filled with silicon to form a protective layer over the dielectric spacer layer and the silicon layer. The substrate was immersed in a reaction solution to Carrying out an anode treatment 丨 'Removing the protective layer;' Carrying out an oxidation treatment to form an eighth-eighth layer on the periphery of the silicon layer 'as a dielectric isolation layer; and one; 丨 electropolishing to remove the second dielectric layer Until the surface of the Shi Xi layer is exposed. 2. The method of “passing through dielectrically isolated silicon” described in item 1 of the scope of the patent application, wherein the first and second dielectric layers are silicon oxide layers. 3. The method of manufacturing a dielectrically isolated silicon crystal according to item 1 of the scope of patent application, wherein the doped layer is formed by an ion implantation method. Meaning 4: The method of making a dielectric isolation silicon crystal as described in item 1 of the scope of the patent application, a method of forming silicon, wherein the silicon layer is formed by a selective epitaxy method, and the silicon layer is a &amp; cm kr7 ο ', The manufacturing method of the dielectric isolation silicon crystal according to item 1 of the patent application scope ', wherein the protective layer is a photoresist layer 557487 六、申請專利範圍 6·如申請專利範圍第1項所述之介電隔離矽晶之製造 方法，其中該反應溶液係氫氟酸溶液及硝酸溶液之混合 液。 7 ·如申請專利範圍第3項所述之介電隔離矽晶之製造 方法，其中該摻雜層之摻雜元素為硼。 8 ·如申請專利範圍第7項所述之介電隔離矽晶之製造 方法’其中該摻雜層之摻雜濃度在1019到1021 atom/cm3的 範圍。 9 · 一種介電隔離矽晶之製造方法，包括下列步驟： 提供一基底，該基底上形成有一罩幕層； 口 定義蚀刻該罩幕層及該基底，以在該基底上形成一開 在該開口内表面順應性形成一第一介電層； 層；實施一離子植入，以在該基底表面形成jp+之摻雜 非等向性餘刻該第一介電層，以在該開口底部 之摻雜層表面並在該開口内側壁形成介電間 。亥 層在内側壁餘留有該介電間隔層之該開口内填滿二矽 去除該罩幕層，以露出該含P+之摻雜層表面· 在該介電間隔層及該石夕層上方形成一光阻層· 將該基底浸入一反應溶液以實施陽極處理·，&quot; ’ 去除該光阻層； ’ 實施一氧化處理，以在該矽層外圍一 /欣第二介電層，557487 6. Scope of patent application 6. The method for manufacturing dielectrically isolated silicon crystals according to item 1 of the scope of patent application, wherein the reaction solution is a mixed solution of a hydrofluoric acid solution and a nitric acid solution. 7. The method for manufacturing a dielectrically isolated silicon crystal as described in item 3 of the scope of patent application, wherein the doping element of the doped layer is boron. 8. The method for manufacturing a dielectrically isolated silicon crystal according to item 7 of the scope of the patent application, wherein the doping concentration of the doped layer is in a range of 1019 to 1021 atom / cm3. 9. A method for manufacturing a dielectrically isolated silicon crystal, comprising the following steps: providing a substrate on which a mask layer is formed; defining a mask layer and the substrate by etching to form an opening on the substrate; The inner surface of the opening conforms to form a first dielectric layer; layer; implements an ion implantation to form a doped anisotropy of jp + on the surface of the substrate, leaving the first dielectric layer to rest on the bottom of the opening. The surface of the layer is doped and a dielectric space is formed on the inner side wall of the opening. The helium layer is filled with di-silicon in the opening with the dielectric spacer layer remaining on the inner side wall to remove the mask layer to expose the surface of the doped layer containing P +. Above the dielectric spacer layer and the stone layer Forming a photoresist layer; immersing the substrate in a reaction solution to perform an anodizing treatment; &quot; 'removing the photoresist layer;' performing an oxidation treatment to form a second dielectric layer on the periphery of the silicon layer; D7487 六、申請專利範圍 以作為介電隔離層；以及 研磨該第二介電層直至露出該矽層表面。 10·如中請專利範圍第9項所述之 方法，其中該罩幕層係由 电二離矽曰曰之製造 成。 虱化矽層及一虱化矽層所構 方、#11 t如/^專利範圍第9項所述之介電隔離石夕晶之製造 法，，、中猎由熱氧化法形成該第一及第二介電層。 12·如申請專利範圍第9項所述之介電隔離矽^之製造 方法’其中該摻雜層之摻雜元素為硼。 、1 3 ·如申咕專利範圍第9項所述之介電隔離矽晶之製造 方法，其中藉由選擇性遙晶法形成該石夕層且該石夕層係一單 晶碎層。 1 4 ·如申凊專利範圍第9項所述之介電隔離矽晶之製造 方法’其中該反應溶液係氫氟酸溶液及硝酸溶液之混合 液。 1 5 ·如申請專利範圍第1 2項所述之介電隔離矽晶之製 造方法’其中該摻雜層之摻雜濃度在1 〇19到1 〇21 a tom/cm3 的範圍。D7487 6. Apply for a patent to serve as a dielectric isolation layer; and polish the second dielectric layer until the surface of the silicon layer is exposed. 10. The method according to item 9 of the Chinese Patent Application, wherein the mask layer is made of ionosilicon. The method of constructing the siliconized silicon layer and the siliconized silicon layer, # 11 t is the manufacturing method of the dielectric isolation Shi Xijing as described in item 9 of the patent scope, and the first method is to form the first by thermal oxidation. And a second dielectric layer. 12. The manufacturing method of the dielectric isolation silicon according to item 9 of the scope of the patent application, wherein the doping element of the doped layer is boron. 1 3 · The method for manufacturing a dielectrically isolated silicon crystal as described in item 9 of the Shengu patent scope, wherein the Shixi layer is formed by a selective telecrystallization method and the Shixi layer is a single-crystal chip layer. [14] The method for manufacturing a dielectrically isolated silicon crystal according to item 9 of the patent scope of Shenying ', wherein the reaction solution is a mixed solution of a hydrofluoric acid solution and a nitric acid solution. 1 5 · The method for manufacturing a dielectrically isolated silicon crystal according to item 12 of the scope of the patent application, wherein the doping concentration of the doped layer is in the range of 1019 to 1021 a tom / cm3. 0503-7158TWF(N) ； TSMC2001-0999 ； spin.ptd 第12頁0503-7158TWF (N); TSMC2001-0999; spin.ptd page 12