TW556343B

TW556343B - Electrically programmable memory element

Info

Publication number: TW556343B
Application number: TW90120438A
Authority: TW
Inventors: Tyler Lowrey; Stephen Hudgens; Patrick Klersy
Original assignee: Ovonyx Inc
Priority date: 2000-07-22
Filing date: 2001-08-21
Publication date: 2003-10-01
Also published as: AU2001275971A1

Abstract

An electrically operated programmable resistance memory element. In one embodiment of the invention the memory element includes an electrical contact having at least a first region with a first resistivity and a second region with a second resistivity higher than the first resistance. The more resistive second region is preferably adjacent to the memory material. In another embodiment of the invention the memory element includes an electrical contact having a raised portion extending to an end adjacent to the memory material.

Description

556343 A7 B7 五、發明說明556343 A7 B7 V. Description of the invention

經濟部帑慧財產局貝工消费合作U 相關申諸資訊本申清案係1999.3.25提出之美國專利申請案多〇9/276,273號之部分延續案，而美國專利申請案旁 5 09/276,273號係1997·1〇·1提出之美國專利申請案！ 08/942,000號（現已放棄）之部分延續案。發明領斑本發明一般係與獨特設計之固態、電氣操作記憶骨元件有關。尤其是本發明與可程式化電阻記憶體元卡 10 有關。t景及先前技藝可程式化電阻記憶體元件係自可經程式化顯示3 少咼或低穩定歐姆狀態之材質形成，如此技藝眾所3 知。此類可程式化電阻元件可經程式化至高電阻并態，以儲存如邏輯1資料位元。其亦可經程式化至4 電阻狀態，以儲存如邏輯〇資料位元。一種可做為可程式化電阻元件之記憶體材質係一相變材質。錢材f可難錢於第—賴狀態（未質一般較非晶系（較無次序））及第二結構狀態（材I 了，較結晶化（較有次序））間。此處所云之"非晶系, 二、曰、、Ό構上相對較無次序或較單晶無序，其並具可領、、!特14如w電氣電阻率。此處所云之"結晶化,,係指結，上相對較非晶系有次序，其並具較非晶系狀態電氣電阻率。將電乳可程式相變材質使用於電氣記體體應 15 20 25 297公釐） 2,000 (請先閲讀背面之注意事項再填寫本頁) ••裝--------訂---------線 _· 556343 A7 ________ B7 五、發明說明（2 ) 概念係揭示如美國專利申請案第3 271 591及3 53〇 441 號’兹將其併於此以為參述。先前在，591及M41號專利中所述相變材質係以局部結構次序之變化為基。此 5結構次序之變化典型係以在材質内特定物種之原子游移為之。此類在非晶系與結晶化狀態間之原子游移使得程式化能量相當高。在這些材質中產生可偵測變化所須之電氣能量的典型約在微焦耳範圍内。此能量值須經傳遞至在記憶 10胞之行列固態矩陣中的各記憶體元件。此高能量需求經轉譯為與各分離記憶體元件相關之位址線及胞絕緣/ 位址裝置的高電流載運需求。在<591及，441號專利中所述對程式化記憶胞所需之高能量使得將該等胞作為目前電腦記憶體應用，諸 15如磁帶、軟碟、磁或光學硬碟、固態磁碟快閃、動態隨機存取記憶體、靜態隨機存取記憶體以及插座式快閃記憶體之直接與廣泛取代受到限制。尤其是當在大型結構儲存中使用電氣可清除程式化唯讀記憶體 (EEPROMs)時，低程式化能量更為重要。以此方式， 20可以EEpR〇M置換目前電腦系統之機械式硬碟（諸如磁或光學硬碟）。以EEPROM〃硬碟"置換習知的機械式硬碟之主因在降低機械系統之功率耗損。在膝上型電腦的應用中對此尤有偏好，此係因機械式硬碟槽#係最大功率耗損源之一。因此減少此功率負載之優點係 25 大抵上藉此可增加供電電池每次充電後之電腦操作時本紙張尺琛適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) !· · I 1« ϋ 1 i·— ϋ 訂--------- 經濟部智慧財產局MK工消费合作社印製 91. 1. 2,000 556343 經濟部智慧財產局貝工消費合作社印製 A7 B7____ 五、發明說明（3 ) 間。但是，如以具高程式化能量需求之EEPROM (並需高功率）置換硬碟，則功率節約即非必然或頂多無實質效益。因此任何考量做為廣泛的記憶體之 5 EEPROM，均需具低程式化能量。可程式化電阻記憶體元件之程式化能量需求，可以不同方式降低之。例如：藉由適當地選擇記憶體材質組成可降低程式化能量。具低能量需求之相變材質之一示例述於美國專利第5，166,758號，茲將此揭示併於 10 此以為參述。其它記憶體材質示例如美國專利第 5,296,716、5,414,27卜 5,359,205 以及 5,534,712 號所揭’亦併於此以為參述。程式化能量需求亦可經由對電氣接點之適當修改而降低，該接點係用以將程式化能量傳遞至記憶體材 15質。例如：可藉由修改電氣接點之組合及7或外型及/或組態（與記憶體材質之相關位置），降低程式化能量。此"接點修改"之示例如美國專利第5,341，328、 5,406,509、5,534,7Π、5,536,947、5,687，112、5,933,365 號所揭，均併於此以為參述。尚有如美國專利申請案 20第09/62〇,318號所揭，亦併於此以為參述。發明概要本發明之一態樣係為一種電氣操作記憶體元件，其包括· 5己憶體材質體，其可程式化於至少第一電‘狀態及第二電阻狀態；以及一電氣接點，其與該記憶體 25材質電氣通連，傳導側壁包含至少具第一電阻率之第 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) ----- nT； (請先閲讀背面之注意事項再填寫本頁)The Ministry of Economic Affairs, the Huihui Property Bureau, Shellfish Consumption Cooperation, U.S. Related Information This application is a partial continuation of US Patent Application No. 09 / 276,273 filed on March 25, 1999, and 5 09 / 276,273 next to US Patent Application The US patent application filed in 1997 · 10.1! Partial continuation of 08 / 942,000 (now abandoned). The invention is generally related to a uniquely designed solid-state, electrically-operated memory bone element. In particular, the present invention relates to a programmable resistive memory element card 10. Scenery and previous techniques Programmable resistive memory elements are formed from materials that can be programmed to display 3 or less stable ohmic states, as known in the art. Such programmable resistive elements can be programmed to a high-resistance parallel to store data bits such as logic one. It can also be programmed to a 4-resistance state to store data bits such as logic 0. A memory material that can be used as a programmable resistance element is a phase change material. Money f can be difficult between the first and the second state (the material is generally more amorphous (less ordered)) and the second structural state (the material I is more crystalline (more ordered)). The "amorphous system" described here is relatively unordered or unordered on the single-crystal structure, and it also has the electrical resistivity of 14 and w, such as w. The "crystallization" mentioned here refers to the junction, the order is relatively amorphous, and it has the electrical resistivity of the amorphous state. The electric milk programmable phase change material should be used for electrical memory (15 20 25 297 mm) 2,000 (Please read the precautions on the back before filling out this page) •• Installation -------- Order-- ------- line _ · 556343 A7 ________ B7 V. Description of the Invention (2) The concept is disclosed as U.S. Patent Application Nos. 3 271 591 and 3 53 441 'hereby incorporated herein by reference. The phase change materials previously described in Patent Nos. 591 and M41 are based on changes in the local structural order. The change of the 5 structural order is typically based on the atomic migration of specific species within the material. This type of atomic migration between the amorphous system and the crystalline state makes the stylized energy quite high. The electrical energy required to generate a detectable change in these materials is typically in the microjoule range. This energy value must be transferred to each memory element in the solid matrix of the ranks of memory 10 cells. This high energy requirement is translated into the high current carrying requirements of the address lines and cell insulation / address devices associated with each discrete memory element. The high energy required for the stylized memory cells described in the < 591 and 441 patents makes these cells the current computer memory applications, such as magnetic tapes, floppy disks, magnetic or optical hard disks, solid state magnetics Direct and widespread replacement of disk flash, dynamic random access memory, static random access memory, and socket flash memory is limited. Especially when using electrically erasable programmable read-only memory (EEPROMs) in large structured storage, low programming energy is even more important. In this way, 20 can replace the mechanical hard disks (such as magnetic or optical hard disks) of current computer systems with EEPROM. The main reason for replacing the conventional mechanical hard disk with EEPROM & hard disk is to reduce the power consumption of the mechanical system. This is especially preferred in laptop applications, because the mechanical hard disk slot # is one of the sources of maximum power loss. Therefore, the advantage of reducing this power load is more than 25. This can increase the power supply battery. When the computer is operated after each charge, this paper rule applies the Chinese National Standard (CNS) A4 specification (21〇X 297 mm). (Please read first Note on the back, please fill in this page again!) ·· · I 1 «ϋ 1 i · — ϋ Order --------- Printed by MK Industrial Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 91. 1. 2,000 556343 Ministry of Economic Affairs A7 B7____ printed by Shelley Consumer Cooperative of Intellectual Property Bureau. 5. Description of invention (3). However, if hard drives are replaced with EEPROMs (which require high power) with high programming energy requirements, then power savings are not necessarily inevitable or at most not material. Therefore, any 5 EEPROM that is considered as a wide memory needs to have low programming energy. The programmable energy requirements of programmable resistive memory components can be reduced in different ways. For example, by appropriately selecting the composition of the memory material, the programming energy can be reduced. An example of a phase change material with a low energy requirement is described in U.S. Patent No. 5,166,758, which is hereby disclosed and incorporated herein by reference. Examples of other memory materials are disclosed in U.S. Patent Nos. 5,296,716, 5,414,27, 5,359,205, and 5,534,712, and are incorporated herein by reference. The stylized energy requirements can also be reduced by appropriate modification of the electrical contacts, which are used to transfer the stylized energy to the memory material. For example, you can reduce the programming energy by modifying the combination of electrical contacts and the 7 or shape and / or configuration (relevant locations of the memory material). Examples of this "contact modification" are disclosed in U.S. Patent Nos. 5,341,328, 5,406,509, 5,534,7, 5,536,947, 5,687,112, 5,933,365, and are hereby incorporated by reference. It is also disclosed in U.S. Patent Application No. 09 / 62〇, 318 and is hereby incorporated by reference. SUMMARY OF THE INVENTION One aspect of the present invention is an electrical operation memory element, which includes a memory body that is programmable in at least a first electrical state and a second resistance state; and an electrical contact, It is electrically connected to the 25 material of the memory, and the conductive side wall includes at least the fifth paper with the first resistivity. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) ----- nT; ( (Please read the notes on the back before filling out this page)

556343 A7 五、發明說明（4 ) 一區以及具第二電阻率之第二區，其中第二電阻率高於第一電阻率。 (請先閱讀背面之注意事項再填寫本頁} 本發明之另一態樣係為一種電氣操作記憶體元件 5 之裝^方法，其包括步驟如次·提供一傳導材質；辦加部分該傳導材質之電阻率；以及沉積與該部分相鄰之纪憶體材質。本發明之另一態樣係為一種電氣操作記憶體元件，其包括：一可程式化電阻記憶體材質；以及一傳導 10層，其與該記憶體材質電氣通連，該傳導層真一加高部分，自該層邊緣延伸至與記憶體材質相鄰之一末端。本發明之另一態樣係為一種可程式化電阻記憶體元件之製造方法，其包括：提供一傳導材質；在部分該傳導材質上形成側壁間隔物；將部分該傳導材質 15移除，在該間隔物下形成自該傳導材質延伸之加高部分，以及形成至少與部分該加高部分相鄰之可程式化電阻材質。 %, 經濟部智慧財產局貝工消費合作社印製 --1^ 本發明之另一態樣係為一種可程式化電阻記憶體元件之製造方法，其包括：提供一傳導層；形成自 20該傳導層邊緣延伸之加高部分；以及形成至少與部分該加高部分相鄰之可程式化電阻材質。本發明之另一態樣係為一種可程式化電阻記憶體件之製造方法，其包括：提供第一介電層；‘該介電層中形成側壁表面；在該側壁表面上形成傳； 25層，在該傳導層上形成第二介電層；形成或露出該傳 6 ^紙張尺夜通用中國國家標準（c卿Μ規格⑵G X 297公釐、' --- 91· 1. 2,〇〇〇 556343 Α7 ______________ Β7 經濟部智慧財產局貝工消費合作社印製五、發明說明（8 ) 本發明之詳細說明本發明與可程式化電阻記憶體元件有關。此記憶體元件包含記憶體材質體，其可響應於電氣信號而可程 5式化於至少第一電阻狀態及第二電阻狀態間。記憶體元件更包含將電氣信號傳遞至記憶體材質體之裝置。傳遞電氣信號之裝置包含與記憶體材質體通連之第一及第二電氣接點較佳。在本發明之第一具體例中，至少電氣接點之一係一傳導側壁間隔物。傳導側壁間隔物與記憶體材質體電氣通連。以下即將做更詳盡的敘述，大抵上所有的該電氣通連經過至少部分傳導側壁間隔物邊緣較佳。亦即，大抵上所有的電氣通連經過傳導側壁間隔物之邊緣或其部分邊緣。注意此處所述之〃至少部分邊緣〃與邊緣或其部分邊緣"之涵義相同，可互為使用。圖1A係第一具體例示例。所示係本發明之記憶艘元件100剖面圖，其形成於半導體基板1〇2上。此剖面圖與x-z平面平行。以x_維度做為記憶體元件1〇() 之”通道長度〃或簡示為〃長度"。記憶體元件之y-z面 (未示於圖1A)與所示平面垂直。以y_維度做為記憶體元件之"通道寬度"或簡示為"寬度,，。在所示示例中，記憶體元件1〇〇包含兩獨立單胞記憶體元件。第-記紐元件包含第—接點mA、」層記憶體材質290以及第二接點3〇〇。第二記憶體元件包含第一接點130B、一層記憶體材質29〇以及第二接點 10 15 20 25 規格⑽ X 297公釐） 2,000 (請先聞讀背面之注意事項再填寫本頁) 556343556343 A7 V. Description of the invention (4) A region and a second region with a second resistivity, wherein the second resistivity is higher than the first resistivity. (Please read the precautions on the back before filling out this page} Another aspect of the present invention is a method for assembling an electrically operated memory element 5, which includes steps such as: providing a conductive material; adding a portion of the conductive material The resistivity of the material; and the deposition of the memory material adjacent to the part. Another aspect of the present invention is an electrically operated memory element, which includes: a programmable resistive memory material; and a conductive 10 Layer, which is in electrical communication with the memory material, and the conductive layer is really a heightened portion extending from the edge of the layer to an end adjacent to the memory material. Another aspect of the present invention is a programmable resistor A method for manufacturing a memory element includes: providing a conductive material; forming a sidewall spacer on a portion of the conductive material; removing a portion of the conductive material 15 and forming a heightened portion extending from the conductive material under the spacer; And to form a programmable resistance material adjacent to at least part of the heightened part.%, Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economy-1 ^ Another aspect of the present invention A method for manufacturing a programmable resistive memory device, comprising: providing a conductive layer; forming a raised portion extending from the edge of the conductive layer; and forming a programmable resistor adjacent to at least a portion of the raised portion Material Another aspect of the present invention is a method for manufacturing a programmable resistive memory device, which includes: providing a first dielectric layer; 'a wall surface is formed in the dielectric layer; and a passivation is formed on the surface of the side wall. 25 layers, forming a second dielectric layer on the conductive layer; forming or exposing the pass 6 ^ paper rule night general Chinese national standard (c Qing M specifications ⑵G X 297 mm, '--- 91 · 1.2 〇〇〇556343 Α7 ______________ Β7 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) Detailed description of the present invention The present invention relates to a programmable resistive memory element. This memory element contains a memory The material body can be converted into at least a first resistance state and a second resistance state in response to an electrical signal. The memory element further includes transmitting the electrical signal to the memory. It is preferred that the device for transmitting electrical signals includes first and second electrical contacts in communication with the material body of the memory. In a first specific example of the present invention, at least one of the electrical contacts is a conductive sidewall Spacer. The conductive sidewall spacer is in electrical communication with the memory material body. The following will be described in more detail. It is better that all of the electrical connections pass through at least part of the conductive sidewall spacer edge. That is, it is almost all The electrical connection passes through the edge or part of the edge of the conductive sidewall spacer. Note that "at least part of the edge" described here has the same meaning as "edge or part of the edge" and can be used for each other. Figure 1A is the first specific example Example. Shown is a cross-sectional view of a memory boat element 100 of the present invention, which is formed on a semiconductor substrate 102. This sectional view is parallel to the x-z plane. The x_dimension is used as the "channel length" of the memory element 10 () or simply "length". The yz plane (not shown in Figure 1A) of the memory element is perpendicular to the plane shown. In the y_dimension As the " channel width " of a memory element, or simply as " width, " In the example shown, the memory element 100 includes two independent single-cell memory elements. The first-key element includes the first -Contact mA, memory layer 290, and second contact 300. The second memory element includes the first contact 130B, a layer of memory material 29〇, and the second contact 10 15 20 25 Specification ⑽ X 297 mm) 2,000 (Please read the precautions on the back before filling this page) 556343

300 〇五、發明說明（9 ) 在所不示例中，記憶體材質體大抵上係記憶體材質 290之水平配置層。如所示，記憶體材質29〇層及第二 5接點300為第-及第二記憶體元件所共享。然而在其匕具體例中，各記憶體元件可能近具單一對應記憶體材質體（或層）及單一對應第二接點。介電區14〇使電氣接點130A與電氣接點13〇B隔絕。上方介電區18〇係配置於記憶體元件100之上。上方介電區18〇可包 10 含硼磷矽玻璃（BPSG)。各電氣接點130A與電氣接點13〇3均係以傳導側壁間隔物型式存在。此處所述之,,傳導側壁間隔物 13〇A、B (單數的）餘傳導間隔物13GA或傳導間隔物130B° "傳導側壁間隔物130A、B,,(複數的）則 15係指元件1〇0之傳導間隔物130A及13〇β。在所示示例中，各傳導側壁間隔物130Α、Β為,，單層"。亦即各傳導側壁間隔物13〇Α、Β為大抵上垂直配置之單-側壁層。各側壁層可由大抵上共形配置於側壁表面128S表面之傳導層形成。（在1Α +，側壁表 20面128s及絲φ 106構成垂直於圖1Α所示平面而延伸之溝槽）。一"單層"傳導間隔物係用以與,,多層,,傳導側壁區隔，其一或多層附加側壁大抵上係共形配置於既存之側壁層表面。 j 在圖1Α所示示例中，記憶體㈣2%層係配置於 25傳導間隔物U0A、B之上，俾使僅有傳導間隔物i3〇A、本紙張尺褎適用中國國家標準（CNS)A4規格（210 X 297公楚1-一~ ---- 91. 1· (請先閲讀背面之注意事項再填寫本頁) 裝訂---------· 經濟部智慧財產局員工消费合作社印製 556343 A7 經濟部智慧財產局貝工消費合作社印製五、發明說明（1〇) B上緣132與記憶體材質290相鄰。其餘傳導間隔物則與記憶體材質有一距離。因此，大抵上所有在傳導間隔物130A、B與記憶體材質290間的電氣通連係經由傳導間隔物之上緣132為之。此處所用術語,,上,,與" 下"以及〃頂〃與〃底"係以其與基板之相對距離界定之*。此術語與基板之幅向無關。在圖1A之具體例中，傳導間隔物13〇A、B上緣係傳導間隔物邊緣（亦即〃上邊緣層邊緣之一示例係大抵上與層的厚度尺寸平行之表面（其中的厚度係為層之最小尺寸較佳）。在圖1A之具體例中，傳導間隔物130A、B大抵上係一垂直配置側壁層。因此，在圖1A中所示傳導間隔物ΠΟΑ、B厚度"t"係大抵上與維度或通道長度平行之側壁層尺寸。在圖1A所示示例申，上緣132大抵上係與基板1〇2平行之表面。可實現之厚度"t〃小於習知顯影技術所能為之尺寸。圖1B係高度理想之傳導間隔物i3〇A、b三維圖，其顯不厚度〃t”、寬度〃w〃及高度"h„。如上述，傳導側壁間隔物130A、B之厚度〃t〃係沿心維度或通道長度之間隔物尺寸（與所示平面平行）。寬度〃w〃係沿严維度或通道寬度之傳導間隔物尺寸（與圖 1A所示平面垂直）。高度〃h〃則係基板1〇2上之距離。各傳導間隔物13〇A、B上緣132與記憶體材質匕90 相鄰’其餘傳導間隔物則與記憶體材質有一距離。因此，大抵上所有在傳導間隔物13〇A、b與記憶體材質閲 15 20 25 中國國家^ x 297公釐） 91. 1. 2,000 12 556343 A7 B7 經濟部智慧財產局員工消f合作社印製五、發明説明（11 ) 290間的電氣通連係經由至少部分上緣132 ^亦即大抵上所有的電氣通連係經所有的或部分的上緣132。注意上緣132無需實際與記憶體材質接觸。 5 在圖1A之具體例中，記憶體材質290係與兩傳導間隔物130A、B的整個上緣132相鄰。然而在另一組態中’其可疋位記憶體材質290層，俾使其僅與傳導間1¾物之一的上緣132相鄰。在另一組態中，其可定位記憶體材質290層，俾使僅有傳導間隔物之一或兩者的部分上緣132與記憶體材質相鄰。在圖1A之具體例中，傳導間隔物13〇A、B係為側壁層，其大抵上垂直配置，並因而大抵上垂直於記憶體材質290層以及基板。亦即當然傳導間隔物13〇A、 B亦可為"傾斜狀"，俾使其大致上與記憶體材質垂直。如圖ic所示，傳導間隔物130A、Bv可形成於,，斜角"側壁表面128s (例如可將傳導間隔物13〇A、B形成於V形溝槽中）。此種結構類型亦在本發明之精神與範疇中。圖1C所示表面132(大抵上與基板平行），亦可視為圖1C之傳導側壁間隔物130A、B〃邊緣"。如所示，層130A、B構成與記憶體材質29〇層之入射角"THETA"。THETA大於30度並小於150度較佳。THETA大於45度並小於135度更佳。THETA大於60度並小於120度最佳。 I 再注意到尚有另一可行組態，其中記憶體材質係與傳導間隔物之底邊或部分底邊相鄰。在另一組態中， 10 15 20 25 G張尺夜適用中國國家標準（CNS〉A4規格⑵G χ 297 91. 1. 2,0〇〇 <請先閲讀背面之注意事項再填寫本頁) i · I I I I I I I 訂·1 — — — I — ΙΛ 13 556343 A7 經濟部智慧財產局8工消費合作社印製五、發明說明（12) 記憶體材質可僅與一或兩傳導間隔物之側邊或部分側邊相鄰。再參閱圖1B ,各傳導間隔物130A、B〃側邊〃係以厚度〃t〃及高度’’h”界定之表面。 5 因此，傳導間隔物係〃沿邊相鄰〃於記憶體材質較佳。亦即僅有傳導間隔物130A、B邊緣或部分邊緣與記憶體材質相鄰。大抵上所有的其餘傳導間隔物均與記憶體材質有一距離。大抵上所有的傳導側壁間隔物間之電氣通連均經傳導間隔物邊緣或部分邊緣較佳。亦即大抵上所有的電氣通連均經至少傳導側壁間隔物之部分邊緣（亦即〃邊緣部分"）較佳。此處所用術語"接點面積〃係電氣接點之部分表面，經由該表面，電氣接點可與記憶體材質電氣通連。如所述，大抵上所有在傳導側壁間隔物13〇A、B與記憶體材質290間之電氣通連均經所有或都分傳導間隔物邊緣較佳（例如經過所有或部分上緣132)。因此傳導間隔物130A、B與記憶趙材質29〇間之接點面積係為傳導側壁間隔物邊緣或部分傳導側壁間隔物邊緣。亦即傳導間隔物與記憶體材質間接點面積係為傳導側壁間隔物之〃邊緣部分〃。再注_傳料隔物無需實際與記憶體材質相接。傳導間隔物與記憶體材質有電氣通連即已足夠。因此接點面積（僅有傳導間隔物之邊緣部分（亦即邊緣或部分邊緣））非常小並 ‘ 隔物厚度成正比。 ' 現參閱圖1D，可見在本發明之-具_中，各傳 10 15 20 25 14 M式張?關家標準（CNS)A4規格 (請先閲讀背面之注意事項再填寫本頁)300 〇 5. Description of the invention (9) In all the examples, the memory material body is more than the horizontally arranged layer of the memory material 290. As shown, the 29th layer of memory material and the second 5 contact 300 are shared by the first and second memory elements. However, in its specific example, each memory element may have a single corresponding memory texture body (or layer) and a single corresponding second contact. The dielectric region 140 isolates the electrical contact 130A from the electrical contact 130B. The upper dielectric region 18 is disposed on the memory device 100. The upper dielectric region 180 may contain 10 borophospho-phosphosilicate glass (BPSG). Each of the electrical contact 130A and the electrical contact 1303 exists as a conductive side wall spacer type. As mentioned here, the conductive sidewall spacers 13A, B (singular), the remaining conductive spacers 13GA, or the conductive spacers 130B ° " the conductive sidewall spacers 130A, B, ((plural)) 15 means Element 100 has conductive spacers 130A and 130β. In the illustrated example, each of the conductive sidewall spacers 130A, B is, a single layer ". That is, each of the conductive sidewall spacers 13OA and B is a single-sidewall layer which is substantially vertically arranged. Each side wall layer may be formed of a conductive layer that is substantially conformally arranged on the surface of the side wall surface 128S. (In 1A +, the side surface of the side wall 128s and the wire φ 106 constitute a groove extending perpendicular to the plane shown in FIG. 1A). A " single layer " conductive spacer is used to separate the conductive sidewall from one or more layers. One or more of the additional sidewalls are conformally arranged on the surface of the existing sidewall layer. j In the example shown in Figure 1A, the memory 2% layer is arranged on the 25 conductive spacers U0A, B, so that only the conductive spacer i3〇A, the size of this paper applies Chinese National Standard (CNS) A4 Specifications (210 X 297 Gong Chu 1-1 ~ ---- 91. 1 · (Please read the precautions on the back before filling out this page) Binding --------- · Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative 556343 A7 Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (10) The upper edge 132 of B is adjacent to the memory material 290. The remaining conductive spacers are at a distance from the memory material. Therefore, Most of the electrical communication between the conductive spacers 130A, B and the memory material 290 is through the upper edge 132 of the conductive spacers. The terms used herein, above, below, and " under " and 〃ding〃 It is defined by its relative distance from the substrate. This term has nothing to do with the width of the substrate. In the specific example of FIG. 1A, the upper edge of the conductive spacers 13A and B is the edge of the conductive spacer ( That is, an example of the edge of the upper edge layer is a surface that is substantially parallel to the thickness dimension of the layer ( The thickness is preferably the minimum size of the layer.) In the specific example of FIG. 1A, the conductive spacers 130A, B are mostly a vertically-arranged sidewall layer. Therefore, the conductive spacers ΠOA, B shown in FIG. 1A The thickness " t " is the size of the side wall layer that is parallel to the dimension or channel length. In the example shown in Fig. 1A, the upper edge 132 is more than the surface parallel to the substrate 102. The achievable thickness " t〃 It is smaller than the size that the conventional developing technology can. Figure 1B is a three-dimensional view of the highly ideal conductive spacers i30A, b, which show the thickness 〃t ", width 〃w〃, and height " h„. As mentioned above, The thickness 〃t〃 of the conductive sidewall spacers 130A and B is the size of the spacer along the core dimension or the length of the channel (parallel to the plane shown). The width 〃w〃 is the size of the conductive spacer along the strict dimension or the width of the channel (as shown in the figure) The plane shown by 1A is perpendicular). The height 〃h〃 is the distance on the substrate 102. The upper edges 132 of each conductive spacer 130A and B are adjacent to the memory material 90. The remaining conductive spacers are connected to the memory. The material has a distance. Therefore, it is probably more Spacer 13〇A, b and memory material (read 15 20 25 Chinese country ^ x 297 mm) 91. 1. 2,000 12 556343 A7 B7 Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs F Cooperatives 5. Description of invention (11) The 290 electrical connections are connected through at least part of the upper edge 132 ^, that is, all electrical connections are connected through all or part of the upper edge 132. Note that the upper edge 132 does not need to actually contact the memory material. 5 The details in FIG. 1A In the example, the memory material 290 is adjacent to the entire upper edge 132 of the two conductive spacers 130A and B. However, in another configuration, it may have 290 layers of memory material, so that it is only adjacent to the upper edge 132 of one of the conductive objects. In another configuration, it can locate 290 layers of memory material so that only a portion of the upper edge 132 of one or both of the conductive spacers is adjacent to the memory material. In the specific example of FIG. 1A, the conductive spacers 130A and B are side wall layers, which are mostly vertically arranged, and thus are substantially perpendicular to the 290 layer of memory material and the substrate. That is, of course, the conductive spacers 13A and B may also be " tilted " so that they are substantially perpendicular to the memory material. As shown in FIG. Ic, the conductive spacers 130A and Bv may be formed on the beveled side wall surface 128s (for example, the conductive spacers 130A and B may be formed in a V-shaped groove). This type of structure is also within the spirit and scope of the present invention. The surface 132 shown in FIG. 1C (which is substantially parallel to the substrate) can also be regarded as the edges of the conductive sidewall spacers 130A, B〃 in FIG. 1C. As shown, the layers 130A, B constitute an incidence angle " THETA " with the memory material 29 layer. Theta is preferably greater than 30 degrees and less than 150 degrees. Theta is more than 45 degrees and less than 135 degrees. Theta is preferably above 60 degrees and below 120 degrees. I noticed that there is another feasible configuration, in which the memory material is adjacent to the bottom edge or part of the bottom edge of the conductive spacer. In another configuration, the 10 15 20 25 G ruler is applicable to the Chinese national standard (CNS> A4 specification⑵G χ 297 91. 1. 2,0〇〇 < Please read the precautions on the back before filling this page) i · IIIIIII Order · 1 — — — I — ΙΛ 13 556343 A7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, 8th Industrial Cooperative Cooperative, V. Description of the invention (12) The material of the memory can only be connected with one or two sides of the conductive spacer The sides are adjacent. Referring again to FIG. 1B, the sides of each of the conductive spacers 130A, B〃 are surfaces defined by the thickness 〃t〃 and the height hh. 5 Therefore, the conductive spacers 〃 are adjacent to each other along the edge and are better for the memory material That is, only the conductive spacer 130A, B edge or part of the edge is adjacent to the memory material. Most of the remaining conductive spacers are at a distance from the memory material. It is probably the electrical communication between all conductive sidewall spacers. It is better to pass the edge or part of the edge of the conductive spacer. That is to say, it is better that all electrical connections pass at least part of the edge of the conductive side wall spacer (that is, the edge part of the 〃). The term used here is " The contact area is a part of the surface of the electrical contact, through which the electrical contact can be electrically connected to the memory material. As mentioned, it is almost as good as all the spacers 13A, B and 290 on the conductive sidewall. It is better for all electrical connections to pass through the edges of the conductive spacer (for example, all or part of the upper edge 132). Therefore, the contact area between the conductive spacers 130A and B and the memory Zhao material 29 is transmitted. The edge of the sidewall spacer or part of the edge of the conductive sidewall spacer. That is, the indirect point area of the conductive spacer and the memory material is the 材质 edge portion of the conductive sidewall spacer. It is sufficient that the conductive spacer is electrically connected to the memory material. Therefore, the contact area (only the edge portion of the conductive spacer (that is, the edge or part of the edge)) is very small and 'the thickness of the spacer is proportional.' Referring to FIG. 1D, it can be seen that in the invention of the invention, each pass 10 15 20 25 14 M type Zhang Family Standard (CNS) A4 specifications (please read the precautions on the back before filling this page)

91. 1. 2,000 556343 A791. 1. 2,000 556 343 A7

五、發明說明（13) 經濟部智慧財產局貝工消費合作社印製導側壁間隔物130A、B可為"多區"。亦即各單一側壁層A、B包含至少具第一電阻率之第一區則以及具第二電阻率之第二區R2。第二區R2之電阻率大於第一 5 區R1之電阻率。概言之，第-及第二區可位於傳導側壁間隔物内任何位置。存在有許多在傳導側壁間隔物内定位的相異方式（，即可能有諸多相異組態）。在一可能的組態中，較局電阻性之第二區R2與記憶體材質相鄰，而電阻性較低之第一區R2與記憶體材質有一距離較佳。在第二種可行之組態中，較高電阻性之第二區R2 與在記憶體材質和傳導間隔物間之接點區相鄰，而電阻性較低之第一區R2與接點區有一距離。在第三種可行之組態中，較高電阻性之第二區可與傳導間隔物邊緣相鄰，而電阻性較低之第一區可與此邊緣有一距離。如上述，記憶體材質和傳導間隔物間之接點區可為傳導間隔物之邊緣部分。因此較高電阻性之第二區幻可與接點區所界定之邊緣部分相_，而電阻性較低之第一區R1可與此接點區所界定之邊緣部分有一距離。記憶體it件之特定具體例在上述組態外亦適用。亦可為其它組態。再者，雖然所述定位第一及第二區則、 R2之可行方式均與傳導側壁間隔物有關，所述亦適用於本發明之所有具體例。例如所述亦適用於下述i傳導襯裡及接點層。較高電阻性之第二區R2係為部分傳導側壁層。此 10 20 25 G張尺料+自驛標準（cns)A4 X 297公釐） 91· 1. 2,000 (請先閱讀背面之注意事項再填寫本頁) » 裝 ----訂— %« A7 五、發明說明（部分傳導側壁層（亦即此〃層部分〃）包含至少側壁層之部分邊緣較佳（亦即較高電阻性之側壁層部分R2包含側壁層之"邊緣部分〃較佳）。在圖1A所示示例中， 5較高電阻性之第二區R2係為傳導間隔物之〃上部,,，其包含上緣132 (並與基板1〇2有一距離）。亦即其自上緣132向下延伸（亦即朝向基板1〇2)至傳導間隔物内部長度"h2"(較高電阻性之第二區R2"高度"）。長度"h2〃並非定值。其可非常小，例如在約1〇至約2〇 1〇埃之間。在此狀況下，較高電阻性之上部基本上係由所有或部分上緣界定之表面。或者長度〃〃可在延伸至上緣132之下，進入傳導間隔物内部。例如長度〃h2" 可為約500埃至約600埃。區域R2之高度"h2"低於約 1〇〇〇埃較佳，低於約800埃更佳，低於约600埃最佳。 15 電阻性較低之第一區R1與上緣132有一距離。在所示示例中，其自第二區尺2底部延伸至基板1〇2。第一區R1之高度’’hi"係如圖ία中所示。區域R1高度低於約1〇,〇〇〇埃較佳，低於約7 〇〇〇埃更佳，低於約 5,〇〇〇埃最佳。經濟部智慧財產局貝工消费合作社印製 (請先閲讀背面之注意事項再填寫本頁) 20 注意在圖1A中所示組態，區域R1、區域R2及記隐體材質係為電氣串聯。更進一步注意到在圖1A所示具體例中，傳導側壁間隔物130A、B僅包含兩區域R1 及R2。然而在其它具體例中，一或兩傳導間隔物 130A、B可包含兩區以上材質。 25 較高電阻性之第二區R2所使用之材質示例包含η 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91. 1. 2,000 556343 A7 經濟部智慧財產局貝工消费合作社印製五、發明說明（I5) 型摻雜多晶矽、p型摻雜多晶矽、η型摻雜矽碳化合物及/或合金、ρ型摻雜矽碳化合物及/或合金、鈦碳氮化物、鈦鋁氮化物、鈦矽氮化物、碳及鈦氮化物型式。 5 電阻性較低之第一區R1所使用之材質示例包含η 型摻雜多晶矽、Ρ型摻雜多晶矽、η型摻雜矽碳化物、 Ρ型摻雜梦碳化物、鈦鎢化物、鎢碎化物、鎮、翻及鈦氮化物。在圖1Α所示記憶體元件100中，各傳導側壁間隔物130Α、Β均傳遞電流至記憶體材質。隨著電流流經傳導側壁間隔物及記憶體材質，至少部分電子之電位能經轉換為週遭材質的熱能。亦即電能藉由焦耳熱轉換為熱能。電能轉換為熱能（亦即焦耳熱）之大小伴隨材質電阻率及流經材質之電流密度的增加而增。如上述，可將本發明之傳導側壁間隔物形成與記憶體材質鄰近者為較高電阻性材質，而與記憶體材質有一距離者為電阻性較低之材質。因此在與記憶體材質相鄰之各傳導間隔物區域R2中因焦耳熱消耗之功率相對較高。在與記憶體材質有一距離之各傳導間隔物區域R1中因焦耳熱消耗之功率則相對較低。多區侧壁間隔物可稱之為"火柴棒"接點。其具相對"較冷"之底部 R1以及相對"較熱"之上部R2。雖不欲以理論限制之，咸信在鄰近記憶體材質處因焦耳熱造成在電氣接“之功率耗損至少可部分促進（甚或主導）記憶體材質之程式化。亦相信在與記憶體材質有一距離之電氣接點 10 15 20 25 91· 1· 2,〇〇〇 (請先閲讀背面之注意事項再填寫本頁)V. Description of the invention (13) The 130A and B spacers printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs may be " multi-zone ". That is, each of the single sidewall layers A, B includes at least a first region having a first resistivity and a second region R2 having a second resistivity. The resistivity of the second region R2 is greater than the resistivity of the first 5 region R1. In summary, the first and second regions can be located anywhere within the conductive sidewall spacer. There are many different ways of positioning within the conductive sidewall spacer (i.e., there may be many different configurations). In a possible configuration, the second region R2, which is more resistive, is adjacent to the material of the memory, and the first region R2, which is less resistive, has a better distance from the memory material. In the second feasible configuration, the second region R2 with higher resistance is adjacent to the contact region between the memory material and the conductive spacer, and the first region R2 with lower resistance is connected to the contact region There is a distance. In a third possible configuration, the second region of higher resistance may be adjacent to the edge of the conductive spacer, and the first region of lower resistance may be at a distance from this edge. As described above, the contact area between the memory material and the conductive spacer may be an edge portion of the conductive spacer. Therefore, the second region of higher resistance may be at the edge portion defined by the contact region, and the first region R1 of lower resistance may be at a distance from the edge portion defined by the contact region. The specific specific example of the memory it is applicable outside the above configuration. Other configurations are possible. Furthermore, although the feasible ways of positioning the first and second regions and R2 are related to the conductive sidewall spacers, the same applies to all the specific examples of the present invention. For example, the same applies to the following i-conductive liner and contact layer. The higher resistance second region R2 is a partially conductive sidewall layer. This 10 20 25 G ruler + self-standard (cns) A4 X 297 mm) 91 · 1. 2,000 (Please read the precautions on the back before filling out this page) »Binding-Order-%« A7 V. Description of the invention (Partially conductive sidewall layer (ie, this “layer layer”) preferably includes at least part of the edge of the sidewall layer (ie, the more resistive sidewall layer portion R2 includes the “edge portion” of the sidewall layer). In the example shown in FIG. 1A, the second region R2 with higher resistance 5 is the upper part of the conductive spacer, which includes the upper edge 132 (and a distance from the substrate 102). That is, its Extending downward from the upper edge 132 (that is, toward the substrate 102) to the internal length of the conductive spacer " h2 " (the higher resistance second region R2 " height "). The length " h2〃 is not a fixed value It may be very small, for example between about 10 and about 20,000 Angstroms. In this case, the higher resistive upper portion is essentially a surface defined by all or part of the upper edge. Or the length may not be Extends below the upper edge 132 and enters the inside of the conductive spacer. For example, the length 〃h2 " may be about 500 angstroms to about 600 angstroms The height " h2 " of the region R2 is preferably less than about 1000 angstroms, more preferably less than about 800 angstroms, and most preferably less than about 600 angstroms. 15 The first region R1, which has a lower resistance, has an upper edge 132 Distance. In the example shown, it extends from the bottom of the second ruler 2 to the substrate 102. The height `` hi " of the first zone R1 is shown in Fig. Α. The height of the zone R1 is less than about 10, Angstroms is better, less than approximately 7,000 angstroms is better, less than about 5,000 angstroms is the best. Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back first) (Fill in this page) 20 Note that in the configuration shown in Figure 1A, the areas R1, R2, and the material of the recess are electrically connected in series. It is further noted that in the specific example shown in Figure 1A, the conductive sidewall spacers 130A, B Only two regions R1 and R2 are included. However, in other specific examples, one or two conductive spacers 130A, B may include more than two regions. 25 Examples of materials used for the second region R2 with higher resistance include η 16 Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 91. 1. 2,000 556343 A7 Printed by the Shell Property Consumer Cooperative of the Intellectual Property Bureau. 5. Description of the invention (I5) doped polycrystalline silicon, p-type doped polycrystalline silicon, n-type doped silicon carbon compound and / or alloy, and p-type doped silicon carbon compound and / or alloy. , Titanium carbonitride, Titanium aluminum nitride, Titanium silicon nitride, Carbon and Titanium nitride types. 5 Examples of materials used in the first region R1 with lower resistance include η-type doped polycrystalline silicon and P-type doped polycrystalline silicon , N-type doped silicon carbide, p-type doped dream carbide, titanium tungsten carbide, tungsten fragment, ball, titanium and titanium nitride. In the memory device 100 shown in FIG. 1A, each of the conductive sidewall spacers 130A and B transmits a current to the memory material. As current flows through the conductive sidewall spacers and the material of the memory, the potential of at least some of the electrons can be converted into the thermal energy of the surrounding material. That is, electrical energy is converted into thermal energy by Joule heat. The amount of electrical energy converted into thermal energy (that is, Joule heat) increases with the increase in the resistivity of the material and the current density through the material. As described above, the conductive sidewall spacer of the present invention may be formed of a material having a higher resistance to a material adjacent to the memory material, and a material having a lower resistance to a distance from the material of the memory. Therefore, the power consumed by Joule heat in each of the conductive spacer regions R2 adjacent to the memory material is relatively high. The power dissipated due to Joule heat in each of the conductive spacer regions R1 at a distance from the memory material is relatively low. Multi-zone sidewall spacers can be called " matchstick " contacts. It has a relatively " cold " bottom R1 and a " hotter " upper R2. Although it is not intended to be limited by theory, Xianxin ’s power loss in the electrical connection due to Joule heat near the memory material can at least partially promote (or even dominate) the programming of the memory material. It is also believed that Distance electrical contacts 10 15 20 25 91 · 1,2 · 〇〇〇 (Please read the precautions on the back before filling this page)

I · · I ϋ ϋ ϋ a·— a·— · 1 1§ i·— I I- ϋ ϋ I %! 17 556343 A7 ____________________ B7 五、發明說明（16) 5 10 15 經濟部智慧財產局貝工消費合作钍印製 20 25 中的功率耗損及總體能量增加需將記憶體材質程式化。因此提供一種電氣接點結構，其在與記憶體材質相鄰處之功率消耗相對較高，而在與記憶體材質有一距離處之功率耗損則相對較低，因而可減少將記憶體材質程式化所需之總功率及總能量。再者，如上述，傳導側壁間隔物可沿邊與記憶體材質相鄰，而在記憶體材質與傳導側壁間隔物間之接點區可為傳導間隔物之一邊緣或部分邊緣。此係相當小的接點區。雖不欲以理論限制之，咸信降低接點區尺寸可降低經程式化之記憶體材f體積，藉此降低記憶體元件程式化所需總電流。因此特別設計以"多區〃料㈣_物做為電氣接點’且傳導_物相對於記憶體㈣之獨特位置可使記憶體材質之加缺有效率，並且供應至記憶體元件之總能使用上更有效率。因此僅雜少總能即可使記憶體材質之狀態改變（亦即元件程式化所需能量較低）。因此多區傳導間隔物提供一種增加流至記憶體材質熱能之方式。為將熱能保留在記㈣材質内，視需要可放置-魏緣材f (未圖示），使其至少部分環繞於記憶體材質。例如：參閱圖1D，可將—層絕緣材質配置於記憶體材質290與部分第二接點綱間，提供對記憶體材質之"熱覆蓋層"，並用以保存記憶體材質層290内之熱能。本紙 (CNS)A4 規格（210 X 297 公餐）I · · I ϋ ϋ ϋ a · — a · — · 1 1§ i · — I I- ϋ ϋ I%! 17 556343 A7 ____________________ B7 V. Description of the invention (16) 5 10 15 Consumption cooperation: The power consumption and overall energy increase in printing 20 25 require programming of the memory material. Therefore, an electrical contact structure is provided, which has a relatively high power consumption adjacent to the memory material and a relatively low power consumption at a distance from the memory material, thereby reducing the programming of the memory material. Required total power and total energy. Furthermore, as described above, the conductive sidewall spacer may be adjacent to the memory material along the edge, and the contact area between the memory material and the conductive sidewall spacer may be one or a part of the edge of the conductive spacer. This is a fairly small contact area. Although it is not intended to be limited by theory, reducing the size of the contact area can reduce the volume of the programmed memory material f, thereby reducing the total current required for programming the memory components. Therefore, it is specially designed to use "multi-zone materials" as electrical contacts, and the unique position of the conductive material relative to the memory can make the addition and absence of memory materials efficient, and supply to the total memory components Can be used more efficiently. Therefore, only a few impurities can always change the state of the memory material (that is, the energy required for programming the component is lower). Multi-zone conductive spacers therefore provide a way to increase the amount of thermal energy flowing to the memory material. In order to keep the thermal energy in the recording material, if necessary, Wei-material f (not shown) can be placed so that it at least partially surrounds the memory material. For example, referring to FIG. 1D, a layer of insulating material may be arranged between the memory material 290 and a part of the second contact outline to provide a " hot cover layer " Thermal energy. Paper (CNS) A4 (210 X 297 meals)

(請先閱讀背面之注意事項再填寫本頁) -I * 1_ n aB-Hi ϋ I ϋ n ϋ I n .^1 —i 1_1 —i I 士 m 91. 1. 2,000 556343 A7 經濟部智慧財產局貝X消費合作钍印製五、發明說明（Π) 自圖ID用以製造記憶體元件100之方法具體例係示如圖2A-2H。首先參閱圖2A，其具一基板1〇2以及配置於基板102上之介電層128，構成圖2A所示結構 200A。介電層128可為諸如二氧化矽Si〇2之介電材質，其可以諸如化學蒸氣沉積法（CVD)配置之。 ♦參閱圖2B，接著將介電層128適當罩之並蝕刻之，俾形成結構200B，其具露出部分基板102之開孔Π0 較佳。在所示具體例中，所形成之開孔為一溝槽 (trench)。然而在其它具體例中，可將開孔形成為一洞（諸如圓形或矩形洞）。溝槽170與所示平面垂直（亦即沿y-維度溝槽170具側壁表面128S (與介電層 128側壁表面相對應）及底表面1〇6。一傳導材質層133經沉積於結構200]B上，形成圖 2C所示結構200C。此沉積以共形（c〇nf〇Tma〖）沉積較佳。層133係沉積於介電層128之側壁表面128T上、介電層128之側壁表面128s上，以及溝槽17〇之底表面106上。因此部分層133係沿溝槽17〇之兩側壁表面128s沉積。該等部分層133係層133之側壁層部分 133s。層133之共形沉積可利用CVD技術為之。亦可採用其它可行之沉積方法，使得層133適當覆蓋於侧壁表面128s。層133材質將構成傳導側壁間隔物 130A、B之第一區R1，如圖1A所示。因此層以所採用之材質以具適當電阻率者較佳。層133可採用適於第-區R1之材質。如上述，這些材質包含n型換雜 5 10 15 20 25(Please read the notes on the back before filling this page) -I * 1_ n aB-Hi ϋ I ϋ n ϋ I n. ^ 1 —i 1_1 —i I mm 91. 1. 2,000 556343 A7 Intellectual Property of the Ministry of Economic Affairs Printing by Bureau X Consumer Cooperation V. Description of the Invention (Π) The specific example of the method for manufacturing the memory element 100 from the ID is shown in Figures 2A-2H. First, referring to FIG. 2A, a substrate 102 and a dielectric layer 128 disposed on the substrate 102 are included to form a structure 200A shown in FIG. 2A. The dielectric layer 128 may be a dielectric material such as silicon dioxide SiO2, which may be configured such as a chemical vapor deposition (CVD) method. ♦ Referring to FIG. 2B, the dielectric layer 128 is appropriately covered and etched to form a structure 200B, which preferably has an opening Π0 that exposes part of the substrate 102. In the specific example shown, the opening formed is a trench. However, in other specific examples, the opening may be formed as a hole (such as a circular or rectangular hole). The trench 170 is perpendicular to the plane shown (ie along the y-dimension trench 170 with a sidewall surface 128S (corresponding to the sidewall surface of the dielectric layer 128) and a bottom surface 106. A conductive material layer 133 is deposited on the structure 200 2B, a structure 200C shown in FIG. 2C is formed. This deposition is preferably conformal (conformation Tma). Layer 133 is deposited on the sidewall surface 128T of the dielectric layer 128 and the sidewall of the dielectric layer 128. On the surface 128s, and on the bottom surface 106 of the trench 170. Therefore, the partial layer 133 is deposited along the two sidewall surfaces 128s of the trench 170. The partial layers 133 are the sidewall layer portions 133s of the layer 133. The CVD technique can be used for this purpose. Other feasible deposition methods can also be used, so that the layer 133 covers the sidewall surface 128s appropriately. The material of the layer 133 will constitute the first region R1 of the conductive sidewall spacers 130A and B, as shown in Figure 1A. As shown above. Therefore, the layer is preferably made of a material with an appropriate resistivity. The layer 133 can be made of a material suitable for the first region R1. As mentioned above, these materials include n-type impurities 5 10 15 20 25

^TcNS)A4 規格(210 X 297 公釐 Y 91· 1. 2,000 (請先閱讀背面之注意事項再填寫本頁) - I ϋ n n -ϋ 1 h:OJ· ϋ ·ϋ n ϋ ϋ I I* 19 556343 A7 _______ B7 五、發明說明（18) 多晶矽、ρ型摻雜多晶矽、n型摻雜矽碳化物、p型摻雜梦碳化物、鈦鎢化物、鎢矽化物、鎢、鉬及鈦氮化物。η型多晶矽可將未摻雜之多晶矽,,在原處"沉積於溝 5槽17()中形成之，其係在閃光下以CVD製程為之。或者可先沉積未摻雜多晶梦，再摻雜含鱗或神之多晶石夕形成η型多晶矽。可先沉積未摻雜多晶矽，再摻雜含硼之多晶矽形成ρ型摻雜多晶石夕。在層133經共形沉積後，接著為異向性蝕刻。異向 10性蝕刻可移除層133大抵上水平配置部分，並留下大抵上垂直配置的部分。尤其是，異向性蝕刻可移除配置於區128之上表面128Τ上之層133大抵上水平配置部分。其亦移除配置於溝槽17〇之底表面106上之層 133大抵上水平配置部分。異向性蝕刻可留下層133沿 15側壁表面128s共形沉積之層133部分。因此異向性钱刻留下層133之側壁層部分133S。異向性蝕刻結果使如圖2D所示結構200D。自傳導側壁間隔物留下側壁層133S。在此製程中的此時，各傳導間隔物僅包含單一側壁層133S，且各側壁層133S僅包含單一材質區。 20在圖2D中，遺留之側壁層133S示如傳導側壁間隔物 130A、B 〇假設層133共形坡覆於其沉積表面，傳導側壁間隔物130A、B之橫向厚度將大抵上與所選之層133厚度相等。沉積之層133使得傳導側壁間隔物13〇a、B之 25 均勻厚度大抵上在約50至約1〇〇〇埃之間較佳，在約 (請先閲讀背面之注意事項再填寫本頁) 144V Γ - · I I I I I aw * ^ ^ · ϋ n Αϋ 11 ϋ n 1 經濟部智慧財產局貝工消费合作社印製本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91« 1. 2,000 556343 一 A7 -------------- 五、發明說明（19) 100至約500埃之間更佳。 (請先閲讀背面之注意事項再填寫本頁) 圖2D所示傳導側壁間隔物130A、B連績沿溝槽 Π〇寬度方向延伸（亦即垂直於圖2D所示平面）。在 5此製程中的次一步驟係將傳導側壁間隔物130A、B罩之並餘刻之’俾沿記憶體陣列寬度方向形成複數個個別傳導側壁間隔物。這些傳導間隔物沿記憶體陣列寬度方向界定個別記憶體元件。在此製程中的次一步驟係以諸如二氧化矽Si〇2之 10介電材質填充溝槽區17G。其可藉由沉積介電材質14〇於結構200D之上，形成如圖2E所示結構200E為之。介電材質140係沉積於溝槽17〇中，以及介電區ι28 上表面之上。此沉積可利用CVD製程為之。接著可以對結構200E施行化學機械拋光（CMP)或乾蝕刻，形 15成如圖迚所示結構200F。以CMP或乾勒刻將傳導間隔物上表面平坦化，形成大抵上為平面之上緣132較佳（如圖2F所示）。經濟部智慧財產局員工消費合作社印製圖2F所示傳導側壁間隔物i3〇a、b係以單層材質沉積及異向性蝕刻形成（亦即圖2C所示層133)。因 20此，圖2F所示各傳導間隔物130A、B係單一側壁層，其包含單區材質。在圖2F中，此材質區係以第一區ri 註之。第二區R2(如圖1D所示）之電阻率高於區域仏，其可在各傳導間隔物130Α、Β中以不同方式形成之。 25所採方法至少部分係示區域R1材質而定。"上部"係指 21 本適財闕豕標¥ (CNS)A4規格⑽χ撕公楚）--- 556343 A7 B7 經濟部智慧財產局貝Η消t合作社印製五、發明說明（20) 傳導側壁間隔物自上緣132 (或部分上緣13)啟始處，並向下延伸（卿誠基板）至料缝咖物内部。因此傳導側壁間隔物上部包含所有或部分傳導間隔物上緣132。概言之，任何在本發明之精神及範疇内之增加材質電阻率方法。材質電阻之增加可利用離子佈植技術及/或改變材質摻雜物濃度為之。例如：可以適當〃相反掺雜 Uoumer-doping)"於圖W所示各傳導間隔物13〇八、 B之區域R1上部，形成第二區R2。尤其是，如區域 R1係以η型多晶矽形成之，接著可以相反摻雜硼於各區R1上部（以熟知之離子佈植技術），形成電阻率大於區域R1之區域R2。如區域fu 型多晶矽係以硼輕微相反摻雜之，則可形成包含η多晶;5夕之區域R2。如區域R1之ρ型多晶矽係以磷重度相反摻雜之，則可形成包含ρ多晶矽之區域R2。類似地，如區域R1係以ρ型多晶矽形成之，則可以礎相反摻雜於各區域R1上部，形成電阻率亦大於區域R1之區域R2。如區域R1之ρ型多晶碎係以填輕微相反掺雜之，則可形成包含ρ多晶矽之區域R2。如區域R1之ρ型多晶矽係以磷重度相反摻雜之，則可形成包含η多晶矽之區域R2。因此，可將第一區R1上部相反摻雜，形成電阻率大於區域R1之區域R2。可將第一區R1上部充分以硼相反摻雜之，俾形成包含η多晶矽之區域R2。或者可 10 裝 « 訂 15 20 22 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 91. 1. 2,000 556343 A7 B7^ TcNS) A4 size (210 X 297 mm Y 91 · 1. 2,000 (Please read the notes on the back before filling out this page)-I ϋ nn -ϋ 1 h: OJ · ϋ · ϋ n ϋ ϋ II * 19 556343 A7 _______ B7 V. Description of the invention (18) Polycrystalline silicon, p-type doped polycrystalline silicon, n-type doped silicon carbide, p-type doped dream carbide, titanium tungsten carbide, tungsten silicide, tungsten, molybdenum, and titanium nitride Η-type polycrystalline silicon can be formed in-situ " deposited in trench 5 groove 17 (), which is under the flash CVD process. Or you can first deposit the undoped polycrystalline silicon Then, doped polycrystalline stones containing scales or gods to form n-type polycrystalline silicon. Undoped polycrystalline silicon can be deposited first, and then boron-containing polycrystalline silicon is doped to form p-type doped polycrystalline silicon. Layer 133 is conformally deposited After that, anisotropic etching is followed. The anisotropic etching removeable layer 133 is substantially above the horizontally disposed portion, leaving a portion substantially opposite to the vertical arrangement. In particular, the anisotropic etching may be removed and disposed in the region 128. The layer 133 on the upper surface 128T is substantially higher than the horizontally disposed portion. It also removes the layer 133 disposed on the bottom surface 106 of the groove 170. Mostly, it is horizontally arranged. Anisotropic etching can leave the layer 133 of the layer 133 conformally deposited along the 15 sidewall surface 128s. Therefore, the anisotropic etching leaves the sidewall layer portion 133S of the layer 133. The anisotropic etching results are shown in the figure. Structure 200D shown in 2D. Self-conducting sidewall spacers leave a sidewall layer 133S. At this time in this process, each conductive spacer includes only a single sidewall layer 133S, and each sidewall layer 133S includes only a single material region. In 2D, the left side wall layer 133S shows that if the conductive side wall spacers 130A and B are assumed to cover the deposited surface of the conformal slope, the lateral thickness of the conductive side wall spacers 130A and B will be much larger than the thickness of the selected layer 133. Equal. The deposited layer 133 makes the uniform thickness of the conductive sidewall spacers 13a, B, 25 is preferably between about 50 and about 1,000 angstroms. It is about about (please read the precautions on the back before filling in this (Page) 144V Γ-· IIIII aw * ^ ^ · ϋ n Αϋ 11 ϋ n 1 Printed on the paper by the Shelley Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) 91 «1. 2,000 556343 A7 -------------- 5. Description of the invention (19) 100 to about 500 angstroms is better. (Please read the precautions on the back before filling this page) Figure 2D conductive sidewall The spacers 130A and B continuously extend along the width of the trench Π0 (that is, perpendicular to the plane shown in FIG. 2D). The next step in this process is to cover the conductive sidewall spacers 130A and B with the remaining time. Zhi'an forms a plurality of individual conductive sidewall spacers along the width of the memory array. These conductive spacers define the individual memory elements along the width of the memory array. The next step in this process is to fill the trench region 17G with a dielectric material such as silicon dioxide SiO2. It can deposit a dielectric material 14 on the structure 200D to form the structure 200E as shown in FIG. 2E. A dielectric material 140 is deposited in the trench 170 and on the upper surface of the dielectric region 28. This deposition can be done using a CVD process. Then, the structure 200E may be subjected to chemical mechanical polishing (CMP) or dry etching to form the structure 200F as shown in FIG. It is better to flatten the upper surface of the conductive spacer by CMP or dry engraving to form a planar upper edge 132 (see FIG. 2F). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The conductive sidewall spacers i30a and b shown in Figure 2F are formed by single-layer material deposition and anisotropic etching (ie, layer 133 shown in Figure 2C). Therefore, each of the conductive spacers 130A and B shown in FIG. 2F is a single sidewall layer, which includes a single region material. In FIG. 2F, this material area is noted with the first area ri. The resistivity of the second region R2 (as shown in FIG. 1D) is higher than that of the region 仏, which can be formed in each of the conductive spacers 130A, B in different ways. The method adopted depends at least in part on the material of the region R1. " Upper " refers to 21 copies of the appropriate financial standard (CNS) A4 specification (× Tear public) --- 556343 A7 B7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative, V. Description of invention (20) Conductive sidewall The spacer starts from the upper edge 132 (or part of the upper edge 13), and extends downward (Qingcheng substrate) to the inside of the seam coffee. The upper part of the conductive sidewall spacer therefore contains all or part of the upper edge 132 of the conductive spacer. In summary, any method of increasing material resistivity within the spirit and scope of the present invention. The increase of material resistance can be achieved by ion implantation technology and / or changing the material dopant concentration. For example: Uoumer-doping) can be appropriately doped on top of the region R1 of each of the conductive spacers 130 and B shown in FIG. W to form a second region R2. In particular, if the region R1 is formed of n-type polycrystalline silicon, then boron can be doped on the upper portion of each region R1 (using the well-known ion implantation technique) to form a region R2 having a resistivity greater than that of the region R1. If the region fu-type polycrystalline silicon is doped with boron slightly oppositely, a region R2 containing η polycrystalline can be formed. If the p-type polycrystalline silicon of the region R1 is heavily doped with phosphorus in the opposite direction, a region R2 containing the p-polycrystalline silicon can be formed. Similarly, if the region R1 is formed of p-type polycrystalline silicon, it can be doped on the upper side of each region R1, and a region R2 having a resistivity greater than that of the region R1 can be formed. If the p-type polycrystalline fragment of the region R1 is filled with slightly opposite doping, a region R2 containing the p-polycrystalline silicon can be formed. If the p-type polycrystalline silicon in the region R1 is doped with phosphorus in the opposite direction, a region R2 containing the η polycrystalline silicon can be formed. Therefore, the upper portion of the first region R1 may be doped oppositely to form a region R2 having a resistivity greater than that of the region R1. The upper portion of the first region R1 may be fully doped with boron in the opposite direction to form a region R2 containing η polycrystalline silicon. Or 10 packs «Order 15 20 22 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm 91. 1. 2,000 556343 A7 B7

五、發明說明（21) 將第-區R1上部充分以硼相反摻雜之，俾形成包含p 多晶石夕之區域R2。多區傳導側壁間隔物mA、b包含第-區RU第二區R2,如圖2G所示。較高電阻性區 5域R2啟始於上緣132。區域R2高度"h2"低於約麵埃較佳，低於約800埃更佳，低於約6〇〇埃最佳。區域只1高度低於約10,000埃較佳，低於約7 〇〇〇埃更佳，低於約5,000埃最佳。當然區域R1及R2之高度亦可變化之。 1〇現參閱圖2H，結構20〇H係將一層記憶體材質29〇沉積於圖2G所示結構之上形成之。接著將一層傳導材質300沉積於記憶體層290之上，形成第二接點。注意所沉積之記憶體層290僅與傳導側壁間隔物13〇a、 B之各上緣132或各上緣132的一部份相接。大抵上在 15各傳導間隔物n〇A、B與記憶體材質間斯有的電氣通連係經由各傳導間隔物之邊緣132或部分邊緣132為之。先閲讀背面之注意事項再填本頁訂經濟部智慧財產局員工消費合作社印製注意可以其它方式製造多區傳導側壁間隔物。其係示如圖2A，_2D，。圖2A，中的結構200A，所示傳導側 20壁間隔物130A、B包含單一側壁層材質ri(圖2A，同於圖2F)。可將結構200A，罩之並選擇性蝕刻之，俾移除傳導側壁間隔物130A、B上部，產生在各傳導側壁間隔物130A、B的材質R1上部中的凹處。參閱圖2诠，，凹處150係示於結構200B’中。凹處15〇之填充係藉 25由沉積一層材質160於結構200B'之上，形成如圖2C, 23V. Description of the invention (21) The upper part of the first region R1 is fully doped with boron in the opposite direction to form a region R2 containing p polycrystalline stone. The multi-region conductive sidewall spacers mA, b include the first-region RU and the second region R2, as shown in Fig. 2G. The higher resistive region 5 domain R2 starts at the upper edge 132. The area R2 height " h2 " is preferably below about Angstroms, more preferably below about 800 Angstroms, and most preferably below about 600 Angstroms. The area 1 is preferably less than about 10,000 Angstroms in height, more preferably less than about 7,000 Angstroms, and most preferably less than about 5,000 Angstroms. Of course, the heights of the regions R1 and R2 can also be changed. 10 Now referring to FIG. 2H, the structure 20H is formed by depositing a layer of memory material 29O on the structure shown in FIG. 2G. A layer of conductive material 300 is then deposited on the memory layer 290 to form a second contact. Note that the deposited memory layer 290 is only in contact with each upper edge 132 or a portion of each upper edge 132 of the conductive sidewall spacers 130a, B. Mostly, there is an electrical connection between the 15 conductive spacers noA, B and the memory material via the edge 132 or a part of the edge 132 of each conductive spacer. Read the notes on the back first and then fill out this page. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, Consumer Cooperatives. Note that the multi-zone conductive sidewall spacers can be made in other ways. Its system is shown in Figure 2A, _2D. The structure 200A in FIG. 2A shows the conductive side 20 wall spacers 130A, B including a single sidewall material ri (FIG. 2A, same as FIG. 2F). The structure 200A can be selectively etched and removed to remove the upper portions of the conductive sidewall spacers 130A, B, resulting in a recess in the upper portion of the material R1 of each conductive sidewall spacer 130A, B. Referring to Fig. 2, the recess 150 is shown in the structure 200B '. The filling of the recess 15 is formed by depositing a layer of material 160 on the structure 200B 'by 25, as shown in FIG. 2C, 23

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91· 1. 2,〇〇〇 556343 A7 經濟部智慧財產局貝工消t合作社印製五、發明說明（22) 所示結構200C，。如圖2C，所示，層160可填充凹處 150並未於介電區128、140之上。接著可將結構2〇〇c，經化學機械拋光（CMP)或乾蝕刻，形成大抵上為平 5面之上緣132,如圖2D，所示結構200Df。結構200D, 包含傳導側壁間隔物130A、B，其中各傳導側壁均包含兩材質區-第一區R1及第二區R2。區R2係由圖2Cy 所示層160材質組成。注意圖2D，所示結構同於圖2G 所示結構。圖2D'所示第二區R2可由未經任何進一步修改之具適當電阻率材質形成。如上述，適當材質示例包含^ 型捧雜多晶矽、p型摻雜多晶矽、n型摻雜矽碳化合物及/或合金、p型摻雜碎碳化合物及/或合金、鈦碳氮化物、鈦鋁氮化物、鈦矽氮化物、碳及鈦氮化物型式。第二區R2所選材質之電阻率較佳高於以蝕刻製程移除’俾產生凹處150之R1材質電阻率（圖2B，所示）。或者可以仍需改變以增加其電阻率之材質啟始形成第二區R2。例如區R2初始時可自未摻雜多晶矽形成之（亦即圖20所示層160可經沉積為未摻雜多晶矽）。接著可將硼摻雜於第二區R2之未摻雜多晶矽中，形成P多晶矽區，或者可將諸如磷或砷摻雜於第二區 R2之未摻雜多晶矽中，形成晶矽區。因此，可藉由改變材質内摻雜物濃度及/或將離子佈植入材質中而使電阻率增加。在圖1A所示記憶體元件具體例中，在此元件中對 10 15 20 25 91. 1· 2,00丨 (請先閱讀背面之注意事項再填寫本頁) 24 556343 經濟部智慧財產局貝工消費合作社印製五、發明說明（23) 各單胞記憶體元件之電氣接點係一傳導側壁間隔物。傳導側壁間隔物130A、B係沿溝槽側壁表面，藉由沉積一層傳導材質於溝槽中，再對該層做異向性蝕刻移一 5除水平配置表面而形成之單一側壁層。圖1八及1B所I 閱示傳導間隔物外型大抵上係為平面側壁層型式。 4 *另一型式之電氣接點可自側壁層形成，其係將材質共形沉積於其它類型之側壁表面上製得（亦即異於溝槽之側壁表面的側壁表面）。例如：可將一層傳導材質大抵上共形沉積於一孔（例如一通路）、一臺或柱之表面。該孔、臺或柱可為圓形、正方形、矩形或不規則形。異向性蝕刻該共形沉積傳導層，移除沉基層之水平配置部分，而僅留下一或多個垂直配置部分。剩下的一或多個垂直配置部分係以傳導側壁間隔物型式存在之側壁層。，、側壁間隔物係以如共形沉積傳導材質於圓柱型通路孔者（緊接著為異向性蝕刻），將成為具雙開端之圓柱型表面型式者（其轴心大抵上與基板垂直）。孔、柱或台之外型變化將造成側壁間隔物外型的改變。亦即與孔、台或柱外型相對應之傳導側壁間隔物橫剖區段 (亦即與基板平行之橫剖區段）。其可為環形物。或者其亦可為矩形或不規則形。圖3A所示係在圓形通路中形成之圓柱形傳導側壁間隔物330立體圖（因此g具環形水平橫剖區段）。圓柱形傳導間隔物33〇係為,,單層"。異及其包含一單一圓柱形側壁層。圓柱形側壁層 10 20 25 25 讀背之注意事項再填寫本頁裝 I 訂 % 本紙張尺摩適用中國國家標準（CNS)A4規格（210 X 297公釐） 91· 1. 2,〇〇〇 556343 A7 五發明說明（24) B7 5 10 15 經濟部智慧財產局貝工消費合作社印製 20 25 开^壁居 A所示内外部圓柱形表面間距。圓柱 =2具兩開端或，，構成上緣332及下緣33卜傳導間隔物330之上緣332及下緣331係將一砉而。與基板平仃之平面貫穿傳導層330形成之環形si圖3A所不具體例中，記憶體材f 290層僅與間隔物330上端相鄰。尤其是，記憶體材質290僅與上緣332相鄰。讀趙材質層29〇係配置於傳導間隔物现之上，而第二接點層_係沉積於記憶體材質29G之上。記从材質層290(大抵上水平配置較佳）僅與和記憶體材質290相鄰之傳導側壁間隔物33〇上緣说或部分上緣332相鄰。所有在傳導間隔物33〇與記憶體材質 290間的電氣通連均係經由上緣332或部分上緣332為之。（亦即所有或部分環形表面332) 一圖3B係一多區圓柱形傳導間隔物33〇示例。圖中所示傳導間隔物33〇至少包含具第一電阻率之第一區R1以及具第二電阻率之第二區R2。第二區R2之電阻率高於第一區FU之電阻率。較高電阻性之第二區 R2與記憶體材質相鄰，而電阻性較低之第一區與記憶體材質有一距離較佳。、在圖3B所示示例中，較高電阻性之第二區^^係為與上緣332相鄰之傳導間隔物〃上部〃（並與基板川2 有一距離）。亦即其自上緣332向下延伸至圓桎形傳導間隔物内部約〃h2〃距離（較高電阻性之第二區R2的„ 請先閲讀背注This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 91 · 1.2, 〇00556343 A7 Printed by Beigong Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (22) Show structure 200C. As shown in FIG. 2C, the layer 160 may fill the recess 150 and not over the dielectric regions 128, 140. Then, the structure 200c can be chemically mechanically polished (CMP) or dry-etched to form an upper edge 132 that is substantially flat and flat. As shown in FIG. 2D, the structure 200Df is shown. The structure 200D includes conductive sidewall spacers 130A and B, wherein each conductive sidewall includes two material regions-a first region R1 and a second region R2. The region R2 is composed of the layer 160 material shown in FIG. 2Cy. Note that FIG. 2D shows the same structure as that shown in FIG. 2G. The second region R2 shown in FIG. 2D 'may be formed of a material with a suitable resistivity without any further modification. As mentioned above, examples of suitable materials include ^ -type heteropolycrystalline silicon, p-type doped polycrystalline silicon, n-type doped silicon carbon compounds and / or alloys, p-type doped carbon compounds and / or alloys, titanium carbonitrides, titanium aluminum Nitride, titanium silicon nitride, carbon and titanium nitride types. The resistivity of the selected material of the second region R2 is preferably higher than the resistivity of the R1 material which is removed by the etching process to generate the recess 150 (Fig. 2B, shown). Or the material that still needs to be changed to increase its resistivity initially forms the second region R2. For example, the region R2 may be initially formed from undoped polycrystalline silicon (that is, the layer 160 shown in FIG. 20 may be deposited as undoped polycrystalline silicon). Then, boron can be doped in the undoped polycrystalline silicon in the second region R2 to form a P polycrystalline silicon region, or phosphorus or arsenic can be doped in the undoped polycrystalline silicon in the second region R2 to form a crystalline silicon region. Therefore, the resistivity can be increased by changing the dopant concentration in the material and / or implanting the ion cloth into the material. In the specific example of the memory element shown in Figure 1A, in this element, 10 15 20 25 91. 1 · 2, 00 丨 (Please read the precautions on the back before filling this page) 24 556343 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Industrial and Commercial Cooperatives V. Description of the Invention (23) The electrical contact of each single cell memory element is a conductive sidewall spacer. The conductive sidewall spacers 130A and B are a single sidewall layer formed by depositing a layer of conductive material in the trench along the trench sidewall surface, and then anisotropically etching the layer to remove the horizontally-arranged surface. Figures 1A and 1B show that the shape of the conductive spacer is mostly a flat sidewall layer. 4 * Another type of electrical contact can be formed from the side wall layer, which is made by conformally depositing the material on the surface of other types of side walls (that is, the side wall surface different from the side wall surface of the trench). For example, a layer of conductive material can be deposited conformally on the surface of a hole (such as a via), a table, or a pillar. The hole, table, or post can be round, square, rectangular, or irregular. The conformally deposited conductive layer is anisotropically etched to remove the horizontally disposed portion of the sinker layer, leaving only one or more vertically disposed portions. The remaining one or more vertically-arranged portions are sidewall layers that exist in the form of conductive sidewall spacers. The sidewall spacers are made of conductive material such as conformal deposition on cylindrical via holes (next to anisotropic etching), and will become cylindrical surface types with double open ends (the axis of which is substantially perpendicular to the substrate) . A change in the shape of the hole, column, or table will cause a change in the shape of the sidewall spacer. That is, the cross-section section of the conductive sidewall spacer corresponding to the shape of the hole, table or pillar (that is, the cross-section section parallel to the substrate). It may be a ring. Or it may be rectangular or irregular. Figure 3A shows a perspective view of a cylindrical conductive sidewall spacer 330 formed in a circular path (hence g has an annular horizontal cross section). The cylindrical conductive spacer 33 is a single layer ". It includes a single cylindrical sidewall layer. Cylindrical sidewall layer 10 20 25 25 Read the notes on the back of the page and fill it in. Binding% This paper ruler applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 91 · 1,2,00. 556343 A7 Description of the five inventions (24) B7 5 10 15 Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 25 The distance between the inside and outside of the cylindrical surface shown in Wall A. Cylinder = 2 with two open ends or, forming the upper edge 332 and the lower edge 33. The upper edge 332 and the lower edge 331 of the conductive spacer 330 will be pulled together. In the specific example shown in FIG. 3A, the ring si formed through the conductive layer 330 on a plane parallel to the substrate is only adjacent to the upper end of the spacer 330 in the memory material f 290 layer. In particular, the memory material 290 is only adjacent to the upper edge 332. The Zhao material layer 29 is disposed on the conductive spacer, and the second contact layer _ is deposited on the memory material 29G. Note that the material layer 290 (which is better in a horizontal configuration is better) is only adjacent to the upper edge or part of the upper edge 332 of the conductive sidewall spacer 33 adjacent to the memory material 290. All electrical communication between the conductive spacer 33 and the memory material 290 is through the upper edge 332 or part of the upper edge 332. (I.e. all or part of the annular surface 332)-Figure 3B is an example of a multi-zone cylindrical conductive spacer 33. The conductive spacer 33 shown in the figure includes at least a first region R1 having a first resistivity and a second region R2 having a second resistivity. The resistivity of the second region R2 is higher than that of the first region FU. The higher resistance second region R2 is adjacent to the memory material, and the lower resistance first region R2 is better from the memory material. In the example shown in FIG. 3B, the second region of higher resistance ^^ is a conductive spacer 〃 upper 相邻 adjacent to the upper edge 332 (and a distance from the substrate 2). That is, it extends from the upper edge 332 down to the circular 桎 -shaped conductive spacer at a distance of about 〃h2〃.

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9l· 1. 2,000 556343 A7 ____ B7 五、發明說明（25) 經濟部智財產局員工消費合作社印製高度〃）。圓柱形傳導間隔物之區域R1及R2可以如圖1A中所示"平面"傳導間隔物130A、B之區域RJ及反2的類 5似形成方法為之。第一區R1及第二區R2之摻雜可相異。例如：較高電阻性之第二區R2可以適當的離子佈植技術形成。此離子佈植技術可利用適當相反摻雜材質R1，形成較高電阻性材質R2。或者，可先對材質 R1蝕刻，再以較高電阻性之材質R2填充之。概言之，上述所有方法及材質（與平面傳導側壁間隔物有關的: 均可應用於此具體例中。在圖1A、ID、3A及3B所示記憶體元件示例中，傳導側壁間隔物130A、B (或330)係與記憶體材質相鄰，使得在記憶體材質與傳導側壁間隔物13〇A、B2 間無"中間"層存在。、在本發明之另一具體例中，在傳導側壁間隔物與記憶體材質間可能會有一或多層中間層存在。示如圖 1E，該處之中間層280係配置於記憶體材質29〇與傳導側壁間隔物130A、B之間。注意在此具體例中，大抵上其記憶體材質290與傳導側壁間隔物13〇A、B間之電氣通連仍係經由傳導側壁間隔物13〇A、B上緣132 或部分上緣m為之，即使層280係配置於記憶體材質290與傳導側壁間隔物130A、B之間亦同。再善，在圖1E所示組態中，較高電阻性之第二區R2係與接點區相鄰（上緣132)，而電阻性較低之第一區R1與接 10 15 20 25 g^B(CNS)A4 ^ (210 X 297公釐） 2,000 (請先閲讀背面之注意事項再填寫本頁) • I > I n n H ϋ n n^OJi n 1 n I n ϋ n · —J ϋ —4 Φ! 556343 A7 經濟部智慧財產局員工消费合作社印製五、發明說明（26) 點區有-距離（上緣132)。亦可見到較高電阻性一區R2與電阻性較低之第一 p 材質290 He 較’其與記憶體 :質："父為接近。亦即第二區R2"貼近,,記憶體材質，而第一區R1貝1J"遠離記憶體材質。在本發明之另-具體例中，傳導侧壁間隔物在圖1”的傳導間隔物130A、B或在圖3A中的傳二間隔物330)除了較高電阻性之第二區R2與電阻低之第-區R1之外，可能尚包含一或多區材質。在圖 1F所示具體例中，傳導側壁間隔物13〇A、B各包含— 配置於記憶體材質290與第二區R2間之第三區幻。注意在此具體例中，大抵上在記憶體材f 29〇與傳導側壁間隔物13GA、B間所有的電氣通連仍係經由上緣 132或部分上緣132為之。再具體例中所示第一區及第二區R1及R2之配位使得區域！^較區域R1接近上緣 132。（亦即第二區R2"貼近"記憶體材質，而第—區則"遠離"記憶體材質）。因此區域R2亦與傳導間隔物及記憶體材質間之接點區較為接近，而區域汉丨則具接點區較遠。再者，區域R2較區域R1接近記憶體材質亦為真。（亦即第二區R2"貼近"記憶體材質29〇,而第一區R1則"遠離"記憶體材質）。在本發明之另一具體例中，以可將可程式化電阻記憶體元件之電氣接點形成如"傳導襯裡"。此傳導襯裡較佳係單層傳導材質以彼覆開孔（諸如溝槽、孔或類似者）側壁表面及下表面。傳導襯裡示例示如圖 10 15 20 259l · 1. 2,000 556343 A7 ____ B7 V. Description of the invention (25) Printed by the Intellectual Property Office of the Ministry of Economic Affairs (Highly printed by the Consumer Cooperatives). The regions R1 and R2 of the cylindrical conductive spacers can be formed as shown in FIG. 1A " planar " The doping of the first region R1 and the second region R2 may be different. For example, the higher-resistance second region R2 may be formed by an appropriate ion implantation technique. This ion implantation technique can use the appropriate oppositely doped material R1 to form a higher resistive material R2. Alternatively, the material R1 can be etched first, and then filled with the more resistive material R2. In summary, all of the above methods and materials (related to planar conductive sidewall spacers: can be applied to this specific example. In the memory element examples shown in Figures 1A, ID, 3A, and 3B, the conductive sidewall spacer 130A , B (or 330) is adjacent to the memory material, so that there is no "middle" layer between the memory material and the conductive sidewall spacers 13A, B2. In another specific example of the present invention, There may be one or more intermediate layers between the conductive sidewall spacer and the memory material. As shown in Figure 1E, the intermediate layer 280 is located between the memory material 29 and the conductive sidewall spacers 130A and B. Note In this specific example, the electrical communication between the memory material 290 and the conductive sidewall spacers 13A, B is still largely through the upper edge 132 of the conductive sidewall spacers 13A, B, or part of the upper edge m. Even if the layer 280 is disposed between the memory material 290 and the conductive sidewall spacers 130A and B. Again, in the configuration shown in FIG. 1E, the second region R2 with higher resistance and the contact region Adjacent (upper edge 132), and the lower resistance first region R1 is connected to 10 15 20 25 g ^ B (CNS) A4 ^ (210 X 297 mm) 2,000 (Please read the notes on the back before filling this page) • I > I nn H ϋ nn ^ OJi n 1 n I n ϋ n · —J ϋ —4 Φ! 556343 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (26) The dot area has a distance (upper edge 132). It can also be seen that the higher resistivity area R2 and The first material 290 He, which has a lower resistance, is closer to the memory: Quality: " Father is close. That is, the second region R2 " is close to the memory material, and the first region R1 is 1J " away from the memory. In another specific embodiment of the present invention, the conductive sidewall spacer is the conductive spacer 130A, B of FIG. 1 ”or the second spacer 330 of FIG. 3A), except for the second region with higher resistance. R2 and the low-resistance first-region R1 may include one or more regions of material. In the specific example shown in FIG. 1F, the conductive sidewall spacers 13A and B each include — arranged in the memory material 290 and the first region. The third area between the two areas R2 is magic. Note that in this specific example, most of the electrical communication between the memory material f 29〇 and the conductive sidewall spacers 13GA, B It is still through the upper edge 132 or part of the upper edge 132. The coordination of the first and second regions R1 and R2 shown in the specific example makes the region! ^ Is closer to the upper edge 132 than the region R1. (Ie, the second Region R2 is "close to" the memory material, and the first region is "distant from" the memory material.) Therefore, the region R2 is also closer to the contact area between the conductive spacer and the memory material, and the region Han is The contact area is far away. Furthermore, it is true that the region R2 is closer to the memory material than the region R1. (That is, the second region R2 is " close " to the memory material 29, and the first region R1 is " away from " the memory material). In another embodiment of the present invention, the electrical contacts of the programmable resistive memory element can be formed as " conductive liner ". The conductive liner is preferably a single layer of conductive material to cover the side wall surface and the lower surface of an opening (such as a groove, a hole, or the like). An example of a conductive liner is shown in Figure 10 15 20 25

X 297公釐） 91. 1. 2,00( (請先閲讀背面之注意事項再填寫本頁) 裝 n I I I I ϋ- I n I I.» 經濟部智慧財產局貝工消費合作社印製 556343 A7 "" '----------B7_ ___ ^__ 五、發明說明（2力 4A-4C。在圖4A中，傳導襯裡430A係形成於溝槽中。X 297 mm) 91. 1. 2,00 ((Please read the precautions on the back before filling out this page) Install n IIII ϋ- I n I I. »Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs 556343 A7 " " '---------- B7_ ___ ^ __ 5. Explanation of the invention (2 force 4A-4C. In FIG. 4A, a conductive liner 430A is formed in the trench.

圖4B係傳導襯裡430B形成於矩形孔之示例。圖4C 係傳導襯裡430C形成於圓形孔之示例。當然其它外形 5亦可。如圖4A_4C所示，各傳導襯裡均具一或多個側壁層部及下層部。傳導襯裡上端係一具上緣432之開鳊·。（在所示特殊示例中，各傳導襯裡"上緣〃432係以貝穿各傳導襯裡之大抵上與基板1〇2平行之平面構成的表面）。注意圖4A所示U形傳導襯裡具〃雙"上緣 !〇 432。 ’、、注意在圖4A-4C所示傳導襯裡示例中，側壁層部大抵上係垂直配置。然而其非必然如此。側壁層部可為傾斜狀。如傳導襯裡係在具斜側壁表面之溝槽或通路中形成即屬之。 15 傳導襯裡沿邊與記憶體材質相鄰較佳、。亦即僅有傳導襯裡之邊緣或部分邊緣與記憶體材質相鄰。大抵上剩下所有的傳導襯裡均與記憶體材質遠離。大抵上所有在傳導襯裡與記憶體材質間之電氣通連係經傳襯裡之邊緣或部分邊緣為之較佳（亦即經由傳導襯裡〃邊緣 2 0 部"）。圖5A及5B係述本發明之記憶體元件具體例，其中電氣接點之-係在-圓形孔（例如一通路）中形成的傳導襯裡63〇。圖5八係記憶體元件之立體圖式；圖 5B則係與χ-ζ平面平行之橫剖圖。 25 如所示，傳導襯裡630係—具上開端（與基板102 29 ^^^^中國_豕標準（CNS)A4規格（210 X 297公爱)------ (請先閲讀背面之注意事項再填寫本頁)FIG. 4B is an example in which a conductive liner 430B is formed in a rectangular hole. FIG. 4C is an example in which a conductive liner 430C is formed in a circular hole. Of course, other shapes 5 are also possible. As shown in FIGS. 4A-4C, each conductive liner has one or more side wall layer portions and a lower layer portion. The upper end of the conductive lining is open with an upper edge 432. (In the particular example shown, each conductive liner " upper edge 〃 432 is a surface formed by penetrating each conductive liner substantially against a plane parallel to the substrate 102). Note that the U-shaped conductive liner shown in Figure 4A has a double " upper edge! 432. ',, Note that in the example of the conductive lining shown in Figs. 4A-4C, the side wall layer portion is mostly vertically arranged. However, this is not necessarily the case. The side wall layer portion may be inclined. This is the case if the conductive liner is formed in a groove or channel with a beveled sidewall surface. 15 The conductive lining is preferably adjacent to the memory material along the edges. That is, only the edge or part of the edge of the conductive liner is adjacent to the memory material. Mostly, all the remaining conductive linings are far away from the memory material. Most of the electrical communication between the conductive lining and the memory material is better via the edge or part of the edge of the transmission lining (that is, via the conductive lining 〃 edge 20). 5A and 5B show a specific example of the memory element of the present invention, in which the electrical contact-is a conductive liner 63 formed in a circular hole (for example, a via). FIG. 5 is a perspective view of an eight-series memory element; FIG. 5B is a cross-sectional view parallel to the χ-ζ plane. 25 As shown, the conductive lining 630 series—with the upper end (with the substrate 102 29 ^^^^ China_ 豕 Standard (CNS) A4 specification (210 X 297 public love) ------ (Please read (Please fill in this page again)

經濟部智慧財產局貝工消費合作社印製 556343 A7 ~—------g_7___ 五、發明說明（28) 遠離並背對之）以及一接近底端（與基板貼近）之圓柱殼。上開端具有一環形上緣632。傳導襯裡630係一圓柱形側壁層部630S及一底層部630B。 5 在圖5A及5B所示示例中，傳導襯裡630係一圓柱形杯。如圖5B所示，側壁層部63〇s構成杯側，而底層部630B則構成杯底。上緣632可稱之為杯〃緣,，。傳導概裡可具其它杯形，諸如拋物形、半球形、圓錐形及平截頭形。 ° 5己憶體材質層290為一大抵上與傳導襯裡630之開端相鄰之水平配置層平面較佳。因此，記憶體材質僅與傳導襯裡630之上緣632 (亦即緣）或傳導襯裡之部分上緣632相鄰。傳導襯裡63〇的其它部分則與記憶體材質遠離。大抵上所有在傳導襯裡63〇與記憶體材 15質間之電氣通連以經由緣632或部分緣632較佳。因此’接點區係由所有或部分緣632(亦即緣部）界定之。緣《2係一環形，其厚度與傳導襯裡63〇之厚度相等。環形之厚度，以及因而在傳導襯裡與記憶體=質間之接點區可因傳導襯裡_沉積於_通路孔之 20度降低而減少。了將傳導襯裡形成為’’多區’’，並至少包含具第一電阻率之第-區R1以及具第二電阻率之第二區幻。第二區R2之電阻率高於第一區R1之電阻率。此係示於圖5C (立體圖）及圖5D(與χ-ζ平面平行之橫剖圖）。 25在所示具體例中，較高電阻性之第二區R2係與記憶體 30 (CNS^i^(21。x 29T^ )--~*--_Printed by Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 556343 A7 ~ -------- g_7___ V. Description of the invention (28) Keep away from and face back) and a cylindrical shell near the bottom end (close to the substrate). The upper opening has an annular upper edge 632. The conductive liner 630 is a cylindrical side wall layer portion 630S and a bottom layer portion 630B. 5 In the example shown in Figures 5A and 5B, the conductive liner 630 is a cylindrical cup. As shown in FIG. 5B, the side wall portion 63s constitutes the cup side, and the bottom layer portion 630B constitutes the bottom of the cup. The upper edge 632 can be called the cup edge. The conduction profile may have other cup shapes, such as parabolic, hemispherical, conical, and frustum. ° 5 The memory material layer 290 is preferably a plane which is a horizontal arrangement layer which is adjacent to the beginning of the conductive liner 630. Therefore, the memory material is only adjacent to the upper edge 632 (ie, the edge) of the conductive liner 630 or a portion of the upper edge 632 of the conductive liner. The other parts of the conductive lining 63 are far away from the memory material. It is better than all the electrical communication between the conductive lining 63 and the memory material 15 to pass through the edge 632 or part of the edge 632. Therefore, the 'contact area' is defined by all or part of the edge 632 (i.e., the edge portion). The margin "2 is a ring, and its thickness is equal to the thickness of the conductive lining 63 °. The thickness of the ring, and thus the contact area between the conductive liner and the memory = mass, can be reduced by a 20 degree reduction in the conductive liner's deposition in the via hole. The conductive liner is formed as a 'multi-region', and includes at least a first region R1 having a first resistivity and a second region having a second resistivity. The resistivity of the second region R2 is higher than that of the first region R1. This is shown in Fig. 5C (a perspective view) and Fig. 5D (a cross-sectional view parallel to the χ-ζ plane). 25 In the specific example shown, the second region R2 with higher resistance is connected to the memory 30 (CNS ^ i ^ (21.x 29T ^)-~ * --_

91· 1. 2,C (請先閲讀背面之注意事項再填寫本頁) · n an ϋ ϋ i_i I n · ϋ I i_i i_i 1· I I ^ 556343 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（29) 材質相鄰，而電阻性較低之第―區R1則與記憶體有一距離。在圖5C及5D所示具體例中，較高電阻性之第二 5區R2係為傳導襯裡之,,上部,,，其與上緣咖相鄰並向下延伸-段距離（朝向基板）至傳導襯裡内部。(亦即傳導襯裡之較高電阻性上部包含所有或部分 632)。刀、注意在傳導襯裡與記憶體材f間可能會有一或多 10層中間層存在。除上述第一及第二區之外亦可包含至少第三區材質。第三區可配置於記憶體材質與較高電阻性第二區之間。自圖5C及5D製造圮憶體元件之方法具體例示如圖6A_6F。首先參閱圖6A，其具一基板1〇2以及 15沉積於基板102上之介電層128。介電層可自二氧化矽形成並可以CVD製程沉積之。接著介電層128經適當罩之並蝕刻形成介電層128中之孔（例如一通路）64〇, 如所示。此孔可為圓形、正方形、矩形或不規則形。在圖6A所示具體例中，所得結構6〇〇A係一在介電層 20 128中形成之圓形通路640。圖6B係圖6A所示結構 600A垂直橫剖圖（與χ-ζ平面平行）。圓柱孔64〇之側壁表面128S及下表面106示如圖6B。一傳導材質層633係沉積於圖6A及6B所示蛐構之上，形成圖6C所示結構600C。傳導材質層633係 25 共形沉積於介電區128之上表面128T、區128之側壁 31 浪尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 91. 1. 2,000 (請先閱讀背面之注意事項再填寫本頁)91 · 1.2, C (Please read the notes on the back before filling out this page) · n an ϋ ϋ i_i I n · ϋ I i_i i_i 1 · II ^ 556343 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (29) The materials are adjacent, and the first-resistance region R1 with a lower resistance is at a distance from the memory. In the specific examples shown in FIGS. 5C and 5D, the second resistive region R2 of higher resistance 5 is a conductive lining, which is adjacent to the upper edge and extends downward for a distance (toward the substrate). To the inside of the conductive liner. (I.e. the higher resistive upper portion of the conductive liner contains all or a portion 632). Note that there may be one or more 10 intermediate layers between the conductive lining and the memory material f. In addition to the above-mentioned first and second regions, at least a third region material may be included. The third region may be disposed between the memory material and the second region having higher resistance. A specific example of a method for manufacturing a memory device from Figs. 5C and 5D is shown in Figs. 6A-6F. First, referring to FIG. 6A, a dielectric layer 128 having a substrate 102 and a substrate 15 deposited on the substrate 102 is shown. The dielectric layer can be formed from silicon dioxide and can be deposited by a CVD process. The dielectric layer 128 is then appropriately masked and etched to form a hole (eg, a via) 64 in the dielectric layer 128, as shown. This hole can be round, square, rectangular, or irregular. In the specific example shown in FIG. 6A, the resulting structure 600A is a circular via 640 formed in the dielectric layer 20128. FIG. 6B is a vertical cross-sectional view of the structure 600A shown in FIG. 6A (parallel to the χ-ζ plane). The side wall surface 128S and the lower surface 106 of the cylindrical hole 64 are shown in Fig. 6B. A conductive material layer 633 is deposited on the structure shown in Figs. 6A and 6B to form a structure 600C shown in Fig. 6C. The conductive material layer 633 is 25 conformally deposited on the surface 128T above the dielectric region 128 and the sidewall 31 of the region 128. The wave size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297). (Read the notes on the back and fill out this page)

556343 Α7 __ Β7 經濟部智慧財產局貝工消f合作社印製五、發明說明（30) 表面128S以及通路孔640之下表面1〇6。因此，層633 具上部633T、側壁層區633S及下層部633B。注意層 633將形成圖5C及5D所示"雙區"傳導襯裡電氣接點之第一區R1。因此所選擇之層633材質應具適當的電阻率。可做為遠端區R1之材質已於上述之。如上述，可做為第一區R1之適當材質示例包含η型摻雜多晶矽、Ρ型摻雜多晶矽、η型摻雜矽碳化物、ρ型摻雜矽碳化物、鈦鎢化物、鎢矽化物、鎢、鉬及鈦氮化物。如所述，可以沉積及摻雜於本質多晶矽而形成η型多晶矽之第一區R1。亦即，藉由摻雜該處之本質多晶矽 (亦即在閃光環境下之CVD沉積）。或者可以先沉基本質多晶矽，再藉由磷或砷之離子佈植來摻雜多晶矽，形成η型多晶矽。可以先沉基本質多晶矽，再藉由硼之離子佈植來摻雜多晶矽，形成ρ型多晶石夕。離子佈植可以"斜角佈植"施行之，藉此將離子束以與垂直於基板之轴成一夾角射入。接者可將一層介電質140 (諸如二氧化石夕）沉積於層633上，俾填充通路670，並形成如圖6D所示結構 600D。接著可對結構600D施行CMP或乾蝕刻，俾將上表面平坦化，藉此移除部分層633之上表面633Τ，並形成圓柱杯形傳導襯裡。此係示如圖6Ε結構600Ε，其中傳導襯裡630具沿側壁128S之側壁層部630S，並具沿下表面106之底層部630Β。再者，傳導襯裡630 具上緣632。平坦化步驟形成大抵上平坦之上緣632較 5 10 15 20 25 32 請先閱讀背之注項再填寫本頁本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） 91. 1. 2,000 556343 A7 五、發明說明（31) 佳。 5 10 15 經濟部智慧財產局貝工消費合作社印製 20 25 在此製程步驟之後，傳導襯裡630僅包含單一材質區，標註如圖6E之第一材質區Rj。次一步驟係增加部分傳導襯裡630之電阻率，其中傳導襯裡630包含上緣632或部分上緣632。如圖6F所示，電阻性高於第r區R1之第二區R2係形成於與原632 W比鄰之傳導概裡上部中。傳導概裡之第二區R2可以具上述與形成多區傳導側壁間隔物相關之方法形成之。例如：可藉由周邊摻雜於第一區R1之η型多晶矽而形成第二區 R2。尤其是’可將η型多晶石夕周邊摻雜棚，形成包含η 或Ρ型多晶石夕之第二區R2。亦可以修改其中的元素與相反摻雜離子合併或獨立佈植於第二區。或者可將第一區R1上部移除（以選擇性蝕刻為之較佳）形成凹處。接著可將此凹處以電阻率較R1材質之電.阻率高之材質填充之。例如··可以諸如η或ρ型多晶矽材質填充此凹處。或者可以未摻雜多晶矽填充此凹處，接著再將其適當摻雜之（以硼、砷或鱗較佳），使其電阻性較高。在形成第一區R2後’接著可沉積記憶體材質層290 及傳導材質層（構成第二電氣接點）3〇〇。傳導襯裡63〇與記憶體材質290間接點區係為傳導襯裡表面部份，大抵上所有的電氣通連均係經由該處（傳導襯裡與記憶體材質間）。其可為上緣632或部分上緣632。（^整個上緣與記憶體材質相接，則接點區為環形）。因此，記憶體材質層290與傳導材質層300僅藉由所有或部本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 91· 1. 2,〇〇〇 (請先閱讀背面之注意事項再填寫本頁) ，· ϋ ϋ ϋ —Bi 11I ·ϋ n I · 33 556343 A7 ---------§7^_______ 五、發明說明（32) 分上緣632電氣通連。因此，本發明之一態樣係一記憶體元件，其包含一可程式化電阻記憶體元件（内含可程式化電阻材 5質）’以及用以傳遞電氣信號至記憶體材質體之裝置。用以傳遞電氣信號之裝置包含第—及第二電氣接點 (或電極）較佳’其中至少電氣接點之—係—多區接點，其包含至少具第-電阻率之第—區則以及具高於第-區R1之電阻率之第二電阻率之第二區R2 :電阻 1〇率較高之第二區R2與記憶體材質相鄰，而電阻率較低之第一區R1與記憶體材質遠離較佳。 -般而言’多區接點可為任何形式。在上述具體例中，多區接點係為襯裡之傳導間隔物型，其沿邊與記憶體材質相鄰。 ^ 15 更廣義些’多區電極可為具任意外型、共形和實際幾何之傳導材質層。在-具體例中，大抵上接點層可與記憶體材質垂直。雖不欲受理論限制，但咸信大抵上接點層與記憶體材質垂直可增加將熱能傳輸至記憶體材質並維持在其中之有效量。當接點層與記憶體材 20質垂直時，接點區（以接點層邊緣界定之）較小。亦咸信電阻性較低材質R1 (遠離記憶體材質者）可充作熱槽，吸收電阻性較高部分R2 (鄰近記憶體材質者）所產生之部分熱量。將接點層置放使其大抵上與記憶體材質垂直，可增加記憶體材質與接點層之電 25阻性較低材質Ri間距。因而在記憶體材質中或與其接 (請先閲讀背面之注意事項再填寫本頁)556343 Α7 __ Β7 Printed by the Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs, Fifth, the description of the invention (30) Surface 128S and the lower surface 106 of the via 640. Therefore, the layer 633 has an upper portion 633T, a sidewall layer region 633S, and a lower layer portion 633B. Note that layer 633 will form the first region R1 of the " dual region " conductive liner electrical contact shown in Figs. 5C and 5D. Therefore, the selected layer 633 material should have an appropriate resistivity. The material that can be used as the remote region R1 has been described above. As mentioned above, examples of suitable materials that can be used as the first region R1 include n-type doped polycrystalline silicon, p-type doped polycrystalline silicon, n-type doped silicon carbide, p-type doped silicon carbide, titanium tungsten carbide, and tungsten silicide. , Tungsten, molybdenum and titanium nitride. As described, the first region R1 of the n-type polycrystalline silicon can be deposited and doped on the intrinsic polycrystalline silicon. That is, by doping the intrinsic polycrystalline silicon there (ie, CVD deposition in a flash environment). Alternatively, the polycrystalline silicon can be first deposited on the base, and then doped with polycrystalline silicon by phosphorus or arsenic implantation to form n-type polycrystalline silicon. The basic polycrystalline silicon can be deposited first, and then doped with polycrystalline silicon by ion implantation of boron to form a p-type polycrystalline stone. Ion implantation can be performed by "bevel implantation", whereby the ion beam is incident at an angle with the axis perpendicular to the substrate. Then, a layer of dielectric 140 (such as SiO 2) can be deposited on the layer 633 to fill the via 670 and form a structure 600D as shown in FIG. 6D. Then, the structure 600D may be subjected to CMP or dry etching to flatten the upper surface, thereby removing a portion of the upper surface 633T of the layer 633 and forming a cylindrical cup-shaped conductive liner. This system is shown in FIG. 6E structure 600E, in which the conductive liner 630 has a side wall portion 630S along the side wall 128S and a bottom layer 630B along the lower surface 106. Furthermore, the conductive liner 630 has an upper edge 632. The flattening step forms a substantially flat upper edge. 632 is higher than 5 10 15 20 25 32. Please read the note on the back before filling in this page. 1. 2,000 556343 A7 V. Description of Invention (31) Good. 5 10 15 Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Affairs Co., Ltd. 20 25 After this process step, the conductive lining 630 contains only a single material area, labeled Rj in the first material area as shown in Figure 6E. The next step is to increase the resistivity of a portion of the conductive liner 630, which includes the upper edge 632 or a portion of the upper edge 632. As shown in Fig. 6F, the second region R2 having higher resistivity than the r-th region R1 is formed in the upper part of the conduction profile adjacent to the original 632 W. The second region R2 in the conduction profile can be formed by the method described above in relation to the formation of a multi-region conductive sidewall spacer. For example, the second region R2 may be formed by n-type polycrystalline silicon doped around the first region R1. In particular, the periphery of the n-type polycrystal can be doped to form a second region R2 containing the n- or P-type polycrystal. It is also possible to modify the elements in the second region by merging them with the oppositely doped ions or independently implanting them. Alternatively, the upper portion of the first region R1 can be removed (preferably by selective etching) to form a recess. This recess can then be filled with a material with a higher resistivity than R1. A material with higher resistivity. For example, the recess may be filled with a polycrystalline silicon material such as η or ρ type. Alternatively, the recess can be filled with undoped polycrystalline silicon and then doped appropriately (preferably boron, arsenic, or scale) to make it more resistive. After forming the first region R2, a memory material layer 290 and a conductive material layer (constituting a second electrical contact) 300 can be deposited. The indirect point area between the conductive lining 63 and the memory material 290 is the surface portion of the conductive lining. Most of the electrical communication is through this place (between the conductive lining and the memory material). It may be the upper edge 632 or a portion of the upper edge 632. (^ The entire upper edge is connected to the memory material, so the contact area is circular). Therefore, the memory material layer 290 and the conductive material layer 300 are only applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm 91 · 1.2, 2.0) by all or part of the paper size (please read the back first) Please note this page, please fill in this page), · ϋ ϋ ϋ —Bi 11I Therefore, one aspect of the present invention is a memory element, which includes a programmable resistive memory element (containing a programmable resistive material 5 masses) and a device for transmitting electrical signals to the memory material. Device: The device for transmitting electrical signals includes the first and second electrical contacts (or electrodes), preferably at least of the electrical contacts, which is a multi-zone contact, which includes at least a first resistivity- Region and second region R2 with a second resistivity higher than the first region R1: The second region R2 with a higher resistance 10 is adjacent to the memory material, and the first region with a lower resistivity It is better that the area R1 and the memory material are far away.-Generally, the 'multi-area contact' can be of any form. In the above specific example, The multi-zone contact is a conductive spacer type of the lining, which is adjacent to the memory material along the edge. ^ 15 More broadly, the multi-zone electrode can be a conductive material layer with any shape, conformal and actual geometry. -In a specific example, the contact layer can be perpendicular to the memory material. Although not intended to be limited by theory, the letter contact layer can be perpendicular to the memory material to increase the transmission of thermal energy to the memory material and maintain it. The effective amount. When the contact layer is perpendicular to the memory material 20, the contact area (defined by the edge of the contact layer) is smaller. It is also believed that the lower resistance material R1 (those far from the memory material) can be charged. As a heat sink, it absorbs some of the heat generated by the more resistive part R2 (near the memory material). Placing the contact layer so that it is almost perpendicular to the memory material can increase the memory material and the contact layer. Electrical 25 low resistance material Ri spacing. Therefore in the memory material or connected to it (please read the precautions on the back before filling this page)

-I · ϋ n n 1· I n n · n ·1 ϋ I n 1 I %! 經濟部智慧財產局貝工消費合作社印製-I · ϋ n n 1 · I n n · n · 1 ϋ I n 1 I%! Printed by Shelley Consumer Cooperative, Bureau of Intellectual Property, Ministry of Economic Affairs

91. 1. 2,000 556343 A7 經濟部智慧財產局昊工消費合作社印製五、發明說明（33) 近處產生之焦耳熱較少為接點層所吸收。如上述’接點層大抵上與傳導間隔物及襯墊垂直配置。如上述’其它大抵上垂直配置層之具體例可能不 5形成傳導間隔物或襯墊。亦即，可形成非共形沉積層於側壁表面之垂直層。例如：可利用氧化物間隔物形成鸯直層。接點層亦可大抵上為水平配置。圖7A所示係在基板102上形成之本發明記憶體元件7⑻具體例三維圖。記憶體元件700包含記憶體材質750體、一接點層730型式之第一電氣接點，以及一與接點層730隔離配置之第二電氣接點770。圖7B係同一記憶體元件 700之垂直橫剖切面圖。接點層73〇具與記憶體材質 750體遠離之第一區R1以及與記憶體材質75〇相鄰之第二區R2。相鄰之第二區R2的電阻率高於遠離之第一區 R1 〇在圖7A、B所示具體例中，第一接點730係大抵上與基板102水平配置之接點層730。接點層73〇沿邊與記憶體材質750相鄰。亦即，接點層730具與記憶體材質750體相鄰之邊緣732。接點層730的其它部分與記憶體材質遠離。因而接點層730與記憶體材質750 間所有的電氣通連係經邊緣732為之。因而接點層730 與記憶體材質75〇間之接點區係接點層73〇之遂線 732。（如所示，在此具體例中，此邊緣係大抵上與接底層厚度平行之表面）。接點層730與記憶體材質750 10 請先閲讀背面之注意事項再填寫本頁裝 I I I I I 訂 15 20 25 3591. 1. 2,000 556343 A7 Printed by Hao Gong Consumer Cooperative, Bureau of Intellectual Property, Ministry of Economic Affairs 5. Description of Invention (33) Joule heat generated nearby is less absorbed by the contact layer. As mentioned above, the 'contact layer is mostly arranged perpendicularly to the conductive spacer and the spacer. As mentioned above, the other specific examples of the vertically arranged layer may not form conductive spacers or spacers. That is, a non-conformally deposited vertical layer can be formed on the sidewall surface. For example, oxide spacers can be used to form a straight layer. The contact layer can also be arranged horizontally. FIG. 7A is a three-dimensional view of a specific example of a memory element 7 of the present invention formed on a substrate 102. As shown in FIG. The memory element 700 includes a memory material 750, a first electrical contact of a type of a contact layer 730, and a second electrical contact 770 disposed in a spaced-apart relation to the contact layer 730. FIG. 7B is a vertical cross-sectional view of the same memory element 700. As shown in FIG. The contact layer 73 has a first region R1 away from the memory material 750 and a second region R2 adjacent to the memory material 750. The resistivity of the adjacent second region R2 is higher than the distant first region R1. In the specific example shown in Figs. The contact layer 73 is adjacent to the memory material 750 along the edge. That is, the contact layer 730 has an edge 732 adjacent to the memory material 750. The other parts of the contact layer 730 are far away from the memory material. Therefore, all electrical connections between the contact layer 730 and the memory material 750 are connected via the edge 732. Therefore, the contact area between the contact layer 730 and the memory material 75 ° is the line 732 of the contact layer 73 °. (As shown, in this specific example, this edge is a surface that is substantially parallel to the thickness of the underlying layer). Contact layer 730 and memory material 750 10 Please read the notes on the back before filling in this page. I I I I I Order 15 20 25 35

91· 1· 2,000 % 556343 A7 經濟部智慧財產局貝工消t合作社印製五、發明說明（34) 間之接點區與接點層730之厚度成比例。邊緣732環繞於記憶體材質750艎橫剖切面較佳。此處所云之〃環繞〃係指邊緣732完全通繞於記憶體材質750體橫剖切面。然而，可將記憶體元件之結構造成其邊緣僅部分環繞於記憶體材質75〇體橫剖切面。在所示具體例中，橫剖切面大抵上與基板1〇2面平行，但若為其它幅向亦可。第二接點770可為傳導材質層，並為薄膜層較佳。在圖7A、B所示具體例中，第二接點77〇係沉積於記憶體材質750上之傳導層，使得傳導層77〇底面與記憶體材質750上表面相鄰。注意可將一或多層中間層沉積於記憶體材質與接點層間。接點層除了上述第一及第二區之外，亦可具一或多個額外區域。此額外區域可能位於接點層之任意位置。在圖8中所示係本發明之另一具體例。圖8所示之記憶體元件800第一接點83〇,其與記憶體材質85〇電氣通連。介電材質828構成溝槽或通路結構。第一接點830包含具第一電阻率之第一區R1以及具第二電阻率之第二區R2。在所示具體例令，第一接點83〇係一單層（亦及其係單一〃接點層"）。電阻率較高之第二區 R2係與記憶體材質相鄰，而電阻率較低之第一區則與記憶體材質遠離。注意在圖8所示具體例中，第一接點830間之電氣通連係經由部分接點層面，而非經由 10 15 20 25 ^ 297公釐） 91. 1. 2,000 (請先閱讀背面之注意事項再填寫本頁) •裝 « — — — — I — — . 36 556343 A7 B7 經濟部智慧財產局消費合作社印製五、發明說明（35) 接點層邊緣。第-及第二區R1及R2可自適當之接點材質形成。適當材質之示例已述之於上。在一具體例中，區R1及區R2之摻雜可相異。記憶體元件800亦包含第二接點870。在另-具體例中，第二接點870亦可為多區結構。亦即其亦可包 s至少具第-電阻率之第_區，以及具高於第一電阻率之第二電阻率的第二區。如所述，在圖1A所示具體例中，大抵上在記憶體材質290與傳導側壁間隔物13〇A、B w所有的電氣通連均係經由所有或部分邊緣132為之。因而記憶體材質290與傳導侧壁間隔物13〇A、B間接點區係至少部分傳導側壁間隔物邊緣。因此接點區非常小，並與和圮憶體材質相鄰之傳導間隔物成正比。圖丨八及1B重製如圖9A及9B。 \ 接點區可更縮減一些。在圖9A及9B中，各傳導側壁間隔物130A、B均具一大抵上均勻寬度〃w"(沿 y-軸間隔物維度方向）。為更進一步縮減在各傳導側壁間隔物130A、B與記憶體材質間之接點區，可形成之各傳導侧壁間隔物使其與記憶體材質相鄰處之寬度降低（亦即傳導間隔物變窄）。縮減與記憶體材質相鄰之側壁間隔物寬度〃 w 〃即可縮減傳導間隔物與記憶體材質間之接點區。此具體例，稱之為傳導間隔物之"減長劍没计’不如圖9C。圖9C係記憶體元件1〇〇’之橫剖面，其即以細長劍設計傳導側壁間隔物130, A、B。 5 10 15 20 25 37 (請先閲讀背面之注意事項再填寫本頁)91 · 1 · 2,000% 556343 A7 Printed by Beige Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. The description of the contact area between (34) and the thickness of the contact layer 730 is proportional. The edge 732 surrounds the cross section of the memory material 750 艎. The cloud around here means that the edge 732 completely passes through the cross section of the memory material 750. However, the structure of the memory element can be made such that its edges only partially surround the cross section of the memory material, the body. In the specific example shown, the cross-sectional plane is substantially parallel to the 102 plane of the substrate, but other width directions are also acceptable. The second contact 770 may be a conductive material layer, and is preferably a thin film layer. In the specific example shown in FIGS. 7A and B, the second contact 770 is a conductive layer deposited on the memory material 750, so that the bottom surface of the conductive layer 770 is adjacent to the upper surface of the memory material 750. Note that one or more intermediate layers can be deposited between the memory material and the contact layer. The contact layer may have one or more additional areas in addition to the first and second areas described above. This extra area may be located anywhere on the contact layer. Shown in FIG. 8 is another specific example of the present invention. The first contact 83 of the memory element 800 shown in FIG. 8 is in electrical communication with the memory material 85. The dielectric material 828 forms a trench or via structure. The first contact 830 includes a first region R1 having a first resistivity and a second region R2 having a second resistivity. In the specific example shown, the first contact 830 is a single layer (and it is a single contact layer "). The second region R2 with higher resistivity is adjacent to the memory material, while the first region with lower resistivity is away from the memory material. Note that in the specific example shown in Figure 8, the electrical connection between the first contacts 830 is through part of the contact level, not through 10 15 20 25 ^ 297 mm. 91. 1. 2,000 (Please read the note on the back first Please fill in this page again for matters) • Install «— — — — I — —. 36 556343 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (35) Edge of the contact layer. The first and second regions R1 and R2 can be formed from appropriate contact materials. Examples of suitable materials have been described above. In a specific example, the doping of the regions R1 and R2 may be different. The memory device 800 also includes a second contact 870. In another specific example, the second contact 870 may have a multi-zone structure. That is, it can also include a second region having at least a first resistivity and a second region having a second resistivity higher than the first resistivity. As described above, in the specific example shown in FIG. 1A, all the electrical connections between the memory material 290 and the conductive sidewall spacers 130A and Bw are made via all or part of the edges 132. Therefore, the indirect point area of the memory material 290 and the conductive sidewall spacers 130A, B is at least part of the edge of the conductive sidewall spacer. Therefore, the contact area is very small and proportional to the conductive spacers adjacent to the MEMS memory material. Figures 丨 8 and 1B are reproduced as shown in Figures 9A and 9B. \ The contact area can be more reduced. In FIGS. 9A and 9B, each of the conductive sidewall spacers 130A, B has a large uniform width 〃w " (along the y-axis spacer dimension direction). In order to further reduce the contact area between the conductive sidewall spacers 130A, B and the memory material, each conductive sidewall spacer can be formed to reduce the width adjacent to the memory material (that is, the conductive spacer Narrowed). By reducing the width 侧壁 w 相邻 of the sidewall spacer adjacent to the memory material, the contact area between the conductive spacer and the memory material can be reduced. This specific example, which is called " reduced length of the conductive spacer " is not calculated, is not as shown in Fig. 9C. Fig. 9C is a cross-section of a memory element 100 ', which uses a slender sword design to conduct sidewall spacers 130, A, and B. 5 10 15 20 25 37 (Please read the notes on the back before filling this page)

- — — I n I I n # ϋ n ϋ 1 I I I I —J 規格⑽ X 297公釐） 556343 A7-— — I n I I n # ϋ n ϋ 1 I I I I —J size ⑽ X 297 mm) 556343 A7

所不平面與y-z面平行。如所示，傳導側壁間隔物上緣 132已經適當姓刻，使其與記憶體材質相鄰處之寬度w 縮減。尤其是，各傳導間隔物均具適當凹處，俾形成 5與a己憶體材質相鄰之突出或加高部135。加高部135自五、發明說明（36) 經濟部智慧財產局貝工消費合作社印製凹處邊緣132’延伸，並終結於與記憶體材質相鄰之末端或上表面137。加高部135之上表面137亦稱之為加馬部之"頂端"或"峰"。g 9D係理想化之傳導間隔物 130'A、B三維表示圖，其具自邊緣132，延伸之加高 10部丨35。各加高部之上表面或頂端137之厚度為"t"且寬度為〃 w2’’。厚度〃 t 〃係與記憶體材質相鄰之傳導間隔物130’A、B厚度（未圖示）。厚度,,t"小於約75〇埃較佳’小於約500埃更佳，小於約3〇〇埃最佳。與記憶體材質相鄰之加高部135寬度〃w2〃低於與基板 15 102相鄰之側壁層i3〇’A、B寬度"wi"較佳。寬度,,w2„ 小於700埃較佳，小於600埃更佳，小於500埃最佳。厚度t、寬度w2〃以及頂端137表面區均小於顯影術所允尺寸。上表面137之維度足夠較佳，俾使加高部 135與記憶體材質間之接點區小於約〇〇〇5/^較佳，小 20 於約0.0025/^2更佳，小於約0 0015⑼2最佳。可將加高部135製為具大抵上垂直側壁（例如：大抵上均勻寬度〃w2〃及大抵上均勻厚度〃t")，或可將其製成向頂端137延伸錐（例如··錐形寬度〃w2〃及/或錐形厚度〃t〃）。概言之，加高部135之外形不僅限於任 25 意特殊外形。可能的外形示例包含圓錐形、角錐形、 (請先閲讀背面之注意事項再填寫本頁) 訂--------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 556343 A7 B7 經濟部智慧財產局貝工消費合社印製五、發明說明（37) 稜形及楔形平截頭形。加高部135可為圓柱形。加高部135之頂端137上表面大抵上可為平坦或圓形。亦可想見將末梢端或頂端137削尖。可控制加高部I% 高度及任意錐形延伸。再參閱圖9C’介電材質145位於傳導側壁層 13γ A、Β與記憶體材質間，使得僅有上表面137露出並與記憶體材質電氣接觸較佳。因而大抵上所有在各傳導層130fA、B與記憶體材質間之電氣通連至少係經加高部135之頂端137或部分上表面。各下電極 130'A、B與記憶體材質間之接點區因而以頂端137或上表面界定較佳。如所註，在本發明之一具體例中，接點區之面積小於約0.005//w2較佳，小於約〇〇〇25卿2 更佳，小於約0.0015//^2最佳。在本發明之另一具體例中，可將加高部135製為突入記憶體材質中，使得較多的加高部135表面與記憶體材質電氣接觸。注意可在各傳導層13〇'a、B之邊緣 132^上形成不只一個加高部。藉由在傳導側壁層130，A、B上形成側壁間隔物可製得加高部135，示如圖1B。尤其是，間隔物位於傳導側壁層130f A、B上方所期置放加高部135位置。間隔物可充作異向性或等向性蝕刻之罩。亦即，側壁層邊緣132露出部分將被钱除並凹陷，同時在罩下_分最終部分免於蝕刻，俾形成自凹緣延伸之加高部或突出。概言之，間隔物係做為罩，不限任何特定材質。 5 10 15 20 25 (請先閱讀背面之注意事項再填寫本頁)All planes are parallel to the y-z plane. As shown, the upper edge 132 of the conductive sidewall spacer has been appropriately scribed to reduce the width w adjacent to the memory material. In particular, each of the conductive spacers has an appropriate recess, forming a protrusion or heightened portion 135 adjacent to the material of the a body. Heightening section 135 has been printed by V. Invention Description (36) Printed by Shellfish Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs, the recessed edge 132 ′ extends and ends at the end or upper surface 137 adjacent to the memory material. The upper surface 137 of the elevated portion 135 is also referred to as the "top" or "peak" of the Canadian Department. g 9D is an idealized three-dimensional representation of 130'A, B conductive spacers, which has a height of 10 extending from the edge 132 and 35. The thickness of the upper surface or tip 137 of each elevated portion is " t " and the width is 〃w2 ''. The thickness 〃 t 〃 is the thickness of the conductive spacers 130'A, B adjacent to the memory material (not shown). The thickness is preferably less than about 75 Angstroms, more preferably less than about 500 Angstroms, and most preferably less than about 300 Angstroms. The width 〃w2 of the height portion 135 adjacent to the material of the memory is lower than the width i3 of the side wall layers i3 ′ and A & B adjacent to the substrate 15 102 " wi ". Width, w2 „is preferably less than 700 angstroms, more preferably less than 600 angstroms, and more preferably less than 500 angstroms. Thickness t, width w2〃, and top 137 surface area are smaller than the size allowed by imaging. The dimension of the upper surface 137 is sufficiently good It is better to make the contact area between the heightened portion 135 and the memory material smaller than about 0.0005 / ^, and more preferably less than 20 to about 0.0025 / ^ 2, and less than about 0 0015⑼2. The heightened portion can be increased. 135 is made with large vertical side walls (for example: large uniform width 〃w2〃 and large uniform thickness 〃t "), or it can be made into a cone extending toward the top 137 (for example, · tapered width 〃w2〃 and / Or the thickness of the cone 〃t〃). In short, the shape of the raised portion 135 is not limited to any 25 special shapes. Examples of possible shapes include cone, pyramid, (Please read the precautions on the back before filling out this Page) Order --------- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 556343 A7 B7 Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs (37) Prismatic and wedge-shaped frustum. Heightening part 135 may be cylindrical. Heightening The upper surface of the top portion 137 of the portion 135 may be flat or round. It is also conceivable to sharpen the distal end or the top portion 137. The height of the heightened portion can be controlled by 1% and any conical extension. See also Figure 9C 'Dielectric The material 145 is located between the conductive sidewall layers 13γ A, B and the memory material, so that only the upper surface 137 is exposed and is in good electrical contact with the memory material. Therefore, it is much better than all the conductive layers 130fA, B and the memory material. The electrical connection is at least through the top 137 or part of the upper surface of the elevated portion 135. The contact area between the lower electrodes 130'A, B and the memory material is therefore better defined by the top 137 or the upper surface. As noted, In a specific example of the present invention, the area of the contact area is preferably less than about 0.005 // w2, more preferably less than about 0.0025 cm2, and most preferably less than about 0.0015 // ^ 2. In another aspect of the present invention, In a specific example, the heightened portion 135 can be made to protrude into the memory material, so that more surfaces of the heightened portion 135 are in electrical contact with the memory material. Note that the edge 132 of each conductive layer 130′a, B can be ^ More than one raised portion is formed on the conductive layer 130, A, and B. The wall spacer can be made as the elevated portion 135, as shown in Figure 1B. In particular, the spacer is located on the conductive sidewall layer 130f A, B, and the elevated portion 135 is placed. The spacer can be anisotropic or equivalent. Anisotropically etched cover. That is, the exposed portion of the side wall layer edge 132 will be removed and recessed, and the final portion under the cover will be free from etching, forming a raised portion or protrusion extending from the concave edge. The spacer is used as the cover, not limited to any specific material. 5 10 15 20 25 (Please read the precautions on the back before filling this page)

-I 0 ϋ ϋ n n I n 一：OJ· ϋ ϋ ϋ n i I %! 91. 1. 2,000 39 556343 A7 - -—_ B7 經濟部智慧財產局貝工消費合作社印製五、發明說明（38) 由諸如氧化物或氮化物材質之介電材質形成經罩蓋之間隔物較佳。然而，經罩蓋之間隔物亦可由諸如多晶矽之半導體材質形成。此外，亦可由諸如鋁之導體形 5 成經罩蓋之間隔物。間隔物可由許多不同方式形成。一種用以製造圖9C之記憶體元件100'方法具體例示如圖10A-10S。首先參閱圖10A，具一基板1〇2以及沉積於基板上之介電層128,構成圖10A所示結構 1000A。介電層128可為一以CVD法沉積之介電材質，諸如二氧化矽Si〇2。參閱圖10B，接著將介電層128適當罩之並蝕刻之’俾形成介電層128中的窗口或開口。此開口露出部分基板較佳（且基板之外露部分係基板之傳導部分較佳）。在具體例中顯示結構1000B，其開孔係一與所示平面垂直之溝槽170。溝槽170具側壁表面128s(與介電層128側壁表面相對應）及底表面1〇6。一傳導材質層133經沉積於結構1000B上，形成圖 10C所示結構2〇〇c。此沉積以共形沉積較佳。層133 係沉積於介電層128之側壁表面128T上、介電層128 之側壁表面128s上，以及溝槽170之底表面1〇6上。因此部分層133係沿溝槽170之兩側壁表面128s沉積。該等部分層133係層133之側壁層部分13孔。層 133之共形沉積可利用CVD技術為之。亦可採用其它可行之沉積方法，使得層133適當覆蓋於側壁表面 25 128s 〇 10 15 20-I 0 ϋ nn nn I n One: OJ · ϋ ϋ ϋ ni I%! 91. 1. 2,000 39 556343 A7--—_ B7 Printed by Shellfish Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (38) The capped spacer is preferably formed of a dielectric material such as an oxide or nitride material. However, the spacer through the cover may also be formed of a semiconductor material such as polycrystalline silicon. Alternatively, a conductor such as aluminum may be used as a cover spacer. The spacer can be formed in many different ways. A specific example of a method for manufacturing the memory element 100 'of FIG. 9C is shown in FIGS. 10A-10S. Referring first to FIG. 10A, a substrate 102 and a dielectric layer 128 deposited on the substrate constitute a structure 1000A shown in FIG. 10A. The dielectric layer 128 may be a dielectric material deposited by a CVD method, such as silicon dioxide (SiO2). Referring to Fig. 10B, the dielectric layer 128 is then appropriately masked and etched to form a window or opening in the dielectric layer 128. It is preferable that this opening exposes part of the substrate (and the exposed part of the substrate is preferably the conductive part of the substrate). The structure 1000B is shown in the concrete example, and its opening is a groove 170 perpendicular to the plane shown. The trench 170 has a sidewall surface 128s (corresponding to the sidewall surface of the dielectric layer 128) and a bottom surface 106. A conductive material layer 133 is deposited on the structure 1000B to form the structure 200c shown in FIG. 10C. This deposition is preferably conformal. The layer 133 is deposited on the sidewall surface 128T of the dielectric layer 128, the sidewall surface 128s of the dielectric layer 128, and the bottom surface 106 of the trench 170. Therefore, part of the layer 133 is deposited along 128s of both sidewall surfaces of the trench 170. These partial layers 133 are 13 holes in the sidewall layer portion of the layer 133. The conformal deposition of layer 133 can be done using CVD techniques. Other feasible deposition methods can also be used, so that the layer 133 covers the sidewall surface properly. 25 128s 〇 10 15 20

(cns)A4 規格 S x 297公釐）(cns) A4 size S x 297 mm)

91. 1. 2,00C (請先閲讀背面之注意事項再填寫本頁)91. 1. 2,00C (Please read the notes on the back before filling this page)

-I · ϋ I ϋ ϋ 1 ff— «1 一·^· ϋ ·1 n I ϋ I %! 40 556343 A7 經濟部智慧財產局貝工消費合作社印製五、發明說明（39) 概言之，材質133可為任何傳導材質。例如：其可為金屬、金屬合金或摻雜之多晶矽。可做為層133之材質示例包含η型摻雜多晶矽、p型摻雜多晶矽、11型摻雜矽碳化物、ρ型摻雜矽碳合金及/或化合物、鈦鎢化物、鎢、鎢矽化物、鉬及鈦氮化物，但不以之為限。其它示例包含鈦碳氮化物、鈦鋁氮化物、鈦矽氮化物及碳。 η型多晶矽可將多晶矽〃在原處"沉積於溝槽17〇中形成之，其係在閃光下以CVD製程為之。或者可先沉積多晶梦’再以墙或珅摻雜於多晶梦中。可先沉積多晶矽，再以硼摻雜於多晶矽形成Ρ型摻雜多晶矽。層133厚度在約50至約1000埃較佳，而在約1〇〇至約500埃更佳。在層133經共形沉積後，接著為異向性蝕刻。異向性姓刻可移除層133大抵上水平配置部分，並留下大抵上垂直配置的部分。尤其是，異向性蝕刻可移除配置於區128之上表面128Τ上之層133大抵上水平配置部分。其亦移除沉積於溝槽170之底表面1〇,6上之層 133大抵上水平配置部分。異向性蝕刻可留下層133沿側壁表面128s共形配置之層133部分。因此異向性餘刻留下層133之側壁層部分133S。異向性蝕刻造成圖 10D所示結構200D。層133之側壁層部分133S 成傳導側壁間隔物130A、B。所形成之側壁間隔物130A、 25 B具上緣132。 5 先閲讀背面之注 10 15 20 41 項再填寫本頁 I 訂本紙張尺莩適用中國國家標準（CNS)A4規格（210 X 297公釐） 91. 1. 2,000 556343 A7 -----—--Β7 五、發明說明（40) 圖10D所示傳導側壁間隔物130A、B沿溝槽170 之y-軸維度連續延伸（亦即與圖2D所示平面垂直）。在此製程中的次一步驟係將傳導側壁間隔物130A、B 5罩之並餘刻之’俾沿記憶體陣列y-轴維度方向形成複數個個別傳導側壁間隔物。這些傳導間隔物沿記憶體陣列y_轴維度方向界定個別記憶體元件。將諸如二氧化矽之介電材質填充沉積於開孔170中及傳導側壁間隔物130A、B之上。以介電材質填充於 1〇開孔170較佳。參閱圖10E，可見將介電材質140沉積於溝槽170中，以及結構1000D之介電區128上表面之上’形成結構1000E。此沉積可利用CVD製程為之。接著可以對結構1000E施行化學機械拋光（CMP)或乾餘刻’形成如圖10F所示結構1000F。以CMP或乾 15餘刻將傳導間隔物130A、B上表面平坦化，露出至少部分兩上緣132或其中之一較佳。圖10F'所示係三維結構200F。經濟部智慧財產局貝工消贄合作社印製 (請先閲讀背面之注意事項再填寫本頁) 將第一氧化層240(例如來自TEOS源之二氧化矽）沉積於結構1000F之上表面形成如圖i〇G所示三維結 20構1000G。圖10G'係相同結構1000G平行於y_Z平面並平行於側壁間隔物13〇A、B寬度之橫剖圖。第一氧化層240之尺度為約200埃至約500埃之間較佳，為約300埃更佳。可利用CVP製程來沉積第一氧化層 24〇。接著將一多晶矽層250沉及於氧化層240上，形 25 成圖1〇H所示橫剖結構200H (平行於y-z平面）及圖 42-I · ϋ I ϋ ϋ 1 ff— «1 一 · ^ · ϋ · 1 n I ϋ I%! 40 556343 A7 Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (39) In summary, The material 133 can be any conductive material. For example, it can be a metal, a metal alloy, or doped polycrystalline silicon. Examples of materials that can be used as layer 133 include n-type doped polycrystalline silicon, p-type doped polycrystalline silicon, 11-type doped silicon carbide, p-type doped silicon-carbon alloy and / or compounds, titanium tungsten compounds, tungsten, tungsten silicide , Molybdenum and titanium nitride, but not limited to this. Other examples include titanium carbonitride, titanium aluminum nitride, titanium silicon nitride, and carbon. The n-type polycrystalline silicon can be formed in situ " deposited in the trench 17 >, which is performed by a CVD process under flash. Alternatively, polycrystalline dreams can be deposited first and then doped into the polycrystalline dreams with walls or osmium. Polycrystalline silicon can be deposited first, and then P-doped polycrystalline silicon is formed by doping polycrystalline silicon with boron. The thickness of layer 133 is preferably from about 50 to about 1000 Angstroms, and more preferably from about 100 to about 500 Angstroms. After the layer 133 is conformally deposited, it is followed by anisotropic etching. The anisotropic engravable removable layer 133 is mostly on the horizontally arranged portion, leaving a portion that is mostly on the vertical arrangement. In particular, the anisotropic etching can remove the layer 133 disposed on the surface 128T, which is the upper surface of the region 128, substantially above the horizontally disposed portion. It also removes the layer 133 deposited on the bottom surface 10,6 of the trench 170, which substantially reaches the horizontally disposed portion. The anisotropic etching may leave a portion of the layer 133 conformally arranged along the sidewall surface 128s. Therefore, the anisotropy leaves a side wall layer portion 133S of the layer 133 in a moment. Anisotropic etching results in the structure 200D shown in FIG. 10D. The side wall layer portion 133S of the layer 133 forms conductive side wall spacers 130A, B. The formed side wall spacers 130A, 25B have upper edges 132. 5 Read the note 10 15 20 41 on the back before filling in this page. I The size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 91. 1. 2,000 556343 A7 -----— --B7 V. Description of the invention (40) The conductive sidewall spacers 130A and B shown in FIG. 10D continuously extend along the y-axis dimension of the trench 170 (that is, perpendicular to the plane shown in FIG. 2D). The next step in this process is to cover the conductive sidewall spacers 130A, B 5 with the remaining '俾' along the memory array y-axis dimension to form a plurality of individual conductive sidewall spacers. These conductive spacers define individual memory elements along the y-axis dimension of the memory array. A dielectric material such as silicon dioxide is filled and deposited in the openings 170 and on the conductive sidewall spacers 130A, B. It is preferable to fill the 10 openings 170 with a dielectric material. Referring to FIG. 10E, it can be seen that a dielectric material 140 is deposited in the trench 170, and a structure 1000E is formed on the upper surface of the dielectric region 128 of the structure 1000D. This deposition can be done using a CVD process. Then, the structure 1000E can be subjected to chemical mechanical polishing (CMP) or dry-etching 'to form the structure 1000F as shown in FIG. 10F. It is preferable to planarize the upper surfaces of the conductive spacers 130A, B by CMP or dry for 15 minutes, exposing at least part of the upper edge 132 or one of them. Fig. 10F 'shows a three-dimensional structure 200F. Printed by Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Deposit the first oxide layer 240 (such as silicon dioxide from TEOS source) on the surface of the structure 1000F to form Fig. 10G shows a three-dimensional structure of 1000G. Fig. 10G 'is a cross-sectional view of the same structure 1000G parallel to the y_Z plane and parallel to the width of the side spacers 130A, B. The scale of the first oxide layer 240 is preferably between about 200 angstroms and about 500 angstroms, and more preferably about 300 angstroms. The CVP process can be used to deposit the first oxide layer 24. Next, a polycrystalline silicon layer 250 is deposited on the oxide layer 240 to form a cross-sectional structure 200H (parallel to the y-z plane) shown in FIG. 10H and FIG. 42.

91. 1. 2,000 55634391. 1. 2,000 556343

五、發明說明（41) 經濟部智慧財產局貝工消費合作社印製 1〇1^所示三維結構。層250之尺度近似1000埃較佳。接著將結構1000H罩之並蝕刻之。將一光阻材質層施於多晶矽250之上。將該光阻層適當圖樣化（亦即 5將在罩上之圖樣轉換至光阻層），並將部分光阻層移除，形成圖101所示三維光阻罩260。平行於义^平面之結構10001頂示圖示如圖101，。圖1〇1，所示係光阻罩260與傳導間隔物130A、B上緣132之相對位置。與y-z平面平行之結構10〇〇1橫剖圖示如圖ι〇ι,,。 10 接著將結構10001乾蝕刻，俾移除未受光阻罩260 保護之部分多晶石夕層250,藉此形成圖1〇J所示結構 1000J。所採用之蝕刻對氧化層240具選擇性。此蝕刻形成多晶矽層250中的側壁表面252。接著將光阻26〇自結構1000J剝除，形成圖10κ所示結構1〇〇〇κ。 15 接著將第二氧化層27G (諸如二氧化碎）沉積於結構1000K上，形成圖10L所示結構1〇〇〇L。所沉積之層270厚度約為_埃較佳。將第二氧化層27〇沉積於多晶石夕層250之上水平表面，以及第一氧化層24〇之暴硌邛刀之上。亦沿多晶石夕層25〇之側壁表面 20 /儿積之。接著對氧化層27G異向性餘刻，移除第二氧化層270之水平配置部分，並留下沿側壁表面252之垂直配置部分270A。所得結構示如圖讀之結構 1000M。氧化層270的剩餘部分係部位27〇A。部位2+〇A 係為側壁間隔物。 25 接著將圖10M*示之多晶矽層250剩餘部分移 43 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (41) The three-dimensional structure shown by 010 ^ was printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The scale of layer 250 is preferably approximately 1000 angstroms. The structure 1000H is then masked and etched. A photoresist material layer is applied on the polycrystalline silicon 250. The photoresist layer is appropriately patterned (that is, the pattern on the cover is converted to the photoresist layer), and a part of the photoresist layer is removed to form a three-dimensional photoresist cover 260 shown in FIG. 101. The top view of the structure 10001 parallel to the meaning plane is shown in Fig. 101. Fig. 101 shows the relative positions of the photoresist cover 260 and the upper edges 132 of the conductive spacers 130A and B. A cross-sectional view of the structure 001 parallel to the y-z plane is shown in Figure ι. 10 Next, the structure 10001 is dry-etched to remove a part of the polycrystalline stone layer 250 that is not protected by the photoresist mask 260, thereby forming the structure 1000J shown in FIG. 10J. The etching used is selective for the oxide layer 240. This etch forms a sidewall surface 252 in the polycrystalline silicon layer 250. Next, the photoresist 26 is stripped from the structure 1000J to form the structure 1000κ shown in FIG. 10κ. 15 Next, a second oxide layer 27G (such as crushed dioxide) is deposited on the structure 1000K to form a structure 1000L as shown in FIG. 10L. The thickness of the deposited layer 270 is preferably about Angstroms. A second oxide layer 270 is deposited on the horizontal surface above the polycrystalline stone layer 250 and on the burr blade of the first oxide layer 24. Also along the surface of the side wall of the polycrystalline stone layer 20/20. Next, the anisotropy of the oxide layer 27G is removed, and the horizontally disposed portion of the second oxide layer 270 is removed, leaving a vertically disposed portion 270A along the sidewall surface 252. The resulting structure is shown as read structure 1000M. The remaining portion of the oxide layer 270 is a portion 270A. Site 2 + OA is a side wall spacer. 25 Next, move the remaining part of the polycrystalline silicon layer 250 shown in Figure 10M *. 43 This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) (Please read the precautions on the back before filling this page)

91. 1. 2,000 556343 A7 經濟部智慧財產局消費合作社印製五、發明說明（42) 除利用夕曰日發乾姓刻為之較佳。亦可利用濕多晶石夕蝕刻為之。所得結構示如圖_之結構1〇眶。之後結構Η)00Ν經異向性侧，移除部分未為間隔物 270A 5覆蓋之部》第-氧化層24G，留下氧化間隔物27〇B，如圖1〇〇所示結構10_。三維結構1〇〇〇〇示如圖 1〇屮。氧化間隔物270B之頂示圖（於x_y平面平行: 以及其與傳導層13GA、B之上表面132的相對位置牙如圖100"。如所示，間隔物270B覆於部分側壁間隔物130A、B露出邊緣132之上。氧化物間隔物27〇£ 之”厚度’’（亦即間隔物在y-軸上之橫向尺寸）低於顯影法所能實現之尺寸較佳（亦即低於顯影術極限）。在一具體例中，氧化物間隔物270B之厚度低於1〇〇〇埃較佳。在另一具體例中，氧化物間隔物厚度低於7〇( 埃較佳，低於600埃更佳，低於約5〇〇埃最佳。以氧化物間隔物270B為罩，接著兹刻傳導層，移除部分傳導層130A、B，形成在間隔物270B下之加高部。參閱圖10P，至少部分未為氧化物間隔物27〇B所覆蓋之傳導側壁被蝕刻移除掉，形成凹緣132。然而，至少部分為氧化物間隔物270B所覆蓋之傳導側壁至少部分免於被蝕刻而形成自凹緣向上延伸之加高部 135。圖10P'係與y-z面平行之凹傳導層13〇，a、b橫剖圖。可利用如施蝕刻或乾蝕刻執行蝕刻。採用^如電漿蝕刻之乾蝕刻較佳。此蝕刻為異向性，俾形成具大抵上俾值側壁之加高部135較佳。然而，可利用異 10 15 20 25 91. 1· 2,000 (請先閲讀背面之注意事項再填寫本頁) · 1111111 訂------111- 44 556343 經濟部智慧財產局貝工消费合作社印製 A7 B7 五、發明說明（43) 向性蝕刻移除部分在間隔物下之傳導材質，並形成具斜或楔形側壁之加高部。因而加高部135可為楔形（楔形程度係受控於所採用之蝕刻製程）。加高部135之高 5 度約為500埃至2500埃較佳。接著利用習知的沉積方法（諸如CVD)將一介電材質層145(諸如二氧化矽）沉積於結構2〇〇p上較佳，形成圖10Q所示結構l〇〇〇Q。將材質沉積於凹處138 中、凹緣上及至少部分加高部之上。接著可對介電材 10質I45及氧化物間隔物270B施以CMP，俾露出至少部分各加尚部135之上表面或尖端137，形成如圖1〇R 所示結構1〇〇〇尺。（當然其可能僅露出部分尖端137之一）。記憶體材質層290及第二電氣接點3〇〇 (亦即上電極）係沉積於圖10R所示結構上，形成圖1〇s所示 15 記憶體元件。、注意經CMP後形成圖10R所示結構2〇〇R(並在記憶體材質沉積前），視需要可在結構1〇〇R之上形成障壁層。（因而在加高部尖端（或上表面）137與記憶體材質間形成障壁材質）。可選擇障壁層材質，使得記憶 20體材質間之傳導率增加，及/或改善電氣接點與記憶體材質間的黏著度，及/或避免電氣接點材質電游移至記憶體材質中。特定的障壁層材質示例包含鈦梦化物、始石夕化物及鶴石夕化物，但不以之為限。 4 在參閱圖10P及10P…再注意钱刻傳導側壁層形 25成窄凹處138，其中傳導層不位在氧化物間隔物2· (請先閲讀背面之注意事項再填寫本頁)91. 1. 2,000 556343 A7 Printed by the Consumer Affairs Cooperative of the Intellectual Property Agency of the Ministry of Economic Affairs 5. Description of the invention (42) It is better to use the engraved name of Xigan Rifa. It can also be etched using wet polycrystalline stones. The resulting structure is shown in Figure 10, orbital. After the structure i) 00N passes through the anisotropic side, the part that is not covered by the spacer 270A 5 is removed-the 24th oxide layer 24G, leaving the oxide spacer 27OB, as shown in the structure 10_ shown in FIG. 100. The three-dimensional structure 100000 is shown in FIG. Top view of the oxidized spacer 270B (parallel to the x_y plane: and its relative position with the upper surface 132 of the conductive layer 13GA, B is shown in Figure 100). As shown, the spacer 270B covers part of the sidewall spacer 130A, B is exposed above the edge 132. The "thickness" of the oxide spacers of 27 ° (that is, the lateral dimension of the spacers on the y-axis) is lower than the size that can be achieved by the development method (that is, less than the development Operating limit). In a specific example, the thickness of the oxide spacer 270B is preferably less than 1000 angstroms. In another specific example, the thickness of the oxide spacer is less than 70 angstroms (preferably, less than 600 angstroms is more preferable, and less than about 500 angstroms is the best. The oxide spacer 270B is used as a cover, and then the conductive layer is etched, and a part of the conductive layers 130A and B is removed to form an elevated portion under the spacer 270B. Referring to FIG. 10P, at least a portion of the conductive sidewall not covered by the oxide spacer 270B is removed by etching to form a recessed edge 132. However, the conductive sidewall covered at least partially by the oxide spacer 270B is at least partially exempted. It is etched to form a raised portion 135 extending upward from the concave edge. FIG. 10 P 'is a cross-sectional view of the concave conductive layer 13a, a, b parallel to the yz plane. Etching or dry etching can be used to perform the etching. Dry etching using plasma etching is preferred. This etching is anisotropic It is better to form a heightened portion 135 with a large upper side wall. However, you can use different 10 15 20 25 91. 1 · 2,000 (Please read the precautions on the back before filling this page) · 1111111 Order --- --- 111- 44 556343 Printed by A7 B7, Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (43) The conductive material under the spacer is removed by etched etching, and a sloped or wedge-shaped sidewall is added. The elevated portion 135 may be wedge-shaped (the degree of wedge shape is controlled by the etching process used). The height of the elevated portion 135 is preferably about 500 Angstroms to 2500 Angstroms. Then, the conventional deposition method is used. (Such as CVD) It is better to deposit a dielectric material layer 145 (such as silicon dioxide) on the structure 2000p to form the structure 1000Q shown in FIG. 10Q. The material is deposited in the recess 138, the recess On the edge and above at least part of the elevation. Next, dielectric material 10 quality I45 and oxide spacer 270B can be applied. Use CMP to expose at least part of the upper surface or tip 137 of each Kashang part 135 to form a structure of 1000 feet as shown in FIG. 10R. (Of course, it may only expose one of the tips 137.) Memory material The layer 290 and the second electrical contact 300 (ie, the upper electrode) are deposited on the structure shown in FIG. 10R to form the 15 memory element shown in FIG. 10s. Note that the structure shown in FIG. 10R is formed after CMP. 200R (and before the memory material is deposited), if necessary, a barrier layer can be formed on the structure 100R. (Therefore, a barrier material is formed between the tip (or upper surface) 137 of the elevated portion and the memory material). The barrier layer material can be selected to increase the conductivity between the memory 20 materials, and / or to improve the adhesion between the electrical contacts and the memory material, and / or to prevent the electrical contact materials from moving to the memory material. Examples of specific materials for the barrier layer include, but are not limited to, titanium dream compounds, starting stone compounds, and crane stone compounds. 4 Refer to Figures 10P and 10P ... and note that the conductive sidewall layer 25 is carved into a narrow recess 138, where the conductive layer is not located on the oxide spacer 2. (Please read the precautions on the back before filling this page)

556343 經濟部智慧財產局員工消费合作社印製 A7 __B7_ _ 五、發明說明（44) 下方。經蝕刻傳導層形成凹處後，接著可期蝕刻氧化區128及140周邊，其钱刻程度與經沉積介電層145 前之凹緣132’相同（如圖2Q所示）。此舉將可消除以 5 介電層145填充窄凹處138之需求。此舉亦可使後續之CMP製程步驟簡單些（得到圖10R所示結構）。 •如上述，可以氧化物間隔物製成加高部135。如上述，可採用其它材質形成間隔物。在本發明之另一具體例中，亦可以氮化物間隔物製成加高部，其中以自 1〇矽氮化物形成較佳。參閱圖10G至10L，可以第一矽氮化物層取代第一氧化層240、以氧化層（諸如來自 TEOS源之二氧化矽）取代多晶矽層250以及以第二矽氮化物層取代第二氧化層270而形成氮化物間隔物。以對下方矽氮化物材質具選擇性之氧化物蝕刻取代多 15 晶矽蝕刻（用以蝕刻圖10J及10N所示多晶矽250)。類似地，以矽氮化物蝕刻取代氧化物蝕刻（用以蝕刻圖10M及1〇〇所示氧化層異向性蝕刻）。更廣義地說，所揭用以在傳導材質上形成加高部之技術不應受限於此處所揭之具體例。可利用諸多不同 20 技術形成間隔物。以可以諸多不同材質形成間隔物，包含介電質（例如氧化物及氮化物）、半導體材質（諸如多晶矽）及導體（諸如鋁）。類似地，對層24〇、250、 260及270所選材質（如圖10G至100所示製成步k) 不以具體例為限，各層可採用多種材質。對各層所選 25之特殊材質以選擇在各式蝕刻製程時，具適當選擇 46 ^紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） ---{ 2>〇〇 (請先閲讀背面之注意事項再填寫本頁)556343 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7_ _ V. Description of Invention (44). After the recess is formed by etching the conductive layer, the periphery of the oxidized regions 128 and 140 may be etched to the same extent as the recess 132 ′ before the dielectric layer 145 is deposited (as shown in FIG. 2Q). This will eliminate the need to fill the narrow recesses 138 with 5 dielectric layers 145. This can also make subsequent CMP process steps simpler (get the structure shown in Figure 10R). As described above, the raised portion 135 can be made of an oxide spacer. As mentioned above, other materials may be used to form the spacer. In another specific example of the present invention, the nitride spacer can also be used to form the elevated portion, and it is preferable to form it from 10 silicon nitride. 10G to 10L, the first oxide layer 240 may be replaced by a first silicon nitride layer, the polycrystalline silicon layer 250 may be replaced by an oxide layer (such as silicon dioxide from a TEOS source), and the second oxide layer may be replaced by a second silicon nitride layer 270 to form nitride spacers. The poly 15 silicon etch is replaced by a selective oxide etch for the underlying silicon nitride material (to etch the poly silicon 250 shown in Figures 10J and 10N). Similarly, a silicon nitride etch is used instead of an oxide etch (to etch the oxide anisotropic etch shown in Figures 10M and 100). In a broader sense, the techniques disclosed for forming elevated sections on conductive materials should not be limited to the specific examples disclosed herein. Spacers can be formed using a number of different technologies. Spacers can be formed from many different materials, including dielectrics (such as oxides and nitrides), semiconductor materials (such as polycrystalline silicon), and conductors (such as aluminum). Similarly, the materials selected for layers 240, 250, 260, and 270 (step k as shown in FIGS. 10G to 100) are not limited to specific examples, and each layer may use multiple materials. For each layer, 25 special materials are selected to select 46. ^ Paper size is applicable to China National Standard (CNS) A4 specifications (21〇X 297 mm) --- {2 > 〇〇 ( (Please read the notes on the back before filling out this page)

556343 A7 經濟部智慧財產局員工消費合作社印製發明說明（45) 性，並可為熟悉此技藝者瞭解者較佳如所述，可以任何傳導材質形成加高部或突出及剩下的傳導層。材質示例包含n型摻雜多晶矽、p型摻雜多晶矽、η型摻雜矽碳化物、p型摻雜矽碳合金及/或化合物、η型摻雜矽碳合金及/或化合物、鈦鎢化物、鎢、鎢矽化物、鉬及鈦氮化物，但不以之為限。其它示例包含鈦奴氮化物、鈦銘氮化物、鈦梦氮化物及碳。現參閱圖11，可見具加高部135之電極結構，其可形成具第一區R1以及電阻率高於第一區R1電阻率之第二區R2。如所示，較高電阻性之第二區R2與記憶體材質相鄰，電阻性較低之第—區R1則遠離記憶體材質。在圖10S所示記憶體元件具體例中，加高部135自傳導層130’A、B邊緣延伸。在所示示例、中，傳導層大抵上係-平面，側壁石夕沿溝槽之側壁表面形成，其係藉由沉積-層傳導材質於溝槽中，接著以異向性餘刻移除水平配置表面為之。更廣義地說，可在具任意實際幾何之純傳導材質上形成加高部。尤其是，可在具任意實際幾何之人和傳導層邊緣上形成加高部或突出。傳導側壁層之另一型式的製造’可將傳導材質共形沉積於具各式外形及組恶之側壁表面上。例如：可將一層傳導材質大滅上共形沉積於開孔（諸如通路）之側壁表面、臺或桂。該孔、臺或柱可為圓形、正方形、矩形或不規則形（類 5 10 15 20 25 (請先閱讀背面之注意事項再填寫本頁)556343 A7 Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives printed the description of the invention (45), and can be familiar to those skilled in the art. As mentioned, any conductive material can be used to form an elevated part or a protrusion and the remaining conductive layer. . Examples of materials include n-doped polycrystalline silicon, p-doped polycrystalline silicon, n-doped silicon carbide, p-doped silicon-carbon alloy and / or compound, n-doped silicon-carbon alloy and / or compound, titanium tungsten compound , Tungsten, tungsten silicide, molybdenum, and titanium nitride, but not limited thereto. Other examples include titanium nitride, titanium nitride, titanium dream nitride, and carbon. Referring now to Fig. 11, it can be seen that the electrode structure with the elevated portion 135 can form a second region R1 having a first region R1 and a resistivity higher than that of the first region R1. As shown, the second region R2 with higher resistance is adjacent to the memory material, and the second region R1 with lower resistance is far away from the memory material. In the specific example of the memory element shown in Fig. 10S, the elevated portion 135 extends from the edges of the conductive layers 130'A and B. In the example shown, the conductive layer is substantially above the system-plane, and the side wall stone is formed along the surface of the side wall of the trench, which is deposited by the layer-conducting material in the trench, and then the level is removed with anisotropy. Configure the surface for this. More broadly, the elevation can be formed on a purely conductive material with any actual geometry. In particular, elevations or protrusions can be formed on people with any actual geometry and on the edges of the conductive layer. Another type of manufacturing of the conductive sidewall layer 'can deposit the conductive material conformally on the surface of the sidewall with various shapes and groups of evils. For example, a layer of conductive material can be conformally deposited on the side wall surface, platform, or cascade of an opening (such as a via). The hole, table or column can be round, square, rectangular or irregular (Class 5 10 15 20 25 (Please read the notes on the back before filling this page)

91. 1. 2,0〇〇 556343 A7 B7 經濟部智慧財產局貝工消費合作社印製五、發明說明（46) 似地，該開孔可為一溝槽）。異向性钱刻該共形沉積傳導層，移除沉積層之水平配置部分，而僅留下一或多個垂直配置部分。剩下的一或多個垂直配置部分係以 5 傳導側壁間隔物型式存在之側壁層。圖12A係圖3A圓柱形傳導侧壁間隔物33〇三維圖式♦。間隔物330係在圓形開孔中形成（並因而具環形水平橫剖面）。可將加高部或突出形成於圓柱形側壁層的環形邊緣之上。圖12B係圓柱形傳導側壁間隔物33〇,之三維圖，其包含自邊緣332,延伸之加高部或突出335。各加高部335自邊緣332'延伸至與記憶體材質相鄰之末梢或尖端337 (未圖示）。如所註，加高部％$不限定為任何特定外形。在所示具體例中，加高部335具厚度t (比例於傳導層厚度）及寬度〃 w〃a傳導層wo, 係為圓柱傳導間隔物型式。可利用如前述之氧化物間隔物或氮化物間隔物，將加高部形成於圓柱形傳導間隔物330'上緣。將加高部形成於圓柱形側壁層之環形緣上示例將述之如次。大抵上所有在傳導間隔物33〇, 與s己憶體材質間之電氣通連係經由一或多個加高部 335較佳。大抵上所有在傳導間隔物33〇，與記憶體材質間之電氣通連係經由一或多個與記憶體材質相鄰之加高部335上表面或尖端337，而大抵上所#電氣义點的剩下部分遠離記憶體材質更佳。圖12C係平行於x-z平面之圓柱形傳導層33〇，二 10 20 2591. 1.2, 〇 00 556 343 A7 B7 Printed by the Shell and Consumer Cooperatives of the Intellectual Property Agency of the Ministry of Economic Affairs V. Description of the invention (46) Similarly, the opening may be a groove). The anisotropic coin engraved the conformal deposition conductive layer, removing the horizontally disposed portion of the deposited layer, leaving only one or more vertically disposed portions. The remaining one or more vertically arranged sidewall layers are in the form of 5-conducting sidewall spacers. Fig. 12A is a three-dimensional view of the cylindrical conductive sidewall spacer 3330 of Fig. 3A. The spacer 330 is formed in a circular opening (and thus has a circular horizontal cross section). Elevations or protrusions may be formed on the annular edges of the cylindrical sidewall layer. FIG. 12B is a three-dimensional view of a cylindrical conductive sidewall spacer 33o, which includes a raised portion or protrusion 335 extending from the edge 332 ,. Each elevated portion 335 extends from the edge 332 'to a tip or tip 337 (not shown) adjacent to the memory material. As noted, the height increase% $ is not limited to any particular shape. In the specific example shown, the heightened portion 335 has a thickness t (proportional to the thickness of the conductive layer) and a width 〃 w〃a of the conductive layer wo, which is a cylindrical conductive spacer type. The elevated portion can be formed on the upper edge of the cylindrical conductive spacer 330 'using the oxide spacer or nitride spacer as described above. An example of forming the raised portion on the annular edge of the cylindrical side wall layer is as follows. Most preferably, all the electrical communication between the conductive spacer 33 and the material of the memory body is better via one or more elevated portions 335. Most of all the electrical communication between the conductive spacer 33 and the memory material is via the upper surface or tip 337 of the elevated portion 335 adjacent to the memory material, and the upper part of the # 电义点的It is better to leave the rest away from the memory. Fig. 12C is a cylindrical conductive layer parallel to the x-z plane.

91. 1. 2,000 (請先閲讀背面之注意事項再填寫本頁)91. 1. 2,000 (Please read the notes on the back before filling this page)

556343 經濟部智慧財產局員工消費合作社印製五、發明說明（47 ) 維側視圖，所示係記憶體材質290及上電氣接點300 (亦含絕緣材質128、140及180)。在圖12C中，兩加高部335均與記憶體材質電氣通連。然而，亦可能加 5 高部335均與記憶體材質之相對位置使得僅有突出335 之一與記憶體材質相接6在圖12C所示具體例中，僅有上表面或尖端337與記憶體材質相鄰，而電氣接點的其它部分則遠離記憶體材質。亦可在傳導襯裡上形成加高部，諸如圖4A至4C 所示傳導襯裡。圖5A及5B所繪係記憶體元件具體例，其中下電氣接點係在圓形開孔中形成之傳導襯裡630。圖13A 及13B係圖5A及5B之傳導襯裡。圖13A係記憶體元件之三維圖，而圖13B則係平行於χ-ζ平面之橫剖圖。如所述，可在傳導襯裡側壁部上緣形成一或多個加向部或突出。圖13C所示係配置於基板1〇2上之圓柱形傳導襯裡630’。在此具體例中，傳導襯裡63〇,包含至少一加高部635。各加高部均自上緣632,延伸至與記憶體材質（圖中未示出此記憶體材質）相鄰之末端或尖端637 (亦可稱之為上表面）。在所示具體例中，加冋部635各具厚度〃t"(大抵上與剩餘之傳導襯裡 630<厚度相同）及寬度〃w 〃。大抵上所有在傳導襯裡 630與§己憶體材質間之電氣通連係經由一或多個*高部635較佳。大抵上所有在傳導襯裡63〇，與記憶體材質間之電氣通連係經由一或多個加高部635上表面或 10 15 20 25 規格⑽： 297公釐） 91. 1. 2,000 (請先閲讀背面之注意事項再填寫本頁)556343 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (47) A side view showing the memory material 290 and the upper electrical contact 300 (also including insulation materials 128, 140, and 180). In FIG. 12C, both the heightened portions 335 are electrically connected to the memory material. However, it is also possible to add 5 the relative positions of the high portion 335 and the memory material so that only one of the protrusions 335 is in contact with the memory material. 6 In the specific example shown in FIG. 12C, only the upper surface or the tip 337 and the memory are The materials are adjacent, while the rest of the electrical contacts are far away from the memory material. Elevations can also be formed on conductive liners, such as the conductive liners shown in Figures 4A to 4C. 5A and 5B are specific examples of the memory device. The lower electrical contact is a conductive liner 630 formed in a circular opening. Figures 13A and 13B are the conductive liners of Figures 5A and 5B. FIG. 13A is a three-dimensional view of the memory element, and FIG. 13B is a cross-sectional view parallel to the χ-ζ plane. As described, one or more directional portions or protrusions may be formed on the upper edge of the side wall portion of the conductive liner. 13C shows a cylindrical conductive liner 630 'disposed on a substrate 102. As shown in FIG. In this specific example, the conductive lining 63, including at least one raised portion 635. Each elevated portion extends from the upper edge 632 to the end or tip 637 (also referred to as the upper surface) adjacent to the memory material (the memory material is not shown in the figure). In the specific example shown, each of the reinforced portions 635 has a thickness 〃t " (mostly the same as the remaining conductive lining 630 < thickness) and a width 〃w 〃. Most preferably, all electrical connections between the conductive lining 630 and the 己 memory body material are preferably via one or more * high portions 635. Most probably all the electrical communication between the conductive lining 63 and the memory material is via the upper surface of one or more elevations 635 or 10 15 20 25 Specification ⑽: 297 mm) 91. 1. 2,000 (Please read first (Notes on the back then fill out this page)

556343 A7 -—_ B7 五、發明說明（48 ) (請先閱讀背面之注意事項再填寫本頁) 尖端637更佳。因而電氣接點630'與記憶體材質之放置’使得僅有一或多個加高部635上表面637與記憶體材質相鄰，而大抵上所有的電氣接點剩下部分均遠 5 離記憶體材質。圖13D所示係與\_：2面平行之記憶體元件側視圖，其採用傳導襯裡630’。所示係記憶體材質290及第二電氣接點300。在圖13D中，兩加高部635均與記憶體材質電氣通連。然而，亦可能記憶體材質之置放使得 10僅有加高部635之一的上表面335之一與之電氣相接。傳導襯裡630'之基底與基板1〇2相鄰並電氣通連。可利用上述側壁間隔物形成加高部635。可以如氧化物或矽氮化物形成側壁間隔物。一種用以製造傳導襯裡630f之方法具體例示如圖14A-14S，。首先參閱圖 15 14A，具一基板1〇2以及沉積於基板上之介電層128，經濟部智慧財產局貝工消费合作社印製介電層128可為一以CVD法沉積，自二氧化梦形成之介電材質。接著將介電層128適當罩之並餘刻之，俾形成介電層128中開孔610型式之窗口或開口，如所示。此開孔可為圓形、正方形、矩形或不規則形。或 20者，亦可將將介電層128罩之並蝕刻之，形成溝槽。此開孔（或溝槽）穿經介電層128至基板1〇2較佳。在圖14A所示具體例中，所得結構14〇〇A係在介電層 128形成之圓形開孔610。圖14B係圖14A所示“構 1400A橫剖圖（平行於y-z面）。圓形開孔61〇之側壁 25表面128s及底表面106示如圖14B。開孔以能至少露 91. 1. 2,000 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）經濟部智慧財產局員工消費合作社印製 556343 A7 ------- 五、發明說明（49) 出部分基板較佳。一傳導材質層633經沉積於圖14A及14B所示結構上’形成圖14C所示結構600C。傳導材質層633係 5以共形沉積於介電區128之側壁表面128T上、區128 之側壁表面128s上，以及開孔640之底表面1〇6上。因此部分層633具上部633T、側壁層部633S及底層部 633B 〇556343 A7 ---_ B7 V. Description of the invention (48) (Please read the precautions on the back before filling this page) Tip 637 is better. Therefore, the placement of the electrical contacts 630 'and the material of the memory' makes only one or more of the upper surface 637 of the elevated portion 635 adjacent to the material of the memory, and most of the remaining electrical contacts are far away from the memory 5 Material. FIG. 13D is a side view of the memory element parallel to the _: 2 plane, which uses a conductive liner 630 '. Shown is a memory material 290 and a second electrical contact 300. In FIG. 13D, the two elevated portions 635 are electrically connected to the memory material. However, it is also possible that the memory material is placed so that only one of the upper surfaces 335 of one of the raised portions 635 is in electrical contact with it. The substrate of the conductive liner 630 'is adjacent to the substrate 102 and is in electrical communication. The above-mentioned sidewall spacers can be used to form the raised portion 635. The sidewall spacers can be formed such as oxides or silicon nitrides. A specific example of a method for manufacturing a conductive liner 630f is shown in Figs. 14A-14S. First, referring to FIGS. 15 and 14A, a substrate 102 and a dielectric layer 128 deposited on the substrate. The dielectric layer 128 printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs can be deposited by a CVD method. The formed dielectric material. Next, the dielectric layer 128 is appropriately covered and left for a while, to form a window or opening of the type 610 in the dielectric layer 128, as shown. This opening can be circular, square, rectangular or irregular. Alternatively, the dielectric layer 128 may be covered and etched to form a trench. This opening (or trench) preferably passes through the dielectric layer 128 to the substrate 102. In the specific example shown in FIG. 14A, the obtained structure 1OOA is a circular opening 610 formed in the dielectric layer 128. FIG. 14B is a cross-sectional view of the structure 1400A (parallel to the yz plane) shown in FIG. 14A. The side wall 25 surface 128s and the bottom surface 106 of the circular opening 61 are shown in FIG. 14B. 2,000 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 556343 A7 ------- V. Description of the invention (49) A conductive material layer 633 is deposited on the structure shown in FIGS. 14A and 14B to form the structure 600C shown in FIG. 14C. The conductive material layer 633 is deposited conformally on the sidewall surface 128T of the dielectric region 128 and the region 128. On the sidewall surface 128s and the bottom surface 106 of the opening 640. Therefore, the partial layer 633 has an upper portion 633T, a sidewall layer portion 633S, and a bottom portion 633B.

接著將一層介電質140 (諸如二氧化矽）沉積於層 10 633之上’俾填充開孔610,形成圖14D所示結構1400D 較佳。接著可對結構1400D施以CMP或乾蝕刻，俾將上表面平坦化，藉此移除部分層14〇及層633之上層部633T。此蝕刻形成圓柱杯形傳導襯裡63(),其具沿侧壁128S之側壁層部630S，並具沿下表面1〇6之底層 15部630B，示如圖6E。在具體例中所示上緣、632為環形。平坦化步驟形成大抵上平坦之上緣632較佳。圓14E, 所示係圖14E所示結構1400E三維圖。可在緣632上形成一或多個加高部或突出。用以形成自傳導襯裡上緣延伸之加高部的製程步驟與上述之 20傳導側壁間隔物相關者類似。將第一氧化層640沉積於傳導襯裡600E之上，形成圖14F所示結構H〇〇F三維圖，以及圖14Ff之橫剖圖（平行於y-z平面）。將一多晶梦層650沉積於第一氧化層640上，形成圖Ag 及14G’所示結構1400G。將一光阻層施於多晶梦層650 25之上，並適當圖樣化形成圖14H所示光阻罩660。光阻 51 本紙^甲國國家標準（CNS)A4規格（210 X 297公楚） (請先閲讀背面之注意事項再填寫本頁)Next, a layer of dielectric 140 (such as silicon dioxide) is deposited on the layer 10 633 'to fill the opening 610 to form the structure 1400D shown in FIG. 14D. Then, the structure 1400D may be subjected to CMP or dry etching to flatten the upper surface, thereby removing a portion of the layer 140 and the layer 633T above the layer 633. This etching forms a cylindrical cup-shaped conductive lining 63 () having a side wall layer portion 630S along the side wall 128S and a bottom layer 630B along the bottom surface 106, as shown in Fig. 6E. In the specific example, the upper edge 632 is shown in a ring shape. The planarization step preferably forms a substantially flat upper edge 632. Circle 14E, shown is a three-dimensional view of the structure 1400E shown in FIG. 14E. One or more raised portions or protrusions may be formed on the edge 632. The process steps used to form the raised portion extending from the upper edge of the conductive liner are similar to those described above for the 20 conductive sidewall spacers. A first oxide layer 640 is deposited on the conductive liner 600E to form a three-dimensional view of the structure H0F shown in FIG. 14F and a cross-sectional view (parallel to the y-z plane) of FIG. 14Ff. A polycrystalline dream layer 650 is deposited on the first oxide layer 640 to form a structure 1400G shown in Figs. Ag and 14G '. A photoresist layer is applied on the polycrystalline dream layer 650 25 and patterned to form a photoresist mask 660 as shown in FIG. 14H. Photoresist 51 Paper ^ National Standard A (CNS) A4 (210 X 297 cm) (Please read the precautions on the back before filling this page)

556343 A7556343 A7

經濟部智慧財產局員工消費合作社印製五、發明說明（5〇) 罩660與傳導杯630之環形緣的相對位置示如圖 14H’。橫剖圖（平行於y-z平面）示如圖14H„。將多晶石夕層650適當圖樣化並餘刻形成在層65〇中的側壁 5表面652，示如圖MI之結構14001。將第二氧化層67〇共形沉積於多晶石夕層650剩餘部分之上表面及側壁表面石52，以及第一氧化層650之上表面，示如圖14K。接著以對氧化層670之異向性蝕刻移除第二氧化層67〇之水平配置部分，並留下沿多晶矽層650側壁表面之垂直配置部分670Α車父佳’不如圖14L。接著移除多晶石夕層650剩餘部分’示如圖14M。剩餘的氧化層64〇及氧化物部6A接著經異向性蝕刻移除部分未為氧化物間隔物670A覆蓋之氧化層640。剩下部分係圖14n(平行於y-z平面）及14N,(三維圖）所示氧化物間隔物 670B。圖14N〃係結構600N在平行於x_y、面之頂示圖。如圖14N"所示’氧化物間隔物670B係在部分上緣632 上。接著以氧化物間隔物670B為罩，蝕刻傳導層630 形成一或多個在間隔物下方之加高部。參閱圖丨4〇,至邵部分未為間隔物覆蓋之傳導層被蝕除，形成凹緣 632<。然而，至少部分為氧化物間隔物67〇b至少部分免於被餘刻，形成自凹緣向上延伸之凹部635。經餘刻之傳導杯630’側視圖（平行於y-z平面）具凹緣及加高部635,示如圖6Ρ。凹處638係氧化物材質128、 Μ0間因蝕刻傳導襯裡63〇形成之間隙。如所述，此蝕 10 15 20 25 (請先閱讀背面之注意事項再填寫本頁) i · I I I I I I I ·1111111··Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (50) The relative position of the annular edge of the cover 660 and the conductive cup 630 is shown in Fig. 14H '. The cross-sectional view (parallel to the yz plane) is shown in Fig. 14H ". The polycrystalline stone layer 650 is appropriately patterned and formed on the side wall 5 surface 652 in the layer 650, as shown in the structure 14001 of Fig. MI. An oxide layer 67 ° is conformally deposited on the upper surface of the remaining polycrystalline stone layer 650 and the surface 52 of the sidewall, and on the upper surface of the first oxide layer 650, as shown in Figure 14K. Next, the anisotropy of the oxide layer 670 is shown. The horizontally etched portion of the second oxide layer 67 is removed by an etching process, and a vertical arrangement portion 670A of the polycrystalline silicon layer 650 is left. This is not shown in FIG. 14L. Then, the remaining portion of the polycrystalline silicon layer 650 is removed. As shown in Figure 14M. The remaining oxide layer 64 and the oxide portion 6A are then anisotropically etched to remove a portion of the oxide layer 640 that is not covered by the oxide spacer 670A. The remaining portion is shown in Figure 14n (parallel to the yz plane) and 14N, (three-dimensional view) oxide spacer 670B. Fig. 14N is a top view of an actinic structure 600N parallel to x_y. As shown in FIG. 14N, the 'oxide spacer 670B is on a part of the upper edge 632. Next, the oxide spacer 670B is used as a cover, and the conductive layer 630 is etched to form One or more elevated portions below the spacer. See Figure 丨 40. The conductive layer that is not covered by the spacer to the Shao portion is etched away, forming a recessed edge 632 < However, at least part of the oxide spacer 67 〇b is at least partially protected from being carved, forming a recessed portion 635 extending upward from the recessed edge. The side view of the conductive cup 630 '(parallel to the yz plane) with a recessed edge and a raised portion 635 is shown in Fig. 6P. The gap formed between the 638 series oxide material 128 and M0 by etching the conductive lining 63. As mentioned, this etch 10 15 20 25 (Please read the precautions on the back before filling this page) i · IIIIIII · 1111111 · ·

X 297公釐） 91. 1. 2,00C 556343 A7 經濟部智慧財產局貝工消費合社印製五、發明說明（51 ) 刻可為異向性或等向性。此#刻亦可為乾蚀刻或濕钱刻。接著將氧化層680沉積於凹處638及介電層128與 140之上（平行於y-z平面橫剖圖），示如圖14q。接著對氧化層680及氧化物間隔物670B施以CMP，露出至少部分加高部635之上表面或尖端637,形成圖 14R所示結構H00R。配置一層可程式化電阻記憶體材質與至少部分加高部相鄰。參閲圓14S，沉積一層記憶體材質690於結構1400R之上，尤其是至少部分一或兩尖端637之上。沉積一傳導層695於記憶體材質690 上’形成圖14S所示記憶艘元件1400S之較上電極（平行於y-z平面之側視）。圖14S'所示係與^；2面平行之另一結構600S側視圖，其顯示傳導襯裡63〇，以及與記憶體材質690相鄰之加高部635與尖端637。僅有加高部上表面637與記憶體材質690相鄰，而加高部的其它部分及傳導襯裡630'之其它部分則遠離記憶體材質 690。注意記憶體材質690之置放使其僅與加高部6乃之一相鄰。注意在沉積圖14Q所示氧化層68〇之前，可蝕刻介電區128及140 (示於圖14P)至凹緣632,水平。此舉可免除需具填充窄間隙638之氧化物材質68〇之需求，並可促進CMP。如上述，亦可形成突出奶/其係利用自諸如梦氮化物之其它介電質形成之間隔物為之。此外，其亦可自諸如多晶梦之半導趙材質或自諸 5 10 15 20 25 本紙張尺"心國國家標準（CNS)A4l格（21G X 297公1" (請先閲讀背面之注意事項再填寫本頁) ----— — II 訂------I--線 ·· 53 556343 A7 經濟部智慧財產局員工消費合作社印製五、發明說明（52) 如銘之導體形成間隔物。注意在用以形成上述加高部之方法具體例中，係以側壁間隔物為罩’並將部分不在罩（側壁間隔物）下 5方之傳導材質移除，形成加高部。亦可採用侧物以外的其它類型罩。例如：可利用不同型之圖樣層為罩’形成加高部。例如··可將圖樣層簡化為部分層 (諸如氧化物、氮化物或多晶矽層），其係在部分傳導層邊緣上形成。或者罩可為薄垂直配置條，而非形成如側壁層。罩之橫向尺寸係為罩與基板平行測量之尺寸。例如·當基板平行於x-y平面時，橫向尺寸可為沿χ_轴或 y-軸測量之罩尺寸。至少罩之橫向尺寸之—低於顯影摘所能實現之尺寸較佳（亦即低於顯影術極限在一具體例中，至少橫向尺寸之一低於1〇〇〇埃較佳。在另一具體例中，至少橫向尺寸之一低於7〇〇埃較佳，低狖 600埃更佳，低於約5〇〇埃最佳。類似地，除上述以外其它方法亦可用以形成罩化側壁間隔物，其係用以形成傳導材質上之加高部。所捋用之方法及材質理當視下方傳導材質而定。例如··在另一方法中，將一層多晶梦（第一層）沉積於傳導材質上。接著將該多晶矽層圖樣化，並蝕刻形成側壁表面。接著將一氧化層（第二層）沉積於多晶矽之‘壁表面上。該氧化層經異向性蝕刻移除水平配置比面，並留下在多晶矽上之側壁間隔物。接著將多晶矽移 10 15 20 25X 297 mm) 91. 1. 2,00C 556343 A7 Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Affairs Co., Ltd. 5. The description of the invention (51) can be anisotropic or isotropic. This #moment can also be a dry etch or a wet engraving. Next, an oxide layer 680 is deposited on the recess 638 and the dielectric layers 128 and 140 (a cross-sectional view parallel to the y-z plane), as shown in FIG. 14q. Next, CMP is applied to the oxide layer 680 and the oxide spacer 670B to expose at least a portion of the upper surface or tip 637 of the elevated portion 635 to form the structure H00R shown in FIG. 14R. A layer of programmable resistive memory material is arranged adjacent to at least part of the elevated portion. Referring to circle 14S, a layer of memory material 690 is deposited on the structure 1400R, especially on at least part of one or both of the tips 637. A conductive layer 695 is deposited on the memory material 690 to form the upper electrode of the memory boat element 1400S shown in FIG. 14S (side view parallel to the y-z plane). 14S 'is a side view of another structure 600S parallel to the two planes, which shows a conductive lining 63, a raised portion 635 and a tip 637 adjacent to the memory material 690. Only the upper surface 637 of the elevated portion is adjacent to the memory material 690, while the other portions of the elevated portion and other portions of the conductive liner 630 'are far away from the memory material 690. Note that the memory material 690 is placed so that it is adjacent to only one of the raised portions 6 or 6. Note that before depositing the oxide layer 68 as shown in FIG. 14Q, the dielectric regions 128 and 140 (shown in FIG. 14P) can be etched to the recessed edge 632, horizontally. This eliminates the need for oxide material 68, which requires a narrow gap 638, and facilitates CMP. As mentioned above, it is also possible to form a protruding milk / spacer using a spacer formed from another dielectric such as a dream nitride. In addition, it can also be made from materials such as the polysilicon semi-conductor Zhao or from 5 10 15 20 25 paper ruler "National Standard (CNS) A4l grid (21G X 297 male 1)" (Please read the back Please fill in this page again for the matters needing attention) —————— Order II ——---- I--line ·· 53 556343 A7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (52) The conductor forms a spacer. Note that in the specific example of the method for forming the above-mentioned elevated portion, the side wall spacer is used as a cover, and a part of the conductive material that is not under the cover (side wall spacer) is removed to form a height. Other types of masks other than side objects can also be used. For example, different types of pattern layers can be used to form the mask's heightened portion. For example, the pattern layer can be simplified into partial layers (such as oxide, nitride, or polycrystalline silicon). Layer), which is formed on the edge of a part of the conductive layer. Or the cover can be a thin vertical configuration strip instead of forming a side wall layer. The lateral dimension of the cover is the size of the cover measured parallel to the substrate. For example, when the substrate is parallel to xy In the plane, the lateral dimension can be measured along the x-axis or y-axis The size of the cover. At least one of the horizontal size of the cover is better than the size that can be achieved by the development (that is, below the imaging limit. In a specific example, at least one of the horizontal sizes is preferably less than 1000 angstroms. In another specific example, at least one of the transverse dimensions is preferably less than 700 angstroms, more preferably 600 angstroms, and most preferably less than about 500 angstroms. Similarly, other methods besides the above can be used. Forming a masked sidewall spacer is used to form a raised portion on a conductive material. The method and material used should depend on the conductive material below. For example, in another method, a layer of polycrystalline dream ( The first layer) is deposited on the conductive material. Then the polycrystalline silicon layer is patterned and etched to form the sidewall surface. Then an oxide layer (second layer) is deposited on the wall surface of the polycrystalline silicon. The oxide layer is anisotropic The etching removes the horizontally-arranged specific surface and leaves the sidewall spacers on the polycrystalline silicon. Then the polycrystalline silicon is moved by 10 15 20 25

297公釐） 91. 1. 2，_ {請先閱讀背面之注意事項再填寫本頁)297 mm) 91. 1.2, _ {Please read the notes on the back before filling this page)

556343556343

經濟部智慧財產局員消費合作社印製五、發明說明（53) 除，僅留下可做為罩之氧化物側壁間隔物。如上述，餘刻部分未為間隔物覆蓋之傳導材質，形成自間隔物下傳導材質延伸之加高部。當然可以其它材質取代多晶矽及氧化物。所選各視層（亦即第一及第二層）材貝係視下方傳導材質以及在各式姓刻製程期間之適當選擇性而定。在此技藝中熟知之其它方法亦可用以死成罩化間隔物。可在各式傳導襯裡之侧壁層邊緣形成加高部或突出。例如：可再如圖4A-4C所示傳導襯裡上形成之。圖7提供在溝槽中形成之u形傳導襯裡72〇示例。圖^ 所示傳導襯裡720具兩側壁層部73〇及底層部74〇。在傳導襯裡720之兩側壁層部73〇邊緣732 ±形成加高部或突出735。突出735自邊緣732延伸至尖端737。大抵上所有在傳導襯裡咖與記憶體材質（未圖示）間的電氣通連係經-或兩加高部735較佳，經由一或兩上表面737更佳。因而如上所揭，可在傳導側壁層邊緣上形成加高部或突出俾形成新型電氣接點結構。更廣義地說，可在卜I或‘向之傳導層邊緣上形成加高部。再更尹:義也說可在具任意實際幾何之任何傳導材質上形成一或多個加高部。如所述，為增加傳輪至記憶體材質之熱能量，4增 =電，點邊緣延伸之加高部或突出上表面或尖端之電阻率。此型社播一、、σ構之一不例示如上圖11。 15 20 25 _ 卿 _Α4 磐 91· 1. 2,000 (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Affairs Bureau of the Intellectual Property Agency of the Ministry of Economic Affairs. 5. Description of Invention (53) Except for the oxide sidewall spacers that can be used as masks. As described above, the remaining part is not the conductive material covered by the spacer, forming an elevated portion extending from the conductive material under the spacer. Of course, other materials can be used instead of polycrystalline silicon and oxides. The material of each selected layer (ie, the first and second layers) depends on the conductive material below and the appropriate selectivity during the various surname engraving processes. Other methods known in the art can also be used to form masked spacers. Elevations or protrusions can be formed on the edges of the sidewall layers of various conductive linings. For example, it can be formed on the conductive lining as shown in FIGS. 4A-4C. FIG. 7 provides an example of a u-shaped conductive liner 72 formed in a trench. The conductive liner 720 shown in Fig. ^ Has two side wall layer portions 73 and a bottom layer portion 74. On both sides of the conductive liner 720, the edge 732 of the side wall layer portion 732 ± forms a raised portion or protrusion 735. The protrusion 735 extends from the edge 732 to the tip 737. It is probably better than all the electrical connections between the conductive lining coffee and the memory material (not shown)-or two heightened sections 735 are better, and one or two upper surfaces 737 are better. Therefore, as disclosed above, a raised portion or a protrusion can be formed on the edge of the conductive sidewall layer to form a new type of electrical contact structure. In a broader sense, a raised portion may be formed on the edge of the conductive layer. Even more Yin: Yi also said that one or more elevations can be formed on any conductive material with any actual geometry. As mentioned, in order to increase the heat energy from the wheel to the memory material, 4 increase = electricity, the resistivity of the heightened portion extending from the edge of the point or protruding from the upper surface or tip. This type of agency broadcast one, σ structure is not exemplified as shown in Figure 11 above. 15 20 25 _ Qing _Α4 Pan 91 · 1. 2,000 (Please read the notes on the back before filling this page)

556343 A7 經濟部智慧財產局員工消费合作社印製五、發明說明5¾ ) 本發明之記憶體元件可與絕緣/選擇元件電氣偶合並將導線定址，俾形成記憶體陣列。絕緣/定址元件使各分離記憶胞可被讀取與寫入，而不與陣列中相鄰或遠離之記憶胞t儲存之資料互相干擾。大體上，本發明並未限制使用任何特定型式乏絕緣/定址元件。絕緣/ 定址元件示例包含場效電晶體、雙載子接面電晶體及二極體。場效電晶體示例包含JFET及MOSFET。 MOSFET示例包含NMOS電晶體及PMOS電晶體。此外，NMOS及PMOS甚至可以CMOS技術在同一晶片上形成之。因而與記憶體陣列結構之記憶體元件有關者係絕緣/定址元件，其可充做對記憶體單元之絕緣/定址元件，藉此使該胞可被讀取與寫入，而不與陣列中相鄰或遠離之記憶胞中儲存之資料互相干擾6、本發明之記憶體元件包含記憶體材質體。概言之，該記憶體材質體係可程式化電阻記憶體材質，其可程式化至至少第-電阻狀態及第二電阻狀態。記憶體材質響應於電氣信號而程式化較佳。用以將材質程式化之電氣、说為流向記憶體材質之電流較佳。在-具體射’可將記賴材質喊化為兩電阻狀態，俾使各記憶體元件均可儲存單一位元資訊◊在另一具體例中，可將記憶體材質程式化為至少三電▲狀態，俾使各記憶體元件均可儲存多於一位元資訊。在另-具想例中，可將記憶趙材質程式化為至少四電阻 5 10 15 20 25 (請先閱讀背面之注意ί項再填寫本頁)556343 A7 Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Affairs 5. V. INTRODUCTION 5¾) The memory element of the present invention can be electrically coupled with the insulation / selection element, and the wires can be addressed to form a memory array. Insulation / addressing elements enable separate memory cells to be read and written without interfering with the data stored by adjacent or remote memory cells in the array. In general, the invention does not restrict the use of any particular type of deficient insulation / addressing element. Examples of insulation / addressing components include field effect transistors, bipolar junction transistors, and diodes. Examples of field effect transistors include JFETs and MOSFETs. Examples of MOSFETs include NMOS transistors and PMOS transistors. In addition, NMOS and PMOS can even be formed on the same wafer using CMOS technology. Therefore, the memory element related to the memory array structure is an insulation / addressing element, which can be used as an insulation / addressing element for the memory unit, thereby enabling the cell to be read and written, instead of being in the array Data stored in adjacent or remote memory cells interfere with each other. 6. The memory element of the present invention includes a memory texture body. In summary, the memory material system can be programmed with a resistive memory material, which can be programmed to at least a first resistance state and a second resistance state. The memory material is better programmed in response to electrical signals. The electrical, which is used to program the material, is better said to flow to the memory material. In the “specific concrete shooting”, the memory material can be shouted into two resistance states, so that each memory element can store a single bit of information. In another specific example, the memory material can be programmed to at least three electricity. Status, so that each memory element can store more than one bit of information. In another example, you can program the memory Zhao material to at least four resistors 5 10 15 20 25 (Please read the note on the back before filling this page)

訂：線. 56 556343 A7 五、發明說明（55)狀態 5 10 15 20 經濟部智慧財產局員工消費合作社印製 25 俾使各記憶體元件均可儲存至少兩位元資訊。因而記憶體材質之電阻值範圍使其可提供多重位元資訊之灰階儲存。記憶體材質可直接重複寫入，使其可自任何電阻狀態程式化至任何其它電阻狀態，無需先被設定至啟始狀態。可採用相同的程式化脈衝或脈衝群將記憶體材質程式化至與其之前電阻狀態無關之特定電阻狀態較佳。（例如·相同的電流脈衝或脈衝群可用以將記憶體材質程式化至高電阻狀態，與其之前狀態無關）。在美國專利第6,075,719號中揭示一種記憶體元件之程式化方法，茲併於此以為參述。記憶體材質可為相變材質。相變材質可為在此技藝中之任意相變記憶體材質。相變材質可顯示第一級相位轉換較佳。材質示例如美國專利號、5，166,758、 5,296,716、5,414,271、5,359,205、5,341，328、5,536,947、 5,534,712、5,687，112 及 5,825，G46 所揭，茲併於此以為參述。相變材質可自複數個原子單元形成。記憶體材質包含至少一硫屬（chalcogen)元素較佳。硫屬元素可自由Te、Se及其混合物或合金組成之群令選擇。記憶體材質更可包含至少自由Ge、Sb、Bi、Pb、Sn、As、S、 Si、P、〇及其混合物或合金組成之群中選擇之一元I。在一具體例中，記憶體材質包含元素Te、及sb。在另一具體例中，記憶體材質基本上係由Te、Qe&sb (請先閲讀背面之注意事項再填寫本頁) •1裝 ϋ n n 一一OJV ai_i ϋ I I I . 57 556343 經濟部智慧財產局貝工消費合作社印製 A7 B7 五、發明說明（56) 組成。可採用之記憶體材質之一示例為Te2Ge2Sb5。記憶體材質可包含至少一過渡金屬元素。此處所採用之"過渡金屬"包含元素21至30、39至48、57及72 5 至80。一或多個過渡金屬元素係選自由Cr、Fe、Ni、 Nb、Pd、Pt及其混合物或合金組成之群中較佳。包含過渡金屬之記憶體材質基本上可修改記憶體材質型式於Te-Ge-Sb三元系統中。此基本修改可將過渡金屬併入基本Te-Ge-Sb三元系統中實現之，具或不具諸如Se ίο 之硫屬元素均可。基本修改之§己憶體材質的第^不例係一相變記憶體材質，其包含Te、Ge、Sb及一過渡金屬，其比例為 (TeaGebSbioo-_))cTMioo-c，其中的下標係組成元素之總體100%之原子百分比，其中TM係一或多個過渡金 15 屬，此處之a與b係對基本Te-Ge-Sb三允系統設定，而c位於約90%與約99.99%間。過渡金屬可包含Cr、 Fe、Ni、Nb、Pd、Pt及其混合物或合金較佳。基本修改之記憶體材質的第二示例係一相變記憶體材質，其包含Te、Ge、Sb、Se及一過渡金屬，其比 2 0 例為(TeaGebSblOO-(a+b))cTMdSeiOCKc+d)，其中的下標係組成元素之總體100%之原子百分比，其中TM係一或多個過渡金屬，a與b係對上述基本Te_Ge-Sb三元系統設定，而c位於約90%與約99.5%間，d在約 0.01% 與10%間。過渡金屬可包含Cr、Fe、Ni、Pd、pt、Nb 25 及其混合物或合金較佳。 58 本紙張尺/夂·甲關家標準（CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁)Order: Line. 56 556343 A7 V. State of the invention (55) 5 10 15 20 Printed by the Intellectual Property Office of the Ministry of Economic Affairs and Consumer Affairs Co., Ltd. 25. Each memory element can store at least two bits of information. Therefore, the resistance range of the memory material makes it possible to provide gray-scale storage of multi-bit information. The memory material can be directly rewritten so that it can be programmed from any resistance state to any other resistance state without first being set to the initial state. The same programmed pulse or burst can be used to program the memory material to a specific resistance state that is independent of its previous resistance state. (For example, the same current pulse or pulse group can be used to program the memory material to a high-resistance state, regardless of its previous state). A stylized method of a memory element is disclosed in U.S. Patent No. 6,075,719, which is hereby incorporated by reference. The memory material can be a phase change material. The phase change material can be any phase change memory material in this technique. Phase change materials can show that the first level phase transition is better. Examples of materials are disclosed in US Patent Nos. 5,166,758, 5,296,716, 5,414,271, 5,359,205, 5,341,328, 5,536,947, 5,534,712, 5,687,112, and 5,825, G46, and are hereby incorporated by reference. The phase change material can be formed from a plurality of atomic units. The memory material preferably contains at least one chalcogen element. The chalcogen can be selected from the group consisting of Te, Se and mixtures or alloys thereof. The memory material may further include at least one element I selected from the group consisting of Ge, Sb, Bi, Pb, Sn, As, S, Si, P, 0, and mixtures or alloys thereof. In a specific example, the memory material includes the elements Te and sb. In another specific example, the material of the memory is basically Te, Qe & sb (please read the precautions on the back before filling out this page) • 1 installation nn -11 OJV ai_i ϋ III. 57 556343 Intellectual Property of the Ministry of Economic Affairs A7 B7 printed by Bureau Shelley Consumer Cooperative 5. Composition of Invention (56). An example of a memory material that can be used is Te2Ge2Sb5. The memory material may include at least one transition metal element. The "transition metal" used here contains elements 21 to 30, 39 to 48, 57 and 72 5 to 80. One or more transition metal elements are preferably selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt, and mixtures or alloys thereof. The memory material containing the transition metal can basically modify the memory material type in the Te-Ge-Sb ternary system. This basic modification can be achieved by incorporating transition metals into the basic Te-Ge-Sb ternary system, with or without chalcogens such as Se ίο. The ^ th example of the basic modified § memory material is a phase change memory material, which includes Te, Ge, Sb, and a transition metal, the ratio is (TeaGebSbioo -_)) cTMioo-c, where the subscript Is an atomic percentage of 100% of the total constituent elements, of which TM is one or more transition metals of 15 metals, where a and b are set to the basic Te-Ge-Sb three-permit system, and c is located at about 90% and about 99.99%. The transition metal may include Cr, Fe, Ni, Nb, Pd, Pt, and mixtures or alloys thereof. The second example of a basic modified memory material is a phase change memory material, which includes Te, Ge, Sb, Se, and a transition metal. The ratio of 20 is (TeaGebSblOO- (a + b)) cTMdSeiOCKc + d ), Where the subscript is the total atomic percentage of 100% of the constituent elements, where TM is one or more transition metals, a and b are set for the basic Te_Ge-Sb ternary system described above, and c is located at about 90% and about 99.5%, d is between about 0.01% and 10%. The transition metal may include Cr, Fe, Ni, Pd, pt, Nb 25 and mixtures or alloys thereof. 58 paper ruler / 夂 · 甲关家 standard (CNS) A4 size (210 x 297 mm) (Please read the precautions on the back before filling this page)

556343 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（57) 瞭解此處所揭係以詳細具體例型式呈現，其目的在對本發明做充分且完全之揭示，然而並不以此類細節限定如隨附之申請專利範圍所界定之本發明真正範 5 疇。圖式之代號說明 100 記憶體元件 102 半導體基板 106 底表面 128 介電層 128s 側壁表面 130 第一接點 132 上緣 133 傳導材質層 135 加高部 137 上表面 138 凹處 140 介電區 145 介電材質 150 凹處 160 材質 170 開孔 180 介電區 200 結構、 240 第一氧化層 250 多晶石夕層 252 側壁表面 260 光阻罩 270 第二氧化層 280 中間層 290 記憶體材質 300 第二接點 330 圓柱形傳導側壁間隔物331 下緣 332 上緣 335 突出 337 尖端 430 傳導襯裡 432 上緣 600 記憶體元件 610 開孔 630 傳導襯裡 632 上緣 633 傳導材質層 59 ----；——*------^裝 i — (請先閱讀背面之注意事項再填寫本頁) tT·556343 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (57) It is understood that what is disclosed here is presented in a detailed and specific form. The details define the true scope of the present invention as defined by the scope of the attached patent application. Description of the drawing code 100 memory element 102 semiconductor substrate 106 bottom surface 128 dielectric layer 128s side wall surface 130 first contact 132 upper edge 133 conductive material layer 135 elevated portion 137 upper surface 138 recess 140 dielectric region 145 dielectric Electrical material 150 Depression 160 Material 170 Opening hole 180 Dielectric area 200 Structure 240 First oxide layer 250 Polycrystalline layer 252 Side wall surface 260 Photoresist cover 270 Second oxide layer 280 Intermediate layer 290 Memory material 300 Second Contact 330 Cylindrical conductive sidewall spacer 331 Lower edge 332 Upper edge 335 Projection 337 Tip 430 Conductive lining 432 Upper edge 600 Memory element 610 Opening 630 Conductive lining 632 Upper edge 633 Conductive material layer 59 ----———— * ------ ^ 装 i — (Please read the notes on the back before filling this page) tT ·

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 556343 A7 B7 五、發明說明（58) 5 經濟部智慧財產局員工消费合作社印製 635 加高部 637 尖端 638 凹處 640 孔 650 多晶碎層 660 光阻罩 670 通路 690 記憶體材質 695 傳導層 700 記憶體元件 720 傳導襯裡 730 第一接點 732 邊緣 740 底層部 750 記憶體材質 770 第二電氣接 800 記憶體元件 828 介電材質 830 第一接點 850 記憶體材質 870 第二接點 1000 記憶體元件 1400 結構This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 556343 A7 B7 V. Description of Invention (58) 5 Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 635 Heightened 637 Tip 638 Depression 640 Hole 650 Polycrystalline layer 660 Photoresist cover 670 Passage 690 Memory material 695 Conductive layer 700 Memory element 720 Conductive lining 730 First contact 732 Edge 740 Bottom portion 750 Memory material 770 Second electrical connection 800 Memory element 828 Dielectric material 830 First contact 850 Memory material 870 Second contact 1000 Memory element 1400 Structure

(請先閲讀背面之注意事項再填寫本頁) 裝(Please read the notes on the back before filling this page)

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims

A8 B8 p年h‘修正 C8 D8 補充 556343 六、申請專利範圍專利申請案第90120438號 ROC Patent Appln. No. 90120438 修正後無劃線之申請專利範圍中文本-附件(一） Amended Claims in Chinese - EncUI) 5 (民國92年7月W曰送呈） (Submitted on July ? 2003) 1. 一種電氣操作之記憶體元件，其包括：記憶體材質體，其可程式化於至少第一電阻狀 10 態及第二電阻狀態；以及一電氣接點，其與該記憶體材質電氣通連，該電氣接點包含至少具第一電阻率之第一區以及具第二電阻率之第二區，其中第二電阻率高於第一電阻率。 15 2.如申請專利範圍第1項之記憶體元件，其中該第二區係與該記憶體材質相鄰。 3. 如申請專利範圍第1項之記憶體元件，其中該電氣接點係一傳導層。 4. 如申請專利範圍第1項之記憶體元件，其中該電氣 20 接點係一傳導側壁襯裡或一傳導側壁間隔物。經濟部智慧財產局員工消費合作社印製 5. 如申請專利範圍第1項之記憶體元件，其中該電氣接點沿邊與該記憶體材質相鄰。 6. 如申請專利範圍第1項之記憶體元件，其中大致上所有之該電氣通連係經至少部分該電氣接點邊緣。 25 7.如申請專利範圍第1項之記憶體元件，其中該第一區及該第二區之摻雜相異。 8.如申請專利範圍第1項之記憶體元件，其中該電氣接點包含一加高部分，延伸至與記憶體材質相鄰之 -61 - 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） 90343B-接.doc 5 一末端。項之記憶體元件，其中該記憶〇體元件之製造方法，其包括步 9·如申請專利範圍第1 體材質係一相變材質 1〇· 一種電氣操作之記憶驟：提供一傳導材質增加部分該傳導材質之電阻率；以及沉積與該部分相鄰之記憶體材質。 10 20 利範圍第1G項之方法，其中該增加電阻平步驟包括改變該部分之摻雜程度的步驟。 12. :申請專利範圍第10項之方法，其中該增加電阻率步驟包括將離子佈植入該層部分的步驟。 13. 如申請專利範圍第1G項之方法，其中該增加電阻率步驟包括步驟：移除該部分以在該傳導材質中形成凹處；以及以電阻率高於該移除部分之電阻率的材質填充 δ亥凹處。 14.如申請專利範圍帛1G項之方法，其中該記憶體材質係一相變材質。 15· —種電氣操作之記憶體元件，其包括一可程式化電阻記憶體材質；以及一傳導層，其與該記憶體材質電氣通連，該傳導層具一加高部分，自該層邊緣延伸至與記憶體材質相鄰之一末端。 25 16·如申請專利範圍第15項之記憶體元件，其中該傳 -62 -A8 B8 p'h h amended C8 D8 supplement 556343 VI. Application for Patent Scope Patent Application No. 90120438 ROC Patent Appln. No. 90120438 Amended Claims without Approved Chinese Scope-Annex (I) Amended Claims in Chinese- EncUI) 5 (Submitted on July? 2003) 1. An electrically operated memory element, which includes: a memory material body that can be programmed in at least a first resistive state of 10 And a second resistive state; and an electrical contact electrically connected to the memory material, the electrical contact including at least a first region having a first resistivity and a second region having a second resistivity, wherein the first The second resistivity is higher than the first resistivity. 15 2. The memory element according to item 1 of the patent application scope, wherein the second region is adjacent to the memory material. 3. For the memory element according to item 1 of the patent application, wherein the electrical contact is a conductive layer. 4. For the memory device according to item 1 of the patent application, wherein the electrical 20 contact is a conductive sidewall lining or a conductive sidewall spacer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. If the memory element of the scope of patent application is No. 1, the electrical contact is adjacent to the memory material along the edge. 6. If the memory element of the scope of the patent application is item 1, substantially all of the electrical connections are connected through at least part of the edge of the electrical contact. 25 7. The memory device of claim 1 in which the doping of the first region and the second region are different. 8. If the memory element of the first patent application scope, the electrical contact includes a heightened portion, which extends to -61 adjacent to the memory material-This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) 90343B-connected to .doc 5 at one end. Item of the memory element, wherein the manufacturing method of the memory element includes the step 9. The first body material is a phase change material 1 as in the scope of the patent application. An electrical operation memory step: Provides a conductive material increase part Resistivity of the conductive material; and deposition of a memory material adjacent to the portion. 10 20 The method of the 1G range, wherein the step of increasing the resistance level includes a step of changing the degree of doping of the portion. 12 .: The method of claim 10, wherein the step of increasing the resistivity includes the step of implanting an ion cloth in the portion of the layer. 13. The method of claim 1G, wherein the step of increasing the resistivity includes the steps of: removing the portion to form a recess in the conductive material; and using a material having a resistivity higher than the resistivity of the removed portion. Fill the delta depression. 14. The method according to the scope of application for patent item 1G, wherein the memory material is a phase change material. 15 · —An electrically operated memory element including a programmable resistive memory material; and a conductive layer electrically connected to the memory material, the conductive layer having a heightened portion from the edge of the layer Extend to the end adjacent to the memory material. 25 16. If the memory element according to item 15 of the patent application scope, wherein the pass -62-

申請專利範圍 5 10 15 經濟部智慧財產局員工消費合作社印製 20 25 導層係一傳導側壁層。 17·如申請專利範圍第15項之記憶體元件，其中該傳導層係一傳導襯裡或一傳導間隔物。 Λ 18·如申請專利範圍第15項之記憶體元件，其中該記憶體材質係一相變材質。 19.—種供半導體元件之電氣接點，其包括：一絕緣層；一開孔，其形成於該絕緣層之中，該開孔具一側壁表面及一底表面；以及一傳導層，其配置於該開孔之側壁表面上，該層具一加高部分，自該側壁表面上之該傳導層邊緣延伸。 20· —種用以製造可程式化電阻記憶體元件之方法，其包括： a 提供一傳導材質；在部分該傳導材質上形成側壁間隔物；將部分該傳導材質移除，以在該間隔物下形成自該傳導材質延伸之加高部分；以及形成至少與部分該加高部分相鄰之可程式化電阻材質。 21·如申請專利範圍第2〇項之方法，其中該形成該側壁間隔物步驟包括：在該傳導材質上形成第一層；在該第一層上形成第二層；在該第二層中形成側壁表面； -63 - 本紙張尺度適用中國國家標準(CNS)A4規格（21〇 x 297公爱） 556343 A8Scope of patent application 5 10 15 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 25 The conductive layer is a conductive sidewall layer. 17. The memory element of claim 15 in which the conductive layer is a conductive liner or a conductive spacer. Λ 18: The memory element according to item 15 of the patent application scope, wherein the memory material is a phase change material. 19. An electrical contact for a semiconductor element, comprising: an insulating layer; an opening formed in the insulating layer, the opening having a sidewall surface and a bottom surface; and a conductive layer, which The layer is disposed on the side wall surface of the opening, and the layer has a raised portion extending from the edge of the conductive layer on the side wall surface. 20 · —A method for manufacturing a programmable resistive memory element, comprising: a providing a conductive material; forming a sidewall spacer on a portion of the conductive material; removing a portion of the conductive material to form a spacer Forming a raised portion extending from the conductive material; and forming a programmable resistive material at least adjacent to the raised portion. 21. The method of claim 20, wherein the step of forming the sidewall spacer comprises: forming a first layer on the conductive material; forming a second layer on the first layer; in the second layer Form side wall surface; -63-This paper size is applicable to Chinese National Standard (CNS) A4 specification (21〇x 297 public love) 556343 A8

看I I I 雇 I I IIII I I I I I I I I II I I 計 I 應 I I II I 馨 II I I I I I 審 I I 娜 I I 556343See I I I hire I I IIII I I I I I I I II I I plan

^、申請專利提供一傳導層； I成自該傳導層邊緣延伸之加高部分；以及开7成至少與部分該加高部分相鄰之可程式化電阻材質。 30· t申請專利範圍第29項之方法，其中該形成該加向部分步驟包括：在部分該邊緣上形成罩；以及移除部分該傳導層，以在該罩下形成該加高部分。側隔 3L如申請專利範圍第3〇項之方法，其中該罩係一壁間隔物，且形成該罩步驟包括形成該側壁間物。 32.=申請專利範圍第31項之方法，其中該形成該側壁間隔物步驟包括：在該邊緣上形成第一層；在該第一層上形成第二層；在該第二層中形成側壁表面；在該側壁表面上形成第三層；經濟部智慧財產局員工消費合作社印製移除部分該第三層； 20 移除該第二層；以及移除部分該第一層。及第 33·如申請專利範圍第32項之方法，其中該第一二層為氧化物，而該第二層為多晶矽。及第 34·如申請專利範圍第32項之方法，其中該第一 25 二層為氮化物，而該第二層為氧化物。 -65 - 本紙張尺度適用中國國家標準(CNS)A4規格（2ω χ 297公^ Apply for a patent Provide a conductive layer; I into a raised portion extending from the edge of the conductive layer; and 70% of a programmable resistive material adjacent to at least part of the raised portion. 30 · t. The method of claim 29, wherein the step of forming the added portion includes: forming a cover on a portion of the edge; and removing a portion of the conductive layer to form the elevated portion under the cover. The side spacer 3L is the method according to item 30 of the patent application scope, wherein the cover is a wall spacer, and the step of forming the cover includes forming the side wall spacer. 32. = The method of claim 31, wherein the step of forming the sidewall spacer comprises: forming a first layer on the edge; forming a second layer on the first layer; forming a sidewall in the second layer The surface; a third layer is formed on the side wall surface; the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints and removes part of the third layer; 20 removes the second layer; and removes part of the first layer. And 33. The method of claim 32 in the scope of patent application, wherein the first and second layers are oxides and the second layer is polycrystalline silicon. And Article 34. The method of claim 32 in the scope of patent application, wherein the first two layers are nitrides and the second layer is an oxide. -65-This paper size applies to China National Standard (CNS) A4 (2ω χ 297 male)

556343 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 35. 如申請專利範圍第29項之方法，其中該可程式化電阻材質包括一相變材質。 36. —種形成可程式化電阻記憶體元件之方法，其包括： 5 提供第一介電層；在該介電層中形成側壁表面；在該側壁表面上形成傳導層；在該傳導層上形成第二介電層；形成或露出該傳導層之一邊緣； 10 形成自該傳導層邊緣延伸之加高部分；以及形成至少與部分該加高部分相鄰之可程式化電阻材質。 37. 如申請專利範圍第36項之方法，其中該形成該加高部分步驟包括： 15 在部分該邊緣上形成罩；以及移除部分該傳導層，以在該罩下形成該加高部分。 38·如申請專利範圍第37項之方法，其中該罩係一側壁間隔物，且形成該罩步驟包括形成該側壁間隔 20 物。 39·如申請專利範圍第38項之方法，其中該形成該側壁間隔物步驟包括：在該邊緣上形成第一層；在該第一層上形成第二層； 25 在該第二層中形成側壁表面； -66 - 本紙張尺度適用中國國家標準(CNS)A4規格（210 X297公釐）計線六、申^--^~_^ 氣在該側壁表面上形成第三層；移除部分該第三層； 5 40. 41· 42. 10 43. 移除該第二層；以及移除部分該第一層。如^請專利範圍第％項之方法，其中該第一及第 -續為氧化物，而該第二層為多晶石夕。 :1明專利範圍第39項之方法，其中該第-及第二層為氮化物，而該第二層為氧化物。 t申請專利範圍第36項之方法，其中該可程式化電阻材質包括一相變材質。 —種用以製造供半導體元件之電極之方法，其包括：提供一傳導層；以及 15 形成自該傳導層邊緣延伸之加高部分。 ^申明專利範圍第43項之方法，其中該形成該加南部分步驟包括：在部分該邊緣上形成罩；以及移除部分該傳導層，以在該罩下形成該加高部經濟部智慧財產局員工消費合作社印製分。 45. 如申請專利範圍第44項之方法，其中該罩係一側壁間隔物，且形成該罩步驟包括形成該側壁間隔物。 46. 如申請專利範圍第45項之方法，其中該形成該側壁間隔物步驟包括： 25 在該邊緣上形成第一層； -67 - 本紙張尺度適用中國國家標準(CNS)A4規格（210X297公釐）九BICID556343 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 VI. Application for patent scope 35. For the method of applying for the scope of patent No. 29, the programmable resistor material includes a phase change material. 36. A method of forming a programmable resistive memory element, comprising: 5 providing a first dielectric layer; forming a sidewall surface in the dielectric layer; forming a conductive layer on the sidewall surface; and forming a conductive layer on the conductive layer Forming a second dielectric layer; forming or exposing an edge of the conductive layer; 10 forming a raised portion extending from the edge of the conductive layer; and forming a programmable resistive material at least adjacent to the raised portion. 37. The method of claim 36, wherein the step of forming the elevated portion includes: 15 forming a cover on a portion of the edge; and removing a portion of the conductive layer to form the elevated portion under the cover. 38. The method of claim 37, wherein the cover is a side wall spacer, and the step of forming the cover includes forming the side wall spacer. 39. The method of claim 38, wherein the step of forming the sidewall spacer comprises: forming a first layer on the edge; forming a second layer on the first layer; 25 forming in the second layer Surface of side wall; -66-This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X297 mm). Calculation line 6. Shen ^-^ ~ _ ^ Gas forms a third layer on the surface of the side wall; removed part The third layer; 5 40. 41 · 42. 10 43. Remove the second layer; and remove part of the first layer. For example, the method of item% of the patent scope, wherein the first and the second-are oxides, and the second layer is polycrystalline. : 1 The method of item 39 of the patent scope, wherein the first and second layers are nitrides and the second layer is an oxide. The method for applying for the patent No. 36, wherein the programmable resistance material includes a phase change material. A method for manufacturing an electrode for a semiconductor element, comprising: providing a conductive layer; and forming a raised portion extending from an edge of the conductive layer. ^ Declaring the method of the 43rd aspect of the patent, wherein the step of forming the Kanan portion includes: forming a cover on a portion of the edge; and removing a portion of the conductive layer to form the elevated intellectual property of the Ministry of Economy Bureau employees print credits for consumer cooperatives. 45. The method of claim 44 in which the cover is a side wall spacer, and the step of forming the cover includes forming the side wall spacer. 46. The method of claim 45, wherein the step of forming the side wall spacer includes: 25 forming a first layer on the edge; -67-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297) %) Nine BICID

556343 六、申請專利範圍在該第一層上形成第二層；在該第二層中形成側壁表面；在該側壁表面上形成第三層；移除部分該第三層； 5 移除該第二層；以及移除部分該第一層。 47. 如申請專利範圍第46項之方法，其中該第一及第三層為氧化物，而該第二層為多晶矽。 48. 如申請專利範圍第46項之方法，其中該第一及第 10 三層為氮化物，而該第二層為氧化物。 49· 一種用以製造供半導體元件之電極之方法，其包括：提供第一介電層；在該介電層中形成側壁表面； 15 在該側壁表面上形成傳導層；在該傳導層上形成第二介電層；形成或露出該傳導層之一邊緣；以及形成自該傳導層邊緣延伸之加高部分。經濟部智慧財產局員工消費合作社印製 50. 如申請專利範圍第49項之方法，其中該形成該加 20 高部分步驟包括：在部分該邊緣上形成罩；以及移除部分該傳導層，以在該罩下形成該加高部分。 51. 如申請專利範圍第50項之方法，其中該罩係一側 25 壁間隔物，且形成該罩步驟包括形成該側壁間隔 -68 - 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） 556343 經濟部智慧財產局員工消費合作社印製 A8 ；； ! B8 %” : ί C8 I 1 D8_L———一… ：.'，.，六、申請專利範圍物。 52. 如申請專利範圍第51項之方法，其中該形成該側壁間隔物步驟包括：在該邊緣上形成第一層； 5 在該第一層上形成第二層；在該第二層中形成側壁表面；在該側壁表面上形成第三層；移除部分該第三層；移除該第二層；以及 10 移除部分該第一層。 53. 如申請專利範圍第52項之方法，其中該第一及第三層為氧化物，而該第二層為多晶矽。 54. 如申請專利範圍第52項之方法，其中該第一及第三層為氮化物，而該第二層為氧化物。本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐）556343 6. The scope of the patent application forms a second layer on the first layer; forms a side wall surface in the second layer; forms a third layer on the side wall surface; removes part of the third layer; 5 removes the first layer Two layers; and removing part of the first layer. 47. The method of claim 46, wherein the first and third layers are oxides and the second layer is polycrystalline silicon. 48. The method of claim 46, wherein the first and third layers are nitrides and the second layer is an oxide. 49 · A method for manufacturing an electrode for a semiconductor element, comprising: providing a first dielectric layer; forming a sidewall surface in the dielectric layer; 15 forming a conductive layer on the sidewall surface; forming on the conductive layer A second dielectric layer; forming or exposing an edge of the conductive layer; and forming a raised portion extending from the edge of the conductive layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 50. If the method of applying for the scope of patent No. 49, the step of forming the plus 20 high part includes: forming a cover on part of the edge; and removing part of the conductive layer to The raised portion is formed under the cover. 51. The method of claim 50, wherein the cover is a 25-wall spacer on one side, and the step of forming the cover includes forming the side wall interval -68-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 556343 Printed A8 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; B8% ": ί C8 I 1 D8_L ——— one ...:. ',., Six, scope of patent application. 52. Such as The method of claim 51, wherein the step of forming the sidewall spacer comprises: forming a first layer on the edge; 5 forming a second layer on the first layer; forming a sidewall surface in the second layer; Forming a third layer on the surface of the side wall; removing a portion of the third layer; removing the second layer; and 10 removing a portion of the first layer. 53. The method of claim 52, wherein the first The first and third layers are oxides, and the second layer is polycrystalline silicon. 54. The method according to item 52 of the patent application, wherein the first and third layers are nitrides and the second layers are oxides. This paper size applies to Chinese national standards Standard (CNS) A4 (210 X 297 mm)