TW556324B - Manufactring method to form control gate and peripheral transistor of flash memory simultaneously - Google Patents

Abstract

A semiconductor substrate having memory cell region and peripheral circuit region is provided. Form a first oxide layer on it. At least one floating gate that is composed of a first poly-silicon layer and gate dielectric layer is set up on the first oxide layer of the memory cell area. Globally deposit a second poly-silicon layer to cover the first oxide layer of the memory cell area and peripheral circuit area. Form a gate pattern on the second poly-silicon layer of the peripheral circuit area. Then execute a dry etching process and stop on the first oxide layer. Simultaneously form the gate-patterned second poly-silicon layer to be the gates of the periphery circuit transistors and form plural spacer-type second poly-silicon layers on the two sides of the floating gates as the control gates of the flash memories in the memory cell area.

Description

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【發明領域】 【發明 傳 電晶體 施力口 一 電子穿 當抹除 入到浮 效應， 界電壓 以確保 為 閃記憶 時代， 術已廣 /C線的 背景】 統的快 結構所 高電壓 過隧穿 數據時 置閘極 穿過隧 。然而 將浮置 了解決 體」構 形成具 泛地運 製造方 閃記憶 構成， 於控制 氧化層 ，則施 的電子 穿氧化 ’在抹 閘極中 過度抹 造被提 有間隔 用於分 法中。 體係以浮置 “進行程式 閘極(cont 而注入浮置 加一高電壓 可藉由所謂 層而流入源 除的過程中 的注入電子 除的問題， 出，而當快 物狀之複晶 離閘極式快 閘極（floating gate ) 化步驟而寫入數據時，係 ro 1 1 i ng gate )，使得熱 閘極’提高其臨界電壓； 於源極區域，使得前述注 的Fowler-Nordheim 隨穿 極區，使其回復原有的臨 ’通常會延長抹除的時間 完全吸出。 有所謂的「分離閘極式快 閃記憶體製程進入次微米 石夕層（poly_spacer)之技 閃記憶體之控制閘極及字 而於分離閘極式快閃記憶體的製造過程中，除了於記 隐胞存在之5己憶體早元區（Memory device area)内進行上 述快閃記憶體之製程，亦因應實際需求與設計，亦於週邊 電路區（periphery circuits area)内進行週邊電晶體之[Field of the invention] [Invention of the power-transmitting crystal force-electron penetrating erasing to the floating effect, the boundary voltage to ensure the era of flash memory, the background of the broad / C line] high-speed tunneling by the traditional fast structure When the data is passed, the gate is passed through the tunnel. However, the "floating solution" structure has a universal flash memory structure, which is used to control the oxide layer, and the applied electron penetrating oxidation 'is excessively wiped in the wiper gate and spaced for separation. The system uses the floating gate to carry out the program gate (cont while injecting the floating plus a high voltage can flow into the source through the so-called layer to remove the injected electrons in the process of removal, and when the fast-shaped complex crystal is off the gate When the data is written in the floating gate step, the gate is ro 1 1 in ng gate, so that the thermal gate 'increases its critical voltage. In the source region, the aforementioned Fowler-Nordheim is worn through The polar region, which allows it to return to its original position, usually prolongs the erasing time and completely sucks it out. There is a so-called "separated gate flash memory system that enters the sub-micron lithography layer (poly_spacer) and controls the flash memory In the manufacturing process of the gate-type flash memory, the gate and the word are not only processed in the memory device area of the 5th memory memory cell, but also corresponding to the flash memory. Actual needs and designs are also carried out in peripheral circuits area

〇548-84947W(N) * 91079 ； Shawn.ptd 第4頁 556324 五、發明說明（2) ，程’例如高電壓電晶體（high voltage transistor)之 製程，.其用途可作為快閃記憶體製程中，快閃記憶體產品 線上（1 η- 1 i ne )電性測試之即時測試元件以及記憶體之相 關電源驅動應用。 以下’利用第1 a圖〜第1 d圖所示之分離閘極式快閃記 憶體的製程剖面示意圖，以說明習知技術之形成記憶胞區 内分離閘極式快閃記憶體之控制閘極與週邊電路區内之週 邊電晶體之製造方法。 、首先，請參照第la圖，該圖符號丨〇為半導體基底，例 如為一半導體矽基底，並於上述半導體基底10内區分為記 憶體單元區（Memory device Area ;MA)及週邊電路區 (Periphery Circuits Area ;PA)，並於上述半 U上，已設置有第一氧化層12，其厚度介於5〇〜i〇〇埃- A ^ ’其形成方法為於高溫含氧的環境下，利用熱氧化法 所形成。並於記憶體單元區MA内之第一氧化層i 2上 二:個由第一複晶石夕層“與閉極間介電_ 1 閘極（floating gate):结構，其中於記憶體單元區内之 置閘極相接觸之第一氧化層1 2即a 士、办罢q 層（turning oxide). ^此⑦置閘極之隨穿氧化 接著並全面性地沉積第二複晶 憶體單元區MA與週邊電路區PA之 1 、’ I盍=上述記 性蝕刻去除上述週邊電路區内第—: 。接著，選擇、 止於第-氧化層12上。㈣—複晶石夕層Μ，並飯刻停 接著，請參閱第_，於高溫含氧的環境下，利用熱〇548-84947W (N) * 91079; Shawn.ptd Page 4 556324 V. Description of the invention (2), process' such as high voltage transistor (high voltage transistor) process, its use can be used as flash memory system process In the flash memory product line (1 η- 1 in ne), instant test components for electrical testing and related power drive applications of memory. The following is a schematic diagram of the process cross-section of the use of the split gate flash memory shown in Figures 1a to 1d to illustrate the control gate of the split gate flash memory in the memory cell area of the conventional technology. Method for manufacturing peripheral transistors in a pole and peripheral circuit area. First, please refer to FIG. 1a, which is a semiconductor substrate, such as a semiconductor silicon substrate, and is divided into a memory device area (MA) and a peripheral circuit area ( Periphery Circuits Area; PA), and on the above-mentioned half U, a first oxide layer 12 has been provided, and its thickness is between 50 and 100 angstroms-A ^ 'Its formation method is in a high-temperature oxygen-containing environment, Formed by thermal oxidation. And two on the first oxide layer i 2 in the memory cell area MA: a dielectric layer between the first polycrystalline stone layer and the closed electrode_ 1 floating gate: structure, in the memory cell The first oxide layer 12 in contact with the gate electrode in the region is a layer and a layer of turning oxide. ^ The gate electrode is subsequently oxidized and then a second complex crystal body is deposited in a comprehensive manner. 1 of the cell area MA and the peripheral circuit area PA, 'I 盍 = the above-mentioned memory etching removes the first-in the peripheral circuit area. Then, select and stop on the first oxide layer 12. ㈣-polycrystalline stone layer M , And the meal stops. Then, see page _, using heat in a high-temperature oxygen-containing environment.

556324 五、發明說明（3) 氧化法形成複晶石夕氧化層20於記憶體單元區^内之上述第 二複晶矽層上，其厚度介於504 90埃（A)。並亦於週邊電 路區PA内第一氧化層12上形成一第二週邊氧化層2〇，，其 厚度介於5 0〜1 9 0埃（A )。接著全面性地沉積一第三複晶矽 層2 2於上述記憶體單元區MA及週邊電路區pA内之既有結構 上’其方法例如為化學氣相沉積法（chemical vap〇r deposition ;CVD)，其厚度介於 1〇〇〇 〜3〇〇〇 埃（a)。接著 塗佈光阻24並利用第1光罩（Mask 1 )並配合微影及顯影程 序，利用溶劑去除顯影後之光阻材料最後於週邊電路區p A 内形成至少一個由光阻形成之閘極光阻圖案2 4，，用以進 步疋義出週邊電路區P A内之閘極圖案，值得注意的，此 時於記憶體單元區Μ A内則為一光阻層2 4所覆蓋。 請繼續參閱第1 c圖，接著利用乾蝕刻法例如為反應性 離子蝕刻法（Reactive Ion Etching ;RIE)，以去除週邊 電路區PA内未受光阻圖案保護之第三複晶矽層2 2，並蝕刻 停止於複晶矽氧化層2 〇與第二週邊氧化層2 〇，上，最後於 週邊電路區P A内形成組成週邊電晶體之具有閘極圖案第三 複晶矽層22，並接著利用溶劑去除光阻層24以及閘極光阻 圖案24 。接著再塗佈光阻於上述週邊電路區pa及記憶體 單元區MA内，並利用第2光罩（Mask 2)並配合微影及&影 程序，利用溶劑去除記憶體單元區MA内之光阻材料最後於 週邊電路區PA内之既有結構上形成之光阻層26，以作為後 續蝕刻製程之保護層。 ” 上述反應性離子蝕刻法（1^3〇1：丨¥61〇11£1：(：11丨11§;556324 V. Description of the invention (3) The polycrystalline oxide layer 20 is formed by the oxidation method on the above-mentioned second polycrystalline silicon layer in the memory cell region ^, and its thickness is between 504 and 90 Angstroms (A). A second peripheral oxide layer 20 is also formed on the first oxide layer 12 in the peripheral circuit area PA, and its thickness is between 50 and 190 angstroms (A). Next, a third polycrystalline silicon layer 22 is deposited on the existing structure in the memory cell area MA and the peripheral circuit area pA. The method is, for example, chemical vapor deposition (CVD). ), And its thickness is between 1000 and 3,000 Angstroms (a). Then, a photoresist 24 is applied, and a first photomask (Mask 1) is used in conjunction with the lithography and development procedures to remove the developed photoresist material by using a solvent. Finally, at least one photoresist gate is formed in the peripheral circuit area p A The aurora pattern 24 is used to improve the gate pattern in the peripheral circuit area PA. It is worth noting that a photoresist layer 24 is covered in the memory cell area M A at this time. Please continue to refer to FIG. 1c, and then use a dry etching method such as a reactive ion etching method (Reactive Ion Etching; RIE) to remove the third polycrystalline silicon layer 22 in the peripheral circuit area PA that is not protected by the photoresist pattern. The etching is stopped on the polycrystalline silicon oxide layer 20 and the second peripheral oxide layer 20, and finally a third polycrystalline silicon layer 22 with a gate pattern constituting a peripheral transistor is formed in the peripheral circuit area PA, and then used The solvent removes the photoresist layer 24 and the gate photoresist pattern 24. Then, a photoresist is coated on the peripheral circuit area pa and the memory cell area MA, and a second photomask (Mask 2) is used in conjunction with the lithography and & shadow program to remove the solvent in the memory cell area MA with a solvent. The photoresist material finally forms a photoresist layer 26 on the existing structure in the peripheral circuit area PA as a protective layer for the subsequent etching process. ”The above reactive ion etching method (1 ^ 3〇1: 丨 ¥ 61〇11 £ 1 :(: 11 丨 11§;

〇548-8494TWF(N) ； 91079 ： Shawn.ptd 第6頁 556324 五、發明說明（4) R 1 E )，係利用含有四氟化碳、氯氣、溴化氫與氧氣之氣體 作為蝕刻氣體，並於主蝕刻步驟（Mai n Etching ; Μ/E)完 成後更包括一過度蝕刻步驟（Over Etching ; 0/E)，以確 保上述之複晶矽層已被蝕刻完畢，最後形成具有閘極圖案 之第三複晶矽層22於週邊電路區PA内，以作為組成週邊電 晶體之閘極。 接著請參閱第1 d圖，接著利用濕蝕刻法去除記憶體單 元區内MA内之第三複晶矽層22，接著更利用浸濕法（wet d i P )，以去除記憶體單元區内Μ A之複晶矽氧化層2 0。接著 再利用乾蝕刻法，例如為反應性離子蝕刻法（Reactive〇548-8494TWF (N); 91079: Shawn.ptd Page 6 556324 V. Description of the Invention (4) R 1 E) is a gas containing carbon tetrafluoride, chlorine, hydrogen bromide and oxygen as the etching gas. After the main etching step (Mai n Etching; M / E) is completed, an over-etching step (Over Etching; 0 / E) is included to ensure that the above-mentioned polycrystalline silicon layer has been etched, and a gate pattern is finally formed. The third polycrystalline silicon layer 22 is located in the peripheral circuit area PA to serve as a gate for forming a peripheral transistor. Next, referring to FIG. 1 d, the third polycrystalline silicon layer 22 in MA in the memory cell region is removed by a wet etching method, and then the wet di P method is used to remove M in the memory cell region. A of the polycrystalline silicon oxide layer 20. Then, dry etching is used, such as reactive ion etching (Reactive Ion Etching).

Ion Etching ;RIE)，回 #(etch back)記憶體單元區内 ΜΑ 上之第二複晶石夕層1 8，並姓刻停止於閘極間介電層1 6與第 一氧化層12上，最後形成兩間隔物狀（spacer look)之第 一複晶石夕層1 8於浮置閘極1 4兩側，其用途為此快閃記憶體 之控制閘極（control gate ;CG)，而先前存在於週邊電路 區内之第三複晶石夕層22即為構成週邊電晶體之複晶石夕層。 上述反應性離子餘刻法（R e a c t i v e I ο η E t c h i n g ; RIE) ’係利用含有氯氣與氧氣之氣體作為餘刻氣體，於主 蝕刻步驟（Mai n Etching ; Μ/E)後，亦具有一過度蝕刻步 驟（Over Etching ; 0/E)，以確保上述之複晶矽層已被蝕 刻完畢。此時，於記憶單元區MA内具有間隔物狀（spacer look)之控制閘極以及於週邊電路區PA内之週邊電晶體之 製程便已完成。 而於實際之週邊電晶體之製程中，其閘極氧化層的厚Ion Etching; RIE), ## etch back) The second polycrystalline stone layer 18 on the MA in the memory cell area, and the last name is engraved on the inter-gate dielectric layer 16 and the first oxide layer 12 Finally, two spacer-shaped first polycrystalline stone layers 18 are formed on both sides of the floating gate electrode 14 for use as a control gate (CG) of the flash memory. The third polycrystalline stone layer 22 previously existing in the peripheral circuit area is a polycrystalline stone layer that constitutes a peripheral transistor. The above-mentioned reactive ion etching method (Reactive I ο η E tching; RIE) 'uses a gas containing chlorine and oxygen as the etching gas. After the main etching step (Mai n Etching; M / E), Over Etching (Over Etching; 0 / E) to ensure that the above-mentioned polycrystalline silicon layer has been etched. At this time, the process of forming a spacer-like control gate in the memory cell area MA and a peripheral transistor in the peripheral circuit area PA is completed. In the actual manufacturing process of peripheral transistors, the thickness of the gate oxide layer is

0548-8494TWF(N) ： 91079 ： Shawn.ptd 第7頁 556324 五、發明說明（5) 一氧化層12與第二週邊氧化層2〇,之複合 +、制 、厚度，無法視需要自由地調整。再者， 上述衣程需要兩道光罩|y (望 ^ η ^ _ Μ 让以&lt; 70皁表私（第1、第2光罩），且步驟繁 徒曰衣程所需時間，而影響產品產出速度。 【發明概要】 f ^ ^ ^此本發明的主要目的就是提供一種快閃記憶 ^ / 且本發明的目的在於提供一種可同時形成快 閃記憶體之？制閘極與週邊電晶體的製造方法，能夠同時 地形成記憶單元區内快閃記憶體之控制閘極以及週邊電路 區内之週邊電晶體，因此可以簡化製程”咸少製程所需步 驟，提升量產速度，減低生產成本。 根據上述目的，本發明提供一種具有週邊電晶體的分 離閘極式快閃記憶體的製造方法，包括下列步驟： 和1供半導體基底11〇，具有記憶體單元區ΜΑ及週邊電 路區ΡΑ，半導體基底110上設置有第一氧化層112，且記憶 體單元區ΜΑ之第一氧化層Π2層上更設有至少一個由第一 複晶矽層11 4與閘極間介電層11 6所組成之浮置閘極；全面 性地〉儿積第一複晶石夕層11 8覆於記憶體單元區Μ Α與週邊電 路區PA上之第一氧化層112 ;形成閘極光阻圖案120於週邊 電路區P A内之第二複晶石夕層11 8上；以及進行一乾餘刻製 程，並蝕刻停止於第一氧化層11 2上，同時地於週邊電路 區P A内形成具閘極圖案之第二複晶矽層11 8以作為組成週0548-8494TWF (N): 91079: Shawn.ptd Page 7 556324 V. Description of the invention (5) The composite +, manufacturing, and thickness of the oxide layer 12 and the second peripheral oxide layer 20, cannot be freely adjusted as required. . In addition, the above clothing process requires two masks | y (望 ^ η ^ _ Μ to let <70 soap table private (the first and second masks), and the steps are complicated and the time required for the clothing process is affected, which affects Product output speed. [Summary of the invention] f ^ ^ ^ The main purpose of the present invention is to provide a flash memory ^ / and the purpose of the present invention is to provide a flash memory can be formed simultaneously? The crystal manufacturing method can simultaneously form the control gate of the flash memory in the memory cell area and the peripheral transistors in the peripheral circuit area, so that the steps required for the manufacturing process can be simplified, the mass production speed can be increased, and the production can be reduced. According to the above objective, the present invention provides a method for manufacturing a split gate flash memory with peripheral transistors, including the following steps: and 1 for a semiconductor substrate 110, having a memory cell region MA and a peripheral circuit region PA A first oxide layer 112 is disposed on the semiconductor substrate 110, and at least one first polycrystalline silicon layer 11 4 and a gate-to-gate dielectric layer 11 6 are disposed on the first oxide layer Π2 layer of the memory cell region MA. A floating gate composed of the semiconductors; comprehensively, the first polycrystalline spar layer 11 8 covers the first oxide layer 112 on the memory cell area Μ Α and the peripheral circuit area PA; a gate photoresist pattern 120 is formed On the second polycrystalline spar layer 118 in the peripheral circuit area PA; and performing a dry-etching process and stopping the etching on the first oxide layer 112, and simultaneously forming a gate pattern in the peripheral circuit area PA with a gate pattern The second polycrystalline silicon layer 11 8 is used as a composition cycle

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邊電晶體之閘極以及於記憶體 間隔物壯彳 〜 早凡區Μ A内形成複數個具有 间阳初狀（spacer i〇ok)之第- ^ 側从作為此快閃記憶體之控制閘極。 扣 【發明之詳細說明】 、特徵、和優點能更明 並配合所附圖式，作詳 為讓本發明之上述和其他目的 顯易僅，下文特舉出較佳實施例， 細說明如下： 【實施例] 心以：第2:;〜第2c圖所示之分離閘極式快閃記 隐體的I私剖面不思圖，以說明本發明之 = 式快閃記憶體之控制問極與週邊 之週邊電晶體的製造方法。 相丨如：先：請參照第23圖，該圖符號110為半導體基底， 導體石夕基底’並於上述半導體基底上可區 二出此憶體單u(MemQry device Area ;ma)及週邊電路 riPh6ry Circuits Area ;PA)，並於上述半導體某 氏ljO上’設置有第一氧化層112，以作為閘介電層 dielectric)使用，其材質為二氧化矽，其厚度介於 50〜100埃（A )，其形成方法為於高溫含氧的環境下，利用 熱氧化法所形成。上述記憶體單元區M A之第一氧化層11 2 上更設置有至少一個由第一複晶矽層丨14與閘極間介q電層 116所組成之浮置閘極（n〇ating gate)，而與上述之浮曰置The gate of the side transistor and the memory spacer are strong ~ The first-^ side with space i0ok is formed in the early fan area ΜA, and it is used as the control gate of this flash memory pole. [Detailed description of the invention], features, and advantages can be made more clear and in conjunction with the drawings, in order to make the above and other objects of the present invention easier, only the preferred embodiments are exemplified below, detailed description is as follows: [Embodiment] Thoughts: Figure 2; ~ ~ 2c Figure I private profile of the split gate flash memory hidden figure to illustrate the control method of the = flash memory of the present invention and Method for manufacturing peripheral transistors. Like this: First: Please refer to FIG. 23, where the symbol 110 is a semiconductor substrate, a conductor stone substrate, and the memQry device area (ma) and peripheral circuits can be distinguished on the semiconductor substrate. riPh6ry Circuits Area; PA), and a first oxide layer 112 is provided on the semiconductor ljO as a gate dielectric layer (dielectric). Its material is silicon dioxide, and its thickness is between 50 and 100 angstroms (A ), Which is formed by thermal oxidation in a high-temperature oxygen-containing environment. The first oxide layer 11 2 of the memory cell area MA is further provided with at least one floating gate composed of a first polycrystalline silicon layer 14 and a gate-to-gate dielectric layer 116. , While floating with the above

556324556324

，，相接觸之第一氧化層丨丨2即可視為為此浮置閘極之隧 牙氧化層（tunneling oxide)，其中上述第一複晶矽層114 之厚度介於500〜2000埃（A)而上述閘極間介電層116之厚 度介於50〜1 90埃（A )，此閘極間介電層丨丨6其材質為二氧 化石夕或二氧化矽/氮化矽/二氧化矽（〇N〇)材料。、 接著’請參閱第2b圖，全面性地沉積第二複晶石夕層 118並覆於上述δ己憶體早元區與週邊電路區之既有結構 上’其厚度介於500〜300 0埃（Α)。接著塗佈光阻材料，並 利用第1光罩（M a s k 1 )並配合微影及顯影程序，利用溶劑 去除顯影後之光阻材料最後於週邊電路區pA内形成至少一 個之閘極光阻圖案1 2 〇。 請繼續參閱第2c圖，接著利用乾蝕刻法例如為反應性 離子蝕刻法（Reactive Ion Etching ;RIE)，以回蝕（etch back)記憶體單元區MA内以及週邊電路區pA内未受上述閘 極光阻圖案1 2 0保護之第二複晶矽層丨丨8，並蝕刻停止於第 一氧化層112上，於記憶體單元區MA内之上述浮置閘極兩 側形成兩間隙物狀（spacer i〇〇k)之第二複晶矽層118，此 第二複晶矽層11 8即為此快閃記憶體之控制閘極，並同時 地於週邊電路區P A内形成具有閘極圖案之第二複晶矽層 Π 8 ’此位於週邊電路區p A内並具有閘極圖案之第二複晶 石夕層11 8即為組成週邊電晶體之閘極。接著再利用溶劑去 除位於週邊電路區PA内第二複晶矽層丨丨2上方之閘極光阻 圖案1 20 ’即完成本發明之可同時形成快閃記憶體之控制 閘極與週邊電晶體的製造方法。The contacting first oxide layer 2 can be regarded as the tunneling oxide of the floating gate electrode. The thickness of the first polycrystalline silicon layer 114 is between 500 and 2000 angstroms (A ) And the thickness of the inter-gate dielectric layer 116 is between 50 and 1 90 Angstroms (A), and the inter-gate dielectric layer is made of stone dioxide or silicon dioxide / silicon nitride / silicon Silicon oxide (〇NO) material. Then, “Please refer to FIG. 2b, comprehensively deposit the second polycrystalite layer 118 and cover the existing structure of the delta element memory early region and the surrounding circuit region.” Its thickness is between 500 and 300. Egypt (Α). Then, a photoresist material is applied, and a photoresist material is used to remove the developed photoresist material by using a first photomask (M ask 1) and a lithography and development process. Finally, at least one gate photoresist pattern is formed in the peripheral circuit area pA. 1 2 0. Please continue to refer to FIG. 2c, and then use a dry etching method such as a reactive ion etching method (Reactive Ion Etching; RIE) to etch back the memory cell region MA and the peripheral circuit region pA without being subjected to the above gates. The second polycrystalline silicon layer protected by the aurora pattern 1 2 0 and 8 is etched and stopped on the first oxide layer 112. Two gaps are formed on both sides of the floating gate in the memory cell area MA ( spacer i〇〇k) second polycrystalline silicon layer 118, this second polycrystalline silicon layer 118 is the control gate of the flash memory, and simultaneously has a gate pattern in the peripheral circuit area PA The second polycrystalline silicon layer Π 8 ′ is located in the peripheral circuit area p A and has a second polycrystalline stone layer 11 8 that is a gate electrode constituting a peripheral transistor. Then, the solvent is used to remove the gate photoresist pattern 1 20 ′ located above the second polycrystalline silicon layer in the peripheral circuit area PA, and the control gate and peripheral transistors of the present invention can be formed simultaneously. Production method.

0548-8494TWF(N) ； 91079 ； Shawn.ptd 第10頁 556324 五、發明說明（8) 而上述之反應性離子蝕刻法（Reactive Ion Etching ; RIE)，係利用含有氣氣（ci2)、四氟化碳（CF4)或 溴化氫（HBr )之氣體作為蝕刻氣體，具有下列兩個主要步 驟：第一為擊穿步驟（break through ; B/T)，以去除於第 二複晶石夕層118表面上之原生氧化層（Native oxide ;未顯 不於圖上）’而其餘刻條件為壓力介於1〜2〇毫托（mTorr)、 電漿源功率介於200〜1 0 0 0瓦（W)、偏壓功率介於10〜3 0 0瓦 (w)、钱刻氣體流量以氣氣為例其流量介於50〜150sccm以 及蝕刻時間介於2〜20秒；第二為主蝕刻步驟（Main Etching ;M/E)，以對未受未受光阻圖案保護之第二複晶 矽層118進行蝕刻，而其蝕刻條件為壓力介於卜1〇〇毫托 (inTorr)、電衆源功率介於2〇〇〜i〇0〇e(w)、偏壓功率介於 10〜300瓦（W)、蝕刻氣體流量以氣氣為例其流量介於 50〜150sccm以及蝕刻時間介於5〜8〇秒。而於上述之擊穿步 驟（break through ; B/T)前，可依照實際蝕刻機台類型， 更加入一起始步驟以確認機台參數是否達到設定值，其中 該起始步驟之姓刻條件為，壓力介於卜2〇毫托（mT〇rr)'、 電聚源功率介於200〜1 00 0瓦（W)、偏壓功率介於1〇〜3〇〇瓦 (w)、蝕刻氣體流量以氣氣為例其流量介於5〇〜15〇sccm&amp; 及蝕刻時間介於2〜20秒。 雖然本發明已以較佳實施例揭露如上，麸並 限定本發明η壬何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保 範圍當視後附之申請專利範圍所界定者為準。0548-8494TWF (N); 91079; Shawn.ptd Page 10 556324 V. Description of the invention (8) The above-mentioned reactive ion etching method (Reactive Ion Etching; RIE) is based on the use of gas (ci2), tetrafluoride Carbon dioxide (CF4) or hydrogen bromide (HBr) gas as an etching gas has the following two main steps: the first is a break through step (B / T) to remove the second polycrystalline stone layer The native oxide layer on the surface of 118 (not shown on the picture) 'and the remaining conditions are a pressure of 1 ~ 20 millitorr (mTorr) and a plasma source power of 200 ~ 100 watt (W), bias power between 10 ~ 300 watts (w), gas flow rate of gas engraved gas, for example, its flow rate is between 50 ~ 150sccm and etching time is between 2 ~ 20 seconds; the second is the main etching Step (Main Etching; M / E), to etch the second polycrystalline silicon layer 118 that is not protected by the unresisted photoresist pattern, and the etching condition is a pressure between 100 millitorr (inTorr), electric mass The source power is between 200 ~ 100e (w), the bias power is between 10 ~ 300 watts (W), the flow rate of the etching gas is taken as an example, and the flow rate is between 50 ~ 150sccm and etching time is between 5 ~ 80 seconds. Before the break through step (B / T) described above, an initial step can be added according to the actual etching machine type to confirm whether the machine parameters have reached the set value. The initial conditions of the initial step are: , The pressure is between 20 millitorr (mT〇rr) ', the power of the electro-polymer source is 200 ~ 100 watts (W), the bias power is between 10 ~ 300 watts (w), the etching gas The flow rate is taken as an example. The flow rate is between 50 and 150 sccm &amp; and the etching time is between 2 and 20 seconds. Although the present invention has been disclosed in the preferred embodiment as above, the gluten is limited to those skilled in the art. Without departing from the spirit and scope of the present invention, it can be modified and retouched. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

556324 圖式簡單說明 第1 a〜第1 d圖係習知之分離閘極式快閃記憶體控制閘 極與週邊電晶體的製程剖面示意圖。 第2a〜第2c圖係根據本發明實施例可同時形成分離閘 極式快閃記憶體之控制閘極與週邊電晶體的的製程剖面示 意圖。 【符號說明】 10、110〜半導體基底； 12、112〜第一氧化層； 14、114〜第一複晶矽層；16、116〜閘極間介電層； 1 8、11 8〜第二複晶矽層；2 0〜複晶矽氧化層； 2 0 ’〜第二週邊氧化層； 2 2〜第三複晶矽層； 24、26〜光阻層； 24’ 、120〜閘極光阻圖案； MA〜記憶體單元區； PA〜週邊電路區。556324 Brief description of diagrams Figures 1a to 1d are cross-sectional schematic diagrams of the conventional process of separating the gate type flash memory control gate and surrounding transistors. Figures 2a to 2c are schematic cross-sectional views of the manufacturing process of a control gate and peripheral transistors that can simultaneously form a separate gate flash memory according to an embodiment of the present invention. [Symbol description] 10, 110 ~ semiconductor substrate; 12, 112 ~ first oxide layer; 14, 114 ~ first polycrystalline silicon layer; 16, 116 ~ inter-gate dielectric layer; 18, 11 8 ~ second Polycrystalline silicon layer; 20 ~ polycrystalline silicon oxide layer; 20 '~ second peripheral oxide layer; 22 ~ third polycrystalline silicon layer; 24, 26 ~ photoresist layer; 24', 120 ~ gate photoresist Pattern; MA ~ memory cell area; PA ~ peripheral circuit area.

0548-8494TWF(N) ； 91079 ； Shawn.ptd 第12頁0548-8494TWF (N); 91079; Shawn.ptd page 12

Claims (1)

556324 六、申請專利範圍 一種可同時形成快 包括以下 提供一半導體基底， 半導體基底 閘介電層上 介電層所組 體的製造方法 邊電路區，該 體單元區之該 層與一閘極間 全面性地 該週邊電路區 形成至少 一複晶碎層上 沉積一第二 上之閘介電 一個閘極光 時地於 複晶碎 元區内 晶矽層 極0 2· 體之控 材質為 3. 體之控 電層材 材料。 4. :以及 進行一乾蝕刻製程， 該週邊電路區内形 層以作為組成週邊 形成複數個具有間 於該浮置閘極兩側 ::?體之控制閘極與週邊電晶 一記憶體單元區·及-週 =有—閘介電層，且該記憶 $ =、Λ至少—個由一第一複晶矽 成之子置閘極； 複日日矽層覆於該記憶體單元區與 層； ’、 阻圖案於該週邊電路區内之該第 並餘刻停止於該閘介電層上，同 成至少一個之具閘極圖案之第二 電晶體之閘極以及於該記憶體單 隔物狀（spacer look)之第二複 ，以作為該快閃記憶體之控制閘 如申請 制閘極 二氧化 如申請 制閘極 質為二 專利範圍第1項所述之可同時形成快閃記憶 與週邊電晶體的製造方法’其中該閘介電層 &gt;5^ 〇 專利範圍第1項所述之可同時形成快閃記憶 與週邊電晶體的製造方法，其中該閘極間介 氧化矽或二氧化矽/氮化矽/二氧化矽（0N0) 如申請專利範圍第1項所述之可同時形成快閃記憶556324 6. Scope of patent application A method for simultaneously forming a semiconductor substrate including a semiconductor substrate, a dielectric layer on a dielectric layer on a semiconductor substrate, and a manufacturing method of a dielectric layer on a semiconductor circuit side circuit region, between the layer of the body cell region and a gate electrode Comprehensively, the peripheral circuit area forms at least one polycrystalline debris layer, a second upper dielectric is deposited, and a gate aurora is present in the polycrystalline debris region. The control material of the crystalline silicon layer is 3. Material of electric control layer material. 4 .: And a dry etching process is performed, and the forming layer in the peripheral circuit area is used as a composition to form a plurality of perimeters with the gate between the floating gate and the peripheral transistor-memory cell area. And-week = yes-gate dielectric layer, and the memory $ =, Λ at least-a son made of a first polycrystalline silicon is placed on the gate; the day after day silicon layer covers the memory cell area and layer; '、 The resistance pattern in the peripheral circuit area stops on the gate dielectric layer for the first time and forms at least one gate electrode of the second transistor with a gate pattern and a single spacer in the memory. The second copy of the spacer look is used as the control gate of the flash memory. If you apply for gate dioxide, you can form a flash memory at the same time as described in the first patent scope. Manufacturing method of peripheral transistor, wherein the gate dielectric layer &gt; 5 ^ 〇 Patent scope item 1 is a manufacturing method capable of forming flash memory and peripheral transistor at the same time, wherein the gate dielectric dielectric silicon oxide or Silicon oxide / silicon nitride / silicon dioxide (0N0) The simultaneous formation of a flash memory 0548·8494TWF(N); 91079 ; Shawn.ptd 第13頁 556324 -------- 申請專利範圍 ' --- L之控制閘極與週邊電晶體的製造方法，其中該乾蝕刻製 L，包括以下步驟·· 程，包括以下步驟： 一、進行一擊穿步驟（break through ;Β/Τ)，以兹刻該第 複89石夕層表面上之原生氧化層（native oxide);以及 第二複晶石夕層 進行一主蝕刻步驟（main etching ; Μ/E)，以蝕刻該 複晶石々js Λ 體 ·如申請專利範圍第4項所述之可同時形成快閃記憶 二之控制閘極與週邊電晶體的製造方法，其中該乾蝕刻製 於進行一擊穿（break through ;Β/Τ)步驟前可更包括一 起始步驟以確認機台參數是否達到設定值。 6 ·如申請專利範圍第5項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該起始步驟 之姓刻條件為，電漿源功率介於20 0〜1 000瓦（W)，偏壓功 率介於1 0〜300瓦（W)。 7·如申請專利範圍第5項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該起始步驟 之钱刻條件為，壓力介於丨〜2〇毫托（mTorr)。 8 ·如申請專利範圍第4項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該擊穿步驟 之钱刻條件為，電漿源功率介於2 0 0〜1 0 0 0瓦（W )，偏壓功 率介於10〜300瓦（W)。 9 ·如申請專利範圍第4項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該擊穿步驟 之蝕刻條件為，壓力介於1〜2〇毫托（mTorr)。0548 · 8494TWF (N); 91079; Shawn.ptd page 13 556324 -------- Patent application scope '--- L manufacturing method of control gate and peripheral transistor, wherein the dry etching process L , Including the following steps: The process includes the following steps: First, a break through step (B / T) to etch the native oxide layer (native oxide) on the surface of the 89th Shi Xi layer; and The second polycrystalline stone layer is subjected to a main etching step (M / E) to etch the polycrystalline stone 々 · body. As described in item 4 of the scope of patent application, flash memory 2 can be formed simultaneously. The manufacturing method of controlling the gate electrode and the surrounding transistor, wherein the dry etching process may further include an initial step to confirm whether the machine parameter reaches the set value before performing a break through (B / T) step. 6 · The manufacturing method of the control gate and the peripheral transistor that can form flash memory at the same time as described in item 5 of the scope of the patent application, wherein the initial condition of the initial step is that the power of the plasma source is between 20 0 ~ 1 000 watts (W) and bias power between 10 and 300 watts (W). 7. The manufacturing method of the control gate and the peripheral transistor that can form a flash memory at the same time as described in item 5 of the scope of the patent application, wherein the initial step is engraved under the condition that the pressure is between 丨 ~ 20 MTorr. 8 · The manufacturing method of the control gate and the peripheral transistor that can form a flash memory at the same time as described in item 4 of the scope of the patent application, wherein the condition of the breakdown step is that the power of the plasma source is between 20 0 ~ 100 watts (W), and the bias power is between 10 ~ 300 watts (W). 9 · The manufacturing method of the control gate and the peripheral transistor that can form a flash memory at the same time as described in item 4 of the scope of the patent application, wherein the etching condition of the breakdown step is that the pressure is between 1 and 20 millitorr (MTorr). 556324 、申請專利範圍 I 〇 ·如申請專利範圍第4項所述之可同時形成快閃圮憶 體之控制閘極與週邊電晶體的製造方法，其中該主蝕刻步 驟之餘刻條件為，電装源功率介於2 0 0〜1 0 0 0瓦（W)’偏壓 功率介於10〜3〇〇瓦（w)。 II ·如申請專利範圍第4項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該主钱刻步 驟之餘刻條件為，壓力介於1〜1 〇 0毫托（m T 〇 r r)。 1 2·如申請專利範圍第1項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該閘介電層 之厚度介於50〜190埃（Α)。 1 3 ·如申請專利範圍第1項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該第二複晶 層之厚度介於5 0 0〜300 0埃（Α)。 1 4·如申請專利範圍第1項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該第二複晶 層之形成方法為化學氣相沉積法。 1 5 ·如申請專利範圍第1項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該閘極間介 電層之厚度介於5〇〜190埃（Α)。 1 6 ·如申請專利範圍第1項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該第一複晶 石夕層之厚度介於50 0〜2000埃（Α)。 1 7 ·如申請專利範圍第1項所述之可同時形成快閃記憶 體之控制閘極與週邊電晶體的製造方法，其中該快閃記憶556324. Application scope of patent I 〇. The manufacturing method of the control gate and peripheral transistor that can form flash memory at the same time as described in item 4 of the scope of patent application, wherein the remaining conditions of the main etching step are: The source power is between 200 and 100 watts (W). The bias power is between 10 and 300 watts (w). II · The manufacturing method of the control gate and the peripheral transistor that can form a flash memory at the same time as described in item 4 of the scope of the patent application, wherein the remaining condition of the main money engraving step is that the pressure is between 1 and 1 〇 0 millitorr (m T rr). 1 2. The manufacturing method of a control gate and peripheral transistors that can simultaneously form a flash memory as described in item 1 of the scope of the patent application, wherein the thickness of the gate dielectric layer is between 50 and 190 Angstroms (A). 1 3 · The manufacturing method of the control gate and peripheral transistors that can simultaneously form a flash memory as described in item 1 of the scope of the patent application, wherein the thickness of the second polycrystalline layer is between 50 and 300 angstroms. (Α). 14. The manufacturing method of the control gate and the surrounding transistor which can simultaneously form a flash memory as described in item 1 of the scope of the patent application, wherein the method of forming the second polycrystalline layer is a chemical vapor deposition method. 1 5 · The manufacturing method of a control gate and peripheral transistors that can simultaneously form a flash memory as described in item 1 of the scope of the patent application, wherein the thickness of the dielectric layer between the gates is 50 to 190 angstroms ( Α). 16 · The manufacturing method of the control gate and peripheral transistors that can simultaneously form a flash memory as described in item 1 of the scope of the patent application, wherein the thickness of the first polycrystalline stone layer is between 50 and 2000 angstroms (Α). 1 7 · The manufacturing method of the control gate and the peripheral transistor that can simultaneously form a flash memory as described in item 1 of the scope of patent application, wherein the flash memory 0548-8494W(N) ； 91079 ； Shawn.ptd 第15頁 5563240548-8494W (N); 91079; Shawn.ptd page 15 556324 體。 六、申請專利範圍 體為一分離閘極式快閃記憶 閘極與週邊電 1 8 · —種可同時形成快閃記憶體之控制 晶體的製造方法，包括以下步驟： 提供一半導體基底’至少具有一記憶體單 邊電路區，該半導體基底上設置有一第一及一週 憶體單元區之該第一氧化層上更設有至少一個由一第;_ j 晶石夕層與一閘極間介電層所組成之浮置問極； H 全面性地沉積一第二複晶石夕層覆於該記憶體單元區與 該週邊電路區上之第一氧化層； 〃 形成至少一個閘極光阻圖案於該週邊電路區内之該第 一複晶碎層上；以及 使用含氣氣、四氟化碳（CF4)或溴化氫（HBr)之蝕刻氣 體進行一乾蝕刻製程，並蝕刻停止於該第一氧化層上，同 時地於該週邊電路區内形成至少一個之具閘極圖案之第二 複晶矽層以作為組成週邊電晶體之閘極以及於該記憶體單 元區内形成複數個具有間隔物狀（spacer look)之第二複 晶矽層於該浮置閘極兩側，以作為該快閃記憶體之控制閘 極0 1 9 ·如申請專利範圍第1 8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該第一氧 化層材質為二氧化石夕。 2 0 ·如申請專利範圍第1 8項所述之可同時形成快閃吕己 憶體之控制閘極與週邊電晶體的製造方法，其中該閘極間 介電層材質為二氧化矽或二氧化矽/氮化矽/二氧化矽body. 6. The scope of the patent application is a separate gate flash memory gate and peripheral circuit. A manufacturing method of a control crystal that can simultaneously form a flash memory includes the following steps: Provide a semiconductor substrate with at least A memory unilateral circuit area, the semiconductor substrate is provided with a first and a week memory cell unit area, and the first oxide layer is further provided with at least one first; a spar layer and a gate A floating interlayer composed of electrical layers; H comprehensively depositing a second polycrystalline stone layer overlying the first oxide layer on the memory cell area and the peripheral circuit area; 至少 forming at least one gate photoresist pattern On the first multi-crystal chip in the peripheral circuit region; and performing a dry etching process using an etching gas containing gas, carbon tetrafluoride (CF4) or hydrogen bromide (HBr), and the etching stops at the first On the oxide layer, at least one second polycrystalline silicon layer having a gate pattern is simultaneously formed in the peripheral circuit region to serve as a gate constituting a peripheral transistor and a plurality of gaps are formed in the memory cell region. A spacer-looking second polycrystalline silicon layer is formed on both sides of the floating gate to serve as the control gate of the flash memory. 0 1 9 · Can be formed simultaneously as described in item 18 of the scope of patent application A method for manufacturing a control gate and a peripheral transistor of a flash memory, wherein the material of the first oxide layer is SiO2. 2 · The manufacturing method of the control gate and the surrounding transistor which can form a flash-type Lu Jiyi body simultaneously as described in item 18 of the scope of the patent application, wherein the material of the dielectric layer between the gates is silicon dioxide or Silicon oxide / silicon nitride / silicon dioxide 0548-8494TWF(N) · 91079 ； Shawn.ptd 556324 六、申請專利範圍 (ΟΝΟ)材料。 2 1 ·如申請專利範圍第1 8項所述之可同時形成快閃記 ，體之控制閘極與週邊電晶體的製造方法，其中使用含氯 氣（c“）、四氟化碳（CF4)或溴化氫（HBr)之蝕刻氣體之該乾 蝕刻製程，包括以下步驟： 進行擊穿步驟（break through ;B/T)，以钱刻該第 一複晶石夕層表面上之原生氧化層（native oxide);以及 進行一主蝕刻步驟（main etching ; Μ/E)，以蝕刻該 第二複晶矽層。 2 2 ·如申請專利範圍第2 1項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該乾蝕刻 製程於進行一擊穿（break through ;Β/Τ)步驟前可更包括 一起始步驟以確認機台參數是否達到設定值。 23·如申請專利範圍第22項所述之可同時形成快閃記· 憶體之控制閘極與週邊電晶體的製造方法，其中該起始步 驟之蝕刻條件為，電漿源功率介於2〇〇〜1〇〇〇瓦（W)，偏壓 功率介於10〜300瓦（w)。 2 4 ·如申請專利範圍第2 2項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法’其中該起始步 驟之蝕刻條件為，壓力介於卜2 〇毫托（mT〇rr )，氣氣流量 介於50〜150sccm。 2 5 ·如申請專利範圍第2 1項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該擊穿步 驟之餘刻條件為，電漿源功率介於2 0 0〜1 0 0 0瓦（W )，偏壓0548-8494TWF (N) · 91079; Shawn.ptd 556324 6. Patent application scope (〇ΝΟ) materials. 2 1 · The manufacturing method of flash gate, body control gate and peripheral transistor as described in item 18 of the scope of patent application, which uses chlorine (c "), carbon tetrafluoride (CF4) or The dry etching process of an etching gas of hydrogen bromide (HBr) includes the following steps: a break through step (B / T) is used to engrav a primary oxide layer on the surface of the first polycrystalline stone layer ( native oxide); and performing a main etching step (M / E) to etch the second polycrystalline silicon layer. 2 2 · Flash memory can be formed simultaneously as described in item 21 of the scope of patent application The manufacturing method of controlling the gate electrode and the surrounding transistor, wherein the dry etching process may further include an initial step to confirm whether the machine parameter reaches the set value before performing a break through (B / T) step. 23 · The manufacturing method of the control gate and the peripheral transistor that can form flash memory and memory at the same time as described in the scope of patent application No. 22, wherein the etching condition of the initial step is that the plasma source power is between 2000 ~ 1000 watts (W) with bias power between 10 300 watts (w). 2 4 · The manufacturing method of the control gate and the peripheral transistor that can form a flash memory at the same time as described in item 22 of the scope of the patent application 'wherein the etching conditions of the initial step are: pressure Between 20 millitorr (mT0rr) and air flow between 50 and 150 sccm. 2 5 · The control gate and peripheral power of flash memory can be formed simultaneously as described in item 21 of the patent application scope. A method of manufacturing a crystal, wherein the condition of the rest of the breakdown step is that the power of the plasma source is between 200 and 100 watts (W), and the bias voltage is 0548-8494TWF(N) ： 91079 ； Shawn.ptd 第17頁 556324 六、申請專利範圍 功率介於10〜300瓦（W)。 2 6 ·如申請專利範圍第2 1項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該擊穿步 驟之蝕刻條件為，壓力介於卜20毫托（mTorr)，氣氣流量 介於 5 0 〜1 5 0 s c c m。 2 7 ·如申請專利範圍第2 1項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該主I虫刻 步驟之蝕刻條件為，電漿源功率介於200〜1 0 0 0瓦（W)，偏 壓功率介於10〜300瓦（W)。 2 8.如申請專利範圍第21項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該主蝕刻 步驟之蝕刻條件為，壓力介於1〜1〇〇毫，托（mTorr)，氯氣流 量介於50〜150sccm。 2 9.如申請專利範圍第丨8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該第一氧 化層之厚度介於5〇〜1〇〇埃（入）。 3 0 ·如申請專利範圍第丨8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該第二複 晶層之厚度介於5〇〇〜3〇〇〇埃（A)。 3 1 ·如申請專利範圍第丨8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該第二複 晶層之形成方法為化學氣相沉積法。 3 2 ·如申請專利範圍第丨8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中遠閘極間0548-8494TWF (N): 91079; Shawn.ptd Page 17 556324 6. Scope of patent application Power is between 10 ~ 300 watts (W). 2 6 · The manufacturing method of the control gate and peripheral transistor that can simultaneously form a flash memory as described in item 21 of the scope of the patent application, wherein the etching condition of the breakdown step is that the pressure is between 20 mTorr (MTorr), the air flow is between 50 and 150 sccm. 2 7 · The manufacturing method of the control gate and peripheral transistor that can form flash memory at the same time as described in item 21 of the scope of patent application, wherein the etching conditions of the main worming step are: At 200 ~ 100 watts (W), the bias power is between 10 ~ 300 watts (W). 2 8. The manufacturing method of the control gate and the peripheral transistor that can simultaneously form a flash memory as described in item 21 of the scope of the patent application, wherein the etching conditions of the main etching step are: the pressure is between 1 and 100. Milli, Torr (mTorr), chlorine gas flow is between 50 ~ 150sccm. 2 9. The manufacturing method of the control gate and the peripheral transistor that can simultaneously form a flash memory as described in item 8 of the scope of the patent application, wherein the thickness of the first oxide layer is between 50 and 100 angstroms. (Into). 3 0 · The manufacturing method of the control gate and the peripheral transistor that can form a flash memory at the same time as described in item 8 of the scope of the patent application, wherein the thickness of the second multiple crystal layer is between 500 and 3 〇〇angstrom (A). 3 1 · The manufacturing method of a flash memory memory control gate and a peripheral transistor as described in item 8 of the patent application scope, wherein the method of forming the second compound layer is a chemical vapor deposition method. 3 2 · Manufacturing method of flash gate memory and control transistor as described in item 8 of patent application scope, in which 0548-8494TWF(N) ； 91079 ； Shawn.ptd 第18頁 556324 六、申請專利範圍 介電層之厚度介於50〜190埃（A)。 3 3.如申請專利範圍第1 8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該第一複 晶石夕層之厚度介於500〜2000埃（A)。 3 4.如申請專利範圍第1 8項所述之可同時形成快閃記 憶體之控制閘極與週邊電晶體的製造方法，其中該快閃記 憶體為一分離閘極式快閃記憶體。0548-8494TWF (N); 91079; Shawn.ptd Page 18 556324 VI. Scope of patent application The thickness of the dielectric layer is between 50 and 190 Angstroms (A). 3 3. The manufacturing method of the control gate and peripheral transistors that can simultaneously form a flash memory as described in item 18 of the scope of the patent application, wherein the thickness of the first polycrystalline stone layer is between 500 and 2000 Angstroms (A). 34. The method for manufacturing a flash memory control gate and peripheral transistors as described in item 18 of the scope of patent application, wherein the flash memory is a separate gate flash memory. 〇548-8494TWF(N) ； 91079 ； Shawn.ptd 第19頁〇548-8494TWF (N); 91079; Shawn.ptd page 19