TW556212B - L2 cache LRU generation method and apparatus - Google Patents
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五、發明說明（/ ) 相關申請案的對照 本申請案係依據一美國專利之暫時申請案 (Provisional Application)而主張優先權，其序號乃 _，於西元2001年10月23日提出申請，名稱則為「[2 CACHE LRU GENERATION METHOD AND APPARATUS」。 (一） 發明技術領域： [0001 ]本發明一般係關於應用於微處理器中之關聯快 取記憶體的領域’尤指在一關聯快取記憶體中，快取、線置 換演算法之資訊的儲存與產生。 (二） 發明技術背景、 [0002] 在計异系統中’ 3己憶儲存（memory storage) 一般皆包含一具有不同記憶儲存裝置類型的層級體系。於 該體系中，不同階層的記憶儲存具有不同的特徵，特別是 容量（capacity)及資料存取時間（data access time)。 在該記憶體系中，一個較低的階層係表示其較接近於系統 的處理器。最遠離處理器的記憶裝置通常擁有最大容量， 並且速度最慢。常見的例子有電子機械 (electro-mechanical)裝置，諸如磁帶（magnetic tape)、 光碟（compact disc)以及硬碟儲存裝置，通稱為大容量 儲存裝置，速度雖相對較慢，但可儲存相當大量的資料。 [0003] 於该體系中再下一層的，一般係為包含固態 (solid-state)記憶裝置的系統記憶體，像是動態隨機存 ----------·裝--------訂---------i (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 2 556212 A7 B7 五 、發明說明（>) 取圯憶體（dynamic random access memory，簡稱 DRAM)， 其存取時間雖是大容量儲存袭置的十的數次方之一，但其 容量亦是如此。 [0004] 在該記憶體系中最接近處理器的階層，處理器 之暫存Is不算，通常可發現—個或多個階層的快取記憶 體。快取纪憶體有著極快的存取時間，一個常見例子是靜 悲隨機存取記憶體（static random access memory，簡稱 SRAM)。在許多情況下，一或多個階層的快取記憶體與處 理器被整合在同一個積體電路上。新型的微處理器特別是 如此。快取記憶體儲存了或「快取」了處理器最常從系統 記憶體存取的資料，以便在處理器提出要求時，能提供更 快速的資料存取。 、 i [0005] 快取記憶體一般皆以快取線（cache line)為 單位來儲存資料。常用之快取線大小為32個位元組。由於 快取記憶體小於系統記憶體，所以當資料從快取記憶體讀 取或被寫入快取記憶體時，資料之系統記憶體位址只有一 部份’通常稱為索引部份（index portion)或索引，被用 來定址快址記憶體。其結果是，多個系統記憶體位址會映 射至相同的快取索引（cache index)。在一直接映射快取 記憶體（direct-mapped cache)中，在映射至相同快取索 引的多個系統記憶體位址中，一次只能快取其中一個。所 以，若一個程式經常存取兩個映射至相同快取索引之系統 記憶體位置，則在快取記憶體中，這兩者會經常互相置換。 為了減少這種情形且增進快取效能，一般皆使用關聯快取V. Description of the Invention (/) Comparison of related applications This application claims priority based on a provisional application of a US patent. Its serial number is _, and was filed on October 23, 2001. "[2 CACHE LRU GENERATION METHOD AND APPARATUS". (1) Technical Field of the Invention: [0001] The present invention relates generally to the field of associative cache memory used in microprocessors, especially information of cache and line replacement algorithms in an associative cache memory. Storage and generation. (II) Background of the Invention [0002] In the differentiating system, '3 memory storage generally includes a hierarchical system with different types of memory storage devices. In this system, different levels of memory storage have different characteristics, especially capacity and data access time. In this memory system, a lower hierarchy indicates that it is closer to the processor of the system. The memory device furthest from the processor usually has the largest capacity and is the slowest. Common examples are electro-mechanical devices, such as magnetic tapes, compact discs, and hard disk storage devices, commonly referred to as mass storage devices. Although relatively slow, they can store a significant amount of data. [0003] The next layer in the system is generally a system memory containing solid-state memory devices, such as dynamic random storage ---------- · installation ---- ---- Order --------- i (Please read the notes on the back before filling out this page) Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 2 556212 A7 B7 V. Description of the invention (>) The fetch memory (dynamic random access memory, DRAM for short), although its access time is one of the tenth power of large-capacity storage, but its capacity is the same. [0004] In this memory system, the level closest to the processor, the temporary storage Is of the processor is not counted, and usually one or more levels of cache memory can be found. Cache memory has extremely fast access times. A common example is static random access memory (SRAM). In many cases, one or more levels of cache memory and processor are integrated on the same integrated circuit. This is especially true of new microprocessors. Cache memory stores or "caches" the data most commonly accessed by the processor from system memory to provide faster data access when requested by the processor. I [0005] Cache memory generally stores data in units of cache lines. The commonly used cache line size is 32 bytes. Because the cache memory is smaller than the system memory, when data is read from or written to the cache memory, the system memory address of the data has only a part of it, which is often called the index portion. ) Or index, which is used to address fast memory. As a result, multiple system memory addresses are mapped to the same cache index. In a direct-mapped cache, only one of the multiple system memory addresses mapped to the same cache index can be cached at a time. Therefore, if a program frequently accesses two system memory locations mapped to the same cache index, the two will often be replaced with each other in the cache memory. In order to reduce this situation and improve cache performance, associative cache is generally used
尺度·中関家標^格moxj /JIT 556212 經濟部智慧財產局員工消費合作社印製 A7 ------- B7 五、發明說明（》） —- 記憶體（associative cache)。 [0006] 不同於直接映射快取記憶體於每—索引僅儲存 單-快取線’關聯快取記憶體在每一索引儲存了一列或一 組之N條快取線。關聯快取記憶體允許一快取線存在於所 選定之列中N個位置的任-個上。這種快取記憶體被稱為n 路關聯快取記憶體’或N路集合關聯快取記憶體，此因在 所選取的-集合或列中’有N個不同的路，快取線可能儲 存於其中。 [0007] ,由於快取線可儲存於N路關聯快取記憶體之任 -路中’當-新快乳線要被寫入快取記憶體時，關聯快取 $己憶體必須決定在所檢索㈣巾，該新快取線要寫入N路 中的哪一路。也就是，1關聯快取記憶體必須確定在所檢索 的列之既有N條快取線中，要置換哪一條。選擇最有可能 的路，亦即快取線，來置換，希望其在最近不會被使用到， 此即快取置換凟异法（cache replacement algorithm)的 任務。用以決定置換哪一路的方式之一例，即是置換所選 取列中农近被隶少使用敢近被最少使用（leas^ recently used，LRU)的路，亦即快取線。快取記憶體則保留在一已 知的列中用以決定哪一路為最近被最少使用之資訊。在習 用之關聯快取記憶體中，此LRU資訊以列為單位，被存放 在一功能方塊（functional block)中，該功能方塊實體 上與儲存快取線本身及其關聯位址標記（address tag)之 功能方塊是分開的。 [0008]習用之關聯快取記憶體包含至少三個相當大的 丨丨---------•裝--------訂---------Φ (請先閱讀背面之注音？事項再填寫本頁)Standards · Zhongguan Family Standard ^ grid moxj / JIT 556212 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------- B7 V. Description of Invention (>>) --- associative cache. [0006] Unlike direct mapping cache memory, each index stores only a single-cache line ' associated cache memory stores one row or group of N cache lines in each index. Associative cache memory allows a cache line to exist on any of the N locations in the selected column. This type of cache memory is called n-way associative cache memory or N-way set-associative cache memory. Because there are N different ways in the selected set or column, the cache line may be Stored in it. [0007] Since the cache line can be stored in any of the N-way associated cache memories-when-the new cache line is to be written into the cache memory, the association cache must be determined in Which of the N ways the new cache line is written to retrieved. That is, the 1-associative cache memory must determine which of the existing N cache lines in the retrieved column is to be replaced. Choose the most probable way, namely the cache line, to replace it. It is hoped that it will not be used in the near future. This is the task of cache replacement algorithm. An example of the method used to determine which way to replace is to replace the selected peasant in the list. The peasant is used less frequently and is leas ^ recently used (LRU), which is the cache line. The cache memory is kept in a known row to determine which way is the least recently used information. In conventional associated cache memory, this LRU information is stored in a functional block in units of rows. The functional block is physically associated with the storage cache line itself and its associated address tag. The function blocks are separated. [0008] The conventional associated cache memory contains at least three relatively large (Please read the Zhuyin on the back? Matters before filling out this page)
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經濟部智慧財產局員工消費合作社印製 功能方塊或陣列（array)，其在實體上皆可區分開來。首 先是資料陣列（dataarray)，其儲存實際的資料快取線， 並配置為複數個具N路快取線之列，如前所述。 [0009]習用關聯快取記憶體所具有的第二個功能方塊 是目錄（directory)，也稱為標記陣列（tag array)。 此目錄以類似具N路之資料陣列的方式來配置。也就是， 系統記憶體位址之索引部份定址此目錄，以選取一具N個 項目（entry)之列。位於此目錄之一已知列的一已知路中 之一項目，儲存了資料陣列中一對應快取線之標記與狀 癌。標3己加上索引便形成該對應快取線之系統記憶體位 址，或至少是系統記憶體位址較前面的部分。當快取記憶 體被存取時，目錄中被選取列之每一標記皆與系統記憶體 位址做比較，並以快取線狀態加以檢驗，以確定是否發生 一快取命中（cache hit)。對應快取線狀態的一個常見例 子，是快取線的MESI狀態。 [0010]習用關聯快取§己憶體所具肴的第三個功能方塊 是LRU陣列。如前所述，在習用之關聯快取記憶體中，LRU 資訊是以列為單位而儲存的。也就是，LRU陣列亦藉由索引 來加以定址。然而，索引僅選取LRU陣列中一個單一項目， 而非一整列的項目。也就是，此被檢索之單一項目包含了 對應資料陣列中整列快取線之LRU資訊。習用之關聯快取 記憶體要將LRU陣列從資料陣列及目錄分隔開的原因是， LRU陣列之項目可能在每次一列中任何快取線被更新時，就 被更新，然而資料陣列或目錄是以快取線為基礎而更新 个取浓人汉週用肀國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 556212 A7 B7 五 、發明說明（ 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 :新也就是，一次只有聽陣列與目錄之N路中的-路被 [0011] 對於快取記憶體，一直都有复六旦 t二別是要跟上處理器速度的持續增加:然 1體的容量增加，又會需要將快取織_實^寸幸 可能縮小。特別是將快取記,_整合在處理器中阶开^ ^需要如此。在新型的微處理器中，整合式快取記^體會 消耗微處理H之碰電路林少寶貴的面積。 心曰 [0012] 不過，習用關聯快取記憶體包含三個實體上分 開且相當大之功能方塊的這個事實，卻與保持快取記憶二 盡可能地小之需求背道而馳。習用方法的一個缺點是，它 複製了陣列中已因目錄而存在的某部分邏輯，像是位址解 碼邏輯（address decode)與寫入邏輯（write 1〇幻〇， 因而需要額外佔用積體電路或電路板的面積。另一個缺點 則是，獨立出來的LRU陣列，比起目錄與資料陣列，通常 具有不同的高寬比（aspect ratio)、，其對於平面配置 (floorplanning)會產生負面的衝擊。也就是，很難用一 種有效使用空間的方式來將這些功能方塊放在積體電路之 晶粒（die)上。另一個缺點是，分開來的LRU陣列構成另 一個功能方塊，需在積體電路或電路板之平面上進行佈局 與繞線（place and route)。 [0013] 因此，我們所需要的是，以更有效使用空間的 方式來產生及儲存關聯快取線之置換資訊，以減少關聯快 取記憶體尺寸及空間配置上的衝擊。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） «t--------IT--------- (請先閱讀背面之注意事項再填寫本頁) 556212 A7 、發明說明（t) (三）發明簡要說明： [0014] 本發明係提供— 之置換資訊錄合在魏秘_，其快取線 小，較容聽局魏線，_H m緣記韻因為較 為達到前述目的，本發日之·。於是， 聯快取記憶體。該快取雜提供一種Ν路關 一複數個儲存元件，以儲^μ—，其具有第Functional blocks or arrays are printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, which can be physically distinguished. The first is a data array, which stores the actual data cache lines, and is configured as a plurality of rows with N cache lines, as described above. [0009] The second functional block that conventional associative cache memory has is a directory, also known as a tag array. This directory is configured similarly to a data array with N channels. That is, the index portion of the system memory address addresses this directory to select a list of N entries. An entry in a known path in a known row of this directory stores a corresponding cache line marker and cancer in the data array. Index 3 has been indexed to form the system memory address corresponding to the cache line, or at least the earlier part of the system memory address. When the cache memory is accessed, each tag in the selected row in the directory is compared with the system memory address and checked with the cache line status to determine if a cache hit has occurred. A common example of a cache line state is the MESI state of the cache line. [0010] The third functional block of conventional association cache § Memories is the LRU array. As mentioned earlier, in conventional associated cache memory, LRU information is stored in units of rows. That is, the LRU array is also addressed by an index. However, the index selects only a single item in the LRU array, not an entire column. That is, the single item retrieved contains LRU information for the entire cache line in the corresponding data array. The reason why the conventional associated cache memory separates the LRU array from the data array and the directory is that the items of the LRU array may be updated every time any cache line in a row is updated, but the data array or directory It is based on the cache line to update the National Standard (CNS) A4 (210 X 297 mm) for the Han National Week. ----------- install ------ --Order --------- (Please read the notes on the back before filling out this page) 556212 A7 B7 V. Invention Description (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: New, that is, only once Listen to the-way in the N way of the array and the directory. [0011] For cache memory, there has always been more than six times t. Secondly, to keep up with the continuous increase in processor speed: then the capacity of the 1 body increases, and it will It is necessary to reduce the cache memory. Fortunately, it may be reduced. In particular, the cache memory is integrated into the processor. ^ ^ This is required. In the new type of microprocessor, the integrated cache memory will consume slightly The precious circuit area that handles the bump circuit of H. Heart said [0012] However, the conventional associative cache memory contains three real The fact that there are separate and fairly large function blocks runs counter to the need to keep the cache memory as small as possible. One disadvantage of the conventional method is that it replicates some of the logic that already exists in the array due to the directory, like It is address decode logic and write logic (write 10), so it needs to occupy the area of the integrated circuit or circuit board. Another disadvantage is that the independent LRU array is compared with the directory and data. Arrays usually have different aspect ratios, which have a negative impact on floorplanning. That is, it is difficult to place these functional blocks in integrated circuits in a way that uses space efficiently. On the die. Another disadvantage is that the separated LRU array constitutes another functional block, which needs to be placed and routed on the plane of the integrated circuit or circuit board. [0013] Therefore What we need is to generate and store the replacement information of the associated cache line in a more efficient use of space to reduce the associated cache memory size The impact of the size and space configuration. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) «t -------- IT --------- (please first Read the notes on the back and fill in this page) 556212 A7 、 Invention description (t) (C) Brief description of the invention: [0014] The present invention provides-the replacement information is recorded in Wei Mi_, its cache line is small, compared with The Rongting Bureau Wei line, _H m Yuan Jiyun, because it achieves the aforementioned purpose, is out today. So, cache the memory. The cache memory provides an N-way switch and a plurality of storage elements for storing ^ μ—
列，該標__$二_^=，_資料障 路m it 倚存凡件，配置成M列與N ^ 1.Γ 儲存疋件皆儲存一對應快取線之- 母二複數個儲存元件亦儲存用來決定要置換n 哪-路的資訊。、該快取記憶體也包含控制邏輯 ,control l〇glc) ’轉接至該標記陣列，用以從μ列甲被 k取之顺所有Ν路中，讀取該資訊。該控制邏輯亦依 據所讀取之資訊，選擇置換N路路，且僅更新所選 取要置換之路的資訊。 [0015] 另一方面，本發明的一項特徵是，提供一種n 路關聯快取記憶體。該快取記憶體包含一資料陣列，配置 成N路，且具有複數列。每一該複數列儲存對應該N路之N 條快取線。該資料陣列也包含一索引輸入端，以選取該複 數列之一。該快取記憶體亦包含一目錄，耦接至該資料陣 列’配置成N路，且具有複數列。每一該複數列儲存快取 線之置換資訊。該快取線置換資訊分布於該N路，以使得 每一路僅儲存一部份的快取線置換資訊。該快取記憶體也 本紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公爱Column, the standard __ $ 二 _ ^ =, _ data barrier m it depends on all pieces of memory, configured as M rows and N ^ 1. Γ storage files are stored one corresponding cache line-mother two multiple storage The component also stores information used to decide which n-way to replace. 2. The cache memory also contains control logic, control l0glc) 'is transferred to the tag array to read the information from all N channels that are taken by μ column A by k. The control logic also chooses to replace N channels according to the read information, and only updates the information of the selected channels to be replaced. [0015] In another aspect, a feature of the present invention is to provide an n-way associative cache memory. The cache memory includes a data array, which is arranged in N ways and has a plurality of rows. Each of the plural series stores N cache lines corresponding to N channels. The data array also includes an index input to select one of the plurality of rows. The cache memory also includes a directory, which is coupled to the data array 'and configured as N channels, and has a plurality of columns. Each of the plural series stores the replacement information of the cache line. The cache line replacement information is distributed on the N channels, so that each channel stores only a part of the cache line replacement information. The cache memory is also compatible with the Chinese National Standard (CNS) A4 specification (21G X 297)
裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) Α7Install -------- Order --------- (Please read the precautions on the back before filling this page) Α7
556212 五、發明說明（7} 包含控制邏輯，耦接至該目錄，用以從所選取之該複數列 其中之一接收快取線置換資訊，並回應地產生一訊號送 回。該訊號指定資料陣列之N路其中之一，用來在所選取 之該複數列之一的N條快取線中，置換其對應的一條快取 線。 [0016]另一方面，本發明的一項特徵是，提供一種四 路關聯快取記憶體。該快取記憶體包含一資料陣列。該資 料陣列有Μ列。該Μ列中的每一列皆具四路，每一路具一 快取線儲存元件（line storage element)，以儲存一快 取線。該快取記憶體也包含一目錄，耦接至該資料陣列。 該目錄具有該Μ列。該Μ列中的每一列皆具該四路，每一 路具一標記儲存元件（、tag storage element)，對存於資 料陣列之一對應快取線儲存元件之該快取線，儲存其一標 記。該標記儲存元件亦儲存兩個位元之快取線置換資气。 該快取記憶體亦包含一編碼器（encoder)，輕接至該目錄， 用以在Μ列之一被選取列的四路中，從每一路讀取包含該 兩個位元快取線置換資訊之八個位元。該解碼器依照—準 最近最少使用（pseudo-ieast-recentiy—used)之編碼方 式，將該八個位元編碼成三個位元。該三個位元在該M列 之被選取_四财，指定哪-狄”场近被最少使 用的。 [0017]另一方面，本發明的一項特徵是，提供一種具 有一整合式標記與錄隸換資訊_之關聯快取纪憶 體。該快取記憶體包含-具Μ列與Ν路之儲存元件的二 ------------裝--------訂--------- (請先閱讀背面之注咅？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 8 556212 »B7 五、發明說明（f ) 每-儲存元件儲存一快取線標記及每路之 列具一用來接收-索引之輸入端，該索_二= 列的Μ列之…該快取記憶體也包含控制邏輯 儲存元件㈣列，用簡所選取㈣敎_崎有，路= 每路之置換資訊編碼成每列之置換資訊。藉此，即 對一分離之快取線_魏之齡元件_的需求。 [0018] 另n本發_—項特徵是，提供ν 路關聯快取記憶體。該快取記憶體包含一二維的^己 ^ 3 = 每一列也儲存準LRu (―) 貝成。辟LRU -貝訊包含分佈於該列之N路的N個部份。 該N個部份集合起來指定了該N路之哪一路是實質上最近 被最少使_。N _記之—對應者的準資 訊’其每-該N個部分隨著該N個標記之該對應者皆可個 別更新。該快取記紐也包含控侧輯，输约陣列， 用來接收分佈於該列之N路的N個部份準咖資訊。控制 邏輯亦在快取記紐之對應職二維標記與⑽陣列之一 二維資料_中，置換-快取線。由該N個部分所指定之 該快取線係為該列中實質上最近被最少使用的。 置 Ν i [0019] 另-方©’本發__項特徵是，提供一種更 新-具有Μ列與N路之關聯快取記憶體的方法。該方法包 含依據-快取線錄，從該絲記，隨的Μ舰取其中一 列’並讀取所選取列的Ν路中，每一路所儲存之快取線 換資訊。該方法亦包含回應該讀取動作，選擇所選取列的 _ 9 t紙張f度翻中關家標準（CNS)A4規格⑵Q χ 297公^· 556212 A7 B7 五 圖 塊圖 、發明說明（ 路其中之一用以置換，並回應該讀取與選擇動作而產生新 快取線置換資訊。該方法也包含在該產生的動作後，以該 新快取線置換資訊更新該路。 [0020] 本發明的一個優點是，可免去對置換演算法的 位元設計一分離陣列的需求。另一個優點則是，可避免重 複大部分的位址解碼邏輯、寫入邏輯及其他類似的邏輯， 此為習知方法必須做的。雖然實作上顯示每一索引需要八 個位元（2位元/路*4路），而習知方法每一索引僅需三 個位το，但本發明已注意到，所複製的陣列控制邏輯與每 -索引三條70合赫，會比本發明之快取記憶體的八個 儲存位元之尺寸來得大。再—個優點則是，增加現存標記 陣列的位元數並騎辨她置上魅—侧外需要繞線 的陣列。 [0021] 本發明之其它特徵與優點，在考察本說明書其 餘部分與圖示後，將可更加明白。 四）發明圖示說明： 料㈣之四路關職取記賴之方塊 [0023]圖二係為圖—習用快取記紐之控制邏輯的方 [〇〇f]、圖三係為說明圖一之習用快取記憶體如何置換 一快取線之運作流程圖。 [ Θ四係依本發明纟t示之四路關聯快取記憶體的 ^--------^--------- (請先閱讀背面之注意事項再填寫本頁)556212 V. Description of the invention (7) contains control logic, coupled to the directory, for receiving cache line replacement information from one of the plurality of selected rows, and in response to generating a signal to return. The signal specifies data One of the N channels of the array is used to replace a corresponding cache line in the selected N cache lines of one of the plural sequence. [0016] On the other hand, a feature of the present invention is Provides a four-way associative cache memory. The cache memory contains a data array. The data array has M rows. Each row in the M row has four lanes, and each lane has a cache line storage element ( line storage element) to store a cache line. The cache memory also contains a directory coupled to the data array. The directory has the M column. Each column in the M column has the four channels, each A tag storage element (a tag storage element) stores a tag for the cache line corresponding to a cache line storage element stored in one of the data arrays. The tag storage element also stores a two-bit cache Line replacement capital. The body also includes an encoder, which is lightly connected to the directory, and is used to read eight of the four channels of one selected column M from each channel containing the two bit cache line replacement information. The decoder uses the pseudo-ieast-recentiy-used encoding method to encode the eight bits into three bits. The three bits are selected in the M column. "Four riches, specify which-Di" field is the least used recently. [0017] On the other hand, a feature of the present invention is to provide an associated cache with an integrated mark and record exchange information_ The cache memory contains two storage elements with M rows and N paths ------------ install -------- order -------- -(Please read the note on the back? Matters before filling out this page) Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 8 556212» B7 V. Description of the invention (f) Each-storage element stores a cache line mark and The column has an input terminal for receiving-indexing, the index_two = the M column of the ... the cache memory also contains a control logic storage element queue, which is selected with a simple崎 _ Qi has, the road = the replacement information of each road is encoded into the replacement information of each row. This is the demand for a separate cache line _ Wei Zhiling element_. [0018] Another feature of this issue is Provides ν-associated cache memory. The cache memory contains a two-dimensional ^^^ 3 = each column also stores quasi-LRu (―) Beicheng. LRU-Beixun contains N-channels distributed in the column The N parts are aggregated to specify which of the N paths is actually the least recently used. N_Remember—the corresponding quasi-information of each of the N parts follows Each of the N tags can be updated individually. The cache button also contains a control profile and an input reduction array, which is used to receive N partial quasi-coffee information distributed in the N channels of the column. The control logic is also the permutation-cache line in the two-dimensional data_, one of the corresponding two-dimensional tags and arrays of the cache memory. The cache line designated by the N sections is the least recently used in this column. [0019] Another feature of the present invention is to provide a method for updating-having an associated cache memory of M columns and N channels. The method includes a basis-cache line record. From the silk record, one of the columns ′ is fetched and the N line of the selected line is read, and the cache line exchange information stored in each line is read. The method also includes a response to the reading action, selecting the selected row of _ 9 t paper, f-degree turn-over standard (CNS) A4 size ⑵Q χ 297 public ^ · 556212 A7 B7 five block diagrams, description of the invention (wherein One is used for replacement, and responds to reading and selecting actions to generate new cache line replacement information. The method also includes updating the path with the new cache line replacement information after the generated action. [0020] This One advantage of the invention is that it eliminates the need to design a separate array of bits for the replacement algorithm. Another advantage is that it can avoid repeating most of the address decoding logic, writing logic, and other similar logic. It must be done for the conventional method. Although it is shown in practice that each index requires eight bits (2 bits / way * 4 ways), and the conventional method requires only three bits το, but the present invention has It is noted that the copied array control logic and three per-indexes of 70 will be larger than the size of the eight storage bits of the cache memory of the present invention. Another advantage is that it increases the number of existing mark arrays. Bit count and ride her to put on charm — An array of windings is required outside. [0021] Other features and advantages of the present invention will become clearer after examining the rest of the description and illustrations in this specification. 4) Description of the invention's illustrations: Notes on the four-way customs clearance of materials Lai Zhifang [0023] Figure 2 is a diagram of the control logic of the conventional cache memory [00f], and Figure 3 is a flowchart illustrating how the conventional cache memory of Figure 1 replaces a cache line. Illustration. [Θ is the four-way associative cache memory ^ -------- ^ --------- according to the present invention (Please read the precautions on the back before filling this page )
本紙張尺度適用中國國家標 0 x 297公釐） 556212 五、發明說明（l 方塊圖。 [0026]圖五係依本發明繪示圖四快取記憶體之 輯的方塊圖。 " 控制邏 [0027]圖六係依本發崎補四之快取記憶體如 換一快取線之運作流程圖。 置 經濟部智慧財產局員工消費合作社印製 圖號說明： 100習用四路關聯快取記憶體 102控制邏輯 106資料陣列 112快取位址. 116索引 、 122新標記 126解多工器 132列選擇訊號 134 rep 1 acement—way—se 1 ect [ 3:0 ]訊號 142 LRU[2:〇]訊號 144 new—LRU[2:0]訊蜆 154標記儲存元件 156快取線儲存元件 158 LRU儲存元件 204置換路產生器 206新LRU產生器 302〜316習用之置換快取線的運作流程 400四路關聯快取記憶體 402控制邏輯 404標記陣列 424解多工器 434 rep 1 acement—way—se 1 ect [ 3:0 ]訊號 104標記陣列 108 LRU陣列 114標記 118位元組偏移量 124解多工器 128新快取線 ------------t— (請先閱讀背面之注意事項再填寫本頁) _ n 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公髮） 556212 A7 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 五、發明說明（ 442 per—way—LRU[ 7:0] §孔號 444 new—per—way_LRU[ 1:0]訊號 454標記與LRU儲存元件 464標記 468每路之LRU資訊 * 502 per—way一LRU 至 per—rowJLRU 編碼器 504置換路產生器 506 per一 way—LRU解碼器 508 per—row—LRU[ 2:0 ]訊號 602〜616本發明之置換快取線的運作流程 (五）發明詳細說明： [0028] 本節將先描述一個不具本發明優點之相關技術 的關聯快取記憶體，以便更理解本發明。 [0029] 現請參閱圖一，其顯示習用之四路關聯快取記 憶體100之方塊圖。在快取記憶體1〇〇之一寫入動作中， 提供了一新快取線128以寫入快取記憶體1〇〇。一指定所要 讀取或寫入的快取線之快取位址112，則被送至快取記憶體 100。特別是，此新快取線128之快取位址112被用來將新 快取線128寫入快取記憶體100中。快取位址112包含一 標δ己部伤114、一索引部份116以及一位元組偏移量（⑽化 offset)部份118。標記114包含快取位址112之最重要位 元。索引116包含快取位址112的中等重要位元，而位元 組偏移量118則包含快取位址112之最不重要位元。 [0030] 快取記憶體1〇〇包含一資料陣列1〇6。資料陣 列106包含複數個用以儲存快取線之儲存元件，其例示於 圖一之快取線儲存元件156。儲存元件156配置為二具複數 1本紙張尺絲时關家標^!S)A4職⑽χ 556212 A7 B7 五、發明說明（1>) 列與複數狀二維_。該概行_桃。快取記憶體 100包含四個路’標示為路〇、路卜路2及路3，如圖所 示。每-快取線係存在位於1與行交又點上之快取線儲 存元件156。快取位址112之索引116則以列選擇訊號（而 select signal·) 132送至資料陣列⑽。列選擇訊號132 選取資料陣列1G6的其中-列，以寫人新快取線丨28。一快 取線可關雜H集合的鹏巾任-路。也就是，將 -快取線寫入列選擇訊號132所選取資料陣列娜其中一 列的任何-路，皆是允許的。在多數應財，相較於直接 映射快取記髓’此種關雛增加了快取記，隨⑽的命 中率（hit rate)及效能。 [0031] 快取；己憶體也包含一解多工琴 (demultiplexer) 126，耦接至資料陣列1⑽。解多工器 126 由 replacement一way—select[3:0]訊號 134 來控制，選 取資料陣列106的四路其中之一，以寫入新快取線128。解 多工器126接收此新快取線128，並遠擇性地將其送至由 replacement—way一select[3:0]訊號 134 所指定資料陣列 106 的四路其中之一。repiacement—way—seiect[3:〇]訊號 134係由控制邏輯1〇2產生，此將於下文圖二部分做詳細說 明。因此，新快取線128被寫入由列選擇訊號132所選取 之列中’由 replacement一way—select[3:0]訊號 134 所選取 之路之一儲存元件156。 [0032] 快取記憶體1〇〇亦包含一標記陣列1〇4，也稱 為目錄104。此標記陣列1〇4包含複數個用來儲存標記的餘 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Μ--------^--------- (請先閲讀背面之注意事項再填寫本頁) 556212This paper size is applicable to the Chinese national standard 0 x 297 mm) 556212 V. Description of the invention (1 block diagram. [0026] FIG. 5 is a block diagram of the four cache memories in accordance with the present invention. &Quot; Control logic [0027] FIG. 6 is a flow chart of the operation of adding four cache memories according to the present invention, such as changing a cache line. Printing the drawing number description of the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: 100 custom four-way associated cache Memory 102 control logic 106 data array 112 cache address. 116 index, 122 new mark 126 demultiplexer 132 column selection signal 134 rep 1 acement-way-se 1 ect [3: 0] signal 142 LRU [2: 〇] Signal 144 new—LRU [2: 0] signal 154 mark storage element 156 cache line storage element 158 LRU storage element 204 replacement circuit generator 206 new LRU generator 302 ~ 316 conventional replacement cache line operation flow 400 four-way associative cache memory 402 control logic 404 tag array 424 demultiplexer 434 rep 1 acement-way-se 1 ect [3: 0] signal 104 tag array 108 LRU array 114 tag 118 byte offset 124 demultiplexer 128 new cache line ------------ t— (Please Read the notes on the reverse side and fill in this page) _ n This paper size is applicable to China National Standard (CNS) A4 (210 X 297) 556212 A7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (442 per— way—LRU [7: 0] § hole number 444 new—per—way_LRU [1: 0] signal 454 mark and LRU storage element 464 mark 468 LRU information for each way * 502 per-way one LRU to per-rowJLRU encoder 504 permutation path generator 506 per-way-LRU decoder 508 per-row-LRU [2: 0] signals 602 ~ 616 Operation flow of permutation cache line of the present invention (five) Detailed description of the invention: [0028] This section will First, a related art associative cache memory without the advantages of the present invention will be described in order to better understand the present invention. [0029] Please refer to FIG. 1, which shows a block diagram of a conventional four-way associative cache memory 100. In one of the write operations of the fetch memory 100, a new cache line 128 is provided to write the cache memory 100. A designated cache address 112 of the cache line to be read or written , It is sent to cache memory 100. In particular, The cache address 112 of the new cache line 128 is used to write the new cache line 128 into the cache memory 100. The cache address 112 includes a standard delta-portion 114, an index portion 116, and a one-byte offset portion 118. The mark 114 contains the most significant bits of the cache address 112. Index 116 contains the medium significant bits of cache address 112, and byte offset 118 contains the least significant bits of cache address 112. [0030] The cache memory 100 includes a data array 106. The data array 106 includes a plurality of storage elements for storing cache lines, which are illustrated in the cache line storage element 156 of FIG. The storage element 156 is configured with two plural numbers and one paper rule when closing the house ^! S) A4 post ⑽ 556 212 A7 B7 V. Description of the invention (1 >) Columns and plural two-dimensional _. The summary line_ peach. The cache memory 100 includes four ways' labeled as way 0, way 2 and way 3, as shown in the figure. A per-cache line is a cache line storage element 156 located at the intersection of 1 and the line. The index 116 of the cache address 112 is sent to the data array 以 with a row select signal (and select signal ·) 132. Column selection signal 132 Selects one of the data arrays 1G6 to write a new cache line 28. A quick take-off can shut off any H-Peng towels set to the road. That is, writing any of the -cache lines into one of the columns of the data array selected by the row selection signal 132 is permissible. In most financial applications, compared with direct mapping of cache memory, this kind of chick increases cache memory, hit rate and efficiency. [0031] Cache; the memory also includes a demultiplexer (126), coupled to the data array (1). Demultiplexer 126 is controlled by replacement_way_select [3: 0] signal 134, and one of the four ways of data array 106 is selected to write new cache line 128. Demultiplexer 126 receives this new cache line 128 and selectively sends it to one of four ways of data array 106 specified by replacement_way_select [3: 0] signal 134. The repiacement-way-seiect [3: 〇] signal 134 is generated by the control logic 102, which will be explained in detail in Figure 2 below. Therefore, the new cache line 128 is written into the storage element 156 which is one of the paths selected by the replacement_way_select [3: 0] signal 134 in the column selected by the row selection signal 132. [0032] The cache memory 100 also includes a tag array 104, also referred to as the directory 104. The mark array 104 contains a plurality of remaining 13 for storing marks. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). M -------- ^ ----- ---- (Please read the notes on the back before filling this page) 556212
經濟部智慧財產局員工消費合作社印製 存元件，其例示於圖-之標記儲存元件154。標記陣列取 以類似資料陣列⑽的方式配置為具有相同數目之列與路 的二維陣列。—快取狀—標記齡在位於-列與行交又 點上之-標記财元件154，該標記儲存元件154係對應於 位於資料_ 1G6相_列與行上之快取線儲存元件156 快取位址112之標記114則藉新標記訊號112送出。列選 擇訊號132選取標記陣列104的其令一列，以寫入新標記 122。此標記係於進行一快取記憶體1〇〇的讀取動作時所讀 取，以確定是否已發生一快取命中（cachehit)。除了儲 存快取線之標記，標記儲存元件154也可_存快取狀態The memory element printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is illustrated in FIG. The marker array is configured as a two-dimensional array with the same number of rows and paths in a similar manner to the data array. —Cache-like—the mark age element 154 is located at the intersection of the column and the row, and the mark storage element 154 corresponds to the cache line storage element 156 located on the data_ 1G6 phase_ column and row. The mark 114 at the address 112 is sent by the new mark signal 112. The row selection signal 132 selects a row of the tag array 104 to write a new tag 122. This flag is read when a read operation of the cache memory 100 is performed to determine whether a cache hit has occurred. In addition to storing the mark of the cache line, the mark storage element 154 can also store the cache status
負 Λ ’諸如 MESI (Modified (修改）’Exclusive (獨占持 有），Shared (共享），jnvalid (無效））狀態資訊，或關 聯於其他快取-致性演算法之快取狀態資訊。若標記儲存 元件154中之標記與快取位址112之標記114吻合，則發 生一快取命中，而快取線則具所需之正確性。 XNegative Λ 'such as MESI (Modified' Exclusive, Shared, jnvalid) status information, or cache status information related to other cache-consistent algorithms. If the mark in the mark storage element 154 matches the mark 114 in the cache address 112, a cache hit occurs, and the cache line has the required correctness. X
[0033]快取記憶體1〇〇也包含一第二解多工器124， 麵接至標記陣列1〇4。解多工器124亦由 replacement—way-Select[3:〇]訊號 134 來控制，選取標記 陣列104的四路其中之一，以寫入新標記122。解多工器 124接收此新標記122，並選擇性地將其送至由 r印lacement—way—Select[3:〇]訊號134所指定標記陣列 104的四路其中之一。因此，新標記122被寫入由列選擇訊 號132所選取之列中，由 訊號134所選取之路之一儲存元件154。 --------1--------- (請先閱讀背面之注意事項再填寫本頁) 14 556212 五 A7 B7 、發明說明（\f〇 [0034] 快取記憶體1〇〇也包含一 陣列⑽， 含複數細來儲存·資訊的儲存元件，其例示於圖二之 LRU儲存兀件158。陣列⑽配置為—維陣列，所呈 的列數與資料_⑽及標記_廟_。哪資訊係存 於-列之- LRU儲存元件158中，該列則對應於位在資料 陣列106之相同列與路之—快取線儲存元件156。列選擇气 號132亦被送至LRU陣列·陣列1〇8從卿一LRu[2.〇°] 訊號144接收新LRU資訊。此新LRU資訊描述由列選擇訊 號132所選取之列的四路中’哪一路是最近被最少使用的。 此新LRU資訊被寫入由列選擇訊號132所選取之列的儲存 元件158中。new_LRU[2:0]訊號144係由控制邏輯1〇2所 產生，如下文關於圖二部分將要說明的。LRU陣列1〇8也從 LRU陣列1〇8中由列選擇峨132所選取之一列來提供咖 負汛，並藉LRU[2:0]訊號142將其送至控制邏輯IQ〗。押 制邏輯102使用於LRU[2:0]訊號142所接收的⑽資訊二 來產生 replacement—way_select[3:0]訊號 134 及 new—LRU[2:0]訊號144，如接下來所要敘述的。 [0035] 現請參閱圖二，其顯示圖一習用快取記憶體 之控制邏輯102的方塊圖。圖二亦顯示出描述内含於圖中 每個方塊之組合邏輯的等式。圖二也顯示一樹狀圖及位元 編碼方式，其描述習知技術中對於一四路準LRU演算法之 已編石馬資訊進行三位元編碼的方法。該四路準LRU演算法 是關聯快取記憶體常用之置換演算法，因為它使用比真正 方法較少的位元數，較易更新，但仍具大部份真正咖 ^ --------^--------- (請先閱讀背面之注意事項再填寫本頁) 556212 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 的特性。準LRU試圖追蹤一選定列之最近被最少使用的快 取線為何。為簡明起見，此處所描述之準LRU資訊及相關 訊號皆稱為LRU，而非準LRU。存於LRU陣列108之LRU資 訊的三個位元以LRU[2:0]訊號142送至圖一之控制邏輯 102，並依據圖二所示之樹狀圖加以編碼。 [0036] 控制邏輯102包含一置換路產生器204，用以 接收來自圖一 LRU陣列108之圖一 LRU[2:0]訊號142。 [0037] 此置換路產生器204基於亦顯示於圖二之下列 規則，以選取一置換路。 若 LRU[2:0] = 3’ b000，則路〇 為 LRU 路 若 LRU[2:0] = 3’ bOOl，則路1 為 LRU 路 若 LRU[2:0] = 3’、b010，則路 〇 為 LRU 路 若 LRU[2:0] = 3’ 1〇011，則路1 為 LRU 路 若 LRU[2:0] = 3’ bl00，則路2 為 LRU 路 若 LRU[2:0] = 3’ blOl，則路2 為 LRU 路 若 LRU[2:0] = 3’ M10，則路3 為 LRU 路 若 LRU[2:0] = 3’ bill，則路3 為 LRU 路 [0038] 置換方式產生器204依據亦顯示於圖二之下列 等式，回應 LRU[2:0]訊號142 而產生 replacement-way_select[3:〇hfli£l34。 replacement—way—select[0]= replacement-Way—select[l]= replacement— way—select[2]= replacement一way—select[3]二 删2] & 〜LRU[0] -LRU[2] & LRU[0] LRU[2] & 〜LRU[1] LRU[2] & LRU[1] [0039]控制邏輯102亦包含一新LRU產生器（new LRU 16 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閲讀背面之注意事項再填寫本頁) 擎裝---- tr---------^^1. 556212[0033] The cache memory 100 also includes a second demultiplexer 124 connected to the tag array 104. The demultiplexer 124 is also controlled by a replacement-way-Select [3: 〇] signal 134, and one of the four ways of the mark array 104 is selected to write a new mark 122. The demultiplexer 124 receives the new tag 122 and selectively sends it to one of the four ways of the tag array 104 designated by the print_way_Select [3: 0] signal 134. Therefore, the new mark 122 is written in the row selected by the row selection signal 132, and the storage element 154 is one of the roads selected by the signal 134. -------- 1 --------- (Please read the precautions on the back before filling out this page) 14 556212 Five A7 B7 、 Invention description (\ f〇 [0034] cache memory 100 also includes an array ⑽, which contains a plurality of storage elements for storing and information, which is exemplified in the LRU storage element 158 of Fig. 2. The array ⑽ is configured as a dimensional array, and the number of rows and data__ and Mark _Temple_. Which information is stored in -column-LRU storage element 158, which corresponds to the same row and path in the data array 106-cache line storage element 156. Column selection gas number 132 also Sent to LRU array · Array 108 receives new LRU information from Qing-LRu [2.〇 °] signal 144. This new LRU information describes which of the four channels selected by the column selection signal 132 is which is the most recent The least used. This new LRU information is written into the storage element 158 selected by the row selection signal 132. The new_LRU [2: 0] signal 144 is generated by the control logic 102, as shown in Figure 2 below. Some of them will be explained. The LRU array 108 also uses one of the columns selected by the column selection E132 from the LRU array 108 to provide the coffee load, and borrows LRU [2: 0] news. 142 sends it to the control logic IQ. The restraint logic 102 uses the second information received by the LRU [2: 0] signal 142 to generate the replacement-way_select [3: 0] signal 134 and the new-LRU [2: 0 ] Signal 144, as will be described next. [0035] Please refer to FIG. 2, which shows a block diagram of the control logic 102 of the conventional cache memory in FIG. 1. FIG. 2 also shows that the description is included in each of the figures. The equation of the combination logic of the blocks. Figure 2 also shows a tree diagram and bit encoding method, which describes the three-bit encoding method for the compiled stone horse information of a four-way quasi-LRU algorithm in the conventional technology. The four-way quasi-LRU algorithm is a commonly used replacement algorithm for associative cache memory, because it uses fewer bits than the real method and is easier to update, but still has most of the real coffee ^ ------ -^ --------- (Please read the notes on the back before filling out this page) 556212 A7 Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economy What is the least recently used cache line for the selected column. For simplicity, here is described The quasi-LRU information and related signals are called LRUs, not quasi-LRUs. The three bits of the LRU information stored in the LRU array 108 are sent to the control logic 102 in FIG. The tree diagram shown in Fig. 2 is encoded. [0036] The control logic 102 includes a replacement circuit generator 204 for receiving the picture-LRU [2: 0] signal 142 from the picture-LRU array 108. [0037] The replacement path generator 204 selects a replacement path based on the following rules also shown in FIG. If LRU [2: 0] = 3 'b000, then route 0 is LRU. If LRU [2: 0] = 3' bOOl, then route 1 is LRU. If LRU [2: 0] = 3 ', b010, then Way 0 is LRU. If LRU [2: 0] = 3 '1〇011, then Way 1 is LRU. If LRU [2: 0] = 3' bl00, then Way 2 is LRU. If LRU [2: 0] = 3 'blOl, then Road 2 is LRU. If LRU [2: 0] = 3' M10, then Road 3 is LRU. If LRU [2: 0] = 3 'bill, then Road 3 is LRU. [0038] The replacement method generator 204 generates replacement-way_select [3: 0hfli £ 134 in response to the LRU [2: 0] signal 142 according to the following equation also shown in FIG. replacement_way_select [0] = replacement-Way_select [l] = replacement_ way_select [2] = replacement_way_select [3] delete 2] & ~ LRU [0] -LRU [2 ] & LRU [0] LRU [2] & ~ LRU [1] LRU [2] & LRU [1] [0039] The control logic 102 also includes a new LRU generator (new LRU 16 This paper size applies to China National Standard (CNS) A4 Specification (210 χ 297 mm) (Please read the precautions on the back before filling out this page) Engine Installation ---- tr --------- ^^ 1. 556212
發明說明（+ 經濟部智慧財產局員工消費合作社印製 generator) 206，用以接收來自 LRU 陣列 1〇8 之 lru[2:0] 訊號142。该新LRU產生器206也從置換路產生器2〇4接收 replacement—way一select[3:0]訊號 134。新 LRU 產生器 206 基於下表一所示之規則（亦顧示於圖二），產生新Lru資 訊0 置換路 位元變化 0 ' 一 0x0=>lxl i ' 0xl=>lx0 2 10x=>01x 3 llx=>00x 表一 [0040] 將表一的規則進一步解釋如下。若路Q是置換 路，則藉由設定LRU[2]、不改變LRU[1]以及設定LRU[0]， 以偏離路0，因為其現在即為最近被最常使用的。若路1是 置換路，則藉由設定LRU[2]、不改變LRU[1]以及重設 LRU[0]，以偏離路1，因為其現在即為最近被最常使用的。 若路2是置換路，則藉由重設LRU[2]、設定LRU[1]以及不 改變LRU[0]，以偏離路2，因為其現在即為最近被最常使 用的。若路3是置換路，則藉由重設lru[2]、重設LRU[1] 以及不改變LRU[0]，以偏離路3，因為其現在即為最近被 最常使用的。 [0041] 新LRU產生器206依據亦顯示於圖二之下列等 式，產生圖一之新LRU[2:0]訊號144。 -----------裝--------訂--------- (請先閱讀背面之注音？事項再填寫本頁) 17 556212 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（丨，） new_LRU[0]= //若置換路〇，設定[0]Description of the invention (+ printed by generator of consumer cooperative of employee of Intellectual Property Bureau of Ministry of Economy) 206 for receiving lru [2: 0] signal 142 from LRU array 108. The new LRU generator 206 also receives a replacement_way_select [3: 0] signal 134 from the replacement way generator 204. The new LRU generator 206 generates new Lru information based on the rules shown in Table 1 below (also shown in Figure 2). 0 Replaces the bit change of the channel. 0 '-0x0 = > lxl i' 0xl = > lx0 2 10x = > 01x 3 llx = > 00x Table 1 [0040] The rules of Table 1 are further explained as follows. If the path Q is a permutation path, it is deviated from the path 0 by setting LRU [2], not changing LRU [1], and setting LRU [0], because it is now the most commonly used. If the way 1 is a replacement way, the way 1 is deviated from the way 1 by setting LRU [2], not changing LRU [1], and resetting LRU [0], because it is now the most commonly used. If way 2 is a replacement way, deviate from way 2 by resetting LRU [2], setting LRU [1], and not changing LRU [0], because it is now the most commonly used. If the way 3 is a replacement way, the way 3 is deviated by resetting lru [2], resetting LRU [1], and not changing LRU [0], because it is now the most commonly used. [0041] The new LRU generator 206 generates a new LRU [2: 0] signal 144 of FIG. 1 according to the following equation also shown in FIG. ----------- Install -------- Order --------- (Please read the phonetic on the back? Matters before filling out this page) 17 556212 Intellectual Property of the Ministry of Economic Affairs A7 B7 printed by the Bureau's Consumer Cooperatives V. Description of the invention (丨,) new_LRU [0] = // If the road is replaced by 0, set [0]
rep 1 acement_way_.se 1 ec t [ 0 ] I //若置換路1，重設[0](不設定） //若置換路2，寫入舊的[0] replacement—way—select[2] & LRU[0] | //若置換路3，寫入舊的[0] replacement—way一select[3] & LRU[0]; new—LRU[1]=： //若置換路〇，寫入舊的[1] replacement—way—select[0] & LRU[1] | //若置換路1，寫入舊的[1] replacement—way—select[l] & LRU[1] | //若置換路2，設定[1] replacement—way—select[ 2]; //若置換路3，重設[1](不設定） new—LRU[2]= //若置換路〇，設定[2] r ep1acement—way—se1ect[0] | //若置換路1，設定[2] replacement_way_select[l]; //若置換路2，重設[2](不設定） //若置換路3，重設[2](不設定） [0042] 現請參閱圖三，其顯示出說明圖—之習 記憶體1GG如何置換-快取線之運作流程圖。此 始於方塊302。 [0043] 於方塊302巾，圖-的索引116藉由圖一之列 選擇訊號132送至圖一 LRU陣列108，以選取LRU陣列1〇8 (請先閱讀背面之注音？事項再填寫本頁) ▼-裝--------訂---------AWI ·rep 1 acement_way_.se 1 ec t [0] I // If the way 1 is replaced, reset [0] (not set) // If the way 2 is replaced, write the old [0] replacement—way—select [2] & LRU [0] | // If the way 3 is replaced, write the old [0] replacement_way_select [3] & LRU [0]; new—LRU [1] =: // if the way is replaced , Write the old [1] replacement_way_select [0] & LRU [1] | // If the way 1 is replaced, write the old [1] replacement_way_select [l] & LRU [1 ] | // If the way 2 is replaced, set [1] replacement—way—select [2]; // If the way 3 is replaced, reset [1] (not set) new—LRU [2] = // If the way is replaced 〇, set [2] r ep1acement_way_se1ect [0] | // If replacing the way 1, set [2] replacement_way_select [l]; // If replacing the way 2, reset [2] (not set) // If the path 3 is replaced, reset [2] (not set) [0042] Please refer to FIG. 3, which shows an explanatory diagram—the operation flow chart of how the memory 1GG is replaced with the cache line. This begins at block 302. [0043] In box 302, the index 116 of FIG. 1 is sent to the LRU array 108 of FIG. 1 through the selection signal 132 of FIG. ) ▼ -install -------- order --------- AWI ·
A7 B7 556212 五、發明說明（β ) 之一列。流程則自方塊302進行至方塊304。 [0044] 於方塊304中，從LRU陣列108之被選取列的 LRU儲存元件158讀取LRU資訊，並藉由LRU [ 2 ·· 0 ]訊號142 送至圖一之控制邏輯102。流程則自方塊304進行到方塊 306。 [0045] 於方塊306中，圖二之置換路產生器204產生 replacement—way—select[3:0]訊號 134，如關於圖二部分 所述。流程則自方塊306進行至方塊308。 [0046] 於方塊308中，圖二之新LRU產生器206產生 圖一之newJLRU[2:0]訊號144，如關於圖二部分所述。流 程則自方塊308進行至方塊312。 [0047] 於方塊312中，圖一之新快取線128被寫入由 列選擇訊號 132 與 replacement_way_select[3:0]訊號 134 所選取之圖一快取線儲存元件156中。流程則自方塊312 進行至方塊314。 [0048] 於方塊314中，圖一之新標記122被寫入由列 選擇訊號 132 與 rep 1 acement—way—se 1 ect [ 3:0 ]訊號 134 所 選取之圖一標記儲存元件154中。流程則自方塊314進行 至方塊316。 [0049] 於方塊316中，new—LRU[2:0]訊號144上之新 LRU資訊被寫入由列選擇訊號132所選取之圖一之LRU儲存 元件158中。流程則終止於方塊316。 [0050] 從圖一到圖三很容易看出，習用的關聯快取記 憶體在標記陣列與資料陣列外，以一分離之陣列來儲存 ---------------------訂---------線--AWI C請先閱讀背面之注音W事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） A7A7 B7 556212 V. One column of the description of the invention (β). Flow proceeds from block 302 to block 304. [0044] In block 304, the LRU information is read from the LRU storage element 158 of the selected row of the LRU array 108, and sent to the control logic 102 of FIG. 1 through the LRU [2 ·· 0] signal 142. Flow proceeds from block 304 to block 306. [0045] In block 306, the replacement path generator 204 of FIG. 2 generates a replacement_way_select [3: 0] signal 134, as described in relation to FIG. 2. Flow proceeds from block 306 to block 308. [0046] In block 308, the new LRU generator 206 of FIG. 2 generates a newJLRU [2: 0] signal 144 of FIG. 1, as described in relation to FIG. The process then proceeds from block 308 to block 312. [0047] In block 312, the new cache line 128 of FIG. 1 is written into the cache line storage element 156 selected by the row selection signal 132 and the replacement_way_select [3: 0] signal 134. Flow proceeds from block 312 to block 314. [0048] In block 314, the new mark 122 of FIG. 1 is written into the mark-mark storage element 154 selected by the column selection signal 132 and the rep 1 acement_way_se 1 ect [3: 0] signal 134. Flow proceeds from block 314 to block 316. [0049] In block 316, the new LRU information on the new-LRU [2: 0] signal 144 is written into the LRU storage element 158 of FIG. 1 selected by the row selection signal 132. The process ends at block 316. [0050] It is easy to see from FIGS. 1 to 3 that the conventional associative cache memory is stored in a separate array outside the mark array and the data array. ------- Order --------- line--AWI C, please read the note W on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperatives Paper size applicable to China National Standard (CNS) A4 Specification (21〇X 297 Public Love) A7
--------^---- (請先閱讀背面之注意事項再填寫本頁) ϋ I ϋ I I 556212 LRU，習用關聯快取記憶體使用一分離之刷陣列的理由 疋，每次在一被選取列之任一路，亦即快取線與標記，被 更新時，-列之LRU資訊也可能隨之更新。相反地，一標 記陣列係以每-路，亦即每一標記為單位來更新。也就是， -次只有標記_ N路巾之-路被更新。如上所討論，採 用實體上分離之資料、標記及LRU陣列，躲明顯的缺點。 因此，如本發明所提供的，只使科—的具複數個儲存元 件之陣列來儲存標記與路置換資訊是非常理想的。然而， 由於標記是以每路為單位來更新的，因此需要一種解決方 法，其允許路置換資訊也能以每路為單位來加以更新。 [0051]本發明提供一種關聯快取記憶體，其將LRU陣 列整合於標記陣列中。、正常的LRU資訊，亦即每列之LRU 資訊或列特定（row-specific)資訊，被解碼成路特定 (way-specific)資訊或以每路為單位之資訊，該資訊係 特定於要被置換之路。這使得每路之LRU資訊在快取線之 個別私§己被寫入（亦即以每路為單位）.的同時，也被存入 私σ己陣列。也就疋，母路之L即資訊可被寫到標記陣列中 經-個別的路，而不需寫到列中所有的路。為了決定一被選 | 取列的哪一路要被置換，自所有的路讀取每路之LRU資訊， | 並編碼成縣鱗狀LRU料。轉碼無碼的步驟有 | 利地使標記及LRU陣列得以整合。如接下來將提到的，要 孟 儲存每路之已解碼LRU位元，會比正常每路之列LRU位元-------- ^ ---- (Please read the precautions on the back before filling out this page) ϋ I ϋ II 556212 LRU, the reason for using a separate brush array for custom associative cache memory, each When any one of the selected rows, namely the cache line and the tag, is updated, the LRU information of the -row may also be updated accordingly. In contrast, a tag array is updated on a per-way basis, i.e., every tag unit. That is, -times only the marked-N way towel-way is updated. As discussed above, the use of physically separated data, tags, and LRU arrays avoids the obvious disadvantages. Therefore, as provided by the present invention, it is very desirable to use only an array of a plurality of storage elements to store marker and path replacement information. However, since the markers are updated on a per-channel basis, a solution is needed that allows the way replacement information to be updated on a per-channel basis. [0051] The present invention provides an associative cache memory that integrates an LRU array into a tag array. Normal LRU information, that is, each row of LRU information or row-specific information, is decoded into way-specific information or information on a per-channel basis, which is specific to the information to be The road to replacement. This allows the LRU information of each channel to be written into the private line of the cache line (ie, each channel is taken as a unit). At the same time, the LRU information is also stored in the private sigma array. In other words, the L of the mother road, that is, the information can be written into the tag array via individual roads, instead of all roads in the column. In order to decide which one of the selected | is to be replaced, read the LRU information of each way from all the ways, and encode it into county scale LRU data. The steps to transcode without code are | enabling the integration of markers and LRU arrays. As will be mentioned next, it is necessary to store the decoded LRU bits of each channel more than the normal LRU bits of each channel.
| &要更多的儲存空間，但如此就可以不需要—分離之LRU $ 陣列，此乃其優點。| & requires more storage space, but this is not necessary-a separate LRU $ array is its advantage.
U I___ 20 本紙張 (CNS)A4 祕（21G x 297^)----—_ 556212 556212 A7 B7U I___ 20 Paper (CNS) A4 Secret (21G x 297 ^) ----—_ 556212 556212 A7 B7
[0052] 現請參閱圖四，其顯示本發明之—四 Γ=㈣，，非有另外指明，快取記憶體_ 夹A二麵，、取5己憶體100的元件標號相同的部分， 表不，、功此類似。符別是，侠取記憶體侧並不包含一如 圖-習用^記憶體1〇〇所具有之分離的⑽陣列。相反 ^ LRU資訊係被整合入快取記憶體彻之一標記陣列刪 [0053] 快取記憶體彻包含一資料陣列⑽及解多工 器126，類似於圖-所述標號近似的元件。於一示範之實施 =中，資料陣列106可儲存_的資料。每一快取線包含 位tl組。因此每-列可以儲存128位元組。所以 陣列106包含了 512列、。 、 [0054] 快取記憶體4〇〇包含一標記陣列4〇 陣列404以類似圖一之標記陣列刚的方式配置；缺而， 標記陣列綱之複數個儲存树，可以圖示之標記與lru 儲存7G件454為例，被組態為不只儲存一標記撕，還存了 每路之LRU資訊468。標記陣列4〇4以類似標記陣列1〇6的 方式’配置成-具有與標記陣列1〇6相同數目之列與路的 二維陣列…快取線標記464係存於位在—列與路之交又 點上之-標記與LRU儲存元件454，該標記與LRU儲存元件 454則對應於資料陣列中位於相同之列與路的快取線儲存 元件156。列選擇訊號132亦被送至標記陣列4〇4。快取位 址112之標記部份114則以新標記訊號122送出。列選擇 訊號132選取標記陣列404之其中一列，以寫入新標記 I______21[0052] Please refer to FIG. 4, which shows the present invention—four Γ = ㈣, unless otherwise specified, the cache memory _ folder A on both sides, and the same component number of 5 memory 100 is taken, No, it's similar. The difference is that the Xia memory side does not contain a separate unitary array as shown in Figure-Conventional ^ Memory 100. On the contrary, the LRU information is integrated into a cache memory and a tag array is deleted. [0053] The cache memory contains a data array and a demultiplexer 126, similar to the components shown in FIG. In a demonstration implementation, the data array 106 can store data. Each cache line contains groups of bits tl. So each column can store 128 bytes. So the array 106 contains 512 columns. [0054] The cache memory 400 includes a tag array 40 and the array 404 is configured in a manner similar to that of the tag array of FIG. 1; As an example, storing 7G pieces 454 is configured not only to store a mark tear, but also to store LRU information 468 for each channel. The marker array 4 ′ is configured in a manner similar to the marker array 106—a two-dimensional array having the same number of columns and paths as the marker array 106… the cache line marker 464 is located in the—column and path The intersection and the point-mark and LRU storage element 454 correspond to the cache line storage element 156 in the same row and path in the data array. The column selection signal 132 is also sent to the mark array 404. The tag portion 114 of the cache address 112 is sent with a new tag signal 122. Column selection Signal 132 selects one of the columns of the mark array 404 to write a new mark I______21
本紙張尺㈣用巾國國家鮮（CNS)A4規格（21GNational Paper (CNS) A4 (21G)
--------t----- (請先閱讀背面之注咅5事項再填寫本頁) ^•1. 556212 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（yl ) 122。在-快取記憶體400的讀取操作中，標記u 做比較，以確定是否發生-快取命中。除了儲存蛛2 記464與每路之LRU資訊，標記儲存元件454也可儲^ 快取狀態資訊，像是腿狀態資訊，或關聯於其他= 致性演算法之快取狀態資訊。 、 [0055] 在一個具體實施例中，每路LRU資訊_包含 二個位元。每路資訊468的編碼方式不同於存在圖一之匕即 陣列108的LRU資訊，此因儲存於標記陣列4〇4之每路的 LRU复468疋以母路為單位而更新，而儲存於^即陣列 108中之LRU資訊則以每列為單位而更新。雖然每路^即資 机468疋以母路為單位而寫入，但卻仍是以每列為單位而 讀取，如同在標記陣列404之被選定列中讀取標記的方式。 也就是’從被選定列的四路中每一路讀取每路Lru資訊 468,以確定哪一路是最近被最少使用的。每路lru資訊468 之編碼與解碼方式將於下文詳述。 [0056] 快取記憶體400也包含一第二解多工器424， 耦接至標記陣列404。解多工器424亦由 replacement-way-select[3:0]訊號 434 來控制，選取標記 陣列404的四路其中之一，以寫入新標記122。解多工器 124接收此新標記122，並選擇性地將其送至由 r印lacement_way—select[3:0]訊號434所指定標記陣列 404的四路其中之一。因此，新標記122被寫入由列選擇訊 號 132 所選取之列中，由 replacement—way—select[3:0] 訊號434所選取之路之一儲存元件454。 22 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------訂--------- (請先閱讀背面之注意事項再填寫本頁) 556212 A7-------- t ----- (Please read Note 5 on the back before filling out this page) ^ • 1. 556212 Printed by A7, Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs yl) 122. In a read operation of the cache 400, the tag u is compared to determine whether a cache-hit occurs. In addition to storing Spider 2 memory 464 and LRU information for each channel, the tag storage element 454 can also store cache status information, such as leg status information, or cache status information associated with other = consistency algorithms. [0055] In a specific embodiment, each channel of LRU information includes two bits. The encoding method of each channel of information 468 is different from the LRU information of array 108 shown in Figure 1. This is because the LRU of each channel stored in the tag array 404 is 468. It is updated in the unit of the parent channel and stored in ^ That is, the LRU information in the array 108 is updated in units of each column. Although each channel ^ is written in units of the parent channel, it is still read in units of each column, just as the marks are read in the selected column of the mark array 404. That is, 'read each Lru information 468 from each of the four channels of the selected column to determine which one has been least recently used. The encoding and decoding methods of each channel of LRU information 468 will be detailed below. [0056] The cache memory 400 also includes a second demultiplexer 424, which is coupled to the tag array 404. The demultiplexer 424 is also controlled by a replacement-way-select [3: 0] signal 434, and one of the four ways of the mark array 404 is selected to write a new mark 122. Demultiplexer 124 receives this new tag 122 and selectively sends it to one of the four ways of tag array 404 specified by print_way_select [3: 0] signal 434. Therefore, the new mark 122 is written into the column selected by the row selection signal 132, and the storage element 454 is one of the roads selected by the replacement_way_select [3: 0] signal 434. 22 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------- Order --------- (Please read the precautions on the back before filling this page ) 556212 A7
五、發明說明（>>) 經濟部智慧財產局員工消費合作社印製 [0057]此外，解多工器424接收由控制邏輯4〇2所產 生之一 new一per一way一LRU[1:0]訊號 444。解多工器 424 接 收new—per__way—LRU [ 1 ·· 0 ]訊號444，並選擇性地提供 new一per一way一LRU [ 1 ·· 0 ]訊號 444 至由 rep 1 acement—way— select[3:0]訊號434所指定之標記陣列404的四路其中之 一。因此，new一per一way一LRU[1:0]訊號 444 隨著新標記 122 一併被寫入由列選擇訊號132所選取之列中，由 rep 1 acement—way一se 1 ect [ 3:0 ]訊號 434 所選取之路的一儲 存元件454中。控制邏輯402產生new—per一way—LRU[ 1:0] 訊號444,以回應來自於標記陣列404 —被選取列的所有四 路之兩位元的per一way一LRU資訊468，該資訊468係經由 per—way_LRU[ 7 ·· 0 ]訊藏442送至控制邏輯402，如下文關於 圖五部分所述。如圖所示，來自於標記陣列404之路〇、路 1、路2及路3的perjay一LRU資訊468分別經由訊號 per一way_LRU [ 1 ·· 0 ] 442、per—way—LRU [ 3 ·· 2 ] 442、 1)61：3^一1^1][5:4] 442 及1361^37—1^1][7:6] 442 送出。控 制邏輯402則根據perjay_LRU[7:0]訊號442來產生 以口13〇611^111：_〜87_5616(：1；[3:0]訊號434，細節如下文依照 圖五將要敘述的部分。 [0058] 現請參閱圖五，其顯示本發明之圖四快取記憶 體400之控制邏輯402的方塊圖。圖五亦顯示描述包含於 每一方塊之組合邏輯的等式。 [0059] 控制邏輯402包含一 per_wayJLRU至 per_row_LRU 編碼器 502。per_way—LRU 至 perjrowJLRU 編 23 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 556212 經濟部智慧財產局員工消費合作社印製 A7 —-----------B7_____ 五、發明說明（Μ) 碼器502接收圖四之per_wayJLRU[7:〇]訊號442，並依據 圖玉所示之下列等式，回應地產生per_r〇w_LRU[2:〇]訊號 508 〇 per 一 row_LRU [2] =per— way—LRU [1] Λ // 路 0[1] per—way—LRU [3] Λ // 路 1[1] per一 way—LRU [5] Λ // 路 2[1] 一row— LRU [1] per一 way一 LRU [7]; // 路 3[1] per. =per_way_LRU [4] // 路 2[0] 一row— LRU [〇] per—way—LRU [6]; // 路 3[0] per =per—way—LRU [0] a // 路 0[0] per一way— LRU [2]; // 路 1[0] [0060] 從 per—way—LRU 至 per_rowJLRU 編碼器 502 之 等式可看出，編碼器5〇έ以預定的方式對per_wayJLRU[7:0] 訊號442執行二進位的互斥或（exciusive-〇R)運算，以 將訊號442上之每路的LRU資訊編碼成標準的三位元準LRU 形式，如關於圖二部分所述。 [0061] 控制邏輯402也包含一類似於圖二之置換路產 生器204的置換路產生器504。此置換路產生器504接收 per一row—LRU[2:0]訊號508，並依據亦顯示於圖五之下列等 式，回應地產生圖四之rep 1 acement—way—se 1 ect [ 3:0 ]訊號 434 〇 replacement—way—select [0]=〜per—row—LRU [2] & 〜perj:ow—LRU[0]; replacement一way—select [1]=〜per—row—LRU [2] & (請先閲讀背面之注意事項再填寫本頁)V. Description of the invention (> >) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0057] In addition, the demultiplexer 424 receives one of the new one per one way one LRU generated by the control logic 40 [1] : 0] signal 444. Demultiplexer 424 receives new_per__way_LRU [1 ·· 0] signal 444, and optionally provides new one per one way one LRU [1 ·· 0] signal 444 to rep 1 acement_way_ select [ 3: 0] one of four ways of the tag array 404 designated by the signal 434. Therefore, the new_per_way_LRU [1: 0] signal 444 is written into the column selected by the row selection signal 132 along with the new mark 122, and is represented by rep 1 acement—way_se 1 ect [3: 0] signal 434 in a storage element 454 of the selected path. The control logic 402 generates a new_per_way_LRU [1: 0] signal 444 in response to the per-way_LRU information 468 from the tag array 404-all four-way two-bits of all the selected rows 468, the information 468 It is sent to the control logic 402 via per-way_LRU [7 ·· 0] Xunzang 442, as described below in relation to Figure 5. As shown in the figure, perjay-LRU information 468 from road 0, road 1, road 2, and road 3 of the tag array 404 passes signals per-way_LRU [1 ·· 0] 442, per-way-LRU [3 · · 2] 442, 1) 61: 3 ^ -1 1 ^ 1] [5: 4] 442 and 1361 ^ 37-1 ^ 1] [7: 6] 442. The control logic 402 generates the port 13〇611 ^ 111: _ ~ 87_5616 (: 1; [3: 0] signal 434 according to the perjay_LRU [7: 0] signal 442, the details are as follows according to the part to be described in Figure 5. 0058] Please refer to FIG. 5, which shows a block diagram of the control logic 402 of the cache memory 400 of the present invention. FIG. 5 also shows an equation describing the combination logic included in each block. [0059] Control logic 402 contains a per_wayJLRU to per_row_LRU encoder 502. per_way—LRU to perjrowJLRU series 23 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------- ----- Order --------- (Please read the precautions on the back before filling out this page) 556212 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 —--------- --B7 _____ 5. Explanation of the invention (M) The encoder 502 receives the per_wayJLRU [7: 〇] signal 442 in FIG. 4 and generates the per_r〇w_LRU [2: 〇] signal 508 in response to the following equation shown in FIG. 〇per one row_LRU [2] = per—way—LRU [1] Λ // way 0 [1] per—way—LRU [3] Λ // way 1 [1] per one way—LRU [5] Λ / / Way 2 [1] one row— LRU [1] per one way—LRU [7]; // way 3 [1] per. = Per_way_LRU [4] // way 2 [0] one row— LRU [〇] per— way—LRU [6]; // way 3 [0] per = per—way—LRU [0] a // way 0 [0] per one way— LRU [2]; // way 1 [0] [0060 From the equation of per-way-LRU to per_rowJLRU encoder 502, it can be seen that encoder 50 performs a binary mutex or (exciusive-〇R) on per_wayJLRU [7: 0] signal 442 in a predetermined manner. The operation is to encode the LRU information of each channel on the signal 442 into a standard three-bit quasi-LRU format, as described in relation to FIG. 2. [0061] The control logic 402 also includes a replacement circuit generator similar to that in FIG. The permutation path generator 504 of 204. This permutation path generator 504 receives a per-row_LRU [2: 0] signal 508, and responds to the rep 1 acement of FIG. 4 according to the following equation also shown in FIG. way_se 1 ect [3: 0] signal 434 〇 replacement_way_select [0] = ~ per_row_LRU [2] & ~ perj: ow_LRU [0]; replacement_way_select [1 ] = ~ Per—row—LRU [2] & (Please read the notes on the back first Complete this page)
_ _ I I I I 一δ,， *_^i ϋ mmae I 1 I 24_ _ I I I I Iδ ,, * _ ^ i ϋ mmae I 1 I 24
556212 A7 B7 五、發明說明（>+ ) rep1acement一 way—se1ect rep1acement—way一se1ect per—row一 LRU [0]; per—row一 LRU [2] i 〜per—row—LRU [1]; per—row—LRU [2] & per_row—LRU [1]; [0062]控制邏輯402也包含一 per_way_LRU解碼器 506。此解碼器 506 接收 per—way—LRU[7:0]訊號 442、 per一row—LRU[2:0]訊號 508 及 replacement—way—select [3:0]訊號434，並根據下列等式回應地產生圖四之 new_per—way—LRU [ 1:0 ]訊號 444。 經濟部智慧財產局員工消費合作社印製 new一per一way—LR|J [1]= replacement一way一select [〇] & //若置換路 〇 〜per一row—LRU [2] & //且 per—row—LRU[2]為 0 〜per一way一LRU [ 1 ] 丨//則切換路0之位元[1 ] replacement—way一select [1] & //若置換路 ι ~per_row_LRU [2] & "且 pe：r'_n)W_LRU[2]為 0 〜per—way一 LRU [3] rep1acement—way_select [2] per一row—LRU [2] 〜per—wayJLRU [5] replacement一way一select [3] & //若晉施攸 q 剛為i 〜peir—way—LRU [7]·’ 々則切換路3之位元[1] new 一per—way—LRU [0]= replacement一way—select [〇] & //若置換路 〇 ~per_row_LRU [0] & "且 Per_r〇w_LRU[0]為 〇 ~per_way_LRU [0] 丨々則切換路〇之位元[0] replacement_way一select [1] & //若置換路工 per_row_LRU [0] & "且 //則切換路1之位元[1] //若置換路2 //且 per—rowjLRU[2]為 1 //則切換路2之位元[1] n ϋ Hi n ϋ ϋ ϋ· i^i · ϋ ϋ a^i n ^^1 in 一 δν I ϋ— 1§ ϋ n ϋ I · (請先閱讀背面之注意事項再填寫本頁) 25 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 2^楚{ 556212 A7 〜per一rowJLRU [1] 〜per一 way一LRU [4] rep 1 acement_way_.se 1 ec t perjrow 一 LRU [1] 〜per一way一LRU [6]; 發明說明（〆） ~per_way_LRU [2] 1 "則切換路i之位元[0] replacement-way—select [2] & //若置換路 2 〒"且per〜r〇w—LRU[l]為 0 丨"則切換路2之位元[〇] I] & //若置換路3 & //且 perjrow—LRUUAl //則切換路3之位元[〇] [0063] 從per一way—LRU解碼器5〇6之等式可看出，此 解碼器506基於被選取用以置換的路來解碼556212 A7 B7 V. Description of the invention (> +) rep1acement-way-se1ect rep1acement-way-se1ect per-row-LRU [0]; per-row-LRU [2] i ~ per-row-LRU [1]; per_row_LRU [2] & per_row_LRU [1]; [0062] The control logic 402 also includes a per_way_LRU decoder 506. This decoder 506 receives per-way-LRU [7: 0] signal 442, per-row-LRU [2: 0] signal 508, and replacement-way-select [3: 0] signal 434, and responds according to the following equation The ground generates the new_per_way_LRU [1: 0] signal 444 in FIG. Printed by the consumer co-operative of the Intellectual Property Bureau of the Ministry of Economic Affairs, new one per one way—LR | J [1] = replacement one way one select [〇] & // If the replacement road 〇 ~ per one row—LRU [2] & // and per-row-LRU [2] is 0 ~ per-way-LRU [1] 丨 // then switch the bit of road 0 [1] replacement-way-select [1] & // if the road is replaced ι ~ per_row_LRU [2] & " and pe: r'_n) W_LRU [2] is 0 ~ per—way-LRU [3] rep1acement—way_select [2] per one row—LRU [2] ~ per-wayJLRU [5] replacement one way one select [3] & // If Jin Shiyou q has just i ~ peir—way—LRU [7] · '切换 then switch the bit of way 3 [1] new one per—way —LRU [0] = replacement_way_select [〇] & // If the replacement path is 0 ~ per_row_LRU [0] & " and Per_r〇w_LRU [0] is 0 ~ per_way_LRU [0] 丨 々 then switch the way The bit of 〇 [0] replacement_way_select [1] & // If the replacement road per_row_LRU [0] & " And // then switch the bit of the road 1 [1] // If the replacement road 2 // And per-rowjLRU [2] is 1 // then switch the bit of path 2 [1] n ϋ Hi n ϋ ϋ i · i ^ i · ϋ ϋ a ^ in ^ ^ 1 in δν I ϋ— 1§ ϋ n ϋ I · (Please read the precautions on the back before filling out this page) 25 This paper size applies Chinese National Standard (CNS) A4 (210 X 2 ^ Chu {556212 A7 ~ Per one rowJLRU [1] ~ per one way one LRU [4] rep 1 acement_way_.se 1 ec t perjrow one LRU [1] ~ per one way one LRU [6]; Invention description () ~ per_way_LRU [2] 1 " then switch the bit of path i [0] replacement-way—select [2] & // If the replacement path 2 〒 " and per ~ r〇w—LRU [l] is 0 丨 " then switch Bit 2 of way 2 [0] I & // If the way 3 is replaced & and perjrow—LRUUAl // then the bit of way 3 is switched [〇] [0063] from per-way-LRU decoder 5 It can be seen from the equation of 〇6 that the decoder 506 decodes based on the path selected for replacement.
per—row—LRU[2:0]訊號508資訊，以產生新的每路之lRU 資訊，在此資訊與從被選取列之其他三路讀取圖四之其他 母路LRU S όίΐ 468集合起來後’將能使per—way—lru至 per一row一LRU編碼器502編碼成原來標準的準LRU形式，如 下文關於圖六部分所述。 [0064] 現請參閱圖六，其為本發明之圖四快取記憶體 400如何置換一快取線之運作流程圖。此流程係始於方塊 602 〇 [0065] 於方塊602中，圖四的索引116藉由圖四之列 選擇訊號132送至圖四標記陣列404，以選取標記陣列404 之一列。流程則自方塊602進行至方塊604。 [0066] 於方塊604中，從標記陣列404之被選取列讀 取 per一way_LRU 資訊 468，並藉由 per jay_LRU[7:0]訊號 442送至圖四之控制邏輯402。流程則自方塊604進行到方 塊 606 〇 [0067] 於方塊606中，圖五之per—way_LRU至 26 表紙張尺度適用中國國家標準（CNS)A4規格（21G X 297公釐） -----------裝--------訂-------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 556212 A7 _、一 B7 五、發明說明（A ) per_row—LRU 編碼器 502 將 per_way—LRU[7:〇]訊號 442 編 碼成perjOW-LRU[2:0]訊號508，如關於圖五部分所述。 而per_wayJJJU[7:0]訊號442於方塊604中係讀取由列選 擇訊號132所選取標記陣列404之列的四路中每一路。流 程則自方塊606進行至方塊608。 [0068] 於方塊608中，圖五之置換路產生器504產生 代？18〇611^111:」^7_3616(：1:[3:0]訊號434，如關於圖五部分 所述。流程則自方塊608進行至方塊612。 [0069] 於方塊612中，圖五之per__way_LRU解碼器506 依據 per_way_LRU[7:0]訊號 442、per_rowJLRU[2:0]訊號 508 及 replacement_way—select[3:0]訊號 434 產生圖四之 newjper_wayJLRU[l:〇l 訊號 444 ，作為 replacement_way_select[3:0]訊號 434 上所指定的置換 路，如關於圖五部份所述。流程則自方塊612進行至方塊 614。 [0070] 於方塊614中，圖四之新快取線128被寫入由 列選擇訊號 132 與 replacement_way_select[3:0]訊號 434 所選取之圖四快取線儲存元件156中。流程則自方塊614 進行至方塊616。 [0071] 於方塊616中，圖四之新標記122與 new一per一way—LRU[1:0]訊號444 一併被寫入由列選擇訊號 132 與 replacement__way_select[3:0]訊號 434 所選取之標 記與LRU儲存元件454中。流程終止於方塊616。 [0072] 從圖四至圖六的實施例可看出’準LRU資訊乃 本紙張尺度適用中國國家標準（CNS)A4規格（21Q x 297公爱了 --------—裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 、發明說明（π ) 跨列分佈，但可以每路為單位而更新，而當一個路被置換 時’準LRU資訊即被更新。此實施例特別適用於犧牲性快 取錢體（victim cache)。然而，此實施例也能簡易地 =用於採用其他LRU更新策略的快取記憶體。例如，準 二貝Λ亦可於其他事件發生時予以更新，像是產生載入命中 (l=ad hit)時。在這樣的實施例中，置換路產生器變成 已存取路產生器」（accessed way generator)，其 在-載人命中（或其他侧更新事件）發生時，選取已存 取之路，並於置換一快取線時選取最近被最少使用之路。 此外丄置換路產生器可將其他用以選取一置換路的因素納 考畺像疋耷在所選取之列中存在一無效的路，則選擇 置換它，而非選擇最近被最少使用的路。 [0073]雖然本發明及其目的、特徵與優點已詳細敘述 了’其它具體實施例仍涵蓋在本發明之範圍内。例如，本 發明適用於具不隨目之路、列及快取線大小的關聯快取 峨體。此外，將·陣合於標記__念以及相 ^之編碼與解碼置_算㈣訊，皆可顧於其他置換演 f法不限於準LRU演算法。再者，本發明也可使用於指 :快取記憶體、資料快取記憶體或組合式的資料/指令快取 ，憶體。最後，本發明並不限於用在將快取記憶體與處理 益整合於相_體電路的_，也可祕_分離之快取 記憶體。 、’悤之’以上所述者’僅為本發明之較佳實施例而已，當 不能以之限定本發_實狀範圍。大驗本發明申請專 556212 A7 _B7_ 五、發明說明（β) 利範圍所作之均等變化與修飾，皆應仍屬於本發明專利涵 蓋之範圍内，謹請貴審查委員明鑑，並祈惠准，是所至禱。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 29 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）per-row—LRU [2: 0] signal 508 information to generate new lRU information for each channel, where this information is assembled with the other parent channels LRU S όίΐ 468 of Figure 4 read from the other three channels selected The latter will enable the per-way-lru to per-row-LRU encoder 502 to be encoded into the original standard quasi-LRU form, as described below with respect to FIG. 6. [0064] Please refer to FIG. 6, which is a flowchart of how the cache memory 400 of FIG. 4 replaces a cache line according to the present invention. This process starts at block 602. [0065] In block 602, the index 116 of FIG. 4 is sent to the mark array 404 of FIG. 4 through the column selection signal 132 of FIG. 4 to select a row of the mark array 404. Flow proceeds from block 602 to block 604. [0066] In block 604, the per-way_LRU information 468 is read from the selected row of the marker array 404, and sent to the control logic 402 of FIG. 4 through the per-jay_LRU [7: 0] signal 442. The flow proceeds from block 604 to block 606. [0067] In block 606, the per-way_LRU to 26 in Figure 5 are applicable to the Chinese national standard (CNS) A4 specification (21G X 297 mm). ----- ------ Equipment -------- Order -------- (Please read the precautions on the back before filling out this page) The Intellectual Property Bureau of the Ministry of Economic Affairs Prints the wisdom of the Ministry of Economy Printed by the Consumer Cooperative of the Property Bureau 556212 A7 _, a B7 V. Description of the invention (A) per_row-LRU encoder 502 encodes per_way-LRU [7: 〇] signal 442 into perjOW-LRU [2: 0] signal 508, As described in relation to Figure 5. And the per_wayJJJU [7: 0] signal 442 in block 604 reads each of the four ways of the row of the mark array 404 selected by the row selection signal 132. Flow proceeds from block 606 to block 608. [0068] In block 608, the replacement circuit generator 504 of FIG. 18〇611 ^ 111: "^ 7_3616 (: 1: [3: 0] signal 434, as described in the fifth part of the figure. The flow proceeds from block 608 to block 612. [0069] In block 612, the fifth figure The per__way_LRU decoder 506 generates the newjper_wayJLRU [l: 〇l signal 444 in Figure 4 according to per_way_LRU [7: 0] signal 442, per_rowJLRU [2: 0] signal 508, and replacement_way_select [3: 0] signal 434 as replacement_way_select [3 : 0] The replacement path specified on signal 434, as described in the part of Figure 5. The flow proceeds from block 612 to block 614. [0070] In block 614, the new cache line 128 of figure 4 is written The four cache line storage elements 156 selected by the row selection signal 132 and the replacement_way_select [3: 0] signal 434. The flow proceeds from block 614 to block 616. [0071] In block 616, the new mark of FIG. 122 and new one per one way—LRU [1: 0] signal 444 are written together with the mark selected by the row selection signal 132 and replacement__way_select [3: 0] signal 434 and the LRU storage element 454. The flow ends in the block 616. [0072] It can be seen from the embodiments of FIGS. The paper size of this paper is applicable to China National Standard (CNS) A4 (21Q x 297). Please read the precautions on the back before filling this page), the description of the invention (π) is distributed across columns, but it can be updated on a per-channel basis, and the 'quasi-LRU' information is updated when a channel is replaced. This embodiment is special It is suitable for victim cache. However, this embodiment can also simply be used as a cache memory for adopting other LRU update strategies. For example, the quasi-two shells can also be updated when other events occur. , Such as when a load hit is generated (l = ad hit). In such an embodiment, the permutation way generator becomes an accessed way generator "(accessed way generator), which is- When an update event occurs, select the accessed path, and select the least recently used path when replacing a cache line. In addition, the replacement path generator can consider other factors used to select a replacement path.存在 If there is an invalid way in the selected column, choose to replace it instead of choosing the most Path is the least used. [0073] Although the present invention and the objects, features and advantages have been described in detail 'still other embodiments encompassed within the scope of the present invention. For example, the present invention is applicable to an associated cache body with a size of a road, a column, and a cache line that is not in sight. In addition, the combination of the encoding and decoding in the mark __ concept and the __ calculation information can be taken into account that other permutation methods are not limited to the quasi-LRU algorithm. Furthermore, the present invention can also be used to refer to: cache memory, data cache memory, or combined data / instruction cache, memory. Finally, the present invention is not limited to the use of integrating the cache memory and the processing benefits in the phase circuit, but can also secretly separate the cache memory. "The above" is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the present invention. Examination of the application for this invention 556212 A7 _B7_ V. The equal changes and modifications made in the scope of the invention (β) should still fall within the scope of the invention patent. I would like to ask your reviewers to make a clear note and pray for approval. All prayers. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 29 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
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| US10/046,056 US20030159003A1 (en) | 2001-10-23 | 2002-01-14 | Associative cache memory with replacement way information integrated into directory |
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| US7139877B2 (en) | 2003-01-16 | 2006-11-21 | Ip-First, Llc | Microprocessor and apparatus for performing speculative load operation from a stack memory cache |
| US7191291B2 (en) | 2003-01-16 | 2007-03-13 | Ip-First, Llc | Microprocessor with variable latency stack cache |
| US7139876B2 (en) * | 2003-01-16 | 2006-11-21 | Ip-First, Llc | Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache |
| US6973540B2 (en) * | 2003-07-25 | 2005-12-06 | Freescale Semiconductor, Inc. | Method and apparatus for selecting cache ways available for replacement |
| TWI294569B (en) * | 2004-01-16 | 2008-03-11 | Ip First Llc | Apparatus and method for performing fast pop operation from random access cache memory and computer-readable storage medium |
| CN106776366B (en) * | 2016-11-18 | 2019-11-22 | 华为技术有限公司 | Address access method and device |
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| MK4A | Expiration of patent term of an invention patent |