TW550824B

TW550824B - A thin film transistor panel for a liquid crystal display

Info

Publication number: TW550824B
Application number: TW91117517A
Authority: TW
Inventors: Dong-Gyu Kim
Original assignee: Samsung Electronics Co Ltd
Priority date: 2001-02-26
Filing date: 2002-08-02
Publication date: 2003-09-01

Abstract

There are provided two subpixels opposite each other with respect to each data line. A pair of gate lines are provided for each row of pixels. A plurality of subsidiary signal lines are provided between the adjoining columns of the pixels. The data lines and the subsidiary signal lines are alternately arranged between the adjoining columns of the pixels. A storage wire is provided between the adjoining rows of the pixels.

Description

550824 柒、發明說明【發明所屬之技術領域】本發明係關於用於一液晶顯示器列基板。【先前技術】液晶顯示器（LCD)係為最常使用之 LCD係包含數個電極於其上與一液晶板，其並藉由施加電壓於電極以重置液以控制入射光線之穿透。在這些LCD中，具有提供於各自 LCD與用於轉換施於電極之電廢之數伯係典型地使用。TFTs係常提供於數個素，且每一像素在TFTs控制下係包含像素電極。此外，分別連結於閘驅動並供應用以控制像素之掃描訊號之閘轉料驅動ICs之輸出終端並供應影像訊韻一薄膜電晶體陣列基板上。矩陣中，相閘線與資料線係經TFTs連接於像素之於一視頻圖形陣列（VGA )尺寸數目為1920時，則閘線數目為48〇，線數目之四倍。此外，於一廣視頻圖子寸LCD中，當資料線數目為2400時，j 資料線數目係為閘線數目之五倍。此# 用數目為閘驅動ICs之四至五倍。之一薄膜電晶體陣平面顯示器之一。層置於其間之兩基 .晶層之液晶分子加基板上之電極之一 3薄膜電晶體（TFTs) 排列於矩陣中之像 -施予影像訊號之一 IC(ICs)之輸出終端 L，及分別連接於資 :之資料線係提供於 I交以界定出像素之像素電極。 LCD中，當資料線資料線數目係為閘咳陣列（WVGA )尺扣閘線數目為480， ^表資料驅動ICs使 3 550824 建立閘驅最小素間型或每一【内液晶一薄示器像素同閘設置素之中，然而，在製造LCD中，需要將製造成本降至最小以在市場上的競爭力。為此目的’因為資料驅動1〇比動ICs更為昂貴，故必須將資料驅動ICs之數目降至 Ο 同時，為了改善-顯示器裝置之能見《，截止相鄰像之光戌漏係十分重|，特別為用於具有—光源之發射半發射型。此外，於半反半透型（transflective type)中，欲求使像素具有均一反射薄膜之反射係數。容】本發明之一目的係提供具有最小化製造成本之用於一顯不器之一薄膜電晶體陣列基板。本發明之另_目的係提供可截止像素電極間光洩漏之膜電晶體陣列基板。本發明之再一目的係獲致具有均一反射係數之液晶顯 :了疋：上述之目❸，一資料線係電性連接於兩相鄰、象素％極並傳送影像訊號，且每一像素係連接於不 ^ 丁万向延伸之資料線與輔助訊號線係交替地儲存線係沿橫列方向延伸。它們與分配於各 if素電極邊緣重疊以截止光洩漏。此外，在一種製作包含一反射膜之液晶顯示器之方法用於在純.邊層表面上形成均—不平坦之—光罩部分係 4 550824 被建立，以較於其他部用於一線路、一資中該閘線路訊號之成對與第二薄膜列；該資料線絕緣並分各自之資料極為基礎與體之汲極；替設置，而個像素電極與資料線，疊。薄膜電線路以形成向貫質延伸電極，而每另一用閘線路、— 含數個成對二薄膜電晶 =對應於資料線路之光罩之可穿透部分刀一縮減之寬度，藉此降低發射之光量液晶顯示器之一薄膜電晶體基板係具有料線路、數個輔助訊號線與數個像素電係包含數個於水平方向實質地延伸並傳閘線，及包含數個分別連接於成對閘線電晶體之閘電極，而每對閘線係分配於線路係包含數個於垂直方向實質地延伸別分配於兩相鄰像素行之資料線，數個線之第一與第二薄膜電晶體之源極，及源極分開並相對立設置之第一與第二薄該數個輔助訊號線係與閘線絕緣並與資每一輔助訊號線係被分配於一像素行；係經第一與第二薄膜電晶體連接於成對像素電極之邊緣係與資料線與辅助訊晶體陣列基板更包含與像素電極重疊之儲存電容。儲存線路係較佳包含數個於之儲存電極線與數個連接於儲存電極線一儲存電極與汉極重疊。於液晶顯示器之薄膜電晶體陣列基板係資料線路與數個像素電極，其中該閘線閘線與數個分別連接於該成對閘線之第體之閘電極，而該成對閘線於水平方向具有相 0 :一閘極，其送掃描之第一一像素、與閘連接於以閘電膜電晶料線交而該數之閘線號線重一儲存水平方之儲存包含一路係包一與第實質地 5 550824 分別像素之頂部與底部及傳送掃描訊號 ’、匕含數個資料線、數個連接於各自之資袓一與第 '-落 n ^ —、膜電晶體之源極、及與該源極分開並w 極為基礎柏掷上人、野互於該源極放置之第一與第二薄膜啦汲·極，而与》、欠电、、以資料線於垂直方向實質地延伸以界定出並與"閘结；姐、、、、彖且分別分配於兩相鄰像素；而該赵電極，係細a、々々 h、’’二孩弟一與第二薄膜電晶體連接於該與該資料線。 :料、、泉較佳地設置於兩像素之一中心。薄膜電晶體陣列基板更包含與像素電極重疊之、泉路以形成儲存電容。儲存線路係較佳包含數個於向實質延伸之儲存電極線與數個連接於儲存電極線電極、於垂直方向實質地延伸並與像素電極之—邊之儲存電極。每一資料線係具有一雙線結構且資料線之雙線藉由數個連接器互連。儲存線路係包含僅一於水平方向延伸並與像素電極儲存電極’且薄膜電晶體陣列基板更包含一連接於像素電極並與儲存電極線重疊之儲存電容導體圖案【實施方式】本發明現將參考後附之圖示及本發明之較佳實以詳加描述。然而，本發明係可以各式不同形式實應不被侷限於在此所提出之實施例。為了使圖示清晰，故放大圖示中各區域與各 ;該資線之第該閘電晶體之該像素個像素之閘線一儲存水平方之儲存緣重疊係較佳重疊之沒極與〇施例加施，故層之厚 6 550824 度，並以參考數字表示各元件。當一元件諸如域或一基板，係被說明為，，在另一元件之上，，時是’其係表示直接在另一元件之上或表示介於故與之相較，當一元件被說明為，，直接在另_ 時’其係代表介於元件之間的情形不存在。用於一 LCD之薄膜電晶體（TFT)陣列基板發明之一實施例並參考所附之圖示加以詳細描首先’ 一半反半透式（transflective)LCD : 基板之結構之佈局圖，係根據本發明之第一實第1圖與第2圖加以描述。第1圖為本發明之一第一實施例，用於_ 膜電晶體（TFT)陣列基板之結構之佈局圖；而著第1圖所示之TFT陣列基板之ιΜι，剖面線如第1圖與第2圖所示，根據本發明之一閘線路係較佳以導體材料或金屬材料（諸如鋁鉬或鎢化鉬合金、鉻、钽 '銅或銅合金）形成於之TFT陣列基板之上。閘線路係包含數個閘 12 12、數個閘墊1251與1252及數個TFTs、與1232，其中該閘線係於水平方向延伸，並於每列像素；該閘塾係連接於各自閘線1 2 1 1 末端，並自外部訊號源傳送閘訊號至相連之間 1 2 1 2 ’而該閘電極係各自連結於閘線1 2 1 1與地設置。 μ 此外，一儲存線路係形成於一基板1 1 〇、一層、一區，應理解的元件之間。一元件之上” ，係根據本述。 t TFT陣列 ‘施例，參考 - LCD之薄第2圖為沿之剖面圖。實施例，一或鋁合金、用於一 LCD 線 1 2 1 1與閘電極1 2 3 1 成對被分配趣1212之一線 1211與 1212並交替上，其包含 7 550824 ，個儲存電㈣131與數個予㈣接之料電極⑴。儲 ^極線131係平行閘線1211與i2i2延伸並設置於像素欲《間。每-儲存電極、線131係接收一電壓，該電壓諸如攸施於一上邵基板、 Mr)乏一共用電極（未示於圖中）之一共用電極電壓。每一靨母儲存電極133係具有大於與其相關之儲存電極線丨31之貧 .v <見度，並被分配至各自之像素。與汲極1751與1 752相互重曇 > 辟六純儲存線路131與133 係電性與物性連接於像素電極19〇1與19〇2,此於稍後描述’以形成改善像素之電荷儲存容量之儲存電容。此外，儲存電極線1 3 1係於垂畫六而α & 于於*罝万向延伸，以被置於像素之間並與像素電極19〇1與Β02之邊唆却八杳田 — 雙、，象4为重畳，藉此防止像素區域間之光洩漏。閘線路 1211 、 1212 、 1231 1232、1251 與 1252 及儲存線路1 3 1與1 3 3係較佳且右〇 —人μ 住八育以包含鋁之材料製成之一單層結構。…替換為多層結構。在此情形中，希望多層結構其中之-層以低電阻材料製成…一層以包含鉻、细、絡合金與4目合金之傳導性材料製成1中該傳導性材料與其他材料諸如銦-錫-氧„ (ΙΤ〇)、銦_鋅_氧化物 (ΙΖΟ )及基板具有良好接觸特性。在基板 110 上，閘線路 1211、1212、123 1 1232 1 25 1 與1252及儲存線路m與133係以閘絕緣層14〇覆蓋，該閘絕緣層係較佳以氮化矽（siNX)材料形成。一半導體層1 5 1與1 5 2係以如非結晶矽之半導體材形成於問絕緣層14〇上並分別與閑電極1231與1232相對 8 550824 以梦化物材料或大量材料形成於半導體層立。歐姆接觸層1632與1652係較佳摻雜η型不純物之n+氫化非結晶矽 151與152上。歐姆接觸層1 632與1 652係具有以每一閘電極123 1或1232為基礎，彼此分開之兩部分I。2與 1 652 0 -資料線路係較佳以導體或金屬材料(諸如銘、銘合金、鉬、鉬合金、鉻與鈕）形成於歐姆接觸層1 632與Μ” 及閘絕緣層140上。550824 2. Description of the invention [Technical field to which the invention belongs] The present invention relates to a substrate for a liquid crystal display. [Prior art] Liquid crystal display (LCD) is the most commonly used LCD system. It includes several electrodes on it and a liquid crystal panel, and the electrode is reset by applying a voltage to the electrode to control the penetration of incident light. Among these LCDs, it is typically used to have a number of systems provided to the respective LCDs and to convert electrical waste applied to the electrodes. TFTs are often provided in several pixels, and each pixel includes a pixel electrode under the control of TFTs. In addition, the output terminals of the gate driver ICs which are connected to the gate driver and supply the scanning signals for controlling the pixels are respectively supplied to the image signal on a thin film transistor array substrate. In the matrix, the gate lines and data lines are connected to the pixels via TFTs in a video graphics array (VGA). When the number of sizes is 1920, the number of gate lines is 48, which is four times the number of lines. In addition, in the Yiguang video picture LCD, when the number of data lines is 2400, the number of j data lines is five times the number of gate lines. This number is four to five times the number of gate drive ICs. One of the thin film transistor arrays is one of the flat panel displays. The two layers are placed between them. One of the liquid crystal molecules of the crystal layer plus one of the electrodes on the substrate. 3 Thin film transistors (TFTs) arranged in a matrix-the output terminal L of one of the ICs (ICs) that applies the image signal, The data lines connected to the data lines are provided at the pixel electrodes to define the pixel electrodes of the pixels. In LCD, when the number of data lines is 480 claw array (WVGA) ruler, the number of gate lines is 480, ^ table data driver ICs enable 3 550824 to build the smallest gate driver type or each [internal liquid crystal thin display Pixels are set in the same gate. However, in manufacturing LCDs, manufacturing costs need to be minimized to be competitive in the market. To this end, because data-driven 10s are more expensive than dynamic ICs, the number of data-driven ICs must be reduced to 0. At the same time, in order to improve the visibility of display devices, the light leakage of cut-off adjacent images is very heavy | , Especially for the semi-emission type with a light source. In addition, in a transflective type, it is desired to make a pixel have a reflection coefficient of a uniform reflection film. It is an object of the present invention to provide a thin film transistor array substrate for a display device with minimized manufacturing cost. Another object of the present invention is to provide a film transistor array substrate capable of blocking light leakage between pixel electrodes. Another object of the present invention is to obtain a liquid crystal display with a uniform reflection coefficient: the above-mentioned purpose: a data line is electrically connected to two adjacent, pixel% poles and transmits an image signal, and each pixel is The data lines and auxiliary signal lines connected to the extended universal line are alternately stored and extended along the horizontal direction. They overlap the edges of the electrode electrodes allocated to each element to stop light leakage. In addition, a method for fabricating a liquid crystal display including a reflective film for forming a uniform-uneven-photomask portion on the surface of a pure edge layer was established 4 550824, compared with other parts for a circuit, a The signal line of the gate line is paired with the second thin film column; the data line is insulated and divided into the respective data base and the drain of the body; the pixel electrode and the data line are stacked instead. Thin-film electrical circuits to form a continuous extension electrode, and each other uses a gate circuit,-containing several pairs of two thin-film transistors = a reduced width corresponding to the penetrable portion of the photomask corresponding to the data circuit, thereby One of the thin-film transistor substrates of a liquid crystal display with reduced light emission has a material line, a plurality of auxiliary signal lines, and a plurality of pixel electrical systems. The gate electrode of the gate transistor, and each pair of gate lines is allocated to the line system and includes a plurality of data lines extending substantially in the vertical direction and allocated to two adjacent pixel rows, and the first and second films of the plurality of lines The source of the transistor and the first and second thin auxiliary electrodes that are separated from each other and are opposite to each other are insulated from the gate wires and are allocated to a pixel row with each auxiliary signal wire; The first and second thin film transistors are connected to the edge system of the pair of pixel electrodes, the data line and the auxiliary signal crystal array substrate and further include a storage capacitor overlapping the pixel electrode. The storage circuit preferably includes a plurality of storage electrode lines and a plurality of storage electrode lines connected to the storage electrode line. A storage electrode overlaps with the Han pole. The thin film transistor array substrate in a liquid crystal display is a data line and a plurality of pixel electrodes, wherein the gate line gate line and a plurality of gate electrodes respectively connected to the body of the pair of gate lines, and the pair of gate lines are horizontal The direction has phase 0: a gate, which sends the first pixel of the scan, and the gate is connected to the gate line with the gate film, and the number of gate lines is the same as the storage level. The storage includes a system package. The first and the first 5 550824 are the top and bottom of the pixel, respectively, and the scanning signal is transmitted, the data line contains several data lines, and several are connected to the respective resources. The first and the first-the source of the film transistor. And the first and second films placed on the source separated from the source and w are extremely basic, and the field and the first and second films are placed on the source, respectively, and "," underpowered, and the data line is in the vertical direction. The ground electrode is extended to define and be associated with the "gate junction"; sister ,,,, and 彖 are respectively assigned to two adjacent pixels; and the Zhao electrode is a thin 々々, 々々h, `` two children one and two thin films '' A transistor is connected to the data line. : Material, spring is preferably set in the center of one of the two pixels. The thin film transistor array substrate further includes a spring circuit overlapping the pixel electrode to form a storage capacitor. The storage circuit preferably includes a plurality of storage electrode lines extending in a substantial direction and a plurality of storage electrodes connected to the storage electrode line electrodes, extending substantially in a vertical direction and on one side of the pixel electrode. Each data line has a two-wire structure and the two lines of the data line are interconnected by several connectors. The storage circuit includes only one horizontal electrode extending to the pixel electrode storage electrode, and the thin film transistor array substrate further includes a storage capacitor conductor pattern connected to the pixel electrode and overlapping the storage electrode line. [Embodiment] The present invention will now refer to The attached drawings and preferred embodiments of the present invention are described in detail. However, the present invention can be in various forms and should not be limited to the embodiments set forth herein. In order to make the illustration clear, the regions and areas in the illustration are enlarged; the storage edge of the gate line of the pixel line of the pixel of the gate transistor and the storage level of the horizontal line overlap is preferably the superimposed pole and 〇. In the embodiment, the thickness of the layer is 6 550 824 degrees, and each element is represented by a reference number. When an element, such as a field or a substrate, is described as, over another element, it is' it means directly above another element or it means somewhere in comparison to it, when an element is The explanation is that, directly at the other time, 'it means that there is no situation between components. One embodiment of the invention of a thin film transistor (TFT) array substrate for an LCD is described in detail with reference to the attached drawings. First, a transflective LCD: a layout drawing of the structure of the substrate according to the present invention. The first embodiment of the invention is illustrated in FIGS. 1 and 2. FIG. 1 is a first embodiment of the present invention, which is a layout diagram of the structure of a film transistor (TFT) array substrate; and the cross section of the TFT array substrate shown in FIG. 1 is as shown in FIG. 1 As shown in FIG. 2, a gate circuit according to the present invention is preferably formed on a TFT array substrate with a conductive material or a metal material (such as aluminum molybdenum or molybdenum tungsten alloy, chromium, tantalum, copper, or copper alloy). . The gate line system includes a plurality of gates 12, 12, a plurality of gate pads 1251 and 1252, and a plurality of TFTs, and 1232. The gate lines extend horizontally and are arranged in each column of pixels. The gate lines are connected to the respective gate lines. 1 2 1 1 at the end, and transmits the gate signal from the external signal source to the connected 1 2 1 2 ', and the gate electrodes are respectively connected to the gate lines 1 2 1 1 and ground. In addition, a storage circuit is formed between a substrate 110, a layer, a region, and components to be understood. "A component above" is based on this description. T TFT Array's Example, Reference-LCD Thin Figure 2 is a cross-sectional view along the example. An embodiment, an aluminum alloy or an aluminum alloy, is used for an LCD line 1 2 1 1 and The gate electrode 1 2 3 1 is paired with one of the lines 1211 and 1212 and is alternately connected. It includes 7 550 824, a storage battery 131 and several pre-connected electrode electrodes. The storage electrode line 131 is a parallel gate line. 1211 and i2i2 are extended and arranged between the pixels. Each-storage electrode, line 131 receives a voltage, such as applied to an upper substrate, Mr.) and one of a common electrode (not shown). Common electrode voltage. Each female storage electrode 133 has a poorer than the associated storage electrode line 31, v < visibility, and is assigned to the respective pixels. Mutually overlap with the drain electrodes 1751 and 1 752 & gt The six pure storage lines 131 and 133 are electrically and physically connected to the pixel electrodes 1901 and 1902, which will be described later 'to form a storage capacitor that improves the charge storage capacity of the pixel. In addition, the storage electrode line 1 3 1 is in vertical painting six and α & It is placed between the pixels and adjacent to the pixel electrodes 901 and Β02, but Hachida — double, like the image 4, is used to prevent light leakage between pixel areas. Gate circuits 1211, 1212, 1231 1232, 1251 And 1252 and storage lines 1 3 1 and 1 3 3 are better and right 0-human μ live eight education is made of a single layer structure made of aluminum-containing materials. ... replaced by a multilayer structure. In this case, multiple layers are desired One of the layers of the structure is made of a low-resistance material ... One layer is made of a conductive material containing chromium, a thin, complex alloy, and a 4-mesh alloy. The conductive material and other materials such as indium-tin-oxygen (1Τ〇 ), Indium_zinc_oxide (IZO) and the substrate have good contact characteristics. On the substrate 110, the gate lines 1211, 1212, 123 1 1232 1 25 1 and 1252 and the storage lines m and 133 are covered with a gate insulating layer 14o, which is preferably formed of a silicon nitride (siNX) material. . A semiconductor layer 1 51 and 15 2 is formed on the interlayer insulating layer 14 with a semiconductor material such as amorphous silicon and is opposite to the idle electrodes 1231 and 1232 respectively. 8 550824 is formed on the semiconductor layer with a dream material or a large amount of material. . The ohmic contact layers 1632 and 1652 are preferably doped on n + hydrogenated amorphous silicon 151 and 152 of n-type impurities. The ohmic contact layers 1 632 and 1 652 have two parts I separated from each other based on each gate electrode 123 1 or 1232. 2 and 1 6520-The data line is preferably formed on the ohmic contact layers 1 632 and M ”and the gate insulating layer 140 with a conductor or a metal material (such as Ming, Ming alloy, molybdenum, molybdenum alloy, chromium and buttons).

資料線路係具有數個沿著垂直方向延伸並與閘線 1211與丨212交叉以界定出像素區域之資料線i7i。每一資料線1 7 1係位於相鄰像素行間並被分配於每兩像素行。The data line has a plurality of data lines i7i extending along the vertical direction and crossing the gate lines 1211 and 212 to define a pixel area. Each data line 17 1 is located between adjacent pixel rows and allocated to every two pixel rows.

資料線更包含彼此相對立之數個源極丄7 3 i與i 7 3 2及數個汲極1751與1 752。一對源極1731與1732係連結於一資料線17丨並延伸至以相連之線路m為基礎彼此相對立的各自閘電極1231與1 232。一對汲極1751與n52係以相連之閘電極1751與1 752為基礎，與各自之源極i73i 與1 732彼此分離並位於相對立之位置。汲極1751與1752 係與儲存線路1 3 1與1 33相互重疊以形成儲存電容。資料線路係也包含連接於資料線1 7丨之一末端，以接收自外部訊號源傳送之影像訊號之數個資料墊1 7 9。此外’資料線路包含數個於垂直方向延伸之輔助訊號線H2以平行於資料線m，並置於像素行間。資料線m 與輔助訊號線172係交替地置放於相鄰像素列間，並與像素電極1901與1 902之邊緣部分相互重疊，此於稍後形成， 9 550824 以截止像素行間之光洩漏。輔助訊號線1 72係作為資料線 1 7 1與閘線1 2 11與1 2 1 2之補償線。此即為，當資料線1 7 i 或閘線1 2 1 1與1 2 1 2被切斷時，輔助訊號線1 72成為資料線1 7 1或閘線1 2 11與1 2 1 2之切斷部分的通路。輔助訊號線1 72係實施與儲存線路1 3 1與1 3 3相同之功能以替代儲存線路1 3 1與1 3 3。資料線 171、1731、1732、1751、1752 與 179 及辅助訊號線172係具有包含鋁或鋁合金材料之一單層結構或一多層結構。在後者情形下，希望多層結構其中之一層以低電阻材料製成，而另一層以具有可與其他材料良好接觸特性之材料製成。鉻/鋁（或鋁合金）或鋁/鉬材料製成之層數即為實例。在鉻/鋁結構中，鉻係防止鋁或鋁合金脫離而進入硬層15卜152、1632與1652中，並確保資料線171、 1731、1732、1751、1752 與 179 及像素電極 1901 與 1902 間的接觸特性。一純態層1 8 0係形成於資料線路1 7丨、丨7 3 i1 7 3 2、 175 1、1 752與179及半導體層15ι與152部分之上，其中該半導體層部分係指未被資料線路1 7 1、1 7 3 1、1 7 3 2、 1751 I752與179覆蓋之部分。純態層係較佳以具有良好平坦化特性及低介電常數之氮化矽材料或丙烯酸感光有機材料加以製成。鈍態層i 8〇係具有數個接觸孔 1851、1852、189、1821與 1822，其中接觸孔 1851、1852 與189係分別暴露汲極1751與1752及資料墊179，而接觸孔1 8 2 1與1 8 2 2係暴露與閘絕緣層1 4 〇相連之閘墊丨2 5 i 10 550824 與 1252 〇在圖示中，鈍態層180係位於墊1251、1252與ι79 所提供之墊區域上《然而，因為有機材料造成墊區域之黏著力降低，故希望去除接近墊區域之鈍態層180之有機材料。同時，鈍態層180之表面之皺摺會引起像素電極1901 與1902之不平坦。像素線路1901、1902、921、922與97係形成於鈍態層180上。像素線路係包含數個像素電極1901與1902、數個輔助閘墊921與922及辅助資料墊97，其中該像素電極1901與1902係分別經接觸孔1851與1 852連接於沒極1751與1752，而該辅助閘塾921與922及輔助資料塾 97係分別經接觸孔1821、1822與189連接於閘塾1251 與1252及資料墊179。每一像素電極1 9 0 1與1 9 0 2係包含一可透性傳導膜 1911或1912與其上之一反射性傳導膜1921或1922。可透性傳導膜1911與1912係較佳以可透性材料諸如ΙΤ〇與ιζο材料製成，而反射性傳導膜1921與1922係較佳以鋁、鋁合金、銀或銀合金材料製成。反射性傳導膜丨92 i 與1922具有暴露可透性傳導膜1911與192i之傳送區域 T。傳送型LCD係僅包含可透性傳導膜1911與1912而不具有反射性傳導膜1921與1 922。有機絕緣材料相較於於μ & _ t 敉於虱化矽在黏著力、抗化學性、硬度、機械強度與應力等方面灼+ 々回$十分不足。因此對於玻璃覆晶封裝（COG)型式，其作4¾番+The data line further includes a plurality of source electrodes 7 3 i and i 7 3 2 and a plurality of drain electrodes 1751 and 1 752 opposite to each other. A pair of source electrodes 1731 and 1732 are connected to a data line 17 and extend to respective gate electrodes 1231 and 1 232 which are opposed to each other based on the connected line m. A pair of drain electrodes 1751 and n52 are based on the connected gate electrodes 1751 and 1 752, and are separated from their respective source electrodes i73i and 1 732 and located at opposite positions. The drain electrodes 1751 and 1752 overlap the storage lines 1 3 1 and 1 33 to form a storage capacitor. The data line also includes several data pads 179 connected to one end of the data line 17 to receive image signals transmitted from an external signal source. In addition, the data line includes a plurality of auxiliary signal lines H2 extending in a vertical direction so as to be parallel to the data line m and placed between pixel rows. The data line m and the auxiliary signal line 172 are alternately placed between adjacent pixel columns and overlap each other with the edge portions of the pixel electrodes 1901 and 1 902. This is formed later. 9 550824 stops light leakage between pixel rows. Auxiliary signal line 1 72 is the compensation line for data line 1 7 1 and gate line 1 2 11 and 1 2 1 2. That is, when the data line 1 7 i or the gate line 1 2 1 1 and 1 2 1 2 is cut off, the auxiliary signal line 1 72 becomes one of the data line 1 7 1 or the gate line 1 2 11 and 1 2 1 2 Cut off part of the access. The auxiliary signal line 1 72 implements the same functions as the storage lines 1 3 1 and 1 3 3 to replace the storage lines 1 3 1 and 1 3 3. The data lines 171, 1731, 1732, 1751, 1752 and 179 and the auxiliary signal line 172 have a single-layer structure or a multi-layer structure including aluminum or aluminum alloy materials. In the latter case, it is desirable that one of the layers of the multilayer structure be made of a low-resistance material and the other layer be made of a material having good contact characteristics with other materials. Examples are layers made of chromium / aluminum (or aluminum alloy) or aluminum / molybdenum materials. In the chrome / aluminum structure, the chromium system prevents the aluminum or aluminum alloy from detaching into the hard layers 152, 1632, and 1652, and ensures that the data lines 171, 1731, 1732, 1751, 1752, and 179 and the pixel electrodes 1901 and 1902 Contact characteristics. A pure state layer 1 80 is formed on the data lines 1 7 丨, 7 3 i1 7 3 2, 175 1, 1 752 and 179 and the semiconductor layers 15 and 152, where the semiconductor layer part means Data line 1 7 1, 1 7 3 1, 1 7 3 2, 1751 I752 and 179 covered. The pure state layer is preferably made of a silicon nitride material or an acrylic light-sensitive organic material having good planarization characteristics and a low dielectric constant. The passivation layer i 8〇 has several contact holes 1851, 1852, 189, 1821, and 1822. The contact holes 1851, 1852, and 189 respectively expose the drain electrodes 1751 and 1752 and the data pad 179, and the contact holes 1 8 2 1 The gate pad connected to the 1 8 2 2 series exposed gate insulation layer 1 4 〇 2 5 i 10 550824 and 1252 〇 In the picture, the passive layer 180 is located on the pad area provided by the pads 1251, 1252, and ι79 << However, since the adhesion of the pad region is reduced by the organic material, it is desirable to remove the organic material near the passivation layer 180 of the pad region. At the same time, wrinkles on the surface of the passive layer 180 may cause unevenness of the pixel electrodes 1901 and 1902. The pixel lines 1901, 1902, 921, 922, and 97 are formed on the passivation layer 180. The pixel circuit system includes a plurality of pixel electrodes 1901 and 1902, a plurality of auxiliary gate pads 921 and 922, and an auxiliary data pad 97. The pixel electrodes 1901 and 1902 are connected to the poles 1751 and 1752 via the contact holes 1851 and 1 852, respectively. The auxiliary gates 921 and 922 and the auxiliary data 塾 97 are connected to the gates 1251 and 1252 and the data pad 179 via the contact holes 1821, 1822, and 189, respectively. Each of the pixel electrodes 19 0 1 and 19 0 2 includes a permeable conductive film 1911 or 1912 and a reflective conductive film 1921 or 1922 thereon. The permeable conductive films 1911 and 1912 are preferably made of a permeable material such as ITO and ιζο, and the reflective conductive films 1921 and 1922 are preferably made of an aluminum, aluminum alloy, silver, or silver alloy material. The reflective conductive films 92 i and 1922 have transmission regions T exposing the permeable conductive films 1911 and 192i. The transmission type LCD system includes only the permeable conductive films 1911 and 1912 and does not have the reflective conductive films 1921 and 1 922. Compared with μ & _ t, the organic insulating material is very inadequate in terms of adhesion, chemical resistance, hardness, mechanical strength and stress. Therefore, for the glass-on-chip package (COG) type,

共係彡又置或貼附薄膜以承載驅動IC 11 550824 以用於捲帶式封裝（TCP)型式或薄膜覆晶（C〇F)型式，當直接設置驅動IC於TFT陣列基板上時，位於墊區域上之剩餘有機材料係造成墊區域不好黏著力之結果進而產生缺陷。黏著力所造成的缺陷常需要重工，其中該重工步騾係包含藉由化學式或機械式方法將驅動1C或薄膜自墊區域分離及非等向性傳導膜之去除。重工步驟係可損傷墊區域之表面並使有機絕緣層與輔助I 9 2 1、9 2 2與9 7剝落。因The common system also mounts or attaches a thin film to carry the driver IC 11 550824 for tape and reel package (TCP) type or thin film chip (COF) type. When the driver IC is directly set on the TFT array substrate, it is located at The remaining organic material on the pad area results in poor adhesion of the pad area and thus defects. Defects caused by adhesion often require rework. The rework step includes separating chemically or mechanically the driving 1C or thin film from the pad area and removing the anisotropic conductive film. The rework step can damage the surface of the pad area and peel off the organic insulating layer and the auxiliary I 9 2 1, 9 2 2 and 9 7. because

此’芫整去除墊區域上之有機絕緣材料係可改善驅動IC 或薄膜與墊之間的黏著力，並導致十分容易之重工步驟的結果。弟3圖係為根據本發明之實施例，用於一 LCD之TFT 陣列基板之等效電路圖。如第1圖和第3圖所示，根據本發明之實施例，用於一 LCD之TFT陣列基板之每一像素係具有以資料線171 為基礎彼此相對立之兩次像素。數個成對之閘線1 2 u與 1 2 1 2係被提供。以資料線1 7丨為基礎彼此相對立之分別的次像素之像素電極1901與1 902係經分別的TFT (TFT 1 與TFT2)連結於相關之資料線ι71。雙閘線i2U與1212 係經包含閘電極1231與1242予以連接之TFT(TFT1與 TFT2) ’分別電性連接於以資料線m為基礎彼此相對立之分別的次像素之像素電極1 9 〇 1與1 9 0 2。根據本發明之此實施例，用於一 LCD之TFT陣列基板，當次像素設置於mxn矩陣時，因為每一資料線171 傳送影像訊號至與其相鄰之兩相對立次像素，所以資料線 12 550824 171之數目縮減成為n/2，而閘線1211與1212 以兩倍。加總閘線1 2 1 1與1 2 1 2之數目與資料線目所得之數目係等於閘與資料驅動1C之輸出目。舉例而言，一廣視頻圖形陣列（WVGA)之閘之數目係分別為 480與 2400，因此全部訊號線 2 8 80。然而，在本發明的結構中，當資料線之數半，如1200,閘線1211與1212之數目乘以兩倍變則本實施例全部訊號線數目變為 2 1 6 0。因此在結構中，全部訊號線之數目相較於傳統技術 2 5 %。故驅動1C之數目，特別是昂貴的資料驅| 目被縮減，藉此將一 LCD之製造成本縮減至最，J 同時，資料線171、輔助訊號線172與儲存與133係與相鄰之像素電極 1901與1902之邊疊，以截止光洩漏產生於像素電極間。在上述半反半透型之實例中，儲存線路係設區域間，以截止光洩漏於其間產生，但儲存線路可用於截止一傳送型之光洩漏於像素區域間產生根據本發明之一第二實施例，用於一傳送变 TFT陣列基板之結構係參考第4圖與第5圖詳細第4圖係為根據本發明之第二實施例詳細描傳送型LCD之TFT陣列基板之佈局圖，而第5 據本發明之實施例用於一 LCD之TFT陣列基板路圖。如第4圖與第5圖所示，根據本發明之一第二之數目乘 171之數終端之數與資料線之數目為目減為一 t 為 960，本發明此係縮減約 » 1C之數、0 •線路1 3 1 緣部分重置於像素之變型係〇 ! LCD 之描述。述用於一圖係為根 .之等效電 •實施例， 13 55〇824 係在用於一 LCD之TFT陣列基板上提供包或具有低電阻之金屬材料（諸如鋁群組、鉬、鉻或妲之一金屬）之一閘線路與一資料線路閘線路係包含數個於水平方向延伸之閑連接於閘線22之TFT(TFT1與TFT2)之閘路係更具有數個連接於閘線2 2 —末端之閘自數個閘驅動1C傳送閘訊號至閘線22。資料線路係包含數個於垂直方向延伸資料線62係與閘線22絕緣並相交。資 TFT(TFT1與TFT2)之數個源極65與數個汲係連接於分別的資料線6 2，而沒極6 6係以基礎與源極6 5分開並相對立。資料線路係結於資料線62之一末端之資料墊，而該資料驅動IC接收影像訊號以傳送訊號至資料: 數個像素電極82係也被提供於各自像電極82係經TFT(TFT1與TFT2)之汲極66 料線路62 ' 65與66，並較佳以可透性傳辱與IZO或具有良好反射係數之材料製成。< 與閘線22重疊以形成一儲存電容。每一 TFT(TFT1或TFT2)係包含具通靖 40。半導體層40係與閘電極26、源極65與像素電極8 2係與閘線2 2重疊。如圖开提供一儲存線路2 8與2 9，係與像素電極用於補償儲存電容之儲存電容。儲存線路存含傳導性材料鎢化鉬合金、〇線22與數個電極2 6。閘線墊，且該閘墊々資料線62。料線路更包含極6 6。源極6 5 (閘電極26為更包含數個連料墊自數個資緣62 〇素P上。像素電性連接於資 r材料諸如ITO 象素電極82係 -之一半導體層汲極6 6重疊。 •中所示，其更 82重疊以形成〖包含數個於水 14 550824 平方向延伸之儲存之儲存電極2 9。根據本發明之基板之每一像素，礎相對立設置之兩接近像素電極82 路62為基礎相對j 各自TFT(TFT1與下部閘線22與26 j 與TFT2)電性連結各自次像素之像素根據本發明之陣列基板係降低驅資料驅動IC之數最小。此外，像素區兩像素電極而增加降低產生於像素電間之光洩漏係藉由極8 2之邊緣而加^ 根據本發明之法中，一傳導層之導性材料（諸如鋁g 光蝕刻方法圖案化電極線 2 8與數個連結於餘存電極線 28 第二實施例，用於— 係也具有以資料線路 LCO之TFT陣列 62、65與60為基次像素兩閘線22與26 之一上部邊緣與一下部邊緣。係分別設置於以資料線 &置之各自次像素之像素電極82係經 TFT2)連接於相關之資料線62。上部與卜別經包含閘電極予以連接之TFUTFT^ 於以資料線路62為基礎相對立設置之電極82。第一貫施例，用於一傳送型LCD之TFT 動1c之總數，明確言之係降低昂貴的目。如此’ LCD之製作成本係可降低至域之孔隙比率因一資料線62分配於每。位於像素電極8 2間之儲存電極2 9係極8 2間之耦合效應。此外，像素區域放置修改形狀之儲存電極29於像素電〈預防。第二實施例，一 LCD之製作TFT之方製作方法係包含沉積一具有低電阻之傳 <銘合金）於基板上，並藉由使用光阻之以形成一閘線路22與26及一儲存線路 15 550824 2 8與2 9。閘線、略22與26及儲存線路28與29係具有包含如鋁或鋁合合 “付料之一單層結構或包含如一層之多層結構之任一者。另外，基板10上 28 與 29。間絶緣層係較佳以氮化矽材料製成並沉積於閘全s & 、、、e緣層係覆蓋閘線路22輿；26及儲存線路而後姆接觸層係較佳導體層係較佳以非結晶係材料製成而-歐氮化非結晶砂材：：化物或具有大量摻雜n型不純物之n+ ,. A 4科紋成，其中半導體層與歐姆接觸層係循序沉積於基板10上並加以圖案化。具有低電阻如知七&入a、 ^ ^ ’— 、呂或鋁合金《一傳導性材料係沉積於基板10上並藉由使用光阻之光蝕刻方法圖案化以形成一資料線路62、65冑66。資料線路62、65與66係具有包含如鋁或鋁合金材料之一單層結構或包含如一層之多層結構之任-者。另夕卜，歐姆接觸層之暴露部分係使用資料線路 62、65與66或-光阻圖案加以㈣，用於形成資料線路 62、65與66以分離歐姆接觸層成為分別設置於源極a 與汲極66 了之部分並暴露半導體層4〇位於該被分離部分間之部分。半導體層40與資料、線路62、65與66係藉由使用具有部分不同厚度之光阻圖案之一光蝕刻步驟加以形成。具有低介電常數與良好平坦特性之氮化矽或一有機材料係接續沉積以形成覆蓋半導體層40之鈍態層。而後，純態層係使用光阻圖案加以光蝕刻以形成數個暴露沒極 16 550824 66之招露用以最加以圖 68之數根陣列基第 TFT陣 TFT陣如係較佳化鉬合閘 222，| 二閘電線路係線2 1 1 211與閘層結構係以低觸特性合金） ^觸孔，而閘絕緣層係同時地圖案化以形成數個暴連接外部電路之資料螯與閘墊之接觸孔。後’沉積一傳導材料如IT〇或IZ〇並使用—光軍案化以形成分別連結於汲極66、閘墊24與資料塾個像素電極8 2、數個補助閘墊與數個輔助資料塾。據本發明之第三實施例，用於一反射型LCD之TFT 板之結構係參考第6圖與第7圖詳細描述。 6圖係為根據本發明之第三實施例用於一 lcD之列基板之佈局圖’而第7圖係為沿著第6圖所示之列基板之VII-VII，剖面線之剖面圖。第ό圖與第7圖所示，一閘線路與數個儲存線2 8 以傳導材料或金屬材料（諸如鋁或鋁合金、鉬、鎢金、絡或鈕）製成並形成於絕緣基板1〇上。線路係包含數個於水平方向延伸之閘線22丨與导數個第一與第二TFT(TFT1與TFT2)之第一與第極2 6 1與2 6 2，其係為閘線2 1 1與2 1 2之部分。閘更包含閘墊（未示於圖中），該閘墊係連接於各自閘與2 1 2之末端並自外部訊號源傳送一訊號至閘線 212 〇線路221、222、261與262及儲存線28係具有單、雙層結構或三層結構。在多層結構情形中，一層電阻材料製成，而另一層以具有與其他材料良好接之材料製成。諸如鉻/鋁（或鋁合金）、或鋁（或鋁 /麵係可達成此目的之需求。 17 550824 閘絕緣層3 0係較佳以氮化矽材料製成路221、222、261與262及儲存線28上。第一與第二半導體層41與42係較佳以製成並分別形成於閘絕緣層3 〇彼此相對立閘電極262與261上。一歐姆接觸層552輿具有摻雜如磷（Ρ)之η型不純物之非結晶秒製成並形成於第一與第二半導體層41與42 層具有以第一與第二閘電極561為基礎彼此之部分552與562。資料線路 62、651、652、661、662 與導材料或金屬材料（諸如銘或銘合金、銷、絡或纽）加以製成並形成於歐姆接觸層552 緣層30上。資料線路係具有數個延伸於垂線62、數個為資料線62之部分之第一與第 652、數個以第一閘電極261為基礎與第一立 < 第一沒極661、數個以第二閘電極262 源極6S2相對立之第二汲極662、及數個連 6 2之資料連接器6 3。資料線路係包含連接^ 自一外部訊號源接收影像訊號以傳送影像訊料線62之數個資料墊（未示於圖中）。第一閘電極261、第一半導體層41、第第一汲極661係形成一第一 TFT(TFTl)， 262、第二半導體層42、第二源極652與第形成一第二 TFT(TFT2)。 ,並形成於閘線 '非結晶發材料 ‘之第一與第二 • 5 6 2係較佳以之半導體材料上。歐姆接觸 ‘分離並相對立 63係較佳以傳鎢化鉬合金、與652或閘絶直方向之資料一源極6 5 1與源極651相對為基礎與第— 接每對資料綠令資料線62 | 號至相連的資一源極651與而第二閘電梳二沒極662你 18 550824 如同I 6 5 2 〜6 6 1 一三層結，低電阻材: 特性之材一鈍形成於資層3 0上。, 與652之第一射係數如並形成於導因於鈍與822之第一與722連號。因一與第二像同時第一閘電其旋轉對 6 6 2 ° 本發洩漏係藉明線路22卜222、261與262,資料線路、662與63係具有一單層結構、一艾增結構或構。在多層結構的情形中，其係較佳炎丨王局—層以一料製成，而另一層以一具有與其他材料良好接觸料製成。態層70係較佳以一感光有機絕緣層材料製成並料線路61、651、652、661、662與63及閘絕緣鈍態層70係不平坦且具有數個分別暴露汲極651 接觸孔721與722。與第二像素電極821與822係較佳以具有良好反鋁、鋁合金、銀或銀合金等一金屬材料加以製成純態層70上。像素電極821與822之不平坦係態層70之不平坦表面，因而增加像素電極821 反射係數。與第二像素電極821與822係分別經接觸孔721 接於第一與第二汲極651與652，以接收影像訊對資料線62經資料連接器63彼此連接，故第一素電極821與822接收相同影像訊號。以將相鄰像素分為上下兩部分之一線為基礎，極261、第一源極651與第一汲極661係具有與稱之第二閘電極262、第二源極652與第二汲極明之第二貫施例中’像素電極8 2丨與8 2 2間之光由放置閘線221與222於接近像素電極821與822 19 550824 之上部與下部邊緣並有效使閘線221與222及資料線62 與以反射性材料製成之像素電極821與822之邊緣重疊而加以截止。此外，像素區域之結構之點對稱導致均一的反射係數。此將經由一製作程序加以詳細描述。根據本發衣ΊΡ 陣列基板之方法，係將參考第8Α圖至第12Β圖加以描述首先，如第8Α圖與第8Β圖所示，用於一閘線路且有U000至3,000Α厚度之一傳導材料或一金屬，係藉由濺鍍等方法沉積於一絕緣基板10上，並藉由使用一光罩之光蝕刻方法加以圖·案化以形成包含數個閘線221與222 及數個閘電極261與262及數個儲存線28之—閘線路。因此’如第9Α圖與第9Β圖所示，一氮化矽層3〇、 -非結晶矽層與-摻雜η型不純物之摻雜非結晶矽層，其分別具“500至5,000入、⑽至⑽入與⑼…。“ 之厚度’係循序以化學氣相沉積法等方法沉積。而後，該三層藉由使用-光罩之光蚀刻方法加以圖案化以形成一閘絕緣層30、數個半導體層41與42與—歐姆接觸層51與 5 2 〇如第1〇Α圖與帛刚圖所示，具有用於一資料線路具有Μ00至3’ΟΟΟΑ厚度之—傳導材料或_金屬係藉由濺.鍍等方法沉積’並藉由使用一光罩之光蝕刻方法加以圖案化以形成包含數個資料線62、數個源極651與652、數個沒極661與662及數個資料連接器63之一資料線路。而後，不被源』651肖652及沒極661肖…覆蓋之歐姆 20 550824 接觸層51與52之部分係被去除，以將歐姆据 52分開為以間電極261與262為基礎之兩部分 561與562並暴露半導體層41與42。之後，如第11圖至第12R国私一甲i2 B圖所示，塗佈米厚度以感光有機絕緣材料说士 ^ ^ 々τ表成义一鈍態層使用一光罩1 0 0之光蚀刻方法士This' curing removal of the organic insulating material on the pad area can improve the adhesion between the driver IC or film and the pad, and lead to the result of a very easy rework step. Figure 3 is an equivalent circuit diagram of a TFT array substrate for an LCD according to an embodiment of the present invention. As shown in FIGS. 1 and 3, according to an embodiment of the present invention, each pixel of a TFT array substrate for an LCD has two pixels that are opposed to each other based on the data line 171. Several pairs of gate lines 1 2 u and 1 2 1 2 are provided. The pixel electrodes 1901 and 1 902 of the sub-pixels which are opposed to each other on the basis of the data line 17 are connected to the relevant data line 71 via the respective TFTs (TFT 1 and TFT 2). The double gate lines i2U and 1212 are TFTs (TFT1 and TFT2) connected via gate electrodes 1231 and 1242. The pixel electrodes are electrically connected to the sub-pixels that are opposed to each other based on the data line m. With 1 9 0 2. According to this embodiment of the present invention, when a TFT array substrate for an LCD is set in an mxn matrix, each data line 171 transmits an image signal to two opposite sub-pixels adjacent thereto, so the data line 12 The number of 550824 171 is reduced to n / 2, and the gate lines 1211 and 1212 are doubled. The total number of gate lines 1 2 1 1 and 1 2 1 2 and the number of data lines are equal to the output of the gate and data drive 1C. For example, the number of gates of a wide video graphics array (WVGA) is 480 and 2400 respectively, so all signal lines are 2 8 80. However, in the structure of the present invention, when the number of data lines is half, such as 1200, the number of gate lines 1211 and 1212 is multiplied by twice, so the number of all signal lines in this embodiment becomes 2 1 6 0. Therefore, in the structure, the number of all signal lines is 25% compared with the conventional technology. Therefore, the number of driving 1C, especially the expensive data drive | is reduced, thereby reducing the manufacturing cost of an LCD to the maximum. At the same time, the data line 171, auxiliary signal line 172 and storage and 133 are adjacent pixels. The edges of the electrodes 1901 and 1902 are stacked to cut off light leakage generated between the pixel electrodes. In the example of the transflective type described above, the storage circuit is provided between the regions to cut off light leakage between them, but the storage circuit can be used to cut off a transmission type of light leakage between pixel regions to generate a second according to the present invention. In the embodiment, the structure for a transmission variable TFT array substrate is referred to FIG. 4 and FIG. 5. FIG. 4 is a detailed layout diagram of a TFT array substrate of a transmission LCD according to a second embodiment of the present invention. Fifth Embodiment A roadmap of a TFT array substrate for an LCD according to an embodiment of the present invention. As shown in Fig. 4 and Fig. 5, according to one of the present invention, the number of the second multiplied by 171, the number of terminals and the number of data lines are reduced to a t of 960, which is reduced by about »1C in the present invention. Number, 0 • Line 1 3 1 The marginal part resets to the pixel's variation system! LCD description. The equivalent electrical embodiment for a picture is a root. 13 55〇824 is a package or metal material with low resistance (such as aluminum group, molybdenum, chromium) provided on a TFT array substrate for an LCD. Or a metal line) a gate line and a data line. The gate line includes a plurality of gate lines extending in the horizontal direction and connected to the TFTs (TFT1 and TFT2) of the gate line 22. The gate system also has several gate lines connected to the gate line. 2 2 —The gate at the end transmits the gate signal to gate line 22 from several gate drives 1C. The data line includes a plurality of data lines 62 that extend in the vertical direction and are insulated from the gate line 22 and intersect. The source 65 and the source TFTs of the TFTs (TFT1 and TFT2) are connected to the respective data lines 62, and the source 65 is separated from the source 65 and opposed to each other on the basis. The data line is tied to a data pad at one end of the data line 62, and the data driver IC receives the image signal to transmit the signal to the data: Several pixel electrodes 82 are also provided to their respective image electrodes 82 through TFT (TFT1 and TFT2 ) Of the drain 66 material lines 62 '65 and 66, and is preferably made of permeable shame and IZO or a material with a good reflection coefficient. < Overlap with the gate line 22 to form a storage capacitor. Each TFT (TFT1 or TFT2) is composed of Tongjing 40. The semiconductor layer 40 is overlapped with the gate electrode 26, and the source 65 and the pixel electrode 82 are overlapped with the gate line 22. As shown in the figure, a storage circuit 2 8 and 29 are provided, which are connected to the pixel electrode to compensate the storage capacitor of the storage capacitor. The storage circuit contains a conductive material, a molybdenum tungsten alloy, a wire 22, and several electrodes 26. Brake wire pad, and the brake pad 々 data line 62. The material line also contains pole 6 6. The source electrode 6 5 (the gate electrode 26 is further composed of a plurality of continuous pads from a plurality of resources 62。 pixel P. The pixel is electrically connected to a material such as ITO pixel electrode 82 series-a semiconductor layer drain electrode 6 6 overlaps. • As shown in the figure, it overlaps 82 to form a storage electrode containing a plurality of storage electrodes extending in the horizontal direction of water 14 550 824 2 9. Each pixel of the substrate according to the present invention is arranged close to two opposite The pixel electrodes 82 and 62 are based on the respective TFTs (TFT1 and the lower gate line 22 and 26 j and TFT2) which electrically connect the pixels of the respective sub-pixels. The array substrate according to the present invention reduces the number of data driving ICs to the smallest. In addition, The increase and decrease of the two pixel electrodes in the pixel area. The light leakage generated between the pixels is increased by the edge of the electrode ^ According to the method of the present invention, a conductive material of a conductive layer (such as an aluminum photolithography method is patterned). The electrode line 28 and a plurality of remaining electrode lines 28 are connected to the second embodiment. The second embodiment is also provided with a TFT array 62, 65, and 60 based on a data line LCO. Edge and lower edge. The pixel electrodes 82 of the respective sub-pixels provided with the data line & are connected to the relevant data line 62 via the TFT 2). The TFUTFT connected to the upper part and the via via including the gate electrode is based on the data line 62. Opposing electrodes 82. The first embodiment, the total number of TFTs 1c used in a transmission LCD, is specifically to reduce the expensive goal. Thus, the production cost of the LCD can be reduced to the porosity ratio of the domain due to a The data lines 62 are allocated to each. The coupling effect between the storage electrodes 29 between the pixel electrodes 82 and the coupling electrodes 82 between the electrodes 82. In addition, the storage electrodes 29 with modified shapes are placed in the pixel area for the pixel electricity <prevention. The second embodiment, a The manufacturing method of TFT for LCD includes depositing a low resistance (transmitting alloy) on a substrate, and using photoresist to form a gate circuit 22 and 26 and a storage circuit 15 550824 2 8 and 2 9. The gate lines, slightly 22 and 26 and the storage lines 28 and 29 have any one of a single-layer structure including aluminum or aluminum alloy or a multilayer structure including one layer. In addition, 28 and 29 on the substrate 10 The interlayer insulation layer is preferably made of silicon nitride material and deposited on the gate s &,, and e edge layer to cover the gate line 22; 26 and the storage line, and then the contact layer is a better conductor layer. It is preferably made of non-crystalline materials and -Nitride non-crystalline sand materials :: compounds or n + with a large amount of doped n-type impurities. A 4 branch pattern is formed, in which the semiconductor layer and the ohmic contact layer are sequentially deposited on the substrate 10 and patterned. It has a low resistance such as known as "a", "^", "Lu" or aluminum alloy "a conductive material is deposited on the substrate 10 and patterned by a photo-etching method using photoresist To form a data line 62, 65、66. The data lines 62, 65, and 66 have any one of a single-layer structure including aluminum or an aluminum alloy material or a multilayer structure including one layer. In addition, ohmic contact The exposed part of the layer is using data lines 62, 65 and 66 or-photoresist In addition, it is used to form the data lines 62, 65, and 66 to separate the ohmic contact layers into portions provided at the source a and the drain 66, respectively, and to expose the semiconductor layer 40 between the separated portions. Semiconductor layer 40 The materials, lines 62, 65, and 66 are formed by using a photo-etching step using a photoresist pattern having a partly different thickness. Silicon nitride or an organic material having a low dielectric constant and good flatness characteristics is successively deposited to A passivation layer covering the semiconductor layer 40 is formed. Then, the pure state layer is photo-etched using a photoresist pattern to form several exposed electrodes 16 550 824 66 to apply the array-based TFT array of FIG. 68. The TFT array is optimized for molybdenum closing 222, | the second gate electrical line system line 2 1 1 211 and the gate layer structure are low-touch alloy) ^ contact hole, and the gate insulation layer is patterned simultaneously to form a number A contact hole for connecting the data cheat of the external circuit with the gate pad. After the 'deposition of a conductive material such as IT0 or IZ〇 and use-light military case to form a connection to the drain 66, the gate pad 24 and the data respectively Pixel electricity Pole 8 2. Several auxiliary brake pads and several auxiliary materials 辅助. According to the third embodiment of the present invention, the structure of a TFT panel for a reflective LCD is described in detail with reference to FIGS. 6 and 7. FIG. 7 is a layout diagram of a substrate for a column of LCDs according to the third embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line VII-VII of the substrate shown in FIG. 6. As shown in Figure and Figure 7, a gate line and several storage lines 2 8 are made of a conductive material or a metal material (such as aluminum or aluminum alloy, molybdenum, tungsten gold, wire or button) and formed on an insulating substrate 10 The line system includes a plurality of gate lines 22 in the horizontal direction and first and second poles 2 6 1 and 2 6 2 of the first and second TFTs (TFT1 and TFT2), which are gate lines 2 1 1 and 2 1 2. The gates also include gate pads (not shown), which are connected to the ends of the respective gates and 2 1 2 and send a signal from an external signal source to the gate line 212. Lines 221, 222, 261, and 262 and storage The wire 28 has a single-, double-, or triple-layer structure. In the case of a multilayer structure, one layer is made of a resistive material and the other layer is made of a material having a good connection with other materials. Such as chromium / aluminum (or aluminum alloy), or aluminum (or aluminum / surface) can achieve this purpose. 17 550824 Gate insulation layer 30 is preferably made of silicon nitride materials Road 221, 222, 261 and 262 And storage line 28. The first and second semiconductor layers 41 and 42 are preferably made and formed on the gate insulating layer 30 respectively on the gate electrodes 262 and 261 opposite each other. An ohmic contact layer 552 has a doping For example, the amorphous second of the n-type impurity of phosphorus (P) is made and formed on the first and second semiconductor layers 41 and 42. The layers have portions 552 and 562 based on each other based on the first and second gate electrodes 561. Data lines 62, 651, 652, 661, 662 and conductive materials or metallic materials (such as inscriptions or inscriptions alloys, pins, wires or buttons) are made and formed on the ohmic contact layer 552 edge layer 30. The data line has several extensions At the vertical line 62, the first and 652 of the data line 62, the number of the first gate electrode 261 based on the first < the first pole 661, the number of the second gate electrode 262 source The pole 6S2 is opposite to the second drain pole 662, and several data connectors 6 3 are connected to 6 2. The data line is a package Including connection ^ Receives image signals from an external signal source to transmit several data pads (not shown) of the image signal line 62. The first gate electrode 261, the first semiconductor layer 41, and the first drain electrode 661 are A first TFT (TFT1), 262, a second semiconductor layer 42, a second source electrode 652, and a second TFT (TFT2) are formed, and are formed on the first and the first of the gate line 'amorphous material'. 2. • 5 6 2 is preferably on semiconductor materials. Ohmic contact is separated and opposed. 63 is preferably transmitted on molybdenum tungsten alloy, and 652 or gate direction. One source 6 5 1 and source 651 is relative to the first—connect each pair of data. Green order data line 62 | No. to the connected source one 651 and the second gate comb two dipoles 662 you 18 550824 like I 6 5 2 ～ 6 6 1 1 Three-layer junction, low-resistance material: a material with a characteristic of bluntness is formed on the asset layer 30., and the first emissivity of 652 and 652 is formed by the first and 722 consecutive numbers due to bluntness and 822. The second image is the same as the first brake, and its rotation is 6 6 2 °. The leakage of the current is based on Ming lines 22, 222, 261, and 262, data lines, 662 The 63 series has a single-layer structure, an Ai Zeng structure or structure. In the case of a multi-layer structure, it is better Yanwang Bureau-the layer is made of one material, and the other layer has a good contact with other materials The state layer 70 is preferably made of a photosensitive organic insulating layer material and the wiring lines 61, 651, 652, 661, 662, and 63 and the gate insulation passivation layer 70 are uneven and have several exposed drains. The pole 651 contacts the holes 721 and 722. The second pixel electrodes 821 and 822 are preferably formed on the pure state layer 70 by using a metal material having good anti-aluminum, aluminum alloy, silver or silver alloy. The uneven surfaces of the pixel electrode 821 and 822's uneven system layer 70 increase the reflection coefficient of the pixel electrode 821. The second pixel electrodes 821 and 822 are respectively connected to the first and second drain electrodes 651 and 652 through the contact holes 721 to receive the image signal and the data lines 62 are connected to each other through the data connector 63. Therefore, the first element electrode 821 and 822 receives the same video signal. Based on a line that divides adjacent pixels into two parts, the electrode 261, the first source electrode 651, and the first drain electrode 661 have a second gate electrode 262, a second source electrode 652, and a second drain electrode. In the second embodiment of the Ming Dynasty, the light between the pixel electrodes 8 2 丨 and 8 2 2 is placed by the gate lines 221 and 222 near the upper and lower edges of the pixel electrodes 821 and 822 19 550824 and the gate lines 221 and 222 and The data lines 62 overlap with the edges of the pixel electrodes 821 and 822 made of a reflective material and are cut off. In addition, the point symmetry of the structure of the pixel region results in a uniform reflection coefficient. This will be described in detail through a production process. According to the method of the hairpin HP array substrate, it will be described with reference to FIGS. 8A to 12B. First, as shown in FIGS. 8A and 8B, it is used for a gate line and has a thickness of U000 to 3,000Α. A material or a metal is deposited on an insulating substrate 10 by sputtering or the like, and is patterned and patterned by a photo-etching method using a photomask to form a plurality of gate lines 221 and 222 and a plurality of gates. The electrodes 261 and 262 and a plurality of storage lines 28 are gate circuits. Therefore, as shown in FIG. 9A and FIG. 9B, a silicon nitride layer 30, an amorphous silicon layer, and a doped amorphous silicon layer doped with an n-type impurity, respectively, have "500 to 5,000, ⑽ to ⑽ and ⑼. "The thickness" is sequentially deposited by chemical vapor deposition and other methods. Then, the three layers are patterned by a photo-etching method using a photomask to form a gate insulating layer 30, a plurality of semiconductor layers 41 and 42 and an ohmic contact layer 51 and 5 2 0 as shown in FIG. 10A and帛 As shown in the figure, a conductive material or metal with a thickness of M00 to 3'〇ΟΟΑ for a data line is deposited by sputtering, plating, etc. and patterned by a photo-etching method using a photomask. In order to form a data line including a plurality of data lines 62, a plurality of source electrodes 651 and 652, a plurality of poles 661 and 662, and a plurality of data connectors 63. Then, the source is not covered by 651 Xiao 652 and Wu Ji 661 Shade ... The ohmic 20 550824 covering parts of the contact layers 51 and 52 are removed to separate the ohmic data 52 into two parts 561 based on the intermediate electrodes 261 and 262. And 562 and the semiconductor layers 41 and 42 are exposed. After that, as shown in Figures 11 to 12R, i2B, the thickness of the coated rice is coated with a photosensitive organic insulating material. ^ ^ Ττ is defined as a passivation layer using a photomask 1 0 0 light Etching method

4万/套加以圖案化該I 以形成數個各自暴露沒極661與662及純態肩之不平坦之接觸孔。此步驟所使用之光罩100係具有數個較佳不透明的部分1 1 0與數個可穿透的部分i u。與7 22係對應於可穿透部分U1。鈍態層7〇平坦係藉由交替地設置不透明部分與可穿而獲致。^ 一光經光罩1 0 0施加時，由於資料線 652、661、662與63反射入射光，於資料線蹲 652、661、662與63上之鈍態層70部分係過此’在進行之後，於資料線路62、651、652 與63上之鈍態層7〇部分之厚度會縮減因而引導致不均一性。因此，欲求可穿透部分111相線路62、651、652、661、662與63上之鈍您之厚度係足夠小以降低該部分相較於其它部量。由於資料線路 62、651、652、661、662 j 區域與右半區域分別具有一第一像素電極821 素電極8 2 2，當以丨g 〇度旋轉時，係具有相同 I觸層5 1與 551、552、具有數個微 70，並藉由 4態層 70，卜70表面上以鉻製成之接觸孔 721 之表面之不透部分1 1 1 路 62、65 1、 r 62 、 651 、度曝光。因 ' 661 > 662 起不平坦並對立於資料 ^層70部分分之光反射 # 63其左半與一第二像形狀，故用 21 550824 於左半區域之光罩係可藉由180度旋轉該光罩以用於右，區域。而後，如第6圖與〜w致如鋁、銘合金、銀或銀合金之一金屬材料係藉由濺舻纖t万法沉積約400至500A厚度於鈍態層70上，並藉由使用—^ 罩之光蝕刻方法加以圖案化，以形成數個第一盥贫 ^罘二像素電極 821 與 822 。如上所述，鈍態層 7 0之均勻地不平i曰本I " τ 一表面係増加像素電極821與822於其上之反射係數。本發明第三實施例中，鈍態層之均勻卞坦係以用於左半區域之光罩經180度旋轉也可用於右半區政场1又一方法而獲致。其係可藉由排列一光罩於依附資料绝一竹、、泉路〈形狀的又替方法而獲致。本發明之第四實施例之插沭、你芩考第1 3 圖至弟19B圖顯tf其特徵。如第1 3圖與第14圖所示，一閘線路與數個儲存線μ 係較佳以傳導材料或如鋁或鋁合金、鉬、轉化銷合金、絡或备等金屬材料製成並形成於絕緣基板1 〇上。閘線路具有數個第一與第二閘線221與222及數個第一與第二閘電極261與262。閘線路之形狀係實質相同於第一實施例之該些形狀。閘絕緣層30係較佳以氮化矽材料製成並形成於閘線路221、222、261與262及儲存線28上，第一與第二半導體層41與42係形成於分別相對於第一與第二閘電極262與261之閘絕緣層30上。歐姆接觸 22 550824 層552與562係形成於第一與第二半導體層4i多歐姆接觸層具有以第一與第二閘電極262為基礎立且分開的部分552與562。 —資料線路 62、651、652、661、662 與 63 傳導材料或如鋁或鋁合金、鉬、鎢化鉬合金、鉻屬材料製成並形成於歐姆接觸層552與562或閘、彳上。資料線路係包含數個雙資料線62、數個連線6 2及連接於以第一閘電極2 6 1為基礎相對立極651之第一汲極661之第一與第二源極652與數個連接於每對資料線62之資料連接器63。資包含第一與第二輔助元件671與672。第一輔助之形狀係藉由倒置第二源極652與第二汲極662 素電極821之區域中而獲致。第二輔助線路672 藉由倒置第一源極6 5 1與第一汲極6 6 1於第二 822之區域中而獲致。第一閘電極261、第一半導體層41、第一源第一汲極 661係形成一第一 TFT(TFTl)，而第 262、第二半導體層42、第二源極652及第二沒形成一第二 TFT(TFT2)。一鈍態層7 0係較佳以感光有機絕緣層製成資料線路 62、651、652、661、662、63、671 與絕緣層30上。鈍態層70具不平坦且具有數個分極661與662之接觸孔721與722。第一與第二像素電極821與822係較佳以具豕42上。彼此相對係較佳以或鈕等金避緣層3 0 接於資料於第一源 652，及料線路更線路6 7 1 於第一像之形狀係像素電極極6 5 1及二閘電極極6 6 2係並形成於 672及閘別暴露汲有良好反 23 550824 射係數如鋁、鋁合金、銀或銀合金之一金屬成於鈍態層7〇上。像素電極821與822之鈍態層70之不平坦表面，其係增加像素電之反射係數。第一與第二像素電極8 2 1與8 2 2係分別與722連接於第一與第二汲極661與Μ], 號。同時，以將相鄰像素分為左右兩部分之第一閘電極261、第一源極651、第一汲極助兀件671，係具有與其旋轉對稱之第二閘一源極6W、第二汲極662與第二辅助元件因此，本發明之第四實施例提供相同於優點。根據本發明之第四實施例，用於製作一 =列基板之方法，係參考第15A至第i9B園第14圖加以描述。首先，如第15A圖與第15B所示，用一傳導材料或一金屬係藉由濺鍍等方法沈積 10上，並藉由使用一光罩之光蝕刻方法加形以形成包含數個閘線221與222及數個閘$ 及數個儲存線28之一閉線路。此後’如第16A圖與第16B圖所示，一：一非結晶硬層與摻雜η型不純物之一摻雜非由CVD等方法循序沉積。而後，該三層係材料製成並形不平坦導因於極821與822 經接觸孔721 以接收影像訊一線為基礎之 661與第一辅電極2 6 2、第 672 〇第三實施例之 LCD 之 TFT i與第13圖與於一閘線路之於一絕緣基板以圖案化，以 S 極 261 與 262 I化碎層3 0、結晶♦層係藉精由使用一光 24 550824 罩之光姓刻方法加以圖案化，以形成個半導肢·層41與42及一歐姆接觸層一閘絕緣層 51 與 52 。 3 0、數如第17A圖與第17B圖所示，且 /、有用於一資料線路之一傳導材料或一金屬，係藉由賤 '观t万法沉積，並藉由使用一光罩之光蝕刻方法加以圖案 & 釆化以形成包含數個資料線62、數個源極651與652、數個 u、 /及極66丨與062及數個資料連接器63之-資料線路。而後，不被源極651與… 及沒極661與662覆蓋之歐姆接觸層51與μ之部分係被去除’以將歐姆接觸層5 1與52分開為刀阅為以閘電極261與262 為基礎之兩部分551、552、561與567 * η… …562並暴露半導體層41 與42。The I was patterned at 40,000 / set to form a number of uneven contact holes each exposing the terminals 661 and 662 and the pure shoulder. The photomask 100 used in this step has a number of better opaque portions 110 and a number of penetrable portions i u. Corresponds to the 7 through 22 series U1. The passivation layer 70 flatness is obtained by alternately arranging opaque portions and wearables. ^ When a light is applied through the mask 100, as the data lines 652, 661, 662, and 63 reflect the incident light, the blunt state layer 70 on the data line 652, 661, 662, and 63 passes through this. Thereafter, the thickness of the portion 70 of the passivation layer on the data lines 62, 651, 652, and 63 will be reduced, thereby causing non-uniformity. Therefore, the thickness of the blunt portions on the 111-phase lines 62, 651, 652, 661, 662, and 63 of the penetrable portion is small enough to reduce this portion compared to other portions. Since the data lines 62, 651, 652, 661, and 662 have a first pixel electrode 821 and a right half region 8 and 2 on the right half area, respectively, when rotated at 丨 g 〇, they have the same I contact layer 5 1 and 551, 552, has several micro 70, and through the 4-state layer 70, the surface of the contact hole 721 made of chromium on the surface of the opaque part 721 1 1 road 62, 65 1, r 62, 651, Degree exposure. Since '661 > 662 is uneven and opposes the light reflection of the 70th part of the data layer # 63 with its left half and a second image shape, using 21 550824 in the left half of the mask system can use 180 degrees Rotate the mask for the right, area. Then, as shown in FIG. 6 and ~ w, a metal material such as aluminum, aluminum alloy, silver, or silver alloy is deposited on the passivation layer 70 by a thickness of 400 to 500 A by sputtering, and is used by — ^ The photolithography method of the mask is patterned to form a plurality of first pixel electrodes 821 and 822. As described above, the uniform unevenness of the passive layer 70 is referred to as the reflection coefficient of the surface on which the pixel electrodes 821 and 822 are added. In the third embodiment of the present invention, the uniformity of the passivation layer is obtained by rotating the photomask in the left half region through 180 degrees, which can also be used in the right half region. This can be achieved by arranging a mask on the attached material, bamboo, spring, and other alternative methods. In the fourth embodiment of the present invention, you can examine the features of tf in Figures 13 to 19B. As shown in Figures 13 and 14, the gate circuit and several storage lines μ are preferably made of conductive materials or metallic materials such as aluminum or aluminum alloys, molybdenum, conversion pin alloys, and metal alloys. On the insulating substrate 10. The gate line has a plurality of first and second gate lines 221 and 222 and a plurality of first and second gate electrodes 261 and 262. The shapes of the gate lines are substantially the same as those of the first embodiment. The gate insulating layer 30 is preferably made of a silicon nitride material and formed on the gate lines 221, 222, 261, and 262 and the storage line 28. The first and second semiconductor layers 41 and 42 are formed opposite to the first On the gate insulating layer 30 with the second gate electrodes 262 and 261. The ohmic contact 22 550824 The layers 552 and 562 are formed on the first and second semiconductor layers 4i. The ohmic contact layer has portions 552 and 562 which are standing and separated on the basis of the first and second gate electrodes 262. —Data lines 62, 651, 652, 661, 662, and 63 are made of conductive materials or materials such as aluminum or aluminum alloys, molybdenum, molybdenum tungsten, and chrome, and are formed on the ohmic contact layers 552 and 562, or the gates and ridges. The data line includes a plurality of dual data lines 62, a plurality of connections 6 2 and first and second source electrodes 652 and 652 connected to the first drain electrode 661 opposite to the vertical pole 651 based on the first gate electrode 2 6 1. A plurality of data connectors 63 are connected to each pair of data lines 62. It includes first and second auxiliary components 671 and 672. The first auxiliary shape is obtained by inverting the second source electrode 652 and the second drain electrode 662 in the region of the element electrode 821. The second auxiliary circuit 672 is obtained by inverting the first source electrode 6 5 1 and the first drain electrode 6 6 1 in a region of the second 822. The first gate electrode 261, the first semiconductor layer 41, and the first source and first drain electrode 661 form a first TFT (TFT1), and the 262nd, second semiconductor layer 42, second source electrode 652, and second electrode are not formed. A second TFT (TFT2). A passive state layer 70 is preferably made of a photosensitive organic insulating layer on the data lines 62, 651, 652, 661, 662, 63, 671 and the insulating layer 30. The passivation layer 70 has contact holes 721 and 722 which are uneven and have a plurality of poles 661 and 662. The first and second pixel electrodes 821 and 822 are preferably formed on the electrode 42. Relative to each other, it is better to use a gold avoiding layer such as or button 3 0 to connect to the data at the first source 652, and to change the line 6 7 1 to the shape of the first image. The pixel electrode 6 5 1 and the second gate electrode 6 6 2 series and formed in 672 and gate exposure have good reflectance 23 550 824 Emission coefficient such as aluminum, aluminum alloy, silver or one of the silver alloys is formed on the passive layer 70. The uneven surfaces of the passivation layer 70 of the pixel electrodes 821 and 822 increase the reflection coefficient of the pixel electricity. The first and second pixel electrodes 8 2 1 and 8 2 2 are connected to the first and second drain electrodes 661 and M, respectively, and 722. At the same time, the first gate electrode 261, the first source electrode 651, and the first drain assisting device 671 which divide adjacent pixels into left and right parts have a second gate-source 6W, second The drain electrode 662 and the second auxiliary element thus provide the same advantages as the fourth embodiment of the present invention. According to a fourth embodiment of the present invention, a method for fabricating a substrate is described with reference to FIGS. 15A to 14B. First, as shown in FIG. 15A and FIG. 15B, a conductive material or a metal system is used to deposit 10 on the substrate 10 by sputtering, and the shape is formed by a photo-etching method using a photomask to form a plurality of gate lines. 221 and 222 and one of several gates and several storage lines 28 are closed. Thereafter, as shown in FIG. 16A and FIG. 16B, one: A non-crystalline hard layer and one of the doped n-type impurities are doped non-sequentially by a method such as CVD. Then, the three-layer material made of the uneven shape is caused by the poles 821 and 822 through the contact hole 721 to receive the first line of video signals 661 and the first auxiliary electrode 2 62, the 672th third embodiment LCD TFT i and Figure 13 are patterned on an insulating substrate on a gate circuit, with S poles 261 and 262 I fragmented layer 30, crystallized. The layer is made by using a light 24 550824. The engraving method is patterned to form semi-conductive limbs 41 and 42 and an ohmic contact layer and a gate insulation layer 51 and 52. 30. The numbers are shown in Figures 17A and 17B, and / or a conductive material or a metal used for a data line is deposited by a low-level method and by using a photomask. The photoetching method is patterned and patterned to form a data line including a plurality of data lines 62, a plurality of source electrodes 651 and 652, a plurality of u, and a plurality of poles 66, 062, and a plurality of data connectors 63. Then, the portions of the ohmic contact layers 51 and μ that are not covered by the source electrodes 651 and ... and the electrodes 661 and 662 are removed 'to separate the ohmic contact layers 5 1 and 52 into the blades and the gate electrodes 261 and 262 as Two parts of the foundation 551, 552, 561, and 567 * η ... 562 and expose the semiconductor layers 41 and 42.

^，1 〃、，里帀以感光琴絕緣材料製成之一鈍態層70,並藉由使用一光罩1〇〇光蝕刻方法加以圖案化該鈍態層70 ,以f山& 以形成數個各自露汲極661與662及鈍態層70表面上> τ τ 叫丄 < 不平坦之接觸此步驟所使用之光罩1 〇〇係具有教伽# A 、^1致個較佳以鉻製4 不透明的部分110與數個可穿透的部分。接觸孔721 與7 22係對應於可穿透部分u i。鈍態層7〇之表面之不平坦係藉由交替地設置不透明部分11 〇與可穿透部分i丄丄而獲致。當一光經光罩100施加時，由於資料線路62、651、 652、661、662、63、671與672反射入射光，於資料線^, 1 〃, 帀帀 is made of a passive layer 70 made of a photosensitive insulating material, and the passive layer 70 is patterned by using a photomask 100 photoetching method. Form several dew-drain electrodes 661 and 662 and the surface of the passivation layer 70 > τ τ is called > uneven contact The photomask 100 used in this step has a teaching ##, ^ 1 to make a comparison The opaque portion 110 made of chrome and several penetrable portions are preferred. The contact holes 721 and 7 22 correspond to the penetrable portions u i. The unevenness of the surface of the passive layer 70 is obtained by alternately arranging the opaque portion 11 0 and the penetrable portion i 丄丄. When a light is applied through the reticle 100, since the data lines 62, 651, 652, 661, 662, 63, 671, and 672 reflect incident light, the data lines

路 62、651、652、661、662、63' 671 與 672 上之純綠層 70部分係過度曝光。因此，在進行之後，於資料線路62、 651、652、661、662、63、671 與 67 2 上之鈍態層 70 部 25 二=厚度會縮減因而引起不平坦並導致不均一性❶因此， ”可穿透#分111相對立於資料線路62、651、652、661、 6 6 2 、、63、671與672上之鈍態層70部分之厚度係足夠小乂降低孩些邵分相較於其它部分之光反射量。由於資料線路 62、651、652、661、66 2、63、671 與其左半區域與右半區域分別具有一第一像素電極821 ’、第一像素電極822，當反轉時，係具有相同形狀，故用於左半區域之光罩係可藉由180度旋轉該光罩以用於右半區域。而後’如第13圖與第14圖所示，具有高反射係數如 ' 口金、銀或銀合金之一金屬材料係藉由濺鍍等方法 '儿積於純怨層7 0上，並藉由使用一光罩之光蝕刻方法加以圖案化’以形成數個第一與第二像素電極821與822。在本發明之第三與第四實施例中，具有第一與第二像素電極821與822之左半與右半區域中，相同的反射係數係乂用於區域之光罩經180度反轉或旋轉也用於另一區域《一方法而獲致。其係可藉由排列一光罩於依附資料線路之形狀的交替方法中而獲致。雖然本發明之第三與第四實施例說明反射性LCD具有良好反射係數之像素電極821與822，該使用中性光而不用背光以顯示影像，但它們可施於半反半透性LCD，其中該半反半透性LCD具有在充足中性光條件下使用中性光顯示影像，與當充足的中性光缺乏時使用背光來顯示之能力。因此，像素電極821與822係應執行反射與傳送 26 550824 兩者。為了此目的，在一挑紐層7〇形成之後，像 82 1與822係藉由圖案化矸透性傳導材料如IT〇與形成，而具有良好反射係數之金屬係藉由圖案化金可透性面積佔有2 0至3 0 % ’形成於穿透性像素電與822上。本發明已參考較佳實施例加以詳細描述，應瞭本發明不侷限於所揭示之實施例，相反的是，本發蓋各式不同的變更體與相似之排列物，其並含於所請專利範圍之精神與範圍中。根據本發明，資料線、辅助訊號線與儲存線路係設素間以與像素電極之邊緣重疊，進而截止像素間漏。此外，線輅之數目之縮減係導致閘與資料驅動數目的縮減，明確言之為昂貴資料驅動1C數目的因此，L C D之製作成本可縮減至最小。【圖式簡單說明】藉由參考下述詳細之描述並結合具有說明相同兀件之參考符號之所附圖示，本發明更完整之認識隨之多項優點，係將更為顯明且易於明瞭，其中：第1圖為本發明之第一實施例用於一 LCD之薄膜 (TFT)陣列基板之佈局圖。第2圖為第1圖所不之TFT陣列基板沿著Π-Π，剖剖面圖。第3圖為本發明之一實施例用於一 LCD之TFT陣之等效電路圖。素電極 IZO而屬以使極 821 解的是明應涵附之申置於像之光洩 1C之縮減。或相似及所伴電晶體面線之列基板 27 550824 第4圖為本發明之第二實施例用於一 LCD之TFT陣列基板之佈局圖。第5圖為為本發明之一實施例用於一 LCD之TFT陣列基板之等效電路圖。第6圖為本發明之第三實施例用於一 LCD之TFT陣列基板之佈局圖。第7圖為第6圖所示之TFT陣列基板沿著VII_vn’剖面線之剖面圖。第8Α圖為說明本發明之第三實施例製作一 TFT陣列基板之第一步騾之佈局圖。第8B圖為第 8A圖所示之TFT陣列基板之沿著VIIIB-VIIIB’剖面線之剖面圖。第9A圖為顯示接續第8A圖所示步·驟之下一步驟之佈局圖。第9B圖為第9A圖所示之TFT陣列基板沿著IXB-IXB’剖面線之剖面圖。第1 0 A圖為顯示接續第9 A圖所示步驟之下一步驟之佈局圖。第10B圖為第10A圖所示之TFT陣列基板沿著XB-XB’ 剖面線之剖面圖。第11圖為顯示接續第1 0 A圖所示步驟之下一步驟之佈局圖。第1 2 A圖為顯示接續第11圖所示步驟之下一步驟之佈局圖0 28 550824 弟12B圖為第12A圖所千土丨甘』、同斤不《TFT陣列基板沿著χΠΒ_χΠΒ，剖面線之剖面圖。第13圖為說明本發明夕楚途^Parts of the pure green layer 70 on roads 62, 651, 652, 661, 662, 63 '671 and 672 are overexposed. Therefore, after the process, the passivation layer 70 on the data lines 62, 651, 652, 661, 662, 63, 671, and 67 2 25 = the thickness will be reduced, causing unevenness and unevenness. Therefore,可以可 # 分 111 The thickness of the portion 70 of the passive layer on the data lines 62, 651, 652, 661, 6 62, 63, 671, and 672 is sufficiently small to reduce the number of points. The amount of light reflection in other parts. Because the data lines 62, 651, 652, 661, 66 2, 63, 671 and their left and right regions have a first pixel electrode 821 'and a first pixel electrode 822, respectively, When reversed, the system has the same shape, so the mask used for the left half area can be rotated by 180 degrees for the right half area. Then, as shown in Figures 13 and 14, it has a high A reflection coefficient such as' a metal material such as gold, silver, or silver alloy is' accumulated on the pure layer 70 by sputtering and the like, and patterned by a photo-etching method using a mask 'to form a number First and second pixel electrodes 821 and 822. In the third and fourth embodiments of the present invention, In the left and right half regions with the first and second pixel electrodes 821 and 822, the same reflection coefficient is used. The mask used for the region is reversed or rotated by 180 degrees and used in another region. It can be obtained by arranging a photomask in an alternating method that depends on the shape of the attached data line. Although the third and fourth embodiments of the present invention describe pixel electrodes 821 and 822 with good reflection coefficients for reflective LCDs, the Neutral light is used instead of backlight to display images, but they can be applied to transflective LCDs, which have the ability to display images using neutral light under conditions of sufficient neutral light, and when sufficient The ability to use a backlight to display when neutral light is lacking. Therefore, the pixel electrodes 821 and 822 should perform both reflection and transmission 26 550824. For this purpose, after the formation of a button layer 70, like the 82 1 and 822 series By forming a patterned transmissive conductive material such as IT0 and forming, and a metal with a good reflection coefficient is formed by patterned gold permeable area occupying 20 to 30% 'formed on the transmissive pixel electrode and 822 The present invention has been referenced The preferred embodiments are described in detail. It should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention covers various modifications and similar arrangements, which are included in the spirit of the scope of the patents. According to the present invention, the data line, the auxiliary signal line and the storage line are arranged between the pixels to overlap the edge of the pixel electrode, thereby blocking the pixel leakage. In addition, the reduction in the number of lines leads to the number of gates and data drives. The reduction is clearly stated as the number of expensive data-driven 1Cs. Therefore, the LCD manufacturing cost can be reduced to a minimum. [Brief description of the drawings] By referring to the following detailed description and combining with reference symbols that describe the same elements The drawings show that a more complete understanding of the present invention is accompanied by a number of advantages, which will be more obvious and easy to understand. Among them: FIG. 1 is a layout of a thin film (TFT) array substrate for an LCD according to a first embodiment of the present invention. Illustration. Fig. 2 is a cross-sectional view of the TFT array substrate shown in Fig. 1 along Π-Π. FIG. 3 is an equivalent circuit diagram of a TFT array for an LCD according to an embodiment of the present invention. The element electrode IZO is used to make the electrode 821 clear, which is the reduction of 1C, which should be attached to the light beam of the image. Or similar and accompanying transistors Top line array substrate 27 550824 Figure 4 is a layout diagram of a TFT array substrate for an LCD according to a second embodiment of the present invention. FIG. 5 is an equivalent circuit diagram of a TFT array substrate for an LCD according to an embodiment of the present invention. Fig. 6 is a layout diagram of a TFT array substrate for an LCD according to a third embodiment of the present invention. FIG. 7 is a cross-sectional view of the TFT array substrate shown in FIG. 6 along a section line VII_vn '. FIG. 8A is a layout diagram illustrating the first step of fabricating a TFT array substrate according to the third embodiment of the present invention. Fig. 8B is a cross-sectional view of the TFT array substrate shown in Fig. 8A along the VIIIB-VIIIB 'section line. Fig. 9A is a layout diagram showing a step following the step shown in Fig. 8A. Fig. 9B is a cross-sectional view of the TFT array substrate shown in Fig. 9A along the line IXB-IXB '. Figure 10A is a layout diagram showing the next step following the step shown in Figure 9A. Fig. 10B is a cross-sectional view of the TFT array substrate shown in Fig. 10A along the XB-XB 'section line. Fig. 11 is a layout diagram showing a step following the step shown in Fig. 10A. Figure 1 2A shows the layout of the next step following the step shown in Figure 11. 0 28 550824 Brother 12B is the best place in Figure 12A. The same TFT array substrate along χΠΒ_χΠΒ, section Sectional view of the line. Fig. 13 illustrates the way of the present invention ^

月 < 罘四實施例，用於一 LCD之TFT 陣列基板之佈局圖。弟14圖為第13圖所示> rppTp备太丨甘吓不义TFT陣列基板沿著XIV-XIV，剖面線之剖面圖。第1 5 A圖為說明本發明之第四實施例，製作一陣列基板之第一步驟之佈局圖。第15B圖為第15A圖所示之TFT陣列基板沿著χνΒ-χνΒ，剖面線之剖面圖。第16A圖為顯示接續第15A圖所示步驟之下一步騾之佈局圖。第16B圖為第16A圖所示之TFT陣列基板沿著χνΐΒ_ X VIΒ ’剖面線之剖面圖。罘17Α圖為顯示接續第16Α圖所示步驟之下一步驟之佈局圖。第17Β圖為第17Α圖所示之TFT陣列基板沿著χνπΒ_ XVIIB，剖面線之剖面圖。第18圖為顯示接續第17Α圖所示步驟之下一步驟之佈局圖。第19Α圖為顯示接續第18圖所示步驟之下一步驟之佈局圖。第19Β圖為第19Α圖所示之TFT陣列基板沿著χΙχΒ ΧΙΧΒ’剖面線之剖面圖。 29 550824 【元件代表符號簡單說明： 1 10 基板 22 閘線 26 閘電極 28 儲存線路 29 儲存線路 30 閘絕緣層 40 半導體層 41 半導體層 42 半導體層 5 1 歐姆接觸層 52 歐姆接觸層 62 資料線 63 資料連接器 65 源極 66 汲極 70 鈍態層 82 像素電極 97 輔助資料塾 100 光罩 110 不透明部分 111 可穿透部分 131 儲存電極線 133 儲存電極 151 半導體層 152 半導體層 171 資料線 172 辅助訊號線 179 資料墊 180 鈍態層 189 接觸孔 221 閘線 222 閘線 261 閘線 262 閘線 552 歐姆接觸層 561 閘電極 562 歐姆接觸層 651 源極 652 源極 661 沒極 662 汲極 671 辅助線路 672 ，輔助線路 721 接觸孔 550824 722接觸孔 821 像素電極 822像素電極 921 輔助閘墊 922輔助閘墊 1211 閘線 1 2 1 2閘線 1231 閘電極 1 2 3 2閘電極 1251 閘墊 12 52閘墊 1632 歐姆接觸層 1 652歐姆接觸層 1731 源極 1 7 3 2源極 1751 汲極 1 7 5 2汲極 1821 接觸孔 1 8 22接觸孔 1851 接觸孔 1 8 5 2接觸孔 1901 像素電極 1 902像素電極 1911 可透性傳導膜 1 9 1 2可透性傳導膜 1922反射性傳導膜 1921 反射性傳導膜&Lt; Twenty-fourth embodiment, a layout diagram of a TFT array substrate for an LCD. Figure 14 is a cross-sectional view of the TFT array substrate along the XIV-XIV line shown in Figure 13 > rppTp. FIG. 15A is a layout diagram illustrating the first step of fabricating an array substrate according to the fourth embodiment of the present invention. FIG. 15B is a cross-sectional view of the TFT array substrate shown in FIG. 15A along the section line χνΒ-χνΒ. Fig. 16A is a layout diagram showing the next step following the steps shown in Fig. 15A. FIG. 16B is a cross-sectional view of the TFT array substrate shown in FIG. 16A along the χνΐΒ_ X VIB 'section line. Figure 17A shows the layout of the next step following the step shown in Figure 16A. FIG. 17B is a cross-sectional view of the TFT array substrate shown in FIG. 17A along the section line χνπΒ_ XVIIB. Fig. 18 is a layout diagram showing a step following the step shown in Fig. 17A. Fig. 19A is a layout diagram showing a step following the step shown in Fig. 18. FIG. 19B is a cross-sectional view of the TFT array substrate shown in FIG. 19A along the χΙχΒ χΙχΒ 'section line. 29 550824 [Simplified description of component representative symbols: 1 10 substrate 22 gate line 26 gate electrode 28 storage line 29 storage line 30 gate insulation layer 40 semiconductor layer 41 semiconductor layer 42 semiconductor layer 5 1 ohmic contact layer 52 ohmic contact layer 62 data line 63 Data connector 65 Source 66 Drain 70 Passive layer 82 Pixel electrode 97 Auxiliary data 塾 100 Photomask 110 Opaque part 111 Penetrable part 131 Storage electrode line 133 Storage electrode 151 Semiconductor layer 152 Semiconductor layer 171 Data line 172 Auxiliary signal Line 179 Data pad 180 Passive layer 189 Contact hole 221 Gate line 222 Gate line 261 Gate line 262 Gate line 552 Ohm contact layer 561 Gate electrode 562 Ohm contact layer 651 Source 652 Source 661 Pole 662 Drain 671 Auxiliary line 672 , Auxiliary line 721 contact hole 550824 722 contact hole 821 pixel electrode 822 pixel electrode 921 auxiliary gate pad 922 auxiliary gate pad 1211 gate line 1 2 1 2 gate line 1231 gate electrode 1 2 3 2 gate electrode 1251 gate pad 12 52 gate pad 1632 Ohm contact layer 1 652 Ohm contact layer 1731 Source 1 7 3 2 Source 1751 Drain 1 7 5 2 Drain 1821 contact hole 1 8 22 contact hole 1851 contact hole 1 8 5 2 contact hole 1901 pixel electrode 1 902 pixel electrode 1911 permeable conductive film 1 9 1 2 permeable conductive film 1922 reflective conductive film 1921 reflective conductive film

Claims

550824 费J、申請專利範圍 1 種薄膜電晶體陣列基板，用於一液晶顯示器，該薄膜電晶體陣列基板至少包含：一閘線路，包含數個於水平方向實質地延伸並傳送掃描訊號之成對閘線，包含及數個分別連接於該成對閘線之第/與第二薄膜電晶體之閘電極，而每對閘線係被分配於 /像素列；一資料線路，包含數個資料線、數個連接於各自之資料線之第一與第二薄膜電晶體之源極及第一與第二薄膜電晶體之汲極，其中該資料線於垂直方向實質地延伸並與該閘線絕緣且分別分配於兩相鄰像素行，而該汲極係以該閘電極為基礎與該源極分開並相對立放置；數個輔助訊號線，係與該閘線絕緣並與該資料線交替地設置’而每一輔助訊號線係被分配於一像素行；及數個像素電極，係經該第一與第二薄膜電晶體連接於藏成對之閘線與該資料線，該像素電極之邊緣係與該資料、、泉與該辅助訊號線重疊。申叫專利範圍第1項所述之薄膜電晶體陣列基板，其更包含一儲存線路，該儲存線路係與該像素電極重疊以形成儲存電容。申請專利範圍第2項所述之薄膜電晶體陣列基板，其上述之儲存、線路係包含數個於水平方向實質地延伸之 32 550824 電極線之儲存電極 6·一禋溥膜電晶體陣 4來一液晶顯示器儲存電極線與數個連接於讀儲存每一儲存電極與該汲極重疊。予 4·如申請專利範圍第3項所逑士 μ、+、、 t <溥膜電晶體陣列基板中上述 < 儲存電極於垂直方平板音雷極門* b 向實質地延伸、設置於素电桎間並與數個像素電梳 < —邊緣重疊。 5.如申請專利範圍第丨項所逑更包本一叙能既薄擬電晶體陣列基板更鈍態層，該鈍態層# 間並且f , 诉置於該汲極與該像素間卫八有數個用於與該像孔。、電極與該汲極連接之電晶體陣列基板至少包含：一閘線路，係包含數個成 Λ斟闡绐、μ 閑、、泉與數個分別成"在<弟-與第二薄膜電晶體之閘電極，其閉線於水平方向實質地延仲並置於分別像素之頂及傳送掃描訊號；一資料/線路，係包含數個資料線、數個連接於各資料線之第一與第二薄膜電晶體之源極與第一與第二電晶體之沒極，其中該資料線於垂直方向實質地延伸定出該像素並與該閘線絕緣且分別分配於兩相鄰像素而該汉極係以該閘電極為基礎與該源極分開並相對置；及，而，其該像，其電極接觸薄膜於該成對底部自之薄膦行，立效 33 、、數個像素電極，係經該第/與第二薄膜電晶體連接於孩成f +、、之閑線與該資料線，JL該像素電極係被分配於各自之像素。令申清專利範圍第6項所述之薄膜電晶體陣列基板，其中上迷之資料線係設置於該雨像素之一中心。 8 ·如申4專利範圍第7項所述之薄膜電晶體陣列基板，其更匕^與孩像素電極重疊之一儲存線路以形成儲存電 9·如申凊專利範園第中上述之儲存線路儲存電極線與數個中該儲存電極係於之一邊緣重疊。 8項所述之薄膜電係包含數個於水平連接於該儲存電極垂直方向實質地延晶體陣列基板，其方向實質地延伸之線之儲存電極，其伸並與該像素電極 i。·如甲:::：固第7項所述之薄膜其中上…-資料線係具有雙」：板，該資料線之該雙線互連之連接器。吏包含數個與 "•如中請專利範團第！。項所述之薄膜電晶其更包含-儲：電極線，該错存電極線係於水平二二伸it與该像素電極重疊。向^ 34 550824 1 2 ·如申請專利範圍第丨丨項所述之薄膜電晶體陣其更包含一儲存電容導體圖案，該儲存電容導連接於該汲極與該像素電極並與該儲存電極線 1 3 · —種薄膜電晶體陣列基板，用於一液晶顯示膜電晶體陣列基板至少包含：一閘線路’係包含數個成對閘線與數個分別成對閘線之第一與第二薄膜電晶體之閘電極，其閘線於水平方向實質地延伸並置於分別像素之頂及傳送掃描訊號；一資料線路，係包含數個資料線、數個連接資料線之第一與第二薄膜電晶體之源極與第一與電晶體之汲極，其中該資料線於垂直方向實質地定出讀像素並與該閘線絕緣且分別分配於兩相鄰而該汉極係以該閘電極為基礎與該源極分開並置；及數個像素電極，係經該第一與第二薄膜電晶該成對之閘線與該資料線，且該像素電極係被分之像素，其中該第一薄膜電晶體之閘電極、源極具有以線為基礎旋轉對稱之閘電極、源極與第二該線係將相鄰之像素分為左右兩半部或上下兩部 14.如申請專利範圍第13項所述之薄膜電晶體陣其更包含一鈍態層，該鈍態層係置於該第一與第列基板，體圖案係重疊。器，該薄連接於％中該成對部與底部於各自之第二薄膜延伸以界像素行，相對立故體連接於配於各自與沒極係沒極，而分。列基板，二薄膜電 35 550824 晶體之汲極與該像素電極間並具有一不平坦表面，該鈍態層至少包含一感光有機材料。 1 5 ·如申請專利範圍第1 3項所述之薄膜電晶體陣列基板，其中上述之像素電極至少包含鋁、鋁合金、銀或銀合金。 1 6.如申請專利範圍第1 3項所述之薄膜電晶體陣列基板，其中每一像素電極係包含一包含ITO或IZO材料之可透性傳導層與一包含鋁、鋁合金、銀或銀合金材料之不透明傳導層，並具有一暴露該不透明傳導層面積20至30百分比之孔徑。 1 7. —種製造液晶顯示器之薄膜電晶體陣列基板之方法，該方法至少包含下列步驟：形成一閘線路，該閘線路包含第一與第二閘線與分別連結於該第一與第二閘線之第一與第二閘電極；形成一覆蓋該閘線路之閘絕緣層；形成一半導體層於該閘絕緣層上；形成一資料線路於該半導體層上，其中該資料線路包含第一與第二資料線、連接於該第一與第二資料線之第一與第二源極、分別與該第一與第二源極分開之第一與第二汲極、與連接於該第一與第二資料線之資料連接器；形成一鈍態層，該鈍態層係具有一不平坦表面與分別暴露該第一與第二汲極之第一與第二接觸孔；及 36 550824 形成經該第一與第二接觸孔分別連接於該第一與第二汲極之第一與第二像素電極，其中形成用於兩相鄰像素之該閘線路、該資料線路、該半導體層、該鈍態層與該像素電極之至少一者之一光罩，係藉由將相鄰像素分為左右兩半或上下兩部分之線為基礎旋轉180度，以被使用於兩相鄰像素。550824 Fee J. Patent application scope 1 thin-film transistor array substrate for a liquid crystal display. The thin-film transistor array substrate includes at least: a gate line, including a pair of substantially extending horizontally and transmitting a scanning signal. The gate line includes and a plurality of gate electrodes of the first and second thin film transistors connected to the pair of gate lines, and each pair of gate lines is allocated in a / pixel column; a data line including a plurality of data lines And a plurality of first and second thin-film transistor sources and drains of the first and second thin-film transistors connected to respective data lines, wherein the data lines substantially extend in a vertical direction and are insulated from the gate line And are respectively distributed in two adjacent pixel rows, and the drain electrode is separated from the source electrode and placed opposite to each other on the basis of the gate electrode; several auxiliary signal lines are insulated from the gate line and alternate with the data line Set 'and each auxiliary signal line is assigned to a pixel row; and several pixel electrodes are connected to the pair of gate lines and data lines hidden by the first and second thin film transistors, Springs ,, edge lines overlap with the signal line and the auxiliary data. The application is referred to as the thin film transistor array substrate described in item 1 of the patent scope, which further includes a storage circuit which overlaps with the pixel electrode to form a storage capacitor. The thin-film transistor array substrate described in item 2 of the scope of the patent application, the storage and wiring mentioned above include a plurality of storage electrodes 6 which are substantially horizontally extending 32 550824 electrode wires. A storage electrode line of a liquid crystal display and a plurality of storage electrodes connected to the read storage overlap each other with the drain electrode. 4. As described in item 3 of the scope of the patent application, μ, +, and t < The above-mentioned < storage electrode in the vertical transistor plate array substrate in the film transistor array substrate * b extends substantially to the The pixels are overlapped with the pixel combs < -edges. 5. As described in the scope of the patent application, the package can be thinner and more passive layer of the pseudo-transistor array substrate, and the passive layer is located between the drain electrode and the pixel. There are several holes for this image. The transistor array substrate whose electrodes are connected to the drain electrode includes at least: a gate circuit, which includes several elements, such as Λ, μ, 泉, 泉, and a plurality of elements, respectively, in the " brother- and second film The gate electrode of the transistor, its closed line extends substantially in the horizontal direction and is placed on top of the respective pixels and transmits the scanning signal; a data / line, which consists of several data lines, several first and The source of the second thin film transistor and the poles of the first and second transistors, wherein the data line substantially extends in a vertical direction to define the pixel and is insulated from the gate line and is respectively allocated to two adjacent pixels and the The Han electrode is based on the gate electrode and is separated from the source electrode and is opposite to the source electrode; and, in the image, the electrode contact film is on the thin phosphine line at the bottom of the pair. Is connected to the f +,,, and leisure lines of the first thin film transistor and the second thin film transistor, and the data line, and the pixel electrodes of JL are allocated to the respective pixels. Let the thin-film transistor array substrate described in item 6 of Shenqing's patent scope, wherein the data lines of the above are arranged in the center of one of the rain pixels. 8 · The thin film transistor array substrate described in item 7 of the scope of patent 4, which is a storage circuit overlapping with the pixel electrode to form a storage circuit 9 · The storage circuit described above in the patent application park The storage electrode line overlaps one edge of the storage electrode. The thin film system described in item 8 includes a plurality of storage electrodes which are substantially horizontally connected to the storage electrode in the vertical direction and which extend substantially in the vertical direction of the crystal array substrate, and which extend substantially in parallel with the pixel electrode i. · A :::: Film described in item 7 where the upper ...- data line has a double ": board, the connector of the data line's two-wire interconnection. Officials include several " • If you ask for patent fan group first! . The thin film transistor described in the above item further includes a storage electrode line, and the staggered electrode line is horizontally overlapped with the pixel electrode. Xiang ^ 34 550824 1 2 · The thin film transistor array described in item 丨丨 of the patent application scope further includes a storage capacitor conductor pattern, and the storage capacitor is connected to the drain electrode, the pixel electrode, and the storage electrode line. 1 3 · —A thin film transistor array substrate for a liquid crystal display film transistor array substrate includes at least: A gate line 'includes first and second pairs of gate lines and a plurality of paired gate lines, respectively. The gate electrode of a thin film transistor, the gate line of which is substantially extended in the horizontal direction and placed on top of the respective pixels and transmits a scanning signal; a data line is a first and a second film including a plurality of data lines and a plurality of connected data lines The source of the transistor and the drain of the first and the transistor, wherein the data line substantially defines a read pixel in a vertical direction and is insulated from the gate line and is respectively allocated to two adjacent ones and the Han electrode is based on the gate electrode It is separated and juxtaposed with the source as a basis; and a plurality of pixel electrodes are passed through the paired gate lines and the data lines of the first and second thin film transistors, and the pixel electrodes are divided pixels, where the first One The gate electrode of the film transistor, the source electrode has a rotationally symmetrical gate electrode based on the line, the source electrode and the second line divide adjacent pixels into left and right halves or upper and lower halves. The thin film transistor array according to item 13 further includes a passivation layer, which is disposed on the first and second rows of substrates, and the body pattern is overlapped. The thin film is connected to the pair of parts and the bottom part of the second thin film extending to the boundary of the pixel line, and the opposite is connected to each of the two electrodes. An array substrate, two thin-film electrical 35 550824 crystals, has an uneven surface between the drain electrode and the pixel electrode, and the passivation layer contains at least a photosensitive organic material. 15 · The thin film transistor array substrate according to item 13 of the scope of patent application, wherein the above pixel electrode includes at least aluminum, aluminum alloy, silver or silver alloy. 16. The thin film transistor array substrate according to item 13 of the scope of patent application, wherein each pixel electrode system comprises a permeable conductive layer containing ITO or IZO material and a layer containing aluminum, aluminum alloy, silver or silver. The opaque conductive layer of the alloy material has a pore size that exposes 20 to 30 percent of the area of the opaque conductive layer. 1 7. A method of manufacturing a thin film transistor array substrate for a liquid crystal display, the method includes at least the following steps: forming a gate circuit, the gate circuit including first and second gate lines and connected to the first and second lines, respectively; First and second gate electrodes of the gate line; forming a gate insulating layer covering the gate line; forming a semiconductor layer on the gate insulating layer; forming a data line on the semiconductor layer, wherein the data line includes the first Connected to the second data line, first and second sources connected to the first and second data lines, first and second drains separated from the first and second sources, respectively, and connected to the first A data connector of a first and a second data line; forming a passive state layer having an uneven surface and first and second contact holes respectively exposing the first and second drain electrodes; and 36 550824 Forming first and second pixel electrodes connected to the first and second drain electrodes via the first and second contact holes, respectively, wherein the gate line, the data line, and the semiconductor layer are formed for two adjacent pixels. The passive layer and the image The mask of at least one of the element electrodes is rotated 180 degrees based on a line that divides adjacent pixels into left and right halves or two parts, so as to be used in two adjacent pixels.

1 8 ·如申請專利範圍第1 7項所述之方法，其中上述之光罩包含數個不透明部分與數個可穿透部分，該數個可穿透部分包含一具有一第一寬度之第一邵份、一具有一小於該第一寬度之第二寬度之第二部份、及一具有一大於該第二寬度且小於該第一寬度之第三寬度之第三部份，而該第一部份對應於該第一與第二接觸孔、該第二部分對應於該資料線路且該第三部份對應於該剩餘之部分。18 · The method as described in item 17 of the scope of patent application, wherein the above-mentioned photomask includes a plurality of opaque portions and a plurality of transparent portions, and the plurality of transparent portions includes a first portion having a first width. A portion, a second portion having a second width smaller than the first width, and a third portion having a third width larger than the second width and smaller than the first width, and the first portion A portion corresponds to the first and second contact holes, the second portion corresponds to the data line, and the third portion corresponds to the remaining portion.

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