TW548838B

TW548838B - DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same

Info

Publication number: TW548838B
Application number: TW091109851A
Authority: TW
Inventors: Wingyu Leung; Fu-Chieh Hsu
Original assignee: Mosys Inc
Priority date: 2001-11-02
Filing date: 2002-05-10
Publication date: 2003-08-21

Abstract

A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrae. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

Description

548838 五、發明說明u) 本案係由Wingyu Leung與Fu-Chieh Hsu所共同擁有申請於2 0 0 1年1月29日之審查中序號為〇 9/772, 434之美國申請案「利用一邏輯程序方法製造之降低拓撲圖DRAM胞元及其操作方法」之部分連續案，而其為Wingyu 1^11叫與{^一 Chieh Hsu所共同擁有，申請於1 9 9 9年1〇月25日之審查中序號為0 9/42 7, 38 3之美國申請案「利用一修飾的邏輯程序製造的DRAM胞元及其操作方法」之一部份連續案，又其為 Wingyu Leung與Fu-Chieh Hsu所共同擁有，頒發於2〇〇〇年 11月14日之美國專利編號6, 147, 914「晶片上字線電壓產生用以耦合DRAM於邏輯製程」之一部份連續案，又其為548838 V. Description of the Invention u) This case is jointly owned by Wingyu Leung and Fu-Chieh Hsu. The US application No. 09/772, 434 under review on January 29, 2001, "Using a Logic Partial continuation of the "Reduction of Topological Map DRAM Cells and Operation Method" by Program Method, which is jointly owned by Wingyu 1 ^ 11 and {^ 一 Chieh Hsu, and applied for October 25, 1999 Part of the serial application of the U.S. application No. 0 9/42 7, 38 3 under review for "DRAM cells manufactured using a modified logic program and its operation method" is also Wingyu Leung and Fu-Chieh Part of the serial case jointly owned by Hsu and issued on November 14, 2000, US Patent No. 6,147,914 "Wordline voltage generation on chip to couple DRAM to logic process", which is

Wingyu Leung與Fu - Chieh Hsu所共同擁有，頒發於2〇〇〇年 6月13日之美國專利編號6, 〇75, 72〇「耦合於記憶胞元」。 T ^ 本發明j關於動態隨機存取記憶體（DRAM)。此外，發明係關於藉由稍加修飾一習用邏輯製程所製造而得之一 DRAf本^日月更係、關於在晶片上產生精確電壓，以操作利用傳統邏輯製程所製造或耦合之DRAM。、 =芩閱第一圖（A)，其係一習用DRAM胞元1〇〇之概示圖，其係利用一習用邏輯製程所製造而得。第一圖^ DRAM胞tlI 00之橫切概示圖。此處所用之該習用 μ ;之其义r用一層多晶石夕，且提供-單槽或雙槽結構之半夺脰衣程。DRAM胞元1〇〇包含一p-通道M〇s存 17連接至位兀、、泉5，以及一來源終端以，連接至一卜通道Wingyu Leung and Fu-Chieh Hsu jointly owned US Patent No. 6,075,72 of June 13, 2000 "Coupled to Memory Cells". T ^ The present invention relates to dynamic random access memory (DRAM). In addition, the invention relates to a DRAf made by slightly modifying a conventional logic process, and is more about generating precise voltages on a wafer to operate a DRAM manufactured or coupled using a conventional logic process. , = Read the first picture (A), which is a general diagram of a conventional DRAM cell 100, which is manufactured using a conventional logic process. The first figure is a schematic cross-sectional view of the DRAM cell t11 00. The customary μ used here; its meaning r uses a layer of polycrystalline stone, and provides a semi-robust clothing process with a single-slot or double-slot structure. The DRAM cell 100 includes a p-channel M0s, 17 connected to a bit channel, a spring 5, and a source terminal to connect to a channel.

第7頁 548838 五、發明說明（2) MOS電晶體2之閘極11。該來源終端is與該閘極丨丨間之連接，令人不滿的是其降低了該DRAM胞元1 0 〇之對齊面積。该P -通道Μ 0 S電晶體2被設定運作為電荷儲存電容器。'今弘日日體2之該輸入與輸出1 9係共同連接。該電晶體2之輸入，輸入與通道係被連接以接收一固定的極板偏壓電^ :ΡΡ。，νρρ電壓正極的升高電壓，其係高於正極的供應電壓Page 7 548838 V. Description of the invention (2) Gate 11 of MOS transistor 2. The connection between the source terminal is and the gate is unsatisfactory because it reduces the alignment area of the DRAM cell by 100. The P-channel MOS transistor 2 is set to operate as a charge storage capacitor. 'The input and output 19 of today's Hongri Sun Body 2 are connected in common. The input, input and channel of the transistor 2 are connected to receive a fixed plate bias voltage ^: PP. , Νρρ The rising voltage of the positive electrode, which is higher than the supply voltage of the positive electrode

Vdd ’咼於一電晶體的臨限電墨。承上所述，該電荷儲存電容器之電極，係定義為至該存T電晶體之節點，且該電荷儲存電容器之計數電口 U定義為耦合以接收一固定極板偏壓電壓之節點。因此，在该D R A Μ胞元1 〇〇中，該電曰 ^ ^ # t s ^ ^ ； Λ V ^ ^€ 電荷儲存電容器、之該計數電極。Β “、運s形成該為了改善該DRAM胞元1〇〇之軟錯誤率係製造於一n-槽區域14中，盆千取这度忒胞兀 G (取於電晶體1之次臨限漏損量最小化，？槽14材二:V 了 SC 漏該次臨限漏損量之；Hn—槽14之該偏壓電壓，使得量。當該儲存 /卫不明顯增加該耦合點之漏損丄谷為’位元線5中之儲在帝y、士 4崔W X:外適當程度（亦即Vdd或中之何被攜帶至该晶體1。因而，誃姓六币—。。、，泉3被活化以活化存取電電荷最小化，需要將子一谷:q之電極被充電。為了將儲存 ^，其小於該供去:動至-負極的升高電麈 M &Vss減去存取電晶體1之該臨限電壓第8頁 548838Vdd 'is trapped in a threshold electric ink of a transistor. As mentioned above, the electrode of the charge storage capacitor is defined as the node to the transistor T, and the counting port U of the charge storage capacitor is defined as the node coupled to receive a fixed plate bias voltage. Therefore, in the DR A M cell 100, the electric charge is ^ ^ # t s ^ ^; Λ V ^ ^ €, the charge storage capacitor, and the counting electrode. Β "This operation was performed in order to improve the soft error rate of the DRAM cell 100. It was manufactured in an n-slot region 14 and was taken at this degree. G (taken from the second threshold of transistor 1) Leakage amount is minimized, the second material of slot 14: V is the threshold leakage quantity of SC leakage; Hn—the bias voltage of slot 14 makes the quantity. When the storage / guard does not increase the coupling point significantly Leakage Kariya is 'bit line 5' stored in Emperor Y, Shi 4 Cui WX: outside the appropriate degree (that is, Vdd or Zhong He is carried to the crystal 1. Therefore, the surname is six coins -..., The spring 3 is activated in order to minimize the access electric charge, and the electrode of the sub-valley: q needs to be charged. In order to store it, it is smaller than the supply: move to the negative electrode of the rising voltage & M & Vss Subtract this threshold voltage for access transistor 1 第 8548548838

五、發明說明（3) (Vtp )之絕對差值。在資料保留狀態中，存取電晶體1係藉由驅動字元線3 至該Vdd供應電壓而關閉。為了將該電容器之該電荷儲存最小化，該計數電極之偏壓係於該正極之升高電壓L。該= 板黾壓Vpp ’其係籍由形成5亥電荷儲存電容器之該電晶體2 ° 之氧分解電壓而受限。 DRAM 胞元 1〇〇及其衍生物，SK.Skjaveland，L Township 與Ρ· Gi11ingham(此後以Skjaveland 等人為替）提供於美國專利編號5，600，598，題目為「|馬合dram於 A S I C製程之記憶胞元與字元線驅動器」，以及1 g g 6年 ISSCC 摘要’第 262 至 263 頁，由p. Gillingham，B.5. Description of the invention (3) (Vtp) Absolute difference. In the data retention state, the access transistor 1 is turned off by driving the word line 3 to the Vdd supply voltage. In order to minimize the charge storage of the capacitor, the bias voltage of the counter electrode is based on the boosted voltage L of the positive electrode. The = plate pressure Vpp ′ is limited by the oxygen decomposition voltage of the ° 2 ° of the transistor forming the 5H charge storage capacitor. DRAM cell 100 and its derivatives, SK. Skjaveland, L Township, and P. Gi11ingham (hereafter replaced by Skjaveland et al.) Are provided in US Patent No. 5,600,598, entitled "| 马合 dram in ASIC process "Memory Cells and Word Line Drivers", and 1 gg 6-year ISSCC Abstract 'pp. 262-263, by p. Gillingham, B.

Hold ’I· Mes ，C· 0’Connell ，Ρ· Schofield ，Κ· Skjaveland’R· Torrance，Τ· Wojcicki’H· Chow(此後以Gill ingham等人為替）所著之「一〇· 8微米邏輯製程中用以 1.244 Gb.s ATM 轉接之一 768k 耦合 DRAM」uSkjaveland 等人與Gi 11 ingham等人皆苗述記憶胞元包含於形成在型基材中之一 η -槽中。第二圖石夕一字元線控制電路2 0 0之一示意圖，其包含 Gi 1 1 ingham等人所述之一字元線驅動器電路2(η以及一字兀線增加產生器201。該字元線控制電路2〇〇包含p—通道電晶體211-217 ’轉換器22卜229，NANd閘極23卜232，以及 Μ 01?閘極2 4 1 ’其連接方式如圖所示。字元線驅動器2 〇工包含P-通逼向上拉電晶體2U，其使得一組合的字元線被向上拉至該vdd供應電壓。提供p—通道向下拉電晶體212 一 548838Hold 'I · Mes, C. 0'Connell, P. Schofield, K. Skjaveland'R. Torrance, T. Wojcicki'H. Chow (hereafter replaced by Gill ingham et al.), "0.8 micron logic 768k coupled DRAM, one of the 1.244 Gb.s ATM switches used in the manufacturing process, "uSkjaveland et al. And Gi 11 ingham et al. Described that the memory cell is contained in an n-groove formed in a type substrate. The second figure is a schematic diagram of a word line control circuit 2000 of Shi Xi, which includes a word line driver circuit 2 (η and a word line increase generator 201 described by Gi 1 1 ingham et al. The word The element line control circuit 200 includes p-channel transistors 211-217 'converter 22, 229, NANd gate 23, 232, and M 01? Gate 2 4 1'. The connection method is shown in the figure. The line driver 200 includes a P-pass pull-up transistor 2U, which causes a combined word line to be pulled up to the vdd supply voltage. A p-channel pull-down transistor 212-548838 is provided.

第ίο頁 548838 五、發明説明C5) 量。Hash 1 mo to等人未能描述該字元線驅動器之結構。因此期望有一字元線驅動器電路，其改善利用一習用邏辑製程製造之DRAM胞元中漏損量電流。再者，期望有一改善的方法，用以偏壓一以習用邏輯製程製造之DRAM胞元。因此，本發明提供一記憶系統，其包含一動態隨機存取記憶體（DRAM)胞元，一字元線，以及利用一習用邏輯製轾製造之D — CMOS字元線驅動器。在此實施利之一特定的變化中，該DRAM胞元包含一存取電晶體，其具有一薄的閘極氧化物，以及一電容器結構，其具有一厚的閘極氧化物且典型地用於高電壓I/O裝置。。在本發明之其他實施例中，一⑽龍胞元係藉由稍加修 ί 1 f f輯程製而製造。在一實施例中，該DRAM胞元之製 :於：由製造一冠狀電極與一dram胞元之板電⑮，其大多電曰麟Γ晶圓下之凹陷區域。該冠狀與板電極係於該存取 ΐ;:::該閑極電極形成前製造而成。該凹陷區域之形成之該凹Ρ Ξ:包ΐ的場氧化物層。該包埋的場氧化物層中冠狀電：D:立置鄰近於該矽晶圓之-暴露部分。該讀暴敷邻^ ν 、於°亥％氧化物知該凹陷區域與該矽晶圓知觸區，w γ j 亥虺狀電極向外擴散造成一摻雜的接極包含—^ # δ亥矽晶圓之先前暴露之部份中。該冠狀電該凹陷Ρ 品或/、係位於该凹陷區域之底部，以及由區域向上延伸之相丨辟八Φ @ 之上。β 您側壁。一介電層係位於該冠狀電極Page ίο 548838 V. Description of the invention C5) amount. Hash 1 mo to et al failed to describe the structure of the word line driver. It is therefore desirable to have a word line driver circuit that improves the leakage current in a DRAM cell manufactured using a conventional logic process. Furthermore, an improved method is desired for biasing a DRAM cell manufactured in a conventional logic process. Therefore, the present invention provides a memory system including a dynamic random access memory (DRAM) cell, a word line, and a D-CMOS word line driver manufactured using a conventional logic system. In a specific variation of this implementation, the DRAM cell includes an access transistor having a thin gate oxide, and a capacitor structure having a thick gate oxide and is typically used for High voltage I / O device. . In other embodiments of the present invention, a dragon cell is made by slightly modifying the 1 f f series system. In one embodiment, the DRAM cell system is manufactured by: manufacturing a plate electrode of a crown electrode and a dram cell, most of which are recessed areas under a wafer. The coronal and plate electrodes are manufactured on the access ΐ; ::: before the idle electrode is formed. The recessed region formed by the recessed region is a field oxide layer. In the buried field oxide layer, the corona: D: stands adjacent to the exposed portion of the silicon wafer. The read exposure layer ^ ν, the oxide of 5%, the depression area and the silicon wafer contact area, w γ j helium-shaped electrode diffuses outwards to cause a doped electrode to include — ^ # δ 海Of previously exposed portions of silicon wafers. The coronal electric product P // is located at the bottom of the recessed area, and the phase extending upward from the area is above Φ @@. β Your sidewall. A dielectric layer is located on the crown electrode

第11頁 Μ电極係位於該介電層之上，因而完成該DRAM胞 548838 五、發明說明（6) ^之兒谷為。該板電極於該基礎區盥兮之上延伸。 /、σΛ难狀電極知該側壁在該電容哭P _ny , 電層係熱生成。該，$， 1以存取電晶體之一閘極介驟，形成於該閘極介雷用白用邏軏製程步 ί存；電晶體至該電容器。該儲存電極因此輕合 i憂點i ,一目七«λ· 〆才反笔才系4M. 、+ , v為具有向電容的DRAM胞元，—^、料卞之構，了的表面形態。此構造更僅需要對 =:與- 取小的修改…月確地，兩個附加的光罩牛二，製程做二曰“夕層被使用於形成該電容器。關於；成；^附加皿度循環並不影響N+與]^淺接合之形成， =，奋态的體製作過程中石夕化物之形成。此外，該内部該^ :取電晶點大多無矽化物於減少的漏損電流。 X電各盗之節此實施例的衍生變化中，該冠狀電極與該鬧自該相同的多晶矽層形成。極電極皆在本發明的另一實施例中，該DRAM胞元包 — 結構，其延伸進入形成於一場介電層之一凹處，容器 °亥兒容器結構具有一相當大的表面區域與一相冬使存區域。在-實施例中，僅增加一光罩步驟至—：田、的對齊製程中，該電容器結構製作如下。一場介電白的邏輯，形成於具有一第一傳導性之一半導體基如：氧 "電層延伸至該半導體基材之一上表面下。一凹声遠場成，係藉由透過一光罩之一開口蝕刻該場介電处2形电層。該凹處 548838Page 11 The M electrode system is located on the dielectric layer, thus completing the DRAM cell. 548838 V. Description of the invention (6) The plate electrode extends above the base area. /, ΣΛ difficult-shaped electrode knows that the sidewall cries at the capacitor P_ny, and the electrical layer generates heat. The $, 1 is used to access one of the gates of the transistor, and is formed in the gate dielectric using a logic process step; the transistor is connected to the capacitor. The storage electrode is therefore lightly connected to the worry point i, and the single-headed «λ · 〆 is only 4M., +, And v are the surface morphology of the DRAM cell with the capacitance, ^, and 卞. This structure only requires a small modification to =: and -... Indeed, two additional photomasks Niu Er, the manufacturing process is called "Xi layer is used to form the capacitor. About; Cheng; ^ additional dishes The cycle does not affect the formation of shallow junctions between N + and ^, =, the formation of stone compounds during the fabrication of the bulk body. In addition, the internal ^: most of the crystal points are free of silicide to reduce leakage current. X In the variation of this embodiment, the crown electrode is formed with the same polycrystalline silicon layer. The electrode is in another embodiment of the present invention, the DRAM cell package-structure, which extends Entering a recess formed in a field dielectric layer, the container structure has a relatively large surface area and a phase winter storage area. In the-embodiment, only a photomask step is added to-: Tian, In the alignment process, the capacitor structure is made as follows. A field of dielectric white logic is formed on a semiconductor substrate with a first conductivity such as: the oxygen layer extends below the upper surface of one of the semiconductor substrates. Concave far field is formed by passing through a One of the openings in the photomask etched the dielectric layer 2 of the field dielectric. The recess 548838

延伸於該基材之由該同一光罩的一臨限與該凹該該標準中該多之圖案體之一基材之一實施之下，該高電壓胞元之壓，以 vss供應提高電壓電晶體字元線該字元之該p- 調節區i或處之該暴光罩被移的多晶發晶石夕層之形成該電閘極電極該上表面例中，該具有不同字元線驅與一負極存取。供一正極致於該負電壓減掉供一耦合產生器之，則該轉產生器。線驅動器通道存取該上表面下開口被隨意。該臨限調露表面延伸除，且一閘閘極層隨後一部份充滿各裔結構之 °該電容器之上，以及閘極介電層的組成。動器受控制的升高電壓的升高電壓才虽的升高電二極體電壓電路於該字一間。例如合電路耦合當該DRAM胞至該負極升電晶體。二臨限調節裝置，隨後可經地執彳- r广丁’因此於該基材中形成郎區rr + 成隧著該基材的該上表面〇極介蕾形成層形成於該結構之上。 =、於該閘極介電層之上，其於該凹_ 一兩=處之内部。該多晶矽層电容器電極，與該存取電晶電極且士一立A有一部份，其延伸於該 4份其延伸於該凹處中。在在σ亥閘極電極與該電容器電極Extending under the threshold of the substrate by one threshold of the same photomask and one of the substrates of the plurality of pattern bodies in the standard, the voltage of the high voltage cell is increased by vss supply Transistor character line, the p-adjustment area i of the character, or the polycrystalline crystallite layer where the exposure mask is moved to form the electric gate electrode. With a negative access. Supplying a positive electrode causes the negative voltage to be subtracted from a coupling generator, then the converter. Line driver channel access The opening under the top surface is free. The threshold surface is extended, and a gate is subsequently partially filled with the structure of the various layers above the capacitor and the composition of the gate dielectric layer. The boosted voltage of the actuator is controlled to increase the voltage, although the voltage of the diode is increased in the circuit. For example, when the DRAM cell is coupled to the negative power-on crystal, the circuit is coupled. A two-threshold adjustment device can be subsequently executed-r Guang Ding 'thus forming a Lang region rr + in the substrate to tunnel the upper surface of the substrate. A polar mesogen formation layer is formed on the structure. . =, Above the gate dielectric layer, which is inside the recess _ one or two =. The polycrystalline silicon layer capacitor electrode has a portion with the access transistor electrode and a ridge A, which extends in the four portions and extends in the recess. At the sigma gate electrode with the capacitor electrode

，以選擇性地提供一正極的升至該字元線，因而控制該DRAM 產生裔以產生正極的升高電壓低於該Vss供應電壓，但大於下降（Vj ) ’其約為〇 · 6伏特。元線驅動裔與該正極或負極升 ’若該DRAM胞元係構成自pmqs 該字元線驅動器至該負極升高元被存取時’該耦合電路耗合高電壓，因而開啟該DRAM胞元In order to selectively provide a positive electrode to the word line, the DRAM generator is controlled to generate a positive electrode whose rising voltage is lower than the Vss supply voltage, but greater than the drop (Vj) 'which is about 0.6 volts. . The element line driver and the positive or negative electrode are raised. ’If the DRAM cell system is composed of pmqs, the word line driver to the negative electrode is accessed’, the coupling circuit consumes high voltage, so the DRAM cell is turned on.

第13頁 548838 五、發明說明才目及士合電路轉1’^賴臟元係構成自_S電晶體，則节耦田邊DRAM胞元被和升冋子兀線產生器。電晶體，電壓，因而開啟該咖胞元之該= 限制：ίΞΪΐί^生；”-電荷幫浦控制電路，其 ^ \。相同地，$自朽斗* 士 ^ 於Vdd加上一極體電壓下其限制該負極升高電 ^ 浦控極體電壓下降v 至電壓，小於Vss加上二該負；升高電壓係在參4;;::^ *邏輯製程n j【：：n:15微米電晶體之深次微 π R°亥身乳化物电晶體之該臨限電壓係/丨私〇· 5伙特。該臨限電壓係小於誃二包&係小於在恢復或存芎運管過浐中、Α 口電壓約0 · 6伏特。道驅動器電晶體，用於該存 =電壓係經由1-通之兮Ρ1扛 ^ 子取笔日日體（亦即該胞元字元繞）之δ亥閘極，其形成於型凡予兀線）程中，該負極升高電壓有助於= 運算過接近該vss供應電壓。理論上，兮=2，谷益充電至相當一P-通道臨限電壓（由於體效應Ί極升兩電麼應該至少於轉移)低於vss，以將該儲存力:的臨限電麼之電廢。然而在一邏輯f程广:之由該電及充電至等於vssPage 13 548838 V. Description of the invention Caime and Shihe Circuitry 1 ′ ^ Lai Zhuang element system is composed of _S transistor, then the node-coupled Tanabe DRAM cell is used as a booster line generator. Transistor, voltage, so turn on this cell = limit: ίΞΪΐί ^ 生; "-charge pump control circuit, which ^ \. Similarly, $ 自自斗 * 士 ^ plus a polar body voltage to Vdd It limits the negative electrode to increase the voltage ^ The voltage of the electrode body of the pump drops v to the voltage, which is less than Vss plus two negative voltages; the increasing voltage is in reference 4 ;; :: ^ * Logical process nj [:: n: 15 microns The threshold voltage of the transistor's deep sub-micron R ° Emulsion transistor is / 5. The threshold voltage is less than the second pack & The voltage across port A is about 0 · 6 volts. The channel driver transistor is used to store the voltage. The voltage is carried by 1- 通之 Ρ1 ^ ^ Take the pen sun body (that is, the cell character winding) The δH gate, which is formed in the Xingfanyu line), the rising voltage of the anode helps = the calculation is too close to the vss supply voltage. In theory, Xi = 2, Gu Yi charges to a considerable P- The threshold voltage of the channel (due to the body effect, the two electric powers should be at least less than the transfer) is lower than vss, so that the storage power of the electric power is: Edit f Cheng Guang: from the electricity and charging to equal vss

+厭 ^ m U中’其中該P 一基材偏壓於該V 電壓，使用一偏壓等於或小於〇 6 土 W侷&於電晶體之該來源，將-志兮·伏特至该11—通道驅動器 ’、、。成^n—通道驅動器電晶體之N+來源 548838 五、發明說明（9) 接合活化。因此，大的基材電流將自該負極升高電壓產生器流出至該基材，因而浪費能源且增加鎖上的可能性。重要的是選擇一負極升高電壓之該絕對電壓，以相當等於一P-通道電晶體（Vtp)之該臨限電壓之該絕對差值，但是小於一 P - N接合之該活化電壓。例如，介於0 . 3與0 . 4伏特之間之一負極升高電壓在使用過程中之Vtp為0. 5伏特或更低。本發明可藉由下列圖示與說明而得到更進一步知了解。第一圖A係一概示圖，說明藉由利用一習用邏輯製程製作之P-通道MOS電晶體習所形成之用DRAM記憶胞元。第一圖B係第一圖中該DRAM胞元之橫切剖面圖。第二圖係一概示圖，說明一習用字元線控制電路，其包含一字元線驅動器與一字元線電壓產生器。第三圖A係一DRAM記憶胞元之概示圖，其係由根據本案一實施例中電壓來源所支援。第三圖B與第三圖C係根據本案不同實施例中第三圖A 之該DRAM記憶胞元之橫切面示意圖。第三圖D係根據本案其他實施例中第三圖A該DRAM記憶胞元之對齊圖。第三圖E-第三圖F係根據本案不同實施例中第三圖A之該DRAM記憶胞元之橫切面示意圖° 第三圖G-第三圖R係根據本案其他實施例中不同的製造階段中，一DRAM記憶胞元的橫切示意圖。+ ^ ^ M U in 'where the P-substrate is biased to the V voltage, using a bias equal to or less than 0 土 W W & the source of the transistor, the-Zhi Xi · Volt to the 11 —Channel driver ',,. N ^ source of channel driver transistor 548838 V. Description of the invention (9) Joint activation. Therefore, a large substrate current will flow from the negative electrode voltage generator to the substrate, thereby wasting energy and increasing the possibility of locking. It is important to select the absolute voltage of a negative electrode boost voltage to be substantially equal to the absolute difference of the threshold voltage of a P-channel transistor (Vtp), but less than the activation voltage of a P-N junction. For example, one of the negative electrode raised voltages between 0.3 and 0.4 volts has a Vtp of 0.5 volts or less during use. The invention can be further understood by the following figures and descriptions. The first diagram A is a schematic diagram illustrating a DRAM memory cell formed by using a conventional P-channel MOS transistor fabricated by a conventional logic process. The first figure B is a cross-sectional view of the DRAM cell in the first figure. The second figure is a schematic diagram illustrating a conventional word line control circuit, which includes a word line driver and a word line voltage generator. The third diagram A is a schematic diagram of a DRAM memory cell, which is supported by a voltage source according to an embodiment of the present invention. The third figure B and the third figure C are schematic cross-sectional views of the DRAM memory cell according to the third figure A in different embodiments of the present case. The third diagram D is an alignment diagram of the DRAM memory cell according to the third diagram A in other embodiments of the present case. The third figure E-the third figure F are schematic diagrams of the cross-section of the DRAM memory cell in the third figure A according to different embodiments of the case. The third figure G-the third figure R are according to different manufacturing in other embodiments of the case. In this stage, a cross-section diagram of a DRAM memory cell.

第15頁 548838 五、發明說明（ίο) 第三圖S係根據本案之一實施例中第三圖R之該DRAM胞元之粗略對齊示意圖。第四圖A-第四圖J係根據本案其他實施例中不同的製造階段中，一DRAM記憶胞元的橫切示意圖。第四圖K -第四圖V係根據本案其他實施例中不同的製造階段中，一 D R A Μ記憶胞元的橫切示意圖。第四圖W -第四圖X係根據本案不同實施例中，包含第四圖V之該DRAM記憶胞元之陣列之對齊示意圖。第四圖Y-第四圖AA係根據本案其他實施例中不同的製造階段中，一 D R A Μ記憶胞元的橫切示意圖。第五圖係根據本案之一實施例中一字元線驅動器之示意圖。第六圖係一方塊圖，係根據本案之一實施例說明一字元線驅動器系統，其包含第一複數個字元線驅動器，一第二複數個VSSB耦合電路，一 VceB電壓產生器以及一 VBBS電壓產生器。第七圖係一示意圖，係根據本案之一實施例說明一 VSSB 耦合電路。第八圖係一波形圖，說明在操作第七圖之VSSB耦合電路過程中產生的不同訊號。第九圖A係一方塊圖，係根據本案之一實施例說明VeCB 與VSSB升高電壓產生器。第九圖B係一簡單示意圖，說明用於習用的正極升高電壓產生器中之一充電幫浦控制電路。Page 15 548838 V. Description of the Invention (3) The third diagram S is a rough alignment diagram of the DRAM cell according to the third diagram R in one embodiment of the present invention. The fourth diagram A to the fourth diagram J are cross-sectional diagrams of a DRAM memory cell according to different manufacturing stages in other embodiments of the present case. The fourth diagram K-the fourth diagram V are schematic cross-sectional views of a DRAM memory cell in different manufacturing stages according to other embodiments of the present invention. The fourth figure W-the fourth figure X are schematic diagrams of the alignment of the array of the DRAM memory cells including the fourth figure V according to different embodiments of the present case. The fourth figure Y-the fourth figure AA are schematic cross-sectional views of a DRAM memory cell in different manufacturing stages according to other embodiments of the present invention. The fifth diagram is a schematic view of a word line driver according to an embodiment of the present invention. The sixth diagram is a block diagram illustrating a word line driver system according to an embodiment of the present case, which includes a first plurality of word line drivers, a second plurality of VSSB coupling circuits, a VceB voltage generator and VBBS voltage generator. The seventh diagram is a schematic diagram illustrating a VSSB coupling circuit according to an embodiment of the present invention. The eighth diagram is a waveform diagram illustrating different signals generated during the operation of the VSSB coupling circuit of the seventh diagram. The ninth figure A is a block diagram illustrating a VeCB and VSSB boosted voltage generator according to an embodiment of the present invention. The ninth figure B is a simple schematic diagram illustrating a charge pump control circuit for a conventional positive voltage boost generator.

第16頁 548838 五、發明說明（11) 第九圖C係一簡單示意圖，說明用於習用的負極升高電壓產生器中之一充電幫浦控制電路。第十圖係一示意圖，係根據本案之一實施例說明一充電幫浦控制電路。第十一圖係一示意圖，係根據本案之一實施例說明一 Vbbs充電幫潘控制電路。第十二圖至第十七圖係說明根據本案之不同實施例中參考電流來源。 ' /第十八圖係一字元線與一電壓耦合電路之示意圖，其係根據本案利用NMOS電晶體形成該DRAM胞元之一實施例0 丨示J符別彳示示之外，以下描述DRAM記憶胞元之電壓 =:。其二用習用邏輯製程所製造，其為單一或雙槽製 Π早；；:曰曰石夕層以及-層或多層金屬層。在所描述的供應電心可具有名義值，例如3·3伏特，；.5 =該正伏特等，端視製造過程而定。該接地供應恭么古1 〇伏特，其被設定為供應電壓ν 。— _/、α电i之名義值合）電遷，之名義值約為〇·6伏特，二極一體落差（或P-N指Page 16 548838 V. Description of the invention (11) Figure 9 is a simple schematic diagram illustrating a charge pump control circuit for one of the conventional negative voltage boost generators. The tenth figure is a schematic diagram illustrating a charging pump control circuit according to an embodiment of the present invention. The eleventh figure is a schematic diagram illustrating a Vbbs charging band control circuit according to an embodiment of the present invention. The twelfth to seventeenth diagrams illustrate reference current sources in different embodiments according to the present case. '/ The eighteenth figure is a schematic diagram of a word line and a voltage coupling circuit, which is an embodiment of the DRAM cell formed by using NMOS transistors according to the present case. Voltage of memory cell = :. The second is made by a conventional logic process, which is a single or double-slot system. Π :; Said Shi Xi layer and-layer or multi-layer metal layer. The described supply core may have a nominal value, such as 3.3V, .5 = the positive volt, etc., depending on the manufacturing process. This ground supply is 10 volts, which is set to supply voltage ν. — _ /, The nominal value of αelectricity i) The nominal value of the electrical migration is about 0.6 volts, and the two-pole integrated drop (or P-N refers to

如第三圖Α所示’用於一實施例、破_=為1。含一P-通道存取電晶體301盥一甲—dram記憶胞元包配置為一儲存電容器。該存取電a曰%^儲存電晶體302，, 至子元線3 〇 3，且存取電晶體3 〇 1之、、☆ 0 1之该閘極係連接 3 0 5。存取電晶體3〇1的來源係 :出係連接至位元線 ° 電晶體3 0 2之該源極 548838 五、發明說明U2) 區。在所描述的實施例中，僅電晶體3 0 2之該源極區係每際上形成的（亦即電晶體3 〇 2沒有汲極區）。在另—每：焉中，該來源與汲極區皆被形成，且這些區域共同被連存取電晶體3 0 1之來源。電晶體3 〇 2之該通道形成該 ^ 容|§之该電極，且電晶體3 〇 2之該閘極形成該儲存帝=六子哭兒之該計數電極。儲存電晶體3 0 2之該通道（亦即該儲%存^ &… •器之該計數電極）係連接以接收一負極升高偏壓電冤，該偏壓電壓Vbbl係受限於該電容器3 0 2之該閘極之分= (Vbd)與儲存於該電極之最高電壓(Vi)。通常，偏】广被設定為大於Vi減掉vbd。在一較佳實施例中，心bl 正極供應電壓vdd，且偏壓電壓、^被設定為_〇.3伏特。、〇 :般而言，該偏壓電壓Vbbl被選擇為強度小於電壓降，為該偏壓電壓^被選擇為強度小-：體特。當電極被充電至該#、. 由增加電容器3 02之容量以應沒有該負極板偏壓Vbbl電ί ，容器302之操作。少，者通過节帝0 + 02之容量傾向於快速減電壓。电&夂传小於該MOS結構之該臨限單曰：ϊί:中所述，DRAM記憶胞元30〇係包含於-As shown in the third figure A, 'is used in one embodiment, and _ = is 1. A P-channel access transistor 301 and a Dram memory cell package are configured as a storage capacitor. The access transistor a refers to the storage transistor 302, to the element line 3 03, and the gates of the access transistor 3 01, ☆ 0 1 are connected to the gate 305. The source of the access transistor 301 is: the source is connected to the bit line. The source of the transistor 302 is 548838. 5. Description of the invention U2) area. In the described embodiment, only the source region of transistor 3 02 is formed (that is, transistor 3 02 has no drain region). In the other-each: 焉, the source and the drain region are both formed, and these regions are commonly connected to the source of the transistor 301. The channel of the transistor 3 02 forms the electrode of the capacitor §, and the gate of the transistor 3 02 forms the counting electrode of the storage emperor = Liuzier. The channel of the storage transistor 3 02 (that is, the counting electrode of the storage device) is connected to receive a negative bias bias voltage, and the bias voltage Vbbl is limited by the The gate of the capacitor 3 02 = (Vbd) and the highest voltage (Vi) stored in the electrode. Normally, the bias is set larger than Vi minus vbd. In a preferred embodiment, the positive voltage of the core bl is supplied with a voltage vdd, and the bias voltage, ^ is set to _0.3 volts. 〇: In general, the bias voltage Vbbl is selected to have a strength smaller than the voltage drop, and the bias voltage ^ is selected to have a low strength-: body characteristic. When the electrode is charged to the capacitor 302, the capacity of the capacitor 302 should be increased so that the Vbbl voltage is not biased by the negative plate, and the container 302 operates. If it is small, the capacity of the emperor 0 + 02 tends to decrease the voltage quickly. The electricity & transmission is smaller than the threshold of the MOS structure.

早日日夕基材3 0 6之η-摻雜槽3〇4中。同，槽3〇4。η-槽304係偏壓至—二重§己胞凡可以分其大於該供應電壓Vdd除以一電塵，：=正極電壓(W 晶體301之該臨限電壓（v /、、，々專於P-通道存取正極電壓V被選擇為小、^值。此外，該升高β 通逼存取電晶體301之該氧4As soon as possible, the η-doped trenches 304 of the substrate 3 06 are formed. Similarly, slot 30. The η-slot 304 is biased to-double § who can divide it above the supply voltage Vdd divided by an electric dust: = positive voltage (W the threshold voltage of crystal 301 (v / ,,, The P-channel access positive voltage V is selected to be small and high. In addition, the increased β forces the oxygen 4 of the access transistor 301

548838 五、發明說明（13) # : 係藉由連接至。型連接區315而偏二r 該^1電壓受控為約〇. 3伏特大# 供應電壓（亦即Vpt = 0.3伏特）。使用該ν ^大特大於4 低存取電晶體301之次臨 ΡΡ. ^ η槽3〇4降容哭彻 ^οπ, 兩属知里’且由於供應雜訊將電谷d ϋ 2與η-槽3 0 4之電極間技人Α 乂你两a 訂％小。麸而你田分π Π接5向刖偏壓的可能性降到- 二9然而’使用^電壓至η-槽304也增加了 V? "3〇2之電極接合漏損*，特別係於高電壓储“容當資料被存寫至記怜朐；q n n # > 一 V供靡+厥七扣心紀凡3 0 0日守’位凡線3 05耦合至兮 ;宜應⑼，以存寫-邏輯零資料值，或至V卩摩電i遠 ”：邏輯—資料值。此外，字元線3。“二接以 =、二f VSSB，其具有一電位約為-〇. 3伏特。根據一每二電壓程度被選擇為=二：於一 1 · 0伏特或争女g姑士人 u · 〇仇符’相比帝m备: 、；一習用DRAM執行。此大於v供 ^減掉-二極體電屋降。該u壓之產生之詳細;^ 當記憶胞元3 0 0係於該資料一先充電至約為該V供應兩、” 心中，位兀線3 0 5預容器3 0 2之該電極之電m之^半。當+位元線305獲該電元30。之次臨限漏損量傾向於工：供：：Π ’該記憶胞電晶體係更加嚴重。為，^，此。人臨限漏損量對於次微 pp ,a ,〇 ^〜為了減少在該資料保留狀態中之戈於限漏知里，予元線3 〇 3係耦合一人實施例，該V⑽電摩量被w j大於^供應電壓。根據一 ⑽包厂土里被廷為〇.2伏特至〇·5伏特大於548838 V. Description of the Invention (13) #: By connecting to. The connection region 315 is biased, and the voltage of ^ 1 is controlled to be about 0.3 volt large # supply voltage (that is, Vpt = 0.3 volt). Use the ν ^ large and larger than 4 low-access transistor 301 for the second time PP. ^ Η slot 3 04 derating and crying ^ οπ, the two belong to Zhili 'and because of the supply noise, the power valley d ϋ 2 and η- The electrode technician A in the slot 3 0 4 is smaller than the order of two a. The probability that your π π is connected to a 5-way bias is reduced to -2. However, the use of ^ voltage to η-slot 304 also increases the V? &Quot; electrode junction leakage of 302 *, especially In the high-voltage storage, "Rongdang data was saved and written to Ji Liao; qnn # > a V supply + Ju Qi Kou Xin Ji Fan 3 0 0 day guard 'Wei Fan line 3 05 coupling to Xi; Yi Ying⑼, To save write-logic zero data value, or to go far away from V ": logic-data value. In addition, the character line 3. "Two connected to =, two f VSSB, which has a potential of approximately -0.3 volts. According to the voltage level of one to two, it is selected as = two: at -1 · 0 volts or the female g u u u 〇 Qiu Fu's comparison with Emperor M ::,; a custom DRAM implementation. This is greater than v supply ^ minus-diode electric house drop. The details of the u voltage generation; ^ when the memory cell 3 0 0 is in the The data is first charged to about two volts of the V supply. In the heart, the voltage of the electrode 305 of the pre-container 3 302 is half of that of the electrode. When + bit line 305 gets this cell 30. The second threshold leakage amount tends to work: supply :: Π 'The memory cell transistor system is more serious. For, ^, this. The human threshold leakage amount is for the second micro pp, a, 〇 ~~ In order to reduce the knowledge leakage limit in the data retention state, Yuyuan Line 3 〇3 is coupled to one person embodiment, the V 该 electric friction amount is wj More than ^ supply voltage. According to a dumpling factory, the ground cover is 0.2 volts to 0.5 volts greater than

第19頁 548838 五、發明說明（14) 應電壓。此小於該、供應同於上述之該習用記憶胞元，直$ 電麼降。此不之詳細說明：；“供應電壓。該正極升高電壓％產生 4第v二圖之P_通道存取電晶體301與P-通道继产干祕 302包，薄閘極介電層各 =儲，晶體層典型被用於製造— _ 廷些缚閘極介電。.㈣米邏輯ί;中== 亥内部邏輯。例如，在約為2.5至广::。中缚間極介電層307與308典型的厚度且閑= 裝置，其閑極長度小於。.15微米，該閘極傳幹I、1二f30埃，通過該M0S館存電晶體302之該_儲傳存輪電V:之传門相Λ重胞元之所需恢復率“机’因而大幅增加該記憶旨數:Vv期望利用一厚的氧化物心伴柱日日肢3 02，因此減少該記憶胞元中該傳輸電流且保符一合理的恢復週期。哭社因此，本案的另一實施例中如第三圖c所示，該電容為結構之該薄閘極氧化物層3 〇 8係置換為厚的閘極氧化物 ^。厚的閘極氧化物層3 0 8A可得自於習用的雙氧化物邏輯製程。雙氧化物邏輯製程常用於製造半導體電路，其係2]用高效能薄氧化物電晶體與高電壓厚氧化物電晶體。 3阿效能薄閘極氧化物電晶體用以建構多數的功能組，且該厚閑極氧化物電晶體用以建構I/O電路與特殊功能組，Page 19 548838 V. Description of the invention (14) Voltage should be applied. This is smaller than the supply of the conventional memory cell described above. The detailed description of this is: "Supply voltage. The positive voltage increase of the positive electrode generates 4 Pv channel access transistors 301 and P-channels to produce dry 302 packages, each with a thin gate dielectric layer. = Storage, the crystal layer is typically used for manufacturing — _ 些 some bound gate dielectric .. ㈣米 Logicί; 中 == Hai internal logic. For example, at about 2.5 to wide ::. The typical thickness of the layers 307 and 308 are idle = device, and the length of the idle pole is less than .15 micrometers. The required recovery rate of the portal phase Λ heavy cell "machine" therefore greatly increases the memory purpose: Vv expects to use a thick oxide heart with pillars of the sun and limbs 3 02, thus reducing the transmission current in the memory cell And guarantee a reasonable recovery period. Therefore, in another embodiment of the present case, as shown in the third figure c, the capacitor is a structure in which the thin gate oxide layer 308 is replaced with a thick gate oxide ^. The thick gate oxide layer 308A is available from a conventional double oxide logic process. The double oxide logic process is often used in the manufacture of semiconductor circuits. System 2] uses high performance thin oxide transistors and high voltage thick oxide transistors. 3 A thin oxide gate transistor is used to build most functional groups, and the thick oxide oxide transistor is used to build I / O circuits and special function groups.

548838 五、發明說明（15) 其需要較高的電壓依從。該厚閘極氧化物電晶體因而非如習用於形成一記憶胞元之儲存電晶體（電容器）。。由於該厚閘極氧化物電晶體可得自習用雙重氧化物邏輯製程中’不需外加的處理步驟以製造厚閘極氧化物層 3 〇 8 A。隨意地，該厚閘極氧化物層3 〇 8A也可利用一外加的光罩步驟而分別形成，因此該層可比該I /0氧化物層薄（其典型厚度為5 0至7 〇埃）。值得注意的是該厚閘極氧化物層 2 8 A比該薄閘極氧化物層3 0 7厚。例如，在0 . 1 3微米邏輯製，中’該厚閘極氧化物層3〇8A之厚度約為25 —5〇埃，且該薄閘極氧化物層3 0 7之厚度約為15 —2〇埃。在一實施例中丄厚閘極氧化物層3 08A約較薄閘極氧化物層3〇7厚百分十尽閘極介電層3 0 8 A有利地降低通過p —通道儲存電晶體3 0 2之該傳輸電流。在另一實施例中，一淺凹處或凹區係形成於閘極氧化物層=8或308A之下，其係利用一外加的光罩步驟以增加閘極氧化物層308或308A之表面積，因而造成電容。 -實施例之詳細說明如第三_至第三圖s:。谷第三圖D係根據本案之一實施例說明記憶胞元3〇〇〇之對齊。位元線305之連接係分享於兩相鄰胞元之間，且電容器3 02之上板31 3係連接於平行該字元線相鄰胞元之兩列。鄰近胞元之電容器係經由場氧化物（F〇x)區314呈電性分離，例如藉由設定規則所允許之最小空間。由於電容哭板313係偏壓至該Vbbl，以使得該卜通道電容器之最大活即化，一較糟的例子為偏壓之存在超過場氧化物（F〇x)3i4為 548838548838 V. Description of the invention (15) It requires higher voltage compliance. The thick gate oxide transistor is therefore not as good as a storage transistor (capacitor) conventionally used to form a memory cell. . Since the thick gate oxide transistor can be obtained from the conventional dual oxide logic process, no additional processing steps are required to manufacture a thick gate oxide layer 308 A. Optionally, the thick gate oxide layer 3 08A can also be formed separately using an additional photomask step, so the layer can be thinner than the I / 0 oxide layer (its typical thickness is 50 to 70 angstroms). . It is worth noting that the thick gate oxide layer 2 8 A is thicker than the thin gate oxide layer 307. For example, in a 0.1 micron logic system, the thickness of the thick gate oxide layer 308A is about 25-50 angstroms, and the thickness of the thin gate oxide layer 307 is about 15- 20 angstroms. In one embodiment, the thicker gate oxide layer 3 08A is approximately thinner than the thinner gate oxide layer 3007, and the gate dielectric layer 3 0 8 A advantageously reduces the storage transistor 3 through the p-channel. 0 2 of the transmission current. In another embodiment, a shallow recess or recess is formed under the gate oxide layer = 8 or 308A, which uses an additional mask step to increase the surface area of the gate oxide layer 308 or 308A. , Thus causing capacitance. -The detailed description of the embodiment is shown in the third to the third figure s :. The third figure D illustrates the alignment of memory cells 3000 according to one embodiment of the present case. The connection of the bit line 305 is shared between two adjacent cells, and the upper plate 31 3 of the capacitor 3 02 is connected to two columns of adjacent cells parallel to the word line. The capacitors adjacent to the cells are electrically separated via the field oxide (Fox) region 314, for example, by setting the minimum space allowed by the rules. Since the capacitor plate 313 is biased to the Vbbl, so that the maximum activity of the Bu channel capacitor is instantiated, a worse example is that the existence of the bias exceeds the field oxide (F0x) 3i4 is 548838.

敢大的漏損置電流，其在魅一將此場漏損量電流最二化:二二錯存節點間流動。為了鄰近儲存節點之對角跨越尸=二各器板3 1 3被允許僅沿著間之可能的漏損量路护，=1物3 1 4。此迫使相鄰胞元隔，且同時減少該儲^節點^414乘以最大的Μ隔離間係藉由該電容器板313隔開/以的部分（於最小間隔），其 (其為電容器3 0 2之該通道區），㈤、於總儲存節點周圍之25% 最小化。而將可能的漏損量電流圖E係說明根據本案之另Dare to set the leakage current, which minimizes the field leakage current in Meiyi: two or two staggered storage nodes flow. For the diagonal crossing of adjacent storage nodes = two slabs 3 1 3 are allowed to protect only along the possible leakage path between them, = 1 3 1 4. This forces adjacent cells to be separated, and at the same time reduces the storage node ^ 414 times the maximum M isolation interval (the minimum interval) by the capacitor plate 313, which is the capacitor 3 0 2 of the channel area), ㈤, 25% around the total storage node is minimized. The potential leakage current, Figure E, illustrates

取電晶體3〇1與P-通道電^ 302力之—放貫大=中’ P-通道存― 施例中，該正常的P—型重來源杈刀圖。在此一貫係自該P-型連接區312排除/此=植，且該來源/排出如同閘料排出漏損量⑹DL)，其片可…少接合漏損量電流充電保留時間。在一習用邏輯製程凋=该儲存節點之該成通常係於(i )圖案化舆蝕刻該衣’了型電晶體之形 (i i)於該閘極邊緣，利用離日曰、-甲亟的程序之後，區，因而形成ρ-LLD區1輕摻雜該來源/汲極暴露：石夕表面，形成石夕化物（自行對齊之石夕化物)(，lv)於 (V)利用•子植入以重摻雜該暴露的 =)’以及Take the transistor 301 and the P-channel power ^ 302 force-put through large = medium 'P-channel storage-In the embodiment, the normal P-type heavy source is a branch knife diagram. Here, it is always excluded from the P-type connection area 312 / this = planted, and the source / discharge is the same as the leakage leakage amount of the discharge material (DL), and the piece can ... reduce the leakage leakage current charging retention time. In a custom logic process, the formation of the storage node is usually tied to (i) patterning and etching the shape of the transistor. (Ii) on the edge of the gate. After the procedure, the region, thus forming ρ-LLD region 1 lightly doped with the source / drain exposed: on the surface of Shi Xi, Shi Xi compounds (self-aligned Shi Xi compounds) (, lv) in (V) use Into heavily doped the exposed =) 'and

，區，因而形成P-S/D區。該p — C、/波成，同時提供高傳導電流與優良的漏損 ^之—步驟形 S/D區通常較該p —LLD區更重摻雜，級控制。該p- 此，該接合分解電壓較低且該p —S/D區之低私旦阻率。因於該_之漏損量電流。該來源/排出二And P-S / D regions. The p — C, / wave formation, while providing a high conduction current and excellent leakage loss — the step-shaped S / D region is usually more heavily doped than the p — LLD region, level control. The p-thus, the junction breakdown voltage is low and the low-density resistivity of the p-S / D region. Because of this leakage current. The Source / Exhaust II

548838 五、發明說明（17) =/排出電阻率，且調降該接合漏損量。因此，重要的是二儲存節點中此幻-型摻靡化物的形成 =案中，312區係被安排為最小的多晶矽閉極間隔，土絕緣側壁間隙3 2 5大小的兩倍。據此料，p_s/D相 :隹驟石夕化物有效地自312區被排除，而不需要處理少驟。 s _如第二圖F所述，薄閘極介電層3 〇 7係形成於該存取電極電_3之下，然而在另—實施例中—厚存閘極-;丨包層3 0 8八係形成於電容器結構31 3之下。第一圖A至第二圖£之該DRAM胞元可被相似地植入，其二的n_通道存取電晶體與電容器，以提供這些元；被位於n—摻雜基材中一p_摻雜槽或一一沬η-摻雜槽中。土〜 $著—3用邏輯製程流程，如第三圖G至第三圖R所二:卜型槽區3111係形成於卜型單晶珍基材3。10中。在所^述的例子中，基材3〇1〇具有之晶格相位為〈〗，〇,〇〉，且払雜濃度約為lXl〇16/cm3。N_槽3〇11其係植入，其推雜濃度約為lx〜。在：案：ί :貝：例中可以使用其他晶格相位與濃度。此外，不同區罢之傳導性形式可相反於其他實施例巾，而具有相果。在所述的實施例中，場介電層3022之形成係利用淺溝槽隔離（STU技術。在STI技術中，溝槽係被钮刻在碎基材 548838 五、發明說明U8) 3 0 1 0，且這些溝槽隨後被介電質填滿，如矽氧化物。結構之該上表面隨後藉由化學-機械膜光（CMp)而被平面化，因而場介電層3022之該上表面係相當於與11—槽3〇11之上平面共平面。在所描述的實施例中，該基材3 〇丨〇之該晶格結構造成溝槽側壁具有約8 0度之角度。緩衝氧化層3 0 2 1為保留自該STi處理步驟，或熱生成於該結構之上表面之上。在所描述的實施例中，氧化物層 3 0 2 1為石夕氧化物’其厚度為5至2 〇 n m。然而，此厚度可以隨所使用之製程而變化。執行非一般的製程步驟，其非包含於一習用的邏輯製程。，光阻光罩3023，其具有一開口 3024，且其係利用以之，，程技術形成於緩衝氧化物層3〇21之上。該開口3〇24係部分位於n—槽上，且部分位於場介電層3022之上。一如第一圖Η所示，透過光阻光罩3023之該開口3024進 1蝕刻，因而移除氧化物層3〇21之該暴露部分。該蝕刻也 =除％ η私層3〇22之一暴露部分，因而在場介電層3〇22中生一凹處3 0 2 5。在該蝕刻結束時，在凹處3〇25下場介電二之厚度T1知圍約為50至2〇〇nm。該1虫刻劑係高度選矽，因此n-型槽3011在蝕刻過程中未被大量移除。貫施例中，此蝕刻為定時的蝕刻。 :Ρ;Λ離田子植入。在一實施例中’彳植入劑量2χΐ〇ΐ3/』3 的能量為10-15 KeV。該p——型離子植入形成電。。£3 0 2 6。電容器區3〇26使得該臨限電壓於隨後形成的如第三圖I所示，透過光阻光罩30 2 3之開口 3 0 24進行 —'TtU *7 I 丄548838 V. Description of the invention (17) = / Release resistivity, and reduce the leakage of the joint. Therefore, what is important is the formation of this phantom-type dopant in the two storage nodes. In the case, the 312 region is arranged as the smallest polycrystalline silicon closed-electrode gap, and the size of the soil-insulating sidewall gap is 3 2 5 times. According to this data, the p_s / D phase: the lithocene compounds were effectively eliminated from the area 312 without the need for processing. s _ As described in the second figure F, a thin gate dielectric layer 307 is formed under the access electrode _3, but in another-embodiment-thick storage gate-; cladding 3 The 0 08 series is formed under the capacitor structure 31 3. The DRAM cells of the first picture A to the second picture can be similarly implanted, the second n-channel access transistor and capacitor to provide these cells; is located in an n-doped substrate a p _ Doped trenches or 沬 η-doped trenches. Soil ~ $ 着 -3 uses a logical process flow, as shown in Figures G through R in Figures III. 2: The Bu-shaped groove region 3111 is formed in Bu-shaped single crystal substrate 3.10. In the example described, the base material 3101 has a lattice phase of <〗, 〇, 〇>, and the doping concentration is about 1 × 10 16 / cm3. The N_slot 3011 was implanted, and its dopant concentration was about lx ~. In: Case: ί: Shellfish: Other lattice phases and concentrations can be used in the example. In addition, the conductive form of the different zones may be opposite to other embodiments and have effects. In the described embodiment, the formation of the field dielectric layer 3022 is performed using shallow trench isolation (STU technology. In the STI technology, the trench is engraved on the broken substrate 548838. V. Invention Description U8) 3 0 1 0, and these trenches are subsequently filled with a dielectric such as silicon oxide. The upper surface of the structure is then planarized by chemical-mechanical film light (CMp), so the upper surface of the field dielectric layer 3022 is equivalent to being coplanar with the plane above the 11-slot 301. In the described embodiment, the lattice structure of the substrate 300 causes the trench sidewalls to have an angle of about 80 degrees. The buffer oxide layer 3 0 2 1 is retained from the STi processing step, or heat is generated on the upper surface of the structure. In the described embodiment, the oxide layer 3 0 2 1 is a stone oxide 'and has a thickness of 5 to 200 nm. However, this thickness can vary depending on the process used. Perform non-trivial process steps, which are not included in a conventional logical process. The photoresist mask 3023 has an opening 3024, and it is formed on the buffer oxide layer 3021 using a process technique. The opening 3024 is partially located on the n-slot, and partially located on the field dielectric layer 3022. As shown in the first figure (1), the opening 3024 of the photoresist mask 3023 is etched, so that the exposed portion of the oxide layer 3021 is removed. This etching also removes one of the exposed portions of the% η private layer 3022, so a recess 3025 is formed in the field dielectric layer 3022. At the end of the etching, the thickness T1 of the field dielectric 2 in the recess 3025 is about 50 to 2000 nm. The 1 insecticide is highly selected from silicon, so the n-type groove 3011 is not removed in a large amount during the etching process. In the embodiments, this etching is a timed etching. : Ρ; Λ 离田子 implantation. In one embodiment, the energy of the '彳 implantation dose 2χΐ〇3 /' 3 is 10-15 KeV. The p-type ion implantation forms electricity. . £ 3 0 2 6. The capacitor region 3026 allows the threshold voltage to be formed later as shown in the third figure I through the opening 3 0 24 of the photoresist mask 30 2 3 —'TtU * 7 I 丄

548838 五、發明說明（19) 電容器更具建設性、，因而該電容器結構可更容易被活化。如第三圖J所述，光阻光罩3〇23與缓衝氧化物層MU 係被剝除的，且閘極介電層3〇3〇隨後形成於該結構㈢之該上表面，上。在所述的實施例中，閘極介電層3 0 3 0俜埶‘成，化物之上’其厚度範圍約紅5至5…：：生: 度可隨所使用之製程而改變。在所描述的實施^中，相^ ::二介電層3030係使用於存取電晶體與而在其他實施例中，可:吏= 層之該電容器介電層。…“ 的組合物，而哕介^彳成自鼠化矽或氧化矽與氮化矽製造外部記憶體陣列之相同的閘極；=， ;些邏輯電晶體之閘極介電層之不同厚二或自此觀點，該習用邏鍺制^ 構上之多…使用。陳基於該結 3〇'事^填充該凹處如;乾圍約為m至3QG。多晶石夕層548838 V. Description of the invention (19) The capacitor is more constructive, so the capacitor structure can be activated more easily. As shown in the third figure J, the photoresist mask 3023 and the buffer oxide layer MU are stripped off, and a gate dielectric layer 3030 is then formed on the upper surface of the structure. . In the described embodiment, the gate dielectric layer 3030 ′ is formed into a thickness of about 5 to 5 ... :: degree depending on the process used. In the described implementation, the phase ^ :: two dielectric layer 3030 is used to access the transistor and in other embodiments, the capacitor dielectric layer may be: … "Composition, and the dielectric layer is made of the same gate of the external memory array made of siliconized silicon or silicon oxide and silicon nitride; =,; the thickness of the gate dielectric layer of some logic transistors is different Second, or from this point of view, the conventional logic germanium structure is used as much as ... used. Chen based on the knot 30 '^ filled the recess such as; the dry circumference is about m to 3QG.

3 0 3 d ; : Ϊ扩：Ϊ阻光罩3°32係形成於多晶矽層義記憶胞元=得知’光阻光伽定所述，冬曰石々思> 極與電容器電極。如第三圖L 閘極電極係透過光阻光罩3 0 32蝕刻，因而形成 3〇31C。極電層二電容器電極多晶石夕部分口口电虽031B之—部分保留在凹處3〇25。藉由3 0 3 d;: Dilatation: Chirped photoresist mask 3 ° 32 is formed on polycrystalline silicon layer. Memory cell = Learned ‘Photoresistance light gading’ As described in Dong Shi Shi Si > electrode and capacitor electrode. As shown in the third figure L, the gate electrode is etched through the photoresist mask 3 0 32, thereby forming 3031C. Polyelectrolyte part of the capacitor electrode of the second electrode layer Although the power of the mouth is 031B-part remains in the recess 3025. By

第25頁 548838Page 548 838

五、發明說明（20) 形成電容器電極3 〇 3 1 B之部份於凹處3 〇 2 5之該側壁，電容的黾極3 〇〇 1 β與電谷裔區3 〇 2 6接合間之區域（亦即該電容器之該區域）被製造相對地大，然而，電容器電極3 〇 3丨Β之所需的對齊被製造相對地小。如第三圖Μ所述，光阻光罩3 〇 3 2被剝除，且執行ρ型離子植入在該結構上。因此，輕摻雜1)型汲極區3〇33與輕摻亦隹Ρ型源極區3 0 3 4係形成於η -槽3 0 1 1中。ρ —型源極區3 〇 3 4 連接該電容器區3 〇 2 6。此外，在此移植中多晶矽區3 〇 3 j Α 至303 1C接收ρ-型雜質。V. Description of the invention (20) The part of the capacitor electrode 3 〇3 1 B is formed on the side wall of the recess 305, the capacitor 黾 pole 3 〇β and the electric valley area 3 〇 2 6 The area (ie, the area of the capacitor) is made relatively large, however, the required alignment of the capacitor electrode 3 03B is made relatively small. As described in the third figure M, the photoresist mask 302 is removed, and p-type ion implantation is performed on the structure. Therefore, the lightly doped 1) -type drain region 3033 and the lightly doped YP-type source region 3 0 3 4 are formed in the n-channel 3 0 1 1. The p-type source region 3 0 3 4 is connected to the capacitor region 3 0 2 6. In addition, polycrystalline silicon regions 3 03 j A to 303 1C receive p-type impurities in this transplant.

如第三圖Ν所述，側壁間隙3 0 3 5係形成於該結構上。側壁間隙3 0 3 5之形成係利用習用製造程序。例如，側壁隔間3 0 3 5之形成可藉由沉積一氮化矽層於該結構上，而後利用習用製程技術執行一非等向性的蝕刻於該氮化矽層。在該飛等向性之蝕刻完成後，維持氮化矽間隔3 〇 3 5。As shown in the third figure N, a sidewall gap 3 0 3 5 is formed on the structure. The sidewall gap 3 0 3 5 is formed using a conventional manufacturing process. For example, the sidewall spacer 3035 can be formed by depositing a silicon nitride layer on the structure, and then performing a non-isotropic etching on the silicon nitride layer using conventional process technology. After the flying isotropic etching is completed, the silicon nitride interval is maintained at 305.

在氮化矽側壁間隙3 0 3 5形成之後，形成一 ρ +光阻光罩 (未顯示）以定義該晶片上所欲得到Ρ+區域之位置。而後進行一Ρ+型離子植入，因而形成Ρ+汲極區3〇36(如同該機直上其他所欲之Ρ+區域）。值得注意的是ρ +汲極區3〇36係依如第三圖Ν中最左邊側壁間隙3〇 35之邊緣對齊。該Ρ+型離子植入更摻雜多晶石夕區3 〇 3 1 Α至3 0 3 1 C。側壁間隙3 q 3 &避免 P +雜質植入至輕摻雜源極區3 0 34。隨意地，該p+光阻光罩 (未顯示）可包含一部分，其P+雜質植入至輕摻雜源極區 3 0 3 4。隨後進行一鍛燒熱循環，以活化該植入的雜質於 3033 ’3034 與3036 區。、After the silicon nitride sidewall gap 3 0 3 5 is formed, a ρ + photoresist mask (not shown) is formed to define the position of the desired P + region on the wafer. Then a P + type ion implantation is performed, thereby forming a P + drain region 3036 (as other P + regions desired by the machine directly). It is worth noting that the p + drain region 3036 is aligned with the edge of the leftmost sidewall gap 3035 in the third figure N. The P + -type ions are implanted with more doped polycrystalline regions 3030-1A to 3031C. The sidewall gap 3 q 3 & avoids implantation of P + impurities into the lightly doped source region 3 0 34. Optionally, the p + photoresist mask (not shown) may include a portion of which P + impurities are implanted into the lightly doped source region 3 0 3 4. A calcination heat cycle is then performed to activate the implanted impurities in regions 3033'3034 and 3036. ,

第26頁 548838 五、發明說明（21) ^請參/閱/三圖〇，一矽化物阻礙之介電層3 037 (例如矽乳化物）係沉積於該結構上。矽化物阻礙光阻 =電=上。形成圖案於光罩3〇38，以暴露Μ 極£ 3 0 3 6，閘極氣極層3 0 3 1 Α之一部分與多晶矽區3〇3κ之一部分。如第三圖P所述，介電層3 03 7係被蝕刻，以去除藉由光罩3 0 38所暴露的介電層3〇37之部份。更特別地，p + 汲極區3 0 3 6，多晶矽閘極電極層3〇31 a之左邊部分以及多晶矽區3 0 3 1 C之右邊部分p+汲極區3 〇 3 6係被暴露。如第三圖Q所述，光罩3038係被剝除，以及一耐火的金屬層3 0 3 9，例如鈦或鈷，係沉積於該結構上。在所描述的實施例中，鈦沉積之厚度約為3〇nm。而後進行鍛燒，因而形成耐火的金屬層3 〇 3 9以與下面的矽區域反應，而形成金屬矽化物區。在第三圖q中，唯矽區域下面的耐火的金屬層3039為P+>及極區3036，多晶矽閘極電極層3〇31a之左邊部分與多晶矽區3 0 3 1 C之右邊部分。如第三圖R所述，而後耐火的金屬層3039之未反應部刀被私除。金屬石夕化物區3041 ,3042與3043係形成於P+汲極區3 0 3 6之上’多晶石夕閘極電極層3 〇 3 1 A之左邊部分與多晶石夕區3 0 3 1 C之右邊部分。較佳為阻礙矽化物形成於該區’其中漏損量電流可被最小化，定義為源極區3〇 34與多晶石夕電容器電極3 〇 3 1 B。值得注意的是介電層3 〇 3 7避免矽化物形成於這些位置中。結果所得的DRAM胞元3000如第三圖R。DRAM胞元3000 之該存取電晶係位於3 0 5 1區，且DRAM胞元3 0 0 0之該電容器Page 26 548838 V. Description of the invention (21) ^ Please refer to / read / triple figure 0, a silicide hindered dielectric layer 3 037 (such as silicon emulsion) is deposited on the structure. Silicide hinders photoresistance = electricity = on. A pattern was formed on the photomask 3038 to expose a portion of the M pole £ 306, a portion of the gate gas layer 3301A, and a portion of the polycrystalline silicon region 3303. As shown in the third figure P, the dielectric layer 3 03 7 is etched to remove a portion of the dielectric layer 3037 exposed by the photomask 3 0 38. More specifically, the p + drain region 3 0 3 6, the left part of the polysilicon gate electrode layer 3031 a, and the right part of the poly silicon region 3 0 3 1 C are exposed. As shown in the third figure Q, the photomask 3038 is peeled off, and a refractory metal layer 3039, such as titanium or cobalt, is deposited on the structure. In the described embodiment, the titanium is deposited to a thickness of about 30 nm. Then, calcination is performed, thereby forming a refractory metal layer 309 to react with the underlying silicon region to form a metal silicide region. In the third figure q, the refractory metal layer 3039 under the silicon-only region is P + > and the polar region 3036, the left portion of the polycrystalline silicon gate electrode layer 3031a and the right portion of the polycrystalline silicon region 3 0 3 1 C. As shown in the third figure R, the unreacted portion of the refractory metal layer 3039 is then removed. The metal stone oxide regions 3041, 3042, and 3043 are formed on the P + drain region 3 0 3 6 'the polycrystalline stone gate electrode layer 3 〇3 1 A to the left and the polycrystalline stone region 3 0 3 1 The right part of C. It is preferable to prevent the formation of silicide in this region 'where the leakage current can be minimized, and it is defined as the source region 3034 and the polycrystalline silicon capacitor electrode 3301b. It is worth noting that the dielectric layer 307 prevents the formation of silicide in these locations. The resulting DRAM cell 3000 is shown in the third figure R. The access transistor of the DRAM cell 3000 is located in the region 305, and the capacitor of the DRAM cell 3000 is

第27頁 548838Page 548 838

結構係位於3 0 5 2區。由於該電容器結構形成於場氧化物中凹處3 0 2 5中，因此該電容器結構具有相對大的表面積。此相對大的表面積造成該電容器結構具有相對大的電容量。而，由於该電谷姦結構係部分形成於凹處3 2 &中，因此孩弘各器結構消耗相對小的對齊面積。有利地，dram胞元 3 0 0 0可藉由猶加修飾習用邏輯製程而製造。The structural system is located in zone 3052. Since the capacitor structure is formed in the recess 3025 in the field oxide, the capacitor structure has a relatively large surface area. This relatively large surface area causes the capacitor structure to have a relatively large capacitance. In addition, since the electric valley structure is formed in the recess 3 2 &, the Hiroko structure consumes a relatively small alignment area. Advantageously, the dram cell 3 0 0 0 can be manufactured by modifying the customary logic process.

第三圖S係DRAM胞元陣列之俯視圖，其包含⑽^胞元值彳亍注思的疋第二圖R所示約相當於第三圖s中所定義之A-A’區段。接觸器其提供一存取電晶體之排出與一位元線之間，其如第三圖s中包含x，s之盒子。因此，接觸哭 3 一0 5 0提供自對齊區30 3 6連接至位元線3〇5(未顯示，請^第二圖A)。接觸器3 0 5 0也提供位於一對稱])RAM胞元之該汲極區連接至DRAM胞元3000之左邊。在此方式中，一接觸器提供接觸至一陣列中之兩胞元。 ^ ;及極區3 〇 Μ與源極區3 〇 3 4係藉由閘極電極3 〇 3 1 Δ而分The third figure, S, is a top view of a DRAM cell array, which contains the cell values. Note that the second figure, R, is approximately equivalent to the A-A 'section defined in the third figure, s. The contactor is provided between the discharge of an access transistor and a bit line, which is a box containing x, s as shown in the third figure s. Therefore, the contact cry 3-0 50 provides a self-aligned area 30 3 6 connected to the bit line 3 05 (not shown, please ^ second picture A). The contactor 3 0 50 is also provided in a symmetrical]) The drain region of the RAM cell is connected to the left of the DRAM cell 3000. In this manner, a contactor provides contact to two cells in an array. ^; And the polar region 300 μM and the source region 300 4 are divided by the gate electrode 3 03 1 Δ

，。光罩3024之位置，其定義電容器區3026之邊界，如第三圖S所示。重線3 0 70，其具有一錘頭形狀，其定義凹處 3 0 2 5之側壁。凹處3 〇 2 5係位於錘頭形狀線3 〇 7 〇之外部，但於光罩3 〇 2 4所定義之邊界内。因此，位於錘頭形狀線哭2内側之電容器電極3 0 3 1 Β之部分係位於較高處。電容 =電極之面積係藉由線3 〇 7 〇所定義之該側壁上之延伸而最化。值得注意的是電容器電極3 〇 3丨Β可延伸至鄰近的胞元，如同第三圖s中所示。弟四圖Α至弟四圖j係根據本案另一實施例不同製造造. The position of the photomask 3024 defines the boundary of the capacitor region 3026, as shown in FIG. 3S. The heavy line 3 0 70 has a shape of a hammer head, which defines a side wall of the recess 3 0 2 5. The recess 3 0 2 5 is located outside the hammer head shape line 3 0 7 0, but within the boundary defined by the mask 3 0 2 4. Therefore, the part of the capacitor electrode 3 0 3 1 B located inside the hammer shape line 2 is located higher. Capacitance = The area of the electrode is optimized by the extension on the side wall as defined by line 3 07. It is worth noting that the capacitor electrode 3 03 3B can extend to adjacent cells, as shown in the third figure s. Figure 4A to Figure 4J are manufactured according to another embodiment of the present case.

548838 五、發明說明（23) 一~--〜一階段中，一DRAM胞元之橫切面。一般而言，DRM胞元4〇包合一電容為、链構，其具有—冠狀與平面結構，其形成係藉由兩外加的多晶矽層。此外加的多晶矽層係形成於丨、+與p + 久接合形成之刖，且係於矽化物形成之前。利用兩外加多晶矽層可使得-較小的電容器結構形成而得一較小的卯龍·· 胞元。548838 V. Description of the invention (23) 1 ~~~ In this stage, a cross section of a DRAM cell. Generally speaking, the DRM cell 40 includes a capacitor, a chain structure, which has a crown-shaped and a planar structure, and its formation is made by two additional polycrystalline silicon layers. The additional polycrystalline silicon layer is formed at the junction of +, + and p +, and is formed before silicide formation. The use of two additional polycrystalline silicon layers enables a smaller capacitor structure to be formed to obtain a smaller cell.

如第四圖A所示，一η-型槽區42係形成於一p—型單晶石夕石夕基材41中。在所描述的例子巾，基材41具有化〇, 〇〉之晶格相位，以及約lxl〇IS/cm3之摻雜濃度。卜槽42其係d 習用製程步驟所形成，例如離子植入，纟摻雜濃度約為 1^1 〇 /cm3。本案中之其他實施例可使用其他的晶格相位麥濃度。此外，不同區域的傳導形式可倒反於其他實施例且有相似的結果。 a 在所描述的貫施例中，場氧化物4 5之形成係利用淺溝槽隔離（STI)技術。在STI技術中，溝槽係被蝕刻於矽基材 41中，且這些溝槽而後係以氧化矽填充。該所得結構之上表面Ik後係藉由化學-機械破壞（p)而平面化，因而場氧化物45之该上表面大致係與n —槽42之該上表面共平面。而後閘極氧化物46係熱生成於所得結構之上表面之上二此多晶矽層隨後被圖案化以形成多晶矽閘極電極47。而後形成一p—型植入光罩（未顯示），且植入之二氟化硼 (BF2)的劑量約為lxl〇14/cm2且植入能量約為151(巧。值得注意的是硼的植入係根據多晶矽閘極電極47之邊緣自身對As shown in the fourth figure A, an η-type groove region 42 is formed in a p-type single crystal stone evening stone substrate 41. In the example towel described, the substrate 41 has a lattice phase of about 0.000, and a doping concentration of about 1 × 10 IS / cm3. The trench 42 is formed by a conventional process step, such as ion implantation, and the erbium doping concentration is about 1 ^ 10 / cm3. Other embodiments in this case may use other lattice phase wheat concentrations. In addition, the conduction patterns in different regions can be reversed to other embodiments with similar results. a In the described embodiment, the field oxide 45 is formed using shallow trench isolation (STI) technology. In the STI technology, trenches are etched into the silicon substrate 41, and these trenches are then filled with silicon oxide. The upper surface Ik of the resulting structure is planarized by chemical-mechanical destruction (p), so the upper surface of the field oxide 45 is substantially coplanar with the upper surface of the n-slot 42. The gate oxide 46 is then thermally generated on the upper surface of the resulting structure. The polycrystalline silicon layer is subsequently patterned to form a polycrystalline silicon gate electrode 47. Then a p-type implantation mask (not shown) was formed, and the implanted boron difluoride (BF2) dose was about 1 × 10 14 / cm2 and the implantation energy was about 151 (coincidentally. It is worth noting that boron The implantation is based on the edge of the polysilicon gate electrode 47 itself.

548838 五、發明說明（24) 如第四圖B听示，一知構之上。在所述的杏31化矽層48而後沉積於所得的結氮化矽48 yt产约成1中’利用習用製程技術所沉積的氧化物的薄層(〜20⑷於氮V:上的貫施例巾，提供-氧化精49而後被沉積； = : =下以降低壓力。-實施例中，氧切層49之；^夕層49之上。纟所描述的習用製程技術而形:。'又約為1 20 0⑽，且其係利用開口⑽。在所描；的實氧化物46形成一半晶約為2 5 0 nm之圓柱。在：：6 :圓筒狀，為具有他形狀與大小。開口6〇係被固開口6〇具有其一部份。 U疋以暴路出P-型源極區44之開口 60之產生係藉由形成一石夕層49之上，且透過該光阻(未顯示)於氧化定義出開口60之位置與形狀先罩中之—開口進行钱刻，其 50於：J : ί J :波：所二形成-傳導性的摻雜多晶石夕層 ^ %所付之結構上。在所描述之實形成係藉由沉積-多晶石夕層至厚度，，晶石夕層50之 50而後被傳導摻雜，其係藉由離 ^ 〇 nm。多晶矽層二論(bf2)，至該…。離另：植入，，型雜質’例如程中可被原位摻雜。多晶石夕層5。延伸至夕二夕在沉積過不之接觸P-型源極區44。汗〇中，且如所如第四圖C所示，所得之該結構在所描述之實施例中，利用—習用之之彳卜上@表面被平面化。白用之化學'•機械破壞（CMP) 548838 五、發明說明（25) =平面化步驟。—般而言，該平面化步驟移，，夕曰曰矽層50之該部分，其位沉積於該開口⑽中，如同，化矽層49之上部分。在進行平面化步驟之後，一租狀5 1保留於開口 6 〇中。多晶石$ gς — 曰曰 ^ ^ 甲夕日日矽訄狀51包含大致平面的基 =1A ’其接觸p_型源極區44(與場氧化物45)。多晶石夕 =狀51也包含垂直壁51B ’其係自基礎區5ia垂直向上延 =四圖D所示，而後利用一蝕刻劑移除氧化物層49，因移除氛化石夕更快。此钱刻步驟係定時的， 2而該蝕刻劑移除氧化矽層49而不移除氮化矽層4 描述的實施例中，此姓刻為丨禆绥俺斤548838 V. Description of the invention (24) As shown in the fourth picture B, one knows the structure. A thin layer of oxide (~ 20% on nitrogen V :) deposited on the aluminized silicon layer 48 and then deposited on the resulting silicon nitride nitride 48 yt yields about 1 'using conventional process technology. For example, provide-oxide fine 49 and then deposited; =: = down to reduce pressure.-In the embodiment, the oxygen cutting layer 49; ^ Xi layer 49 on top. 纟 Shaped by the conventional process technology: ' It is about 1 200 ⑽, and it uses open ⑽. In the depicted; the solid oxide 46 forms a half-crystal cylinder of about 2 50 nm. In: 6: cylindrical shape, with other shapes and sizes The opening 60 is a part of the fixed opening 60. U 疋 generates the opening 60 of the P-type source region 44 in a violent way by forming a stone layer 49 and transmitting the photoresist (Not shown) The position and shape of the opening 60 is defined by oxidation—the opening is engraved with money, which is 50: J: ί J: wave: the second formation-conductive doped polycrystalline stone layer ^ % Paid for the structure. In the described actual formation is by deposition-polycrystalline stone layer to thickness, 50 to 50 of the crystal stone layer is then conductively doped, which is by ionization ^ 〇nm. The second theory of polycrystalline silicon layer (bf2), to this ... From the other: implanted, type impurities can be doped in situ during the process. Polycrystalline layer 5. Extend to the second layer after deposition Do not touch the P-type source region 44. In Khan, and as shown in Figure 4C, the resulting structure is used in the described embodiment, which is used in the conventional practice. @ 表面被平面Chemicals used in white ”mechanical damage (CMP) 548838 V. Description of the invention (25) = Planarization step. Generally speaking, the planarization step shifts, the part of the silicon layer 50, its position Deposited in this opening, as if on the siliconized layer 49. After the planarization step, a rent 5 1 remains in the opening 6 0. Polycrystalline $ gς — ^ ^ ^ Evening sun silicon The ridge 51 includes a substantially planar base = 1A ', which contacts the p-type source region 44 (with field oxide 45). The polycrystalline stone ridge 51 also includes a vertical wall 51B', which extends vertically upward from the base region 5ia. = As shown in Figure D, and then using an etchant to remove the oxide layer 49, because the atmospheric fossils are removed faster. This money engraving step is timed, and the etching Agent is removed without removing the silicon oxide layer 49 of the fourth embodiment described silicon nitride layer, this moment is the name I Shubi Sui kg

酸。右气於二η 的，或不緩衝的氫I 辟υίΛ 被移除後’保留多晶秒冠狀51與垂直壁51Β升局於氮化石夕層48上。在所描述的實施例中，多曰直矽訄狀5J之該壁51Β延伸約8〇〇 nm於氮化矽層48上。曰曰在# t _所述，氧化物-氮化物—氧化物（_)結構52 弟一氣化碎層，一氮化碎層係=成=夕晶矽冠狀51之上。此〇N〇結構52之形成係以及一第二氧化矽沉積一 ^ #，· · - ^ 層。在所描述的實施例中’該第一氧化矽層之厚度 nm，該氮化矽層之厚度約為7 nm，以及該第二氧化矽層严度約為2 nm。這些層之沉積係利用已知之製程技術。‘：相對南的熱循環以形成不同的0N0結構52層。例如，需一總熱循環範圍為850 — 95(rc進行2〇_6〇分鐘，以形成^〇結構52。如同熟習該技藝之人士所了解，熱循環溫度與時間。為acid. After the right gas is removed from the two η or unbuffered hydrogen I, the remaining polycrystalline crown 51 and the vertical wall 51B are lifted on the nitrided layer 48. In the described embodiment, the wall 51B of the straight silicon wafer 5J extends approximately 800 nm on the silicon nitride layer 48. As stated in # t _, the oxide-nitride-oxide (_) structure 52 is a gasification fragmentation layer, and a nitride fragmentation system is equal to or above the crystalline silicon crown 51. The formation system of the OO structure 52 and a second silicon oxide deposit a ^ #, · ·-^ layer. In the described embodiment, the thickness of the first silicon oxide layer is nm, the thickness of the silicon nitride layer is about 7 nm, and the severity of the second silicon oxide layer is about 2 nm. These layers are deposited using known process techniques. ‘: Thermal cycling to the south to form different 52 layers of 0N0 structure. For example, a total thermal cycling range of 850-95 ° C is required for 20-60 minutes to form the ^ 〇 structure 52. As understood by those skilled in the art, the thermal cycle temperature and time are as follows:

548838 五、發明說明（26) 如第四圖F所示，多晶矽53之傳導摻雜層係形成於〇N〇結構5 2之上。在所描述的實施例中，多晶矽層5 3沉積之厚度約為1 5 0 nm。而後多晶矽層5 3之傳導摻雜係藉由離子植入一 P -型雜質，例如硼，至該多晶矽中。另一方面，多晶石夕層ο 3可在沉積過程中被原位摻雜。548838 V. Description of the invention (26) As shown in the fourth figure F, the conductive doped layer of polycrystalline silicon 53 is formed on the 0N0 structure 52. In the described embodiment, the polycrystalline silicon layer 53 is deposited to a thickness of about 150 nm. Then, the conductive doping of the polycrystalline silicon layer 53 is implanted with a P-type impurity, such as boron, into the polycrystalline silicon by ions. On the other hand, the polycrystalline stone layer ο 3 may be doped in-situ during the deposition process.

請參閱第四圖G，如圖所示一光阻光罩5 4係形成於多晶石夕層5 3之上。光阻光罩5 4係位於多晶矽冠狀5 1及緊鄰區域之上。如第四圖Η所示，進行一系列蝕刻以移除該多晶石夕層53與ΟΝΟ層52之暴露部分。多晶石夕層53之其餘部分形成一多晶矽板結構57。而後光阻光罩5 4被移除，且進行一熱循環以鍛燒多晶矽層5 1與5 3。在此步驟中，該熱循環典型使用快速熱鍛燒 (RTA)，於相當高的溫度95 0 — 1 0 5 0進行3〇_9〇秒。藉由在 Ρ+與Ν+淺皆接合形成與矽化物結構形成之前，進行這些高輒熱循環’有利的是這些高溫熱循環不會影響這些後續進行的製程。、Please refer to the fourth figure G. As shown in the figure, a photoresist mask 5 4 is formed on the polycrystalline silicon layer 5 3. The photoresist mask 5 4 is located above the polycrystalline silicon crown 51 and the immediate area. As shown in FIG. 4 (a), a series of etchings are performed to remove the exposed portions of the polycrystalline silicon layer 53 and the ONO layer 52. The rest of the polycrystalline slab layer 53 forms a polycrystalline silicon plate structure 57. Then, the photoresist mask 5 4 is removed, and a thermal cycle is performed to burn the polycrystalline silicon layers 5 1 and 5 3. In this step, the thermal cycle is typically performed using rapid thermal forging (RTA) at a relatively high temperature of 950-1050 for 30-30 seconds. By performing these high-temperature thermal cycles' before P + and N + are both formed by bonding and forming a silicide structure, it is advantageous that these high-temperature thermal cycles do not affect these subsequent processes. ,

如第四圖I所示，利用習用製程技術進行一非等向性蝕刻於氮化矽層48之上。在非等向性蝕刻完成後，保留氮化矽區48Α至48C。氮化矽區48Α形成一側壁間隙於多晶矽閘極47之一邊上。氮化矽區48Β形成—側壁間隙於多晶矽閑極47相對之一邊上。氮化矽區48Β延伸至多晶矽冠狀 1 ’ 0Ν0結構52與多晶矽板53所形成之該電容器結構。氮 ^夕區48C接合氮化石夕區48Β於第四圖！之平面外因而側向地環繞多晶矽冠狀5 1。As shown in the fourth figure I, an anisotropic etching is performed on the silicon nitride layer 48 using conventional process technology. After the anisotropic etching is completed, the silicon nitride regions 48A to 48C remain. The silicon nitride region 48A forms a sidewall gap on one side of the polysilicon gate 47. A silicon nitride region 48B is formed—the sidewall gap is on the opposite side of the polycrystalline silicon free electrode 47. The silicon nitride region 48B extends to the capacitor structure formed by the polycrystalline silicon crown-like 1 'ONO structure 52 and the polycrystalline silicon plate 53. The nitrogen ^ Xi region 48C is joined with the nitride stone Xi region 48B in the fourth picture! Out of the plane, it surrounds the polycrystalline silicon crown 5 1 laterally.

第32頁 548838 五、發明說明（27) 在氮化矽區48A至48C已被形成後，形成一P+光阻光罩 I禾顯示）以定義所欲之p +區域於該晶片上之位置。而後進行一P+型離子植入，因而形成淺P+汲極區55(如同該基材 i之其他所欲之P+區域）。值得注意的是P+汲極區55係隨 I侧壁間隙48A之邊緣對齊。在所描述的實施例中，該P + 離子植入之濃度為5xl015/cm2且能量小於15KeV。執行典型白勺一短鍛燒熱循環，利用RT A於85 0 -95 0 °C，進行10-15 秒。請見第四圖J，一耐火金屬層例如鈦或鈷，係覆蓋沉積於所得的結構上。在所描述的實施例中，所沉積的鈦厚度約為3 0 nm。而後進行一鍛燒步驟以形成鈦矽化物於鈦與石夕接觸之處。更特別地，鈦係反應於P+區域55，因而形成鈦矽化物區域5 6 A。鈦也反應於多晶矽閘極4 7，因而形成鈦矽化物區域5 6 B。最後，鈦反應於多晶矽板5 3，因而形成鈦矽化物區域56C。此鍛燒更進一步活化P+區域55中之P +離子。在所描述的實施例中，此熱循環之執行通常係利用RY A於8 5 0-9 5 0 °C進行10-30秒。值得注意的是在電容器結構形成的過程中（亦即85 0-9 5 0 °C進行2 0-6 0分鐘， 9 5 0 - 1 0 5 0 °C進行30-9 0秒）所進行的熱循環，係大於在淺汲極區55與金屬石夕化物區56A至56C形成的過程中（亦即850 -9 5 0 °C進行1 0 - 1 5分鐘，8 5 0 - 9 5 0 °C進行1 0 - 3 0秒））所進行的熱循環。根據本發明之一實施例，於在淺汲極區5 5與金屬矽化物區5 6 A至5 6 C形成的過程中所進行的熱循環，係可比車父的或小於在電谷器結構形成的過程中所進行的熱循Page 32 548838 V. Description of the invention (27) After the silicon nitride regions 48A to 48C have been formed, a P + photoresist mask (I (shown) is formed) to define the desired position of the p + region on the wafer. Then, a P + type ion implantation is performed, thereby forming a shallow P + drain region 55 (like other desired P + regions of the substrate i). It is worth noting that the P + drain region 55 is aligned with the edge of the I sidewall gap 48A. In the described embodiment, the concentration of the P + ion implantation is 5 × 1015 / cm 2 and the energy is less than 15 KeV. A typical short forging heat cycle was performed using RT A at 85 0-95 0 ° C for 10-15 seconds. See figure J. A refractory metal layer, such as titanium or cobalt, is deposited and deposited on the resulting structure. In the described embodiment, the thickness of the deposited titanium is about 30 nm. Then a calcination step is performed to form a titanium silicide where the titanium contacts the stone. More specifically, the titanium system reacts with the P + region 55, thereby forming a titanium silicide region 5 6 A. Titanium also reacts with polycrystalline silicon gates 4 7 and thus forms titanium silicide regions 5 6 B. Finally, titanium reacts with the polycrystalline silicon plate 5 3, thereby forming a titanium silicide region 56C. This calcination further activates the P + ions in the P + region 55. In the described embodiment, this thermal cycle is typically performed using RY A at 85-50 ° C for 10-30 seconds. It is worth noting that during the formation of the capacitor structure (that is, 85 0-9 5 0 ° C for 2 0-60 minutes, 9 5 0-1 0 5 0 ° C for 30-9 0 seconds) The thermal cycle is greater than that during the formation of the shallow drain region 55 and the metal oxide region 56A to 56C (that is, 850 -9 5 0 ° C for 1 0-1 5 minutes, 8 5 0-9 5 0 ° C for 10 to 30 seconds)). According to an embodiment of the present invention, the thermal cycle performed during the formation of the shallow drain region 55 and the metal silicide region 5 6 A to 5 6 C is comparable to that of the vehicle driver or smaller than that of the valley device. Thermal cycling

第33頁 548838 五、發明說明（28) 壞。而後進行一蝕刻，因而移除鈦層所有未反應的部分 (例如位於氮化矽區4 8 A至4 8 B與場氧化物4 5上之鈦層上）。所得之DRAM胞元40如第四圖J中所示。DRAM胞元40之存取笔as體’其係猎由〉及極區4 3與5 5，源極區4 4，咬化物區域5 6 A至5 6 B，氮化物間隔4 8 A至4 8 B，多晶矽閘電極4 7與 η-槽42而形成。 DRAM胞元40之該電容器結構係藉由多晶矽冠狀5 j， ΟΝΟ結構52，多晶矽板57與矽化物區域56C而形成。由於板 57延伸於壁51Β之内部與外部上，如同於基礎區域51Α上般，此電容器結構於多晶矽冠狀5丨與多晶矽板5 7之間具有一相當大的表面積。此相當大的表面積較成該電容器結構具有相當大的電容量。此外，由於該電容器結構係以垂直方式形成’因此該電容器佔據相當小的對齊面積。在一習用的邏輯製程中，形成優良的Ν+與？+淺接合與矽，物之能力預測，為在Ν+與Ρ+植入與矽化物沉積之後^ 有最小的熱循環。在Ν+與ρ+植入與矽化物形成之前，藉由形成電容器結構其典型地使用較高的熱循環，該外加^埶循環其係藉由電容器結構之形成而引入，對於電容器^ 製造的電晶體所造成的影響為最小。卜DRAM胞元40之偏壓係相同於DRAM胞元3 0 0 (第三圖Α至第三圖D)。因此，矽化物區域56Α係連接至位元線3 化物區域56Β係連接至自字元線3〇3，且η_槽42係連結於 vppl電壓供應終端。矽化物區域56C可被連接至^與、之間^Page 33 548838 V. Description of Invention (28) Bad. An etching is then performed to remove all unreacted portions of the titanium layer (for example, on the titanium layer on the silicon nitride regions 4 8 A to 4 8 B and the field oxide 45). The resulting DRAM cell 40 is shown in the fourth figure J. The access pen of the DRAM cell 40 is as follows: and the polar regions 4 3 and 5 5, the source region 4 4, the bite region 5 6 A to 5 6 B, and the nitride interval 4 8 A to 4 8 B, a polysilicon gate electrode 47 and an n-groove 42 are formed. The capacitor structure of the DRAM cell 40 is formed by a polycrystalline silicon crown 5 j, an ONO structure 52, a polycrystalline silicon plate 57 and a silicide region 56C. Since the plate 57 extends on the inside and the outside of the wall 51B, as in the base area 51A, the capacitor structure has a considerable surface area between the polycrystalline silicon crown 5 丨 and the polycrystalline silicon plate 57. This considerable surface area has a relatively large capacitance compared to the capacitor structure. In addition, since the capacitor structure is formed in a vertical manner, the capacitor occupies a relatively small alignment area. In a customary logic process, a good N + and? + Shallow junctions and silicon and physical capabilities are predicted to have minimal thermal cycling after N + and P + implantation and silicide deposition. Before N + and ρ + implantation and silicide formation, the capacitor structure typically uses a higher thermal cycle by forming the capacitor structure. The additional cycle is introduced by the formation of the capacitor structure. The effect of the transistor is minimal. The bias voltage of the DRAM cell 40 is the same as that of the DRAM cell 300 (the third figure A to the third figure D). Therefore, the silicide region 56A is connected to the bit line 3 and the silicide region 56B is connected to the self-word line 303, and the n-slot 42 is connected to the vppl voltage supply terminal. The silicide region 56C can be connected between ^ and, ^

548838 五、發明說明（29)548838 V. Description of Invention (29)

值得注說明不 DRAM 之任何電麗，以使得兮雨六口。,, 立& 3 Μ,0便计3亥电谷益結構之電容最大化思的疋η 槽4 2之連接#开彡# # $ 化按知形成於弟四圖J所示之外部弟四圖κ至弟四圖¥係根據本案之二:步Λ中—咖胞元4 0 0之橫切面。-般而言，一二—二容器結構’其之形成係較習用邏輯製程夕了兩個夕曰日石夕層。這此外力歸夕兮夕s仏日日卜加的多晶矽層係於該存取電晶肢之该夕日日石夕閘極電極形成之前形成。如弟四圖所示，一 η ~划描π 。 ^ _砂曰& β 1 生槽Ε域42與場氧化物45係形成於η-产早曰日石夕石夕基材中。這些元件已被詳細描述於第四圖 Α。在所描述的實施例巾，場氧化物託之深度範圍約為 250-4GG⑽。薄氧化物層4G1係熱生成於所得結構之上面 =mm施例中’薄氧化物層4 ，其厚度I』約為ho nm。然而此厚度 ^同而改變。氮化石夕層402係沉積於薄氧化物層4〇1之在所m氮化石夕層402其厚度範圍約為5〇_3〇〇。而後一光阻層403沉積於所得之結構上。光阻層4。3 ’因而產生開口 404。更詳細？所展開口 404定義-嵌壁式之館存區域，其將包含該隨斤胞元之一冠狀電極與一包埋的接觸區。如第四圖L所述，透過開口 404蝕刻氮氧化物層4〇1，因而移除這些層401_4〇2之暴露^分:該\ 刻亦移除該場乳化物層之暴露部分，因而於場產生一凹處4 0 5。在姓刻結束時，在凹處4 : 45之厚度抓其範圍約為5〇至_ nm。該㈣係 548838 五、發明說明（30) 岛矽，因而η-型槽42在該蝕刻過程中未被實質移除。在一實施例中，此蝕刻為定時的蝕刻。如第四圖Μ所述，光阻層4〇3被剝除，而多晶矽層4〇 6 之厚度範圍約為2 0至4 0 nm，其係沉積於所得結構之上。夕μ石夕層406延伸入凹處405，且接觸n-型石夕區域42之該暴露區。如第四圖Ν所述，進行一化學—機械破壞（CMp)破壞步驟，以移除位於氮化矽層402上之多晶矽層406之部分。因此，形成一嵌壁式冠狀電極40 6A。冠狀電極4 0 6A具有較低的基礎部分40 6L，其係沿著凹處4〇5底部，沿著凹處側壁延伸之側壁406S，以及延伸於該係基材42之上表面上之一上基礎部分40 6U。可在CMP製程進行之前或之後，摻雜與，燒多晶矽層40 6。在一實施例中，多晶矽層4〇6之摻雜係藉由植入一p-型雜質，例如硼，至該多晶矽。多晶矽層、 40 6而後進行rta(快速熱鍛燒）溫度為95〇 — 1 0 5 0 °c，進行 2 0 - 6 0秒。摻雜的多晶矽層4 〇 6之向外擴散於該鍛燒步驟發生’因而形成一p-型接觸區407於該η-槽42，其係緊鄰冠^ 狀電極4 0 6 Α。如第四圖0所述，氮化矽層之剩餘部分被剝除，且— 電谷裔介電層4 0 8係沉積於所得結構上。在所描述之實施例中，電容器介電層4 0 8係一氮化物層，其厚度範圍約為5 至8 nm。在沉積之後，介電層4〇8係被氧化且以總熱循環鍛燒’溫度範圍約8 0 0 - 9 0 0。〇進行2 0至6 0分鐘。一第二傳導摻雜多晶矽層40 9係沉積於介電層40 8上。在所描述之實It is worth noting that there is no electricity in DRAM, so that it rains six. 3, 0, 3 μ, 0 will be calculated as the maximum capacitance of the Haidian Guyi structure. 疋 η The connection of the slot 2 2 # 开彡 # # $ Huazhizhi is formed in the external brother shown in Figure 4J Four pictures κ to four pictures ¥ are according to the second part of the case: step Λzhong-cross section of coffee cell element 4 0 0. -Generally speaking, the one-two-two container structure is formed more than the conventional logic process. In addition, the polycrystalline silicon layer of the day after day is added before the day when the gate electrode of the access transistor is formed. As shown in Figure 4, one η ~ stroke π. ^ _Sands & β 1 raw trough E domain 42 and field oxide 45 are formed in the η-early-born Nishi-Shi-Xishi-Xi-Xi substrate. These elements have been described in detail in Figure 4A. In the described embodiment, the depth of the field oxide holder is about 250-4 GG⑽. The thin oxide layer 4G1 is thermally generated above the obtained structure = mm In the example, the 'thin oxide layer 4' has a thickness I 'of about ho nm. However, the thickness is the same. The nitrided oxide layer 402 is deposited on a thin oxide layer 401. The thickness of the nitrided oxide layer 402 is about 50-300. A photoresist layer 403 is then deposited on the resulting structure. The photoresist layer 4.3 'creates an opening 404. More detail ? The displayed opening 404 defines a wall-mounted storage area, which will contain a coronal electrode of the random cell and an embedded contact area. As shown in the fourth figure L, the oxynitride layer 401 is etched through the opening 404, so the exposure of these layers 401-402 is removed. This moment also removes the exposed portion of the field emulsion layer. The field produces a recess of 4 0 5. At the end of the last name engraving, the thickness in the recess 4: 45 is about 50 to _ nm. The actinide system 548838 V. Description of the invention (30) Island silicon, so the η-type groove 42 is not substantially removed during the etching process. In one embodiment, the etching is a timed etching. As shown in the fourth figure M, the photoresist layer 403 is stripped, and the polycrystalline silicon layer 406 has a thickness ranging from about 20 to 40 nm, which is deposited on the obtained structure. The Xishi Xixi layer 406 extends into the recess 405 and contacts the exposed area of the n-type Shixi area 42. As shown in FIG. 4N, a chemical-mechanical destruction (CMp) destruction step is performed to remove a portion of the polycrystalline silicon layer 406 on the silicon nitride layer 402. Therefore, a recessed-type crown electrode 40 6A is formed. The coronal electrode 4 0 6A has a lower base portion 40 6L, which extends along one of the upper surfaces of the substrate 42 along the side wall 406S along the bottom of the recess 405, along the side wall of the recess. Basic part 40 6U. The polycrystalline silicon layer 406 can be doped and burned before or after the CMP process is performed. In one embodiment, the polycrystalline silicon layer 406 is doped by implanting a p-type impurity, such as boron, to the polycrystalline silicon. The polycrystalline silicon layer was subjected to rta (rapid thermal forging) at a temperature of 950-1050 ° C for 20-60 seconds. The out-diffusion of the doped polycrystalline silicon layer 4 06 occurs in the calcination step, thereby forming a p-type contact region 407 in the n-groove 42, which is adjacent to the crown electrode 4 0 A. As shown in FIG. 4 of the fourth figure, the remaining portion of the silicon nitride layer is stripped off, and the dielectric layer 408 is deposited on the resulting structure. In the described embodiment, the capacitor dielectric layer 408 is a nitride layer and has a thickness in the range of about 5 to 8 nm. After deposition, the dielectric layer 408 is oxidized and calcined in a total thermal cycle temperature range of about 800-900. 〇 Perform for 20 to 60 minutes. A second conductively doped polycrystalline silicon layer 409 is deposited on the dielectric layer 408. In the described reality

548838 五、發明說明（31) 施例中，沉積、暴露與發展一光阻層，因而形成光阻光罩 4 1 0。該上多晶石夕層4 〇 9與介電層4 〇 8係透過此光罩4 1 〇而被怎虫刻，因而形成板電極4〇9A與電容器介電408A。如第四圖Q所述，光阻光罩4丨〇被剝除，而後移除薄氧化物層410。同時，繼續標準的邏輯製程步驟。因此，一閘極介電層411之生成係藉由熱氧化該暴露的矽表面。值付注意的是介電層41 1係延伸於冠狀電極4〇6A與板電極 40 9A之暴露衣面上。一傳導摻雜多晶矽閘極電極412之厚度範圍約為1 0 0至2 5 0 nm，係形成於閘極介電層4丨i上。而後進行一P-型離子植入步驟，因而各自形成輕摻雜排出與源極區41 3與41 4。如第四圖R所述’側壁間隙415與416之形成係利用習用邏輯製程步驟。在形成側壁間隙41 5與41 6的過程中，閘極介電層411係自未被閘極電極412與間隔4i5_4i6保護之位置移除。進行-p+型離子植入，因而各自形成重摻雜排極區417與418。值得注意的是輕摻雜源極區414與重払雜源極區4 18係連續以接觸區4〇7包埋。因此，該電晶體之來源係電性耦合至冠狀電極4〇6人。 μ 在另-實施例中，在該ρ+型離子植入的過程中區414被阻塞，因而未形成ρ+型區418。在此每得結構之該接合分解電壓得到改蓋。貝β例中，所548838 V. Description of the invention (31) In the embodiment, a photoresist layer is deposited, exposed, and developed, thereby forming a photoresist mask 4 1 0. The upper polycrystalline silicon layer 409 and the dielectric layer 408 are engraved through the photomask 4 1 0, thereby forming a plate electrode 409A and a capacitor dielectric 408A. As shown in the fourth figure Q, the photoresist mask 4 is removed, and then the thin oxide layer 410 is removed. At the same time, the standard logical process steps continue. Therefore, a gate dielectric layer 411 is formed by thermally oxidizing the exposed silicon surface. It is worth noting that the dielectric layer 41 1 extends on the exposed garment surfaces of the crown electrode 406A and the plate electrode 40 9A. A conductively doped polysilicon gate electrode 412 has a thickness ranging from about 100 to 250 nm and is formed on the gate dielectric layer 4i. Then, a P-type ion implantation step is performed, thereby forming lightly doped drain and source regions 413 and 414, respectively. The formation of the 'side wall gaps 415 and 416 as described in the fourth figure R uses conventional logic process steps. In the process of forming the side wall gaps 41 5 and 4 16, the gate dielectric layer 411 is removed from a position not protected by the gate electrode 412 and the interval 4i5_4i6. The -p + type ion implantation is performed, and thus heavily doped drain regions 417 and 418 are formed. It is worth noting that the lightly doped source region 414 and the heavily doped source region 418 are continuously embedded with the contact region 407. Therefore, the source of the transistor is electrically coupled to the coronal electrode 406. In another embodiment, the region 414 is blocked during the p + -type ion implantation, and thus the p + -type region 418 is not formed. The junction decomposition voltage of each structure is changed here. In the beta case, all

爹裎中以不间的氺伽1 °因為在一標準的CMOS 衣私中以不同的先阻光罩，分別形成p + 加光罩步驟以阻塞卜型區414。、料移植，不而外而後沉積一介電層419(例如氧化石夕）於所得結構上。 548838In the standard case, the temperature is 1 °, because in a standard CMOS clothing, different pre-blocking masks are used to form p + mask steps to block the b-shaped region 414. After the material is transplanted, a dielectric layer 419 (such as oxidized stone) is deposited on the resulting structure. 548838

介·：二四則所3 ’形、成-矽化物阻塞之光阻光罩420於 .7 ! 上。光罩42 0被圖案化以暴露P+型汲極區41 7與朵】：極4 1 2之，伤。而後介電層4 1 9被儀刻，因而移除 1罩42 0所暴露介電層419之部分。更特別地，“汲極區與多晶石夕間極412之左邊部分被暴露。矽化物阻塞之光且、> 罩420係典型使用於標轉邏輯製程，以阻塞不需要矽化物之區域，例如I/O緩衝與電阻器。因此，光罩42〇非標準邏輯製程中之外加光罩。··: The 2′-type, 3′-shaped, silicide-blocked photoresist mask 420 is on .7 !. The photomask 42 0 is patterned to expose the P + -type drain region 41 7 and】]: the pole 4 1 2 is injured. Then, the dielectric layer 419 is engraved, so the part of the dielectric layer 419 exposed by the cover 420 is removed. More specifically, "the left part of the drain region and the polycrystalline silicon pole 412 is exposed. Silicide blocks light and the mask 420 is typically used in standard logic processes to block areas that do not require silicide. For example, I / O buffers and resistors. Therefore, the photomask 42 is added to the non-standard logic process.

如第四圖T所述，光罩420被剝除，且沉積一耐熱金屬層4 2 1於所得結構上。而後進行一鍛燒，因而造成該耐熱金屬層42 1與其下之矽區域反應，以形成金屬矽化物區# 域。在第四圖T中，耐熱金屬層421下之.唯一矽區域為該p + >及極區41 7與多晶石夕閘極電極41 2之左邊部分。As shown in the fourth figure T, the photomask 420 is peeled off, and a heat-resistant metal layer 4 2 1 is deposited on the resulting structure. Then, a calcination is performed, thereby causing the heat-resistant metal layer 421 to react with the silicon region below it to form a metal silicide region. In the fourth figure T, the only silicon region under the heat-resistant metal layer 421 is the left portion of the p + > and pole region 4 17 and the polycrystalline silicon gate electrode 41 2.

如第四圖U所示，形成金屬矽化物區422與423於該p + 汲極區41 7與多晶石夕閘極電極41 2之左邊部分。耐熱金屬層 4 2 1之未反應部分而後被移除，如同第四圖v所示。值得注意的是金屬矽化物區423係至少部分形成於閘極電極422 上。較佳為阻塞矽化物形成於區域，其中漏損量電流鶯被最小化，稱為源極區41 8，冠狀電極40 6A與板電極40 9A。值得注意的是介電層419避免矽化物形成於冠狀電極40 6A 或板電極40 9A上。兩外加光罩403與410，以及兩外加多晶石夕層406與409 被使用以形成一具有大的三維表面積之電容器，且為具有較小的物理維之較高電容。關係電容器形成之溫度循環不As shown in the fourth figure U, metal silicide regions 422 and 423 are formed on the left side of the p + drain region 4 17 and the polycrystalline silicon gate electrode 41 2. The unreacted portion of the heat-resistant metal layer 4 2 1 is then removed, as shown in the fourth figure v. It should be noted that the metal silicide region 423 is formed at least partially on the gate electrode 422. It is preferable that the blocking silicide is formed in a region in which the leakage current is minimized and is called a source region 41 8, a crown electrode 40 6A and a plate electrode 40 9A. It is worth noting that the dielectric layer 419 prevents silicide from being formed on the crown electrode 40 6A or the plate electrode 40 9A. Two additional photomasks 403 and 410, and two additional polycrystalline silicon layers 406 and 409 are used to form a capacitor having a large three-dimensional surface area and having a relatively high capacitance with a small physical dimension. The temperature cycle of the capacitor is not related

第38頁 548838Page 548 838

f f , f的N+與p+淺接合與碎化物形成。此外，較佳為保遽说電谷器之内部節點，且對於減少的漏損量電流而言，貝貝上然石夕化物之形成。汝第四圖W所述，說明根據本案之一實施例中記憶胞元4 0 0之對齊。提供一存取電晶體之排出與一位元線之間接觸之接觸器，其係如第四圖W中含有X，s之盒子所示。因此’接觸器430提供將DRAM胞元40 0之汲極區41 7連接至位兀線3 0 5 (未顯示，請見第三圖A)。接觸器430也提供連接將一對稱胞元之該汲極區至位於DRAM胞元4〇〇之左邊。在此方式中，一接觸器提供一陣列中兩DRAM胞元之連接。位元線3 0 5沿著第四圖W中的水平軸延伸，因此位元線 3 0 5係連接至接觸器4 3 〇與4 3 1。其他位元線係以此相似方式輕合於DRAM胞元之其他部分。第四圖W中，該DRAM胞元陣列之結構，使得鄰近列中之某些鄰近的DRAM胞元，與其他五個DRAM胞元共用板電極 4 0 9 A。板電極4 〇 9 A沿著第四圖W之垂直軸延伸，且平行於位元線（例如閘極4 1 2 )。鄰近胞元之電容器係透過場氧化物（F Ο X)區4 5而電性連接，例如一所設計的規則之最小間隔。板電極40 9A之偏壓為vbbl以使得該電容器之最大活化。如第四圖X所述，說明本案之贈一實施例中記憶胞元 4 0 〇之對齊。第四圖X之對齊係相似於第四圖w之對齊。然而’第四圖X中之板電極4 〇 9 A，包含一系列的凹口，以使得該存取電晶體之冠狀電極4〇 6A與來源41 8之間具有較好的電性連接。The f +, fN + and p + shallow junctions and fragmentation are formed. In addition, it is preferable to protect the internal nodes of the electric valley device, and for the reduction of the leakage current, the formation of lithium oxide on the babe. The fourth figure W illustrates the alignment of the memory cell 400 according to an embodiment of the present invention. A contactor is provided for contact between the discharge of the access transistor and a bit line, as shown in the box containing X, s in the fourth figure W. Therefore, the 'contactor 430 provides a connection of the drain region 41 7 of the DRAM cell 40 0 to the bit line 3 0 5 (not shown, see the third figure A). The contactor 430 also provides a connection from the drain region of a symmetrical cell to the left of the DRAM cell 400. In this way, a contactor provides the connection of two DRAM cells in an array. The bit line 3 0 5 extends along the horizontal axis in the fourth figure W, so the bit line 3 0 5 is connected to the contactors 4 3 0 and 4 3 1. The other bit lines are similar to other parts of the DRAM cell in a similar way. In the fourth figure W, the structure of the DRAM cell array is such that some adjacent DRAM cells in adjacent columns share the plate electrode 409 A with the other five DRAM cells. The plate electrode 4 0 9 A extends along the vertical axis of the fourth figure W and is parallel to the bit line (for example, the gate electrode 4 1 2). Capacitors adjacent to the cell are electrically connected through the field oxide (F 0 X) region 45, such as a designed minimum interval. The plate electrode 409A is biased at vbbl to maximize the activation of the capacitor. As shown in the fourth figure X, the alignment of the memory cells 4 0 0 in one embodiment of the present case is illustrated. The alignment of the fourth figure X is similar to the alignment of the fourth figure w. However, the plate electrode 409 A in the fourth figure X includes a series of notches so that the crown electrode 406A of the access transistor and the source 418 have a good electrical connection.

第39頁 548838 __— —_ 五、發明說明（34) 在另一實施例:’可利用一單一多晶矽層，以產生該記憶胞元之該閘極電極與該板電極。此一實施例係如第四圖Y-第四圖Z所述。如第四圖Y戶斤示，形成一光阻光罩43Q於介電層408之上（於沉積板電極之前）。光阻光罩43 0覆蓋冠狀電極 4 0 6 A。而後進行/蝕刻以移除介電層4 〇 8與薄氧化物層4 0 1 之暴露部分。在蝕刻結束時，形成該存取電晶體之^型區域4 2之該部分係被暴露。而後光罩4 3 〇被剝除。如第四圖Z所示，而後藉由熱氧化形成閘極介電層 431。此熱氧化實質上不影響電容器介電層4〇8，其材質為氮化矽。而後沉積一多晶矽層4 3 2於所得結構上。 ,如第四圖AA所示，多晶矽層43 2被圖案化且蝕刻，以形成该閘極電極432A與電容器板電極432B。後續的製程如第四圖Q至第四圖V所示。此實施例之優點為製程簡單化，其僅較習用製程多一外加光罩步驟。由於係自相同的多晶石夕層圖案化’因此板電極與閘極電極（字元線）間之交換具較大間隔。Page 39 548838 __ — — — V. Description of the invention (34) In another embodiment: ’a single polycrystalline silicon layer may be used to generate the gate electrode and the plate electrode of the memory cell. This embodiment is described in the fourth figure Y-fourth figure Z. As shown in the fourth figure, a photoresist mask 43Q is formed on the dielectric layer 408 (before the plate electrode is deposited). The photoresist mask 43 0 covers the crown electrode 406 A. It is then performed / etched to remove the exposed portions of the dielectric layer 408 and the thin oxide layer 401. At the end of the etching, the portion forming the ^ -type region 42 of the access transistor is exposed. Then the mask 4 3 0 is removed. As shown in the fourth figure Z, the gate dielectric layer 431 is then formed by thermal oxidation. This thermal oxidation does not substantially affect the capacitor dielectric layer 408, which is made of silicon nitride. A polycrystalline silicon layer 4 3 2 is then deposited on the resulting structure. As shown in the fourth diagram AA, the polycrystalline silicon layer 432 is patterned and etched to form the gate electrode 432A and the capacitor plate electrode 432B. Subsequent processes are shown in Figures Q through V. The advantage of this embodiment is the simplification of the manufacturing process, which is only one additional mask step than the conventional manufacturing process. Because it is patterned from the same polycrystalline stone layer, the exchange between the plate electrode and the gate electrode (character line) is relatively large.

第五圖係字元線驅動器5 0 0之示意圖，根據本案之一貝施例其可用於驅動字元線3 0 3 (第三圖A)，字元線47 (第四圖J)+、’、字元線412(第四圖V)或字元線432A(第四圖AA)。 f =描述的貫施例中，字元線驅動器5 0 0所供應之輸出電 f ^被提供至字元線3 〇 3 (第三圖A)。字元線驅動器5 0 0包含一P— $逼電晶體5(Π-5 0 2與η-通道電晶體5 0 3 -5 0 5。為了去活化字疋線3〇3，電晶體501被活化，因而將字元線303The fifth diagram is a schematic diagram of the word line driver 500. According to one example of the present case, it can be used to drive the word line 3 03 (third picture A), the word line 47 (fourth picture J) +, ', Character line 412 (fourth figure V) or character line 432A (fourth figure AA). f = In the described embodiment, the output power f ^ supplied by the word line driver 500 is supplied to the word line 3 03 (third figure A). The word line driver 5 0 0 includes a P- $ force transistor 5 (Π-5 0 2 and η-channel transistor 5 0 3-5 0 5. In order to deactivate the word line 3 03, the transistor 501 is Activated, so the character line 303

第40頁 548838 五、發明說明（35) 向工拉升至正極并古々々給兩高足以關Μ户π ,问卞線笔⑽。該VCCB字元線電壓之问疋以辦]閉吞取電晶體3〇1。低電晶體503，因，化你——了化子兀線3〇3，開始拉元線電壓產生之二V二疋線303至該Vssb電壓。該U字二〜汗、細描述如下。之間：疋ί Ϊ : ΐ f f:01之間極與字元線降低電晶體503 托。舍兩日、/、冋义接至由p—通道電晶體5 02形成之通過閘 ^一田包日日體5〇2被開啟時，耦合電晶體5〇1與5〇2，以接 JUS::"551。提供之一輸出訊號Xi。電晶體502之閘極釦a如接收列位址解碼器51〇提供之另一輸Page 40 548838 V. Description of the invention (35) Raise the anode to the positive pole and give the two high enough to close the household π, ask the line pen. The VCCB word line voltage does not matter] to close the transistor 301. The low-voltage crystal 503, because of you, has changed the ziwu line 303, and started to pull the second voltage 303 to the Vssb voltage. The U-shaped two Khan, detailed description is as follows. Between: 疋 ί Ϊ: ΐ f f: 01 between the pole and the word line lower the transistor 503 Torr. After two days, /, Yi Yi was connected to the pass gate formed by the p-channel transistor 502. When the Yata package sun body 502 was turned on, the transistors 501 and 502 were coupled to connect to JUS. :: " 551. Provide one of the output signals Xi. The gate buckle of the transistor 502 is the same as that provided by the receiving column address decoder 51.

Xj#田連接至字兀線3 0 3之該記憶胞元係選擇於存取^夺，列位址解碼器51〇首先驅動該訊號^為高，而後驅動訊麥 X〆為低。該Xj#訊號之低狀態活化通過電晶體5〇2，其提u 該邏輯高\訊號至該升高與降低電晶體5〇1與5〇3之閑、極八在這些情形下，降低電晶體5 0 3被開啟，因而耦合f元綠 3 0 3以接收該VSSB字元線電壓。、、' 更詳細之說明如下，列位址解碼器5丨〇控制一第一元線組’其包含子元線3 0 3與一複數之其他字元線。—^ 元線3 0 3未被選擇於存取（但是其他在該第一位元線組在子另一字元線被選擇為存取）時，則該列位址解碼器5=:= 邏輯低值於訊號Χι與訊號Xj #。在這些條件下，兮1 _ '、低電晶體501與5 0 3之閘極係藉由η-通道電晶體5〇4維持、、1牛邏輯低狀態。因此，當字元線3 0 3未被存取時，電晶體於被開啟，因而耦合該電晶體501與5 3 0之閘極5 _ 5〇4 王邊V $ ς供靡+ 壓。該VSSB字元線電壓開啟上升電晶體501且關閉降低電曰电The memory cell of Xj # field connected to the word line 3 03 is selected for access. The column address decoder 51 first drives the signal ^ high, and then drives the signal mic X〆 low. The low state of the Xj # signal is activated by transistor 502, which raises the logic high \ signal to the rise and fall of transistor 501 and 503. In these cases, the voltage is reduced. The crystal 503 is turned on, so the f-ary green 303 is coupled to receive the VSSB word line voltage. A more detailed description is as follows. The column address decoder 5 controls a first meta line group, which includes a sub meta line 3 03 and a plurality of other character lines. — ^ Element line 3 0 3 is not selected for access (but the other bit line is selected for access in the other word line), then the column address decoder 5 =: = The logic low is the signal Xι and the signal Xj #. Under these conditions, the gates of the low-voltage transistor 501 and 503 are maintained by the n-channel transistor 504, a logic low state. Therefore, when the word line 303 is not accessed, the transistor is turned on, and thus the transistor 501 and the gate 5_504 of the transistor 503 are coupled to each other. The VSSB word line voltage turns on the rising transistor 501 and turns off to reduce the voltage.

第41頁 548838 五、發明說明（36) 體5 0 3 ’因而維持-邏輯高電壓（亦即^)於字元線3〇3。、在資料保留狀態過程中（亦即當該第一位元線組中無被存取的字兀線），、該列位址解螞器51〇驅動該訊號為高，因而開啟η-通這電晶體5〇5。開啟的電晶體5〇5耦合至該上升與降低電晶體501與5 0 3之閘極至該Vss供應電壓。因此，上升電晶體501被開啟而降低電晶體5〇3被關閉。同時，電晶體501耦合字元線3 0 3以接收該丨⑶電壓，因而關閉纪憶胞兀3 0 0之存取電晶體3〇1 (或記憶胞元4〇或4〇〇之該存取電晶體）。選擇一降低電晶體5 〇 3作為一 n _通道電晶體，以加速字兀線30 3之活化。然而，在此實施例中，所有n—通道電晶體組塊之形成被連接以接收該供應電壓。（請見第三圖B，其說明耦合p—型基材3〇6以接收該該供應電壓）。因此’該VSSB供應電壓之最小值係侷限於該V%供應電壓下之一二極體電壓降（亦即一二極體電壓降下接地）。甚者，記憶胞凡之每一列具有一相連之字元線驅動器。在一包埋的 €憶體中’通常記憶胞元有很多列（例如大於丨〇〇 )。因此大量的字元線驅動器，該基材與該η-通道降低電晶體（如降低電晶體5 0 3 )之該來源間之反接合為相當大量的。當該 vs別控制電壓變得更加負值時，該反接合漏損量係呈指數地 _ 增加。為了限制該反接合漏損量，該字元線驅動器被分為幾群32 ’且每一群係耦合至一耦合電路7〇〇之一共用。 · 因此’該包埋的記憶體系被分割至3 2列，如同相比於標準 -DRAM製程中之每一堆1 28至5 1 2列。此優點為由於習用製程Page 41 548838 V. Description of the invention (36) The body 5 0 3 ′ is thus maintained-the logic high voltage (ie ^) is on the word line 3 03. During the data retention state (that is, when there is no word line being accessed in the first bit line group), the column address solver 51 drives the signal to be high, so the η-pass is turned on. This transistor is 505. The turned-on transistor 505 is coupled to the rising and lowering transistors 501 and 503 to the Vss supply voltage. Therefore, the rising transistor 501 is turned on and the lower transistor 503 is turned off. At the same time, the transistor 501 is coupled to the word line 3 03 to receive the CD voltage, so the access transistor 3 0 (or the memory cell 40 or 400) of the memory cell 300 is turned off. Take the transistor). A reduction transistor 503 is selected as an n_channel transistor to accelerate the activation of the word line 303. However, in this embodiment, the formation of all n-channel transistor blocks is connected to receive the supply voltage. (See the third figure B, which illustrates coupling the p-type substrate 306 to receive the supply voltage). Therefore, the minimum value of the VSSB supply voltage is limited to a diode voltage drop (ie, a diode voltage drop to ground) at the V% supply voltage. Furthermore, remember that each column of the cell fan has a connected word line driver. In a buried € memory body, there are usually many columns of memory cells (for example, greater than 丨 00). Therefore, a large number of word line drivers, the anti-junction between the substrate and the source of the n-channel reduced transistor (eg, reduced transistor 50 3) are quite large. When the vs. control voltage becomes more negative, the amount of anti-joint leakage increases exponentially. In order to limit the amount of anti-junction leakage, the word line driver is divided into groups 32 'and each group is coupled to one of the coupling circuits 700. · Therefore, the embedded memory system is divided into 32 columns, as compared to 128 to 5 12 columns per stack in a standard-DRAM process. This advantage is due to customary processes

第42頁 548838 五、發明說明（37) 中所製造之DRAM胞元，具有胞元電容器，其需為非常的小 (例如3至1 0 femto-Farads)，其係小於習用製程中所製造〜DRAM胞元之胞元電容器（例如20至40 femto-Farads)，以保持小的DR AM胞元大小。在記憶體感應運作過程中，較小堆成比例地降低寄生物或雜訊。在一實施例中，每一堆包含64或較少列。在另一實施例中，每一堆包含32或更少列。值得注意的是這些實施例可能包含一個或多個外加的多餘列。Page 42 548838 5. The DRAM cell manufactured in the description of the invention (37) has a cell capacitor, which needs to be very small (for example, 3 to 10 femto-Farads), which is smaller than that manufactured in the conventional process ~ Cell capacitors (for example, 20 to 40 femto-Farads) of DRAM cells to keep the DR AM cell size small. Smaller heaps reduce parasitics or noise proportionally during memory sensing operation. In one embodiment, each stack contains 64 or fewer columns. In another embodiment, each stack contains 32 or fewer columns. It is worth noting that these embodiments may contain one or more extra columns.

第六圖係一方塊圖，其說明一字元線驅動器系統 6 0 0 ’其係包含一第一複數個字元線驅動器5 〇〇，一第二複數個VSSBI馬合電路70 0，一 VCCB電壓產生器8〇〇與一 Vbbs電壓產生器9 0 0 °每一個vssb耦合電路7 0 0係耦合至一相對的3 2群之子元線驅動器5 〇〇。更詳細之說明如下，當一群中之一字凡線被開啟時，該對應的VSSB耦合電路7 〇〇受控制以耦合該 vbbs電壓產生器9 0 0至對應群3 2之字元線驅動器。因此，該 vSSB竊合電路搜尋如同該Vssb電壓之該Vbbs電壓產生器9〇〇所產生之，負極的升高電壓VBBS。更詳細之說明如下，VBBS電壓產生為9 0 0產生一 vBBs電壓，其值於小於該L供應電壓下之一臨限電壓（VtP)。因而該VBBS電壓係大於該Vss供應電壓減掉一二極體電壓降。當一堆中無字元線被活化時，該對應的vSSB搞^電路700受控制以耦合該L供應電壓至該對應的群32之子凡線驅動器。即該耦合電路7〇〇搜尋如同該Vssb 電壓之該Vss供應電壓。由於僅該字元線驅動器5 0 0組係被耦合以於任何時間The sixth diagram is a block diagram illustrating a word line driver system 600 ', which includes a first plurality of word line drivers 500, a second plurality of VSSBI horse circuit 700, and a VCCB. The voltage generator 800 and a Vbbs voltage generator 900 ° each of the vssb coupling circuits 700 are coupled to a relative 32-element sub-line driver 500. A more detailed explanation is as follows. When one of the word lines in a group is turned on, the corresponding VSSB coupling circuit 70 is controlled to couple the vbbs voltage generator 900 to the word line driver of the corresponding group 32. Therefore, the vSSB stealing circuit searches for the boosted voltage VBBS of the negative electrode as generated by the Vbbs voltage generator 900 of the Vssb voltage. A more detailed explanation is as follows. The VBBS voltage is generated as 900 to generate a vBBs voltage, which is less than a threshold voltage (VtP) below the L supply voltage. Therefore, the VBBS voltage is greater than the Vss supply voltage minus a diode voltage drop. When no word line is activated in a bunch, the corresponding vSSB circuit 700 is controlled to couple the L supply voltage to the corresponding line driver of the corresponding group 32. That is, the coupling circuit 700 searches for the Vss supply voltage as the Vssb voltage. Since only the word line driver 5 0 system is coupled at any time

548838548838

接收該VBBS電壓，該反接合漏損量係被大量降低。甚者，藉由限制該VBBS電壓至一小於該Vss供應電壓下之一臨限電壓: 该反接合漏損量更加被降低。五、發明說明（38) 第七圖係根據本案之一實施例之示意圖，說明Vssb耗合電路70 0。VSSB耦合電路70 0包含p-通道電晶體7〇1_7〇S3SB, 通道電晶體704與反用換流器71卜714。ρ-通道電晶體7’〇Υ 係連接於vSSB與vBBS電壓供應線。電晶體701之閘極係耦入至節點N2。電晶體702係連接於節點”與\以電壓供應線之= 間。p-通道電晶體70 3係連接如一電容器，與其來源與排出共同連接至節點N1，且其閘極連接至節點N2。卜通道電晶體704係連接於該VSSB電壓供應線與該&電壓供應終間。電晶體704之該閘極係連接至節點^。反用換^流器 711:714係呈連續連接，且反用換流器711係自該列位址解二該訊號Μ，反用換流器714提供該延遲的訊號程第八圖係一波形圖，其說明在'Μ耦合電路7〇〇運作中所產生之不同的訊號。在活化字兀線30 3之前’該訊號\係低的，而訊號乂 # 的。在這些條件下，反用換流器711_714鏈提供一邏 ^訊號至節點N1，因而開啟n一通道電晶體m。因此， 5亥VSSB電壓供應線係維持於該&供應電壓（〇電壓）。同樣 :’在活化字元線30 3之前’電晶體7〇2之次臨限漏損 :該郎點N2至一電壓’其在U壓之上而小於一臨限電壓 !V(Vt)，而避免活化電晶體7〇ι。 548838 五、發明說明（39) 如上所述巧見第五圖，驅動 Μ為低’以活化字元線303。在這：條：二’：後驅” 器5 0 0之降低電晶體5 0 3 (第五圖），、下，子凡線驅動 3 0 3至該VSSB電壓供應線。電晶體5〇3被’因而耗合^元線低狀態傳輸係經由反用換流器7丨丨—7 1之\、fXj #之 N1。此時，η-通道電晶體7〇4保持為啟，，入達即點供應線以接收該Vss供應電壓。且同、、時馬。。亥VSSB包饜升搞合電晶麵電容器之來源與 7 η 〇 ^ ^ ^ 1 μ ^ 出至而狀悲。電晶體門極盥排出’Τ、σ因一此S二極體與其連接至該V·電壓供應線气閘極與排出。因此’電晶體702限制該電壓於節點N2，至气Upon receiving the VBBS voltage, the amount of anti-joint leakage is greatly reduced. Furthermore, by limiting the VBBS voltage to a threshold voltage that is less than the Vss supply voltage: the anti-joint leakage is further reduced. V. Description of the Invention (38) The seventh diagram is a schematic diagram illustrating an embodiment of the Vssb consumable circuit 700 according to one embodiment of the present invention. The VSSB coupling circuit 70 0 includes a p-channel transistor 70-70S3SB, a channel transistor 704, and an inverter 71b. The p-channel transistor 7'〇Υ is connected to the vSSB and vBBS voltage supply lines. The gate of transistor 701 is coupled to node N2. Transistor 702 is connected between the node and the voltage supply line. The p-channel transistor 70 is connected as a capacitor, and its source and drain are connected to node N1, and its gate is connected to node N2. The channel transistor 704 is connected between the VSSB voltage supply line and the & voltage supply terminal. The gate of the transistor 704 is connected to the node ^. The inverter 711: 714 is connected continuously, and The inverter 711 is used to decompose the signal M from the column address, and the inverter 714 is used to provide the delayed signal path. The eighth diagram is a waveform diagram, which is explained in the operation of the 'M coupling circuit 700. Different signals are generated. Before the word line 30 3 is activated, the signal \ is low, and the signal 乂 #. Under these conditions, the inverter 711_714 chain provides a logic signal to node N1, so Turn on the n-channel transistor m. Therefore, the 5 VSSB voltage supply line is maintained at the & supply voltage (0 voltage). Similarly: 'Before activating the word line 30 3', the second threshold of the transistor 702 Leakage: The Lang point N2 to a voltage 'It is above U voltage and less than a threshold voltage! V (Vt) and avoid activating the transistor 70. 548838 V. Description of the invention (39) As shown in the fifth figure, driving M is low 'to activate the character line 303. Here: Article: Two': The rear-driving device 500 reduces the transistor 503 (fifth figure), and the lower and lower lines drive the 303 to the VSSB voltage supply line. Transistor 503 is thus consumed by the element line. The low-state transmission is via N1 of the inverters 7 and fXj #. At this time, the η-channel transistor 704 remains on, and the point-to-point supply line is reached to receive the Vss supply voltage. And the same, when the horse. . The source of the VSSB package is to combine the source of the electric crystal plane capacitor with 7 η 〇 ^ ^ ^ 1 μ ^ Out of sadness. The transistor gate discharges' T, σ are thus connected to the S · diode and the V · voltage supply line air gate and discharge. Therefore, the transistor 702 limits this voltage to node N2,

该VBBS電屋之上不尚於臨限電壓(Vt)，或至潛在約等於該V ，應電壓。因此，電容器703最初被充電至一電壓，其約於等於该vdd供應電屋（亦即該電壓存取電晶體7〇3係約等於 V. ^ - » * afl號Xj #之低狀態達到節點N丨時，電晶體7 〇 4被關閉，而自該vss供應電壓終端解耦合該VssB電壓供應線。節點 N 1之低電壓也造成電容器7 〇 3將節點N 2降低至等於-ydd之電壓。節點N2之-Vdd電壓開啟p-通道電晶體7〇1，而耦合該電壓供應線至該vBBS電壓供應線。值得注意的是此時僅32 $ 元線驅動斋係I馬合至該vBBS電壓供應線（為該vBBS電壓產生器 9 0 0 )。由於相當小量的字元線驅動器係連接至該電壓供應線，因此所得之接合漏損量係相當小。該晶片上VBBS電壓產生器9 0 0係設計以保持vBBS於約-〇. 3 伏特’係於该Vss供應電壓沉積該接合漏損量之下。值得注The voltage on the VBBS electric house is not less than the threshold voltage (Vt), or the potential should be approximately equal to the V, which should be the voltage. Therefore, the capacitor 703 is initially charged to a voltage, which is approximately equal to the vdd supply house (that is, the voltage access transistor 703 is approximately equal to V. ^-»* afl 号 Xj # The low state reaches the node At N 丨, transistor 704 is turned off, and the VssB voltage supply line is decoupled from the vss supply voltage terminal. The low voltage at node N1 also causes capacitor 703 to reduce node N2 to a voltage equal to -ydd .The -Vdd voltage of node N2 turns on the p-channel transistor 701, and couples the voltage supply line to the vBBS voltage supply line. It is worth noting that at this time only 32 $ yuan line drives Zhai Imahe to the vBBS Voltage supply line (for the vBBS voltage generator 900). Since a relatively small number of word line drivers are connected to the voltage supply line, the resulting joint leakage is relatively small. The VBBS voltage generator on the chip The 900 series is designed to keep vBBS at about -0.3 volts' under the Vss supply voltage to deposit the junction leakage. It is worth noting

第45頁 548838 五、發明說明（40) 意的是在字元線3 0 3開啟過程中，該字元線3 0 3最初係耦合以接收該Vss供應電壓。當該字元線30 3之電壓降至該Vdd供應電壓下時，則耦合該字元線3 〇 3以接收該負極升高電壓 VBBS。此限制該字元線降低電晶體5 0 3之該來源至排出電壓，以小於VCCB減掉yBBS，而避免電晶體5 0 3被暴露於高電壓壓力下。Page 45 548838 V. Description of the invention (40) means that during the opening of the character line 3 0 3, the character line 3 3 is initially coupled to receive the Vss supply voltage. When the voltage of the word line 303 drops to the Vdd supply voltage, the word line 303 is coupled to receive the negative voltage VBBS. This restricts the word line from reducing the source of the transistor 503 to the discharge voltage, reducing yBBS by less than VCCB, and preventing the transistor 503 from being exposed to high voltage pressure.

為了解活化該字元線，該訊號Xj #被列位址解碼器5 〇〇驅動為高。而後該字元線驅動器5 〇〇中之上升電晶體5 〇 1被開啟，而將字元線3〇3升高至該VCCB電壓。在VSSB耦合電路 7〇〇中，該訊號Xj#之高狀態傳輸係經由反用換流器711—714 形成之延遲鏈，因而於節點N1提供一高電壓，其開啟電晶體7 0 4。節點N1之高電壓亦搞合節點n 2至約Vss電壓，因而關閉電晶體70 1。在這些情形下，該ν%Β電壓供應線係耦合至該Vss電壓供應終端。電壓參考之產生 _ 根據本案之一實施例’藉由晶片上充電幫浦電壓產生該VCCB與VSSB電壓。第九圖A係一方塊圖，說明根據本案之一實施例中該VCCB與¥8以升高電壓產生器8〇〇與9〇〇之一般結構。每一個VCCB與VSSB升高電壓產生器包含一環狀振動器 8 0 1，一充電幫浦8 0 2與一幫浦控制器8 〇 3，其係控制該環狀振動器801與該充電幫浦802之運作。環狀振動器8〇ι與充電幫浦802為習用之元件，可參閱美國專利5,7〇3, 827與 5, 267, 2 0 1。 ’ 第九圖A係一簡圖，以說明用於習用正極升高電壓產In order to understand the activation of the character line, the signal Xj # is driven high by the column address decoder 500. Thereafter, the rising transistor 501 in the word line driver 500 is turned on, and the word line 303 is raised to the VCCB voltage. In the VSSB coupling circuit 700, the high-state transmission of the signal Xj # is through a delay chain formed by the inverters 711-714, so a high voltage is provided at the node N1, which turns on the electric crystal 704. The high voltage of the node N1 also matches the voltage of the node n 2 to about Vss, so the transistor 70 1 is turned off. In these cases, the ν% B voltage supply line is coupled to the Vss voltage supply terminal. Generation of voltage reference _ According to an embodiment of the present case, the VCCB and VSSB voltages are generated by a charging pump voltage on a chip. The ninth figure A is a block diagram illustrating the general structure of the VCCB and ¥ 8 to raise the voltage generators 800 and 900 in an embodiment according to the present case. Each VCCB and VSSB boosted voltage generator includes a ring vibrator 801, a charging pump 802, and a pump controller 803, which control the ring vibrator 801 and the charging pump The operation of Pu 802. The ring vibrator 800m and the charging pump 802 are conventional components, see U.S. Patent Nos. 5,703,827 and 5,267,201. ’The ninth figure A is a simplified diagram to illustrate the use of conventional positive electrode

第46頁 548838 五、發明說明（41) 1:二之=，控制電路9〇1。充電幫浦控制電麵〜1^兒晶體9 1 1，其具有耦合一閘極以接 -應私壓，耦合一來源與主體以接收該正極升高電壓/如亦一排出至一參考電流來源912。電晶"^體^1之亦，丁、連接至抑制控制線。電流來源9 1 2可以一電阻哭置換。 V供t ί ΐ ΐ升高電壓、一+藉由臨限電壓(V。，而高於該 =t /了电¥，電晶體91 1係被開啟。自電晶體91 1之來、万電流係對照於藉由電流來源9 1之^原恭、dd2 S間之電位差增加時，自電晶體911之來源电机S加。§該來源電流係大於該參考 a* , ^ ^ 抑制控制線以接收該V带懕。兮如^ 咖寸耦合§亥 boost+ 4 〇亥抑制*|瓦號夕古业能你/曰該該環狀振動器801失去功#，A,市』°Κ唬之同狀悲使得 Αν fM旱争二去功此因而停止該充電幫浦且阻 b〇OSt+、欠付更向。端視參考電流強产，壓Vk 可姑纲々々士人》T7 . 又該正極升南電壓而可中 [Vb00st+ 了被凋即於該Vdd供應電壓加 /古4曰、士立〜聊Π7(电/至 !=:?是竊合電晶體911之主體以接收Vl 高。佶撂、;丰咅从曰一&人^。u艮電@(Vtp)或更 ® ^ λ t ^ ^ ^^ ± ^ ^ VVT^T^ ^ ^ t μ t a, r, 9 π ^ ± 该基材分離，或當雷晶I# g 1 1佐 /、立#低廢夺贫形成於一n-型基材 ”係偏反至專於或大於VbQQSt+。第九圖C係一簡圖，說明用於— t _ _ ^ ^ 哇哭由々古^用負極升高電壓產生為中之一充電幫浦控制電路9〇2。包含-η-通道電晶體921，其具有叙i電幫浦控制電路902 供β帝廢：，翻^入八、 5 一閘極以接收該VSs ίΉ搞合一來源與主體以接收該負極升高電壓 548838 五、發明說明（42)Page 46 548838 V. Description of the invention (41) 1: Erzhi =, control circuit 9101. Charging pump control electrical surface ~ 1 ^ crystal 9 1 1 which has a gate coupled to-should be private pressure, coupled to a source and the main body to receive the positive voltage increase / as a discharge to a reference current source 912. The transistor " ^ body ^ 1 is also connected to the suppression control line. The current source 9 1 2 can be replaced by a resistor. V supply t ί ΐ ΐ raises the voltage, one + by the threshold voltage (V., and higher than this = t / electricity ¥, transistor 91 1 is turned on. Since the transistor 91 1 comes, 10,000 current This is in contrast to the increase in the potential difference between the current source 9 1 ^ Yuan Gong, dd 2 S, and the source motor S of the transistor 911 is increased. § The source current is greater than the reference a *, ^ ^ suppress the control line to receive The V-band 懕. Xi Ru ^ Coinch coupling § boboost + 4 〇抑制 suppression * | Watts Xiguye can you / said that the ring vibrator 801 loses power #, A, city 『° the same thing The tragedy caused Αν fM to work hard, so it stopped the charging pump, blocked b0OSt +, and owed more. The end-view reference current is strong, and the voltage Vk can be a stunner. T7. And the positive electrode rises. South voltage but can be [Vb00st + + Vdd supply voltage plus / ancient 4th, Shili ~ Liao Π7 (electric / to! = :? is the main body of the stolen transistor 911 to receive Vl high. 佶撂,; 咅咅一一 amp u。 u @@ Vtp) or more ^ λ t ^ ^ ^ ± ^ ^ VVT ^ T ^ ^ t μ ta, r, 9 π ^ ± this basis Material separation, or when Lei Jing I # g 1 1 Zuo, 立 # Low waste and lean shape "An n-type substrate" is reversed to be specialized or greater than VbQQSt +. The ninth figure C is a simplified diagram illustrating the use of — t _ _ ^ ^ One of the charging pump control circuits 902. Contains a -η-channel transistor 921, which has an electric pump control circuit 902 for β imperfections, and turns into a gate electrode to receive the VSs. Combining a source and a subject to receive the negative voltage rise 548838 V. Description of the invention (42)

V boost- 且耦5 排出至一麥考電流來源9 2 2。電晶體9 2 1之徘出亦係連接至抑制#控制線。電流來源922可以一電阻器置換。 _ 當該正極升高電壓vb〇〇s卜藉由臨限電壓（D，而小於該 V:供應電壓時，電晶體921係被開啟。自電晶體921之來源 :流係對照於藉由電流來源922提供之該參考電流{。當與Vss電壓間之電位差增加時，自電晶體921之來源 =流增加。當該來源電流係大於該參考電流〗_時，耗合該〜P制#控制線以接收該vbQQst電壓。該抑制#訊號之高狀態使传該該環狀振動器8()1失去功能，因而停止該充電幫細2 古^ ^ Vb°°St—交得更咼。端視芩考電流IREF強度，該正極升 =私壓VbQQSt-可被調節於該VSS供應電壓減掉一臨限電壓（) 或，鬲值传，主思的疋耗合電晶體9 2 1之主體以接收vbQ〇st_ 電壓’因此此電晶體之該來源至主體接合未向前偏壓。然 ’此連接僅可能於當該電晶體921之主體係一p—槽，其、可自該基材分離，或當電晶體921係形成於一n—型基材中，其係偏壓至等於或較vb〇〇st_更為負值。、充電幫浦控制電路901與9 0 2不存在於習用邏輯製程， ^為此一製程受到侷限，在一個槽中僅一種電晶體可被分維。因此，習用邏輯製程無法得到此處所指一槽與 $ °再者，由於記憶胞元3〇〇之該p—型基材係偏壓於vss電 f (第二圖B )，記憶胞元3 0 0之該p -型基材係偏壓於一等於 ^交°亥負極升南字元線電壓VBBS更為負值。甚者，由於充電 3浦控制電路901造成一VbQQSt+電壓大於或等於vdd加上Vtp，V boost- and coupling 5 is discharged to a McCaw current source 9 2 2. Transistor 9 2 1 is also connected to the suppression # control line. The current source 922 may be replaced by a resistor. _ When the positive electrode voltage rises vb〇〇s by the threshold voltage (D, but less than the V: supply voltage, the transistor 921 is turned on. From the source of the transistor 921: the current is compared with the current The reference current provided by the source 922 {. When the potential difference from the Vss voltage increases, the source of the self-transistor 921 = the current increases. When the source current is greater than the reference current 〖_, the ~ P 制 # control is consumed Line to receive the vbQQst voltage. The high state of the inhibit # signal disables the transmission of the ring vibrator 8 () 1, and thus stops the charging help. 2 ^ ^ Vb °° St-better. Depending on the strength of the current IREF, the positive electrode rise = private voltage VbQQSt- can be adjusted at the VSS supply voltage minus a threshold voltage () or, the value is passed, the main body of the consumable power transistor 9 2 1 In order to receive the voltage of vbQost_, therefore, the source-to-body junction of this transistor is not forward biased. However, this connection is only possible when the main system of the transistor 921 is a p-slot, which can be removed from the substrate Separation, or when the transistor 921 is formed in an n-type substrate, it is biased to be equal to or less than vb〇〇st_ The values are negative. The charging pump control circuits 901 and 902 do not exist in the conventional logic process. For this reason, this process is limited. Only one transistor can be fractalized in a slot. Therefore, the conventional logic process cannot be obtained. Here, a slot and $ ° are referred to, and since the p-type substrate of the memory cell 300 is biased to the vss electric f (second figure B), the p-type of the memory cell 300 The base material is biased to a voltage VBBS which is equal to the voltage of the negative electrode line in the south, and the voltage VBBS is more negative. Furthermore, a voltage of VbQQSt + is greater than or equal to vdd plus Vtp due to the charging of the 3P control circuit 901

第48頁 548838Page 48 548838

五、發明說明（43) 此充琶^浦控制電路Q Q 1益電壓，但是如本素所需小；:該/ 一^:電塵大於^供應。、 ^ ί、應電壓加上該臨限電壓同樣地’由於充電幫浦控制小於或等於該^佴廊雷茂路902 4成一 VbQQSt_電壓控制電卿限電⑼，此充機如本大於该Vss供應電壓減掉該臨限。第十圖係根據本幸之一奋 tn 路1 0 0 0之示意圖。v充電幫在中u電幫浦控制電第九圖Α)，因而產生-V⑽參考電壓產 1 0 0 0 ^ ^ 所欲之7咖電壓。V⑽充電幫浦控制電路二二P_ 1 00 1 — 1 0 0 3與參考電流來源1004- 1^05。搞合P-通道電晶體1QQ1之來源，以接收該州供應電麼，且p~通道電晶體夕兮扣 .、 > 體U ϋ 1之该閘極與排出係共同連接至爹考电k來源1 004。？-通道電晶體1〇〇1因而連接如一二體於該Vdd供應電壓與參考電流來源丨〇產生-參考電流，W，其建立一參考電考壓電原於 P-通道電晶體1 0 0 2之閘極。 ' P-通道電晶體1001之通道寬度為Wp。p-通道電晶體 1001與1 0 0 2具有相同的通道長度。然而，P—通道電晶體 1002之通道寬度為m乘以Wp，其中m係一常數。電晶體丨〇〇2 之排出係連接至另一參考電流來源1 〇〇 5，其產生一參考電流Vrefpi。電晶體1 〇〇 2之來源係連接至節點\。節點v亦連<接至Ρ -通道電晶體1 0 0 3之排出與閘極。電晶體丨〇〇 3之來源被 548838 五、發明說明（44) 連接以自充電幫浦8 0 2接收該正極升高電壓vccB。若該參考電流Irefp與Irefpi相等，且電晶體1002之通道寬度與電晶體 1 ο ο 1相同，則節點vp將被維持於一電壓等於該Vdd供應電壓。，這些情形下，該正極升高電壓Vccb將高於該Vdd供應電壓’藉由一電壓大於P—通道電晶體之該臨限電壓V之絕對差值。 tp 在此實施例中，設定該參考電流IREFP約等於參考電流 Lefpi，且常數m被設定等於4。由於電晶體1〇〇2之通道長度係四倍長於電晶體1001之通道長度，該電晶體1 0 0 2之1^ ^閑極電壓係小於電晶體1〇〇1之來源至閘極電壓。因此，' 即點vp之電壓係小於該^供應電壓。例如，若參考電流I 與IREFP1皆被設定等於50//A，則節點、之電壓將約為〇.f‘FP ，，，小於該L供應電壓。電晶體1 0 0 3之通道寬度選擇為相例如，因而電晶體觀之來源至閘極電擇壓為相 v tt電晶體1 0 0 3之臨限電壓（例如0.5伏特）。結果，誃 V(：CB笔壓係維持於的〇 9你杜丄士人》τγ 〆 Φ授丨狄符於約〇·3伙特大於該Vdd供應電壓。因而該¥ 包i ；一臨限電壓大於該I供應電壓。咖至接實施例、中，p—通道電晶體1〇03可被刪除，因而 _ 體。然而，在此實施例中，電晶 Wp。即該見度^須被選為小於電晶體1001之通道寬度 ^至門 111必須選擇為小於1，因而該電晶體1 0 0 2之來〇:、3伏V(晶體1001之來源…^ Μ 私反其小於該ρ -通道臨限電壓）。弟—圖係根據本案之一實施例中一 VBBS充電幫浦控制V. Description of the invention (43) This charging control circuit Q Q 1 has a good voltage, but it is as small as required by this element ;: This / a ^: The electric dust is greater than ^ supply. , ^ Ί, the voltage plus the threshold voltage is the same 'because the charging pump control is less than or equal to the 902 佴 Lei Mao Road 902 4 into a VbQQSt_ voltage control electric power limiter, this charger is greater than this The Vss supply voltage subtracts this threshold. The tenth picture is a schematic diagram of a tn road 1 0 0 0 according to one of the local fortunes. The v-charging power is controlled by the U-power pump in the ninth figure A), which results in a -V⑽ reference voltage to produce a desired voltage of 7 Ω. V⑽Charging pump control circuit 22 P_ 1 00 1 — 1 0 0 3 and reference current source 1004- 1 ^ 05. Connect the source of the P-channel transistor 1QQ1 to receive the power supplied by the state, and the p ~ channel transistor is connected., &Gt; The gate of the body U ϋ 1 and the discharge system are connected to the Dakau power k Source 1 004. ? -The channel transistor 1001 is thus connected as a two-body body to the Vdd supply voltage and the reference current source. The reference current, W, establishes a reference electro-test piezoelectric element on the P-channel transistor 100. 2 gate. 'The channel width of the P-channel transistor 1001 is Wp. The p-channel transistors 1001 and 1002 have the same channel length. However, the channel width of the P-channel transistor 1002 is m times Wp, where m is a constant. The output of the transistor is connected to another reference current source 105, which generates a reference current Vrefpi. The source of transistor 100 is connected to node \. Node v is also connected to the drain and gate of the P-channel transistor 103. The source of the transistor 丨〇 03 is 548838 V. Description of the invention (44) is connected to the self-charging pump 802 to receive the positive voltage vccB. If the reference current Irefp is equal to Irefpi and the channel width of transistor 1002 is the same as transistor 1 ο ο 1, the node vp will be maintained at a voltage equal to the Vdd supply voltage. In these cases, the positive voltage Vccb will be higher than the Vdd supply voltage 'by a voltage greater than the absolute difference of the threshold voltage V of the P-channel transistor. tp In this embodiment, the reference current IREFP is set to be approximately equal to the reference current Lefpi, and the constant m is set to be equal to 4. Since the channel length of transistor 1002 is four times longer than the channel length of transistor 1001, the voltage of the transistor 1 ^^^^ is smaller than the source-gate voltage of transistor 1001. Therefore, the voltage of the 'point vp' is smaller than the supply voltage. For example, if both the reference current I and IREFP1 are set equal to 50 // A, the voltage at the node will be approximately 0.f'FP, which is less than the L supply voltage. The channel width of transistor 1 0 0 3 is selected as phase. For example, the source-to-gate voltage selection of transistor 10 3 is the threshold voltage of transistor 1 0 3 (eg 0.5 volt). As a result, 誃 V (: CB pen pressure is maintained at 〇9 you du shi shi ren ττ 〆〆 Φ 授丨 Di Fu is approximately 0.3 times larger than the Vdd supply voltage. Therefore, the ¥ package i; a threshold The voltage is greater than the I supply voltage. In the embodiment, in the embodiment, the p-channel transistor 1003 can be deleted, so the body. However, in this embodiment, the transistor Wp. That is, the visibility ^ must be The width of the channel selected to be less than the transistor 1001 ^ to the gate 111 must be selected to be less than 1, so the transistor comes from 0 2 0: 3 volts V (the source of the crystal 1001 ... ^ M privately it is less than the ρ- Threshold voltage of the channel). Brother-the picture is based on a VBBS charging pump control in one embodiment of the present case

548838 友、發明說明（45) 電路Π 0 0之不意圖。vBBS充電幫浦控制電路丨丨〇〇係用以置換充電幫浦控制電路80 3 (第九圖A)，而產生—Vbbs參考電壓產生電路，其可產生所欲之vBBS電壓。Vbbs充電幫浦控制電路 \100包含11-通這電晶體11〇1-1102，{)_通道電晶體11〇3與翏考電流來源1 1 04- 1 1 05。η -通道電晶體1丨〇丨之來源係連接以接收該Vss供應電壓。電晶體丨丨01之該排出與閘極係丑 '同連接至參考電流來源n 04。因此，電晶體11〇1係連接為' 「二極體。麥考電流來源丨丨〇4係連接於該電壓供應與卜通迢電晶體1 1 0 1之共同連接的排出與閘極排出之間。參電抓來源1 1 〇 4提供一參考電流丨狀醋至^通道電晶體。建立一參考電壓，v_，於…電晶體 inn m,晶體1101之通道寬度為Wn。n-通道電晶體 1 1 02 i、i…二有相同的通道長度。然而，η-通道電晶體之排出ίΪ:度為η乘以?Π，其中η係一常數。電晶體1102 :排出係連接至另一參考電流來源11〇5，其產 Ϊ _通°•首/Λ1102之來源係連接至節點％。節點vN亦連接 i同；體1103之來源。電晶體之排出與閉極被厂门二妾以妾收該負極升高電壓V·。若該參考電流‘與 ΓΓ=1)、，則松電晶體1102之通道寬度與電晶體1101相同（亦 :這二青:;；點、將被維持於-電壓等於該vss供應電壓。548838 Friends, invention description (45) The intention of the circuit Π 0 0. The vBBS charge pump control circuit 丨丨〇〇 is used to replace the charge pump control circuit 80 3 (ninth figure A) to generate a -Vbbs reference voltage generation circuit, which can generate the desired vBBS voltage. Vbbs charge pump control circuit \ 100 contains 11-pass transistor 110-102, {) _channel transistor 110 and test current source 1 1 04- 1 1 05. The source of the n-channel transistor 1 丨〇丨 is connected to receive the Vss supply voltage. The output of the transistor 丨丨 01 is connected to the reference current source n 04 in the same way as the gate system. Therefore, the transistor 1101 is connected as a "diode. The source of the McCaw current is connected to the voltage supply and the discharge of the common connection of the transistor 1 1 0 1 and the gate discharge. The reference source 1 1 04 provides a reference current to the channel transistor. Establish a reference voltage, v_, at the transistor inn m, the channel width of the crystal 1101 is Wn. N-channel transistor 1 1 02 i, i ... the two have the same channel length. However, the discharge of the η-channel transistor Ϊ: the degree is η times the? Π, where η is a constant. Transistor 1102: The discharge system is connected to another reference The current source is 1105. The source of the current source is connected to the node%. The node vN is also connected to the same source; the source of the body 1103. The discharge of the transistor and the closed electrode are controlled by the factory door. Take the negative electrode to increase the voltage V. If the reference current 'and ΓΓ = 1), the channel width of the pine crystal 1102 is the same as that of the transistor 1101 (also: these two blues: ;; points, will be maintained at- Equal to the vss supply voltage.

Vss供應電壓下之 '負：t :電壓V，將被調節於-電壓約該土 r之一限電壓（V )。在此實施例巾，設定該參^電流1酬約等於參考電流 548838 五、發明說明Vss supply voltage 'negative: t: voltage V, will be adjusted to-the voltage is about one of the limit voltage (V). In this embodiment, the reference current is set to approximately equal to the reference current 548838. V. Description of the Invention

%FN1，且¥敛Γ1被設定等於4。由於電晶體11〇2之通道長产係四倍長於電晶體1101之通道長度，該電晶體1102之來ς 至間極電壓係小於電晶體1101之來源至閘極電壓。因此，、 :，νΝ，電壓係小於該Vss供應電壓。例如，若參考電流^ =则^被没疋等於5〇#A，Μ節點VN之電壓將約為〇· 2伏 4寸，大於該vss供應電壓。電晶體11〇3之通道寬度選擇為，當大（例如50，）’因而電晶之來源至閘極電壓，約等於電晶體11 03之臨限電壓（例如〇5伏特）。結果， :V:S ^壓係維持於約〇. 3伏特小於該^供應電壓。因而該 BBS私堅小於一臨限電壓小於該k供應電壓。，另一實施例中，P-通道電晶體11〇3可被刪除，因而壓至節點Vn。然*，在此實施例中，電晶 02之通迢覓度必須被選為小於電晶體丨丨0丨之通道寬产該常數n必須選擇為小於1，因而該電晶體1102之來又 '、f甲極电壓係大於該電晶體丨丨0丨之來源至閘極電壓約 U. 3伏特（或另一電壓其小於該？_通道臨限電壓）。% FN1, and ¥ 敛 Γ1 is set equal to 4. Since the channel length of the transistor 1102 is four times longer than the channel length of the transistor 1101, the voltage from the transistor 1102 to the inter-electrode voltage is smaller than the source-gate voltage of the transistor 1101. Therefore, the voltage of,:, νN, is smaller than the Vss supply voltage. For example, if the reference current ^ = ^ is not equal to 50 # A, the voltage of the node VN will be about 0.2 volts 4 inches, which is greater than the vss supply voltage. The channel width of the transistor 110 is chosen to be. When the value of the transistor (for example, 50 Ω) is large, the source voltage to the gate of the transistor is approximately equal to the threshold voltage of the transistor 110 (for example, 0.5 volt). As a result, the: V: S voltage is maintained at about 0.3 volts less than the voltage supply. Therefore, the BBS is less than a threshold voltage and less than the k supply voltage. In another embodiment, the P-channel transistor 1103 can be deleted, and thus pressed to the node Vn. However, in this embodiment, the passivity of the transistor 02 must be selected to be less than the channel width of the transistor 丨丨 0 丨 The constant n must be selected to be less than 1, so the transistor 1102 comes again. The f voltage of f is greater than the voltage from the source of the transistor 丨丨 0 丨 to the gate voltage of about U. 3 volts (or another voltage which is less than the threshold voltage).

=而可得以在不同溫度中，相當維持該％⑶與電壓 :吊、、般而言，當溫度增加時，該電晶體臨限電壓V 少。為了補償此溫度效應，建構參考電流來源10心 ^ 4，因而參考電流hFP與IREFN1具有負的溫度係數（亦即萄溫，增加時，參考電流^吓與^_減少）。一 ^十—圖係根據本案之一實施例中參考電流來源1 〇〇 4 之不意圖。參考電流來源1 0 04包含p—通道電晶體12〇1一= And can be maintained at different temperatures, the% ⑶ and the voltage is quite maintained: In general, when the temperature increases, the threshold voltage V of the transistor is less. In order to compensate for this temperature effect, a reference current source of 10 cores ^ 4 is constructed, so the reference currents hFP and IREFN1 have negative temperature coefficients (that is, when the temperature increases, the reference current ^ scares and ^ _ decreases). 1 ^ Ten-the diagram is based on the intention of the reference current source 1004 in one embodiment of the present invention. Reference current source 1 0 04 contains p-channel transistor 12〇1

1 2 0 2，電阻器1 0 2 3，與n—通道電晶體1 2 04- 1 2 0 6。電阻器 548838 五、發明說明（47) 1 2 0 3係連接於V d d電壓供應與電晶體1 2 0 1之間 ^ 定電晶體1 2 0 1之偏壓。經過電阻器1 2 0 3之電^蛋^因〃而°又電阻器1 2 0 3之電阻劃分之電晶體丨2 〇丨之臨限=^係等於由 %廢V 。雷流 IR係直接關聯於該臨限電壓vtp。電流IR流經D、、、/p ^ 1 2 0 2與η-通道電晶體1 2 0 5。 4 4 t Μ 電晶體1 2 0 2之閘極與來源係各自耦合至電曰體1 2 〇 1之該排出與來源。電晶體1 2 〇 2之閘極電壓係轉變為電晶體 1 2 0 2之排出。Ν-通道電晶體1 204- 1 20 6，其久目”、士曰曰十版広終端耦合至電晶體1 2 0 2之排出，因而形成—電流反射電路。該電流IR係轉變至電晶體丨2 〇 6。因此，經通道電晶體1 2 0 6之電流（亦即lREFp)係直接關聯於p—通道電晶體一 1 ·2 0 1之臨限電壓Vtp。曰曰參考電流來源1 0 〇 4提供溫度補償如下所述。當溫度增加時，電晶體1 0 0 2與1〇〇3(第十圖）之臨限電疋Vtp卩+低’因而造成该VCCB電壓之減少。然而，當溫度增加時，電晶體1201(第十二圖）之臨限電壓Vtp降低。因此，電流IR降低而降低該IREFP電流。結果，p —通道電晶體i 〇〇丨（第十圖）之該閘極致來源電壓降低，而增加該VREFP電壓。該增加的VREFP電壓依次造成電壓Vp增加，而增加該Vc⑶電壓。電晶體1 0 0 2與1 ο 〇 3之臨限電壓vtp之溫度效應，因而藉由該 IREFP電流之負溫度係數而得到部分補償。在此方式中，參考電流來源1 0 0 4提供溫度補償至VCCB幫浦控制電路1 0 0 0。第十三圖係根據本案之一實施例中參考電流來源11 0 4 之示意圖。由於參考電流來源丨丨〇 4係相似於參考電流來源1 2 0 2, resistor 1 0 2 3, and n-channel transistor 1 2 04- 1 2 0 6. Resistor 548838 V. Description of the invention (47) 1 2 0 3 is connected between the voltage supply of V d d and transistor 1 2 0 1 ^ bias voltage of fixed transistor 1 2 0 1. The electric voltage passing through the resistor 1 2 0 ^ is changed due to 〃, and the transistor divided by the resistance of the resistor 1 2 0 3 The threshold of ^ 2 is equal to% waste V by%. The lightning current IR is directly related to the threshold voltage vtp. The current IR flows through D,,, / p ^ 1 2 0 2 and the η-channel transistor 1 2 0 5. The gate and source of the 4 4 t transistor 1220 are each coupled to the discharge and source of the transistor 1220. The gate voltage of the transistor 12 2 is converted to the discharge of the transistor 1 2 02. Ν-channel transistor 1 204- 1 20 6, whose long-term ", Shiyue tenth edition 広 terminal is coupled to the discharge of transistor 1 2 02, thus forming a current reflection circuit. The current IR is converted to a transistor丨 2 〇 6. Therefore, the current through the channel transistor 1 2 06 (ie lREFp) is directly related to the threshold voltage Vtp of the p-channel transistor 1 · 2 0 1. The reference current source 1 0 〇4 provides temperature compensation as described below. When the temperature increases, the threshold voltage of the transistor 10 02 and 100 3 (tenth figure) 疋 Vtp 卩 + low 'causes the VCCB voltage to decrease. However, When the temperature increases, the threshold voltage Vtp of the transistor 1201 (Figure 12) decreases. Therefore, the current IR decreases to reduce the IREFP current. As a result, p-the channel transistor i 〇〇丨 (Figure 10) The gate causes the source voltage to decrease and increase the VREFP voltage. The increased VREFP voltage in turn causes the voltage Vp to increase, which increases the Vc⑶ voltage. The temperature effect of the threshold voltages vtp of the transistors 1 0 2 and 1 ο 03, therefore Partial compensation is obtained by the negative temperature coefficient of the IREFP current. The reference current source 1 0 0 4 provides temperature compensation to the VCCB pump control circuit 1 0 0. The thirteenth figure is a schematic diagram of the reference current source 11 0 4 according to one embodiment of the present case. Because the reference current source 丨丨〇4 is similar to the reference current source

第53頁 [548838 五、發明說明（48) 1 0 0 4 (第十二圖），第十二圖與第十三圖中相似的元件具有，似的標示符號。因此，參考電流來源丨i 0 4包含P通道電體1 20 1 - 1 20 2 ’電阻器1 20 3與Π-通道電晶體1 2 04- 1 205。曰曰Page 53 [548838 V. Description of the invention (48) 1 0 0 4 (12th figure), similar elements in the 12th figure and the 13th figure have a similar symbol. Therefore, the reference current source i 0 4 includes the P-channel transistors 1 20 1-1 20 2 ′, the resistor 1 20 3 and the Π-channel transistor 1 2 04- 1 205. Yue

此外，芩考電流來源1 1 〇 4包含一 Ρ _通道電晶體1別1，其具有一問極耦合至電晶體12〇1之該閘極，且耦合一來源^接收該Vdd供應電壓。參考電流來源11 0 4提供之溫度補償敘述如下。In addition, the current source 1 104 includes a P_channel transistor 1 and 1 which has a gate coupled to the gate of the transistor 1201 and is coupled to a source to receive the Vdd supply voltage. The temperature compensation provided by reference current source 11 0 4 is described below.

^ 當溫度增加時，電晶體U02與1103(第十一圖）之臨限私壓Vt降低，因而造成該電壓之減少。然而，當溫度增加時，電晶體1 2 0 1之臨限電壓vtp降低。因此，電流Ir降低。由於電晶體1 2 〇 1與1 3 0 1係耦合以形成一電流反射電路，電流iR降低造成電流iREFN1降低。電流Irefni降低依次造成Vrefn電壓降低（第十一圖）。VREFN電壓降低造成電壓％降低。在此方式中，參考電流來源丨丨04提供溫度補償至'π幫浦控制電路11 〇〇。^ When the temperature increases, the threshold of the transistor U02 and 1103 (Figure 11) decreases the private voltage Vt, which causes the voltage to decrease. However, as the temperature increases, the threshold voltage vtp of the transistor 1 2 0 1 decreases. Therefore, the current Ir decreases. Since the transistors 1 2 0 1 and 1 3 0 1 are coupled to form a current reflection circuit, a decrease in the current iR causes a decrease in the current iREFN1. The decrease in current Irefni in turn causes a decrease in Vrefn voltage (Figure 11). A decrease in VREFN voltage causes a decrease in voltage%. In this manner, the reference current source 04 provides temperature compensation to the 'π pump control circuit 11 00.

若该電流IREFP1為獨立溫度，則該參考電流來源1 〇〇 4 (第十二圖）主要係補償電晶體1〇〇2之溫度效應，因而留下電晶體1 0 0 3大量未被補償之溫度效應。同樣地，若電流為獨立溫度，則該參考電流來源丨丨〇 4 (第十三圖）主要係補償電晶體11 〇 2之溫度效應，因而留下電晶體丨丨0 3大量未被補償之溫度效應。為了補償電晶體1 0 0 3與丨丨〇3之未補償之溫度效應’建構參考電流來源1 〇〇 5與1 1 〇 5，使得參考電流 Irefpi 與IREFN具有正的溫度係數（亦即當溫度增加時，參考電流 IREFP1 與 iREFN 增加）。If the current IREFP1 is an independent temperature, the reference current source 1004 (Figure 12) is mainly to compensate the temperature effect of transistor 1002, thus leaving a large amount of transistor 1003 uncompensated. Temperature effect. Similarly, if the current is an independent temperature, the source of the reference current 丨 4 (Figure 13) is mainly to compensate the temperature effect of the transistor 11 〇2, leaving a large number of uncompensated 丨丨 3 Temperature effect. In order to compensate the uncompensated temperature effects of the transistors 1 0 03 and 丨丨 03, the reference current sources 1 0005 and 1 1 05 are constructed so that the reference currents Irefpi and IREFN have a positive temperature coefficient (that is, when the temperature As it increases, the reference currents IREFP1 and iREFN increase).

第54頁 548838Page 54 548838

第十四圖係根據本案之一實施例中參考電流來源ι〇〇5 之不意圖。參考電流來源1 0 0 5包含p-通道電晶體14〇1一 1 40 3 ’n~逋迢電晶體141卜1414，pNp兩極電晶體丨42卜 1 4 2 2以及電阻為丨4 3 1。電晶體1 4 〇 1 ，丨4 11與i 4 2 1係連續連接於該vdd與vss電壓供應之間。電晶體14〇3係連續連接於平The fourteenth figure is based on the intention of the reference current source ι005 in one embodiment of the present case. The reference current source 1 0 0 5 includes a p-channel transistor 1401- 1 40 3 ′ n to a pseudo transistor 141b 1414, a pNp bipolar transistor 42b 1 4 2 2 and a resistance 4l 1. Transistors 1 4 0 1, 4 11 and i 4 2 1 are continuously connected between the vdd and vss voltage supplies. The transistor 1403 is continuously connected to the flat

二連接電晶體14 13-1 41 4於該Vdd與vss電壓供應之間。p—通迢電晶體1 40 1 - 1 40 3係形成一電流反射電路，因而同樣的電流通過三個電晶體1 4 0 1 — 1 40 3。電晶體1 422之發射器之選擇為m次大於電晶體1421之發射器，其中爪係一常數'在所描述之實施例中，該常數111等於4。該常數m與電阻器 1 4 3 1之電阻值係被選擇的，因而該電流係約等於。電晶體1411與1 42 2之來源電壓係保持與電晶體14〇1一 1402與1411-1412之電壓相同。所以，電壓橫過電晶體 1 4 2 1係等於電壓橫過電晶體丨4 3丨與電晶體丨4 2 2。The two connecting transistors 14 13-1 41 4 are between the Vdd and the vss voltage supply. The p-thru transistor 1 40 1-1 40 3 forms a current reflection circuit, so the same current passes through the three transistors 1 4 0 1 — 1 40 3. The transmitter of transistor 1 422 is chosen to be m times larger than the transmitter of transistor 1421, where the claw is a constant 'in the embodiment described, the constant 111 is equal to four. The constant m and the resistance value of the resistor 1 4 3 1 are selected, so the current is approximately equal to. The source voltages of transistors 1411 and 1 42 2 remain the same as the voltages of transistors 1401-1402 and 1411-1412. Therefore, the voltage across the transistor 1 4 2 1 is equal to the voltage across the transistor 4 4 and the transistor 4 2 2.

參考電流來源1 0 0 5之運作請參閱p· R. Gray與R. G. Meyer所著之「類比積體電路之分析與設計」第33〇 —333 頁。通過電阻器1341之電流IR係等於vT/R in (m)。VT = kT/q，其中k係等於Bol tzmann，s常數，T係等於絕對溫度，且q係等於電荷。通過電阻器丨3 4 1之電流係與溫度直接相關。通過電阻器1431之電流IR係係被轉換以產生通過電晶體1 40 3與1413-1414之電流IREFP1。所以，電流IREFP1 係與溫度直接相關。該增加的電流irefpi增加第十圖中電晶體1 〇 0 2與1 〇 0 3之閘極至來源電壓，因而抵銷電晶體1 〇〇 3之臨限電壓Vtp之減少，其發生於溫度增加之時。如上所述，Refer to p. R. Gray and R. G. Meyer, "Analysis and Design of Analog Integrated Circuits," pages 33-333 for the operation of the reference current source 105. The current IR through the resistor 1341 is equal to vT / R in (m). VT = kT / q, where k is equal to Boltzmann, s constant, T is equal to absolute temperature, and q is equal to charge. The current through the resistor 丨 3 4 1 is directly related to temperature. The current IR passing through the resistor 1431 is converted to generate a current IREFP1 passing through the transistors 1 40 3 and 1413-1414. Therefore, the current IREFP1 is directly related to temperature. This increased current irefpi increases the gate-to-source voltage of transistors 1 2 and 1 03 in the tenth figure, thus offsetting the decrease in threshold voltage Vtp of transistor 1 3, which occurs as the temperature increases Time. As mentioned above,

第55頁 548838 五、發明說明（50) 電晶體丨0 0 3之該臨限電壓Vtp之減少傾向於增加該VCCB電壓。然二’θ該增加的電流IREFP1傾向於增加該vCCB電壓。淨結果為 vCCB電壓在運作的溫度範圍内，係保持於固定的。一 2十五圖係根據本案之一實施例中參考電流來源1 1 0 5 之不思圖。參考電流來源11 〇 5包含p -通道電晶體1 4 0 1 - 1 40 2與1501 ’n—通道電晶體1411-1412，PNP兩極電晶體 1421-1422 與電阻器1431。電晶體14〇1一14〇2，1411一 14 U ’1421 — 1422與電阻器1432之連接方式如第十四圖中所不°此外’電晶體丨5 〇丨之閘極係共同連接至電晶體 1 4 0 1 - 1 4 0 2之閘極。如上所述，通過電晶體丨4 3丨之電流、係直接，聯於溫度。所以，當溫度增加時，通過電晶體丨43丄之電流Ir係增加。此增加的電流係被轉換至電晶體1 5 0 1，因而造成一增加的電流Irefn。該增加的電流IREFN增加第十一圖中之電^體1102與丨丨03之閘極至來源電壓，因而抵銷第十囷中龟日日肢11 〇 3之臨限電壓vtp減少。如上所述，電晶體1101之臨限電壓k減少傾向於增加該vBBS電壓。結果為該Page 55 548838 V. Description of the invention (50) The decrease of the threshold voltage Vtp of the transistor 丨 0 3 tends to increase the VCCB voltage. However, this increased current IREFP1 tends to increase the vCCB voltage. The net result is that the vCCB voltage remains fixed over the operating temperature range. The twenty-fifth figure is a schematic diagram of a reference current source 1 1 0 5 according to an embodiment of the present invention. The reference current source 11 05 includes p-channel transistors 1 4 0 1-1 40 2 and 1501 ′ n-channel transistors 1411-1412, PNP bipolar transistors 1421-1422, and a resistor 1431. The connection methods of the transistors 1401-1402, 1411-1414 U 1421-1422 and the resistor 1432 are not as shown in the fourteenth figure. In addition, the gate of the transistor 丨 5 〇丨 is connected to the transistor in common. Gate of crystal 1 4 0 1-1 4 0 2. As mentioned above, the current through the transistor 4 3 is directly connected to the temperature. Therefore, as the temperature increases, the current Ir through the transistor 43 increases. This increased current is switched to the transistor 1501, thus causing an increased current Irefn. This increased current IREFN increases the gate-to-source voltages of the electric bodies 1102 and 03 in the eleventh figure, and thus offsets the decrease in the threshold voltage vtp of the turtle's solar limb 11 03 in the tenth line. As described above, the decrease in the threshold voltage k of the transistor 1101 tends to increase the vBBS voltage. The result is this

Vbbs電壓係保持為相對的固定於該參考電流電路之範圍中。第=二圖係根據本案之另一實施例中參考電流電路 1 6 0 0之示意，。參考電流電路16〇〇耦合參考電流電路丨〇⑽ 與1104 = 一單—電路中，因而降低所得電路之所需的對齊面積第十一圖，第十三圖與第十六圖中相同的元件具有 ^的兀件符號。參考電流電路16 GQ以相同的方式如时考電流電路1 〇〇 4與1 1 〇 4之運作。The Vbbs voltage remains relatively fixed in the range of the reference current circuit. The second diagram is a schematic diagram of a reference current circuit 1600 according to another embodiment of the present invention. The reference current circuit 1600 is coupled to the reference current circuit 丨〇⑽ and 1104 = a single-circuit, thereby reducing the required alignment area of the resulting circuit. Figures 11 and 13 are the same components as in Figure 16. Elements with ^. The reference current circuit 16 GQ considers the operation of the current circuits 1 004 and 1 104 in the same way.

548838 五、發明說明（5υ 第十七圖係根據本案之另一實施 1 7 0 0之示意圖。參考電流電路1 6 0 0搞人I二t y峨電路與1105於一單一雷踗φ 耦口 $考電流電路1005 面積。第十四圖，第十五圖盥第十之所品的對齊相同的元件符沪。夂 ά f十七圖中相同的元件具有548838 V. Description of the invention (5υ The seventeenth figure is a schematic diagram of another implementation of 1700 according to the present case. The reference current circuit 1600 is a circuit of 1 ty and 2105 in a single thunder φ coupling port. Consider the area of the current circuit 1005. The fourteenth, fifteenth, and fifteenth figures are aligned with the same components. The same elements in the seventeenth figure have

匕什付就參考電流電路1 7 0 0以相闾沾古斗L 考電流電路1005與1105之運作。的方式如同芩上ΐ之；ΪΓ“列使用職電晶體於該記憶胞元。f 運電晶體於P-基材上之^槽中。在_ - s子兀、、袭被活化為高且解活化為低。中第十八圖係一示意圖，其係說明字元線驅 1 6 0 0與一vBBc耦合電路18〇〇，其、' 、路建構之圮fe胞凡。字元線驅動器電路16〇〇包電晶體501與11—通道下降電晶體5〇3，其係如 =—升線驅動器5 0 0連接（第五圖）。字元線哭币與子元予凡綠驅動态電路1 6 0 0之1 $予元線驅動器500之互補電路。該互補電路之獲Please refer to the reference current circuit 1700 to test the operation of the current circuits 1005 and 1105 with respect to each other. The method is the same as that of 芩上 ΐ; ΪΓ “uses a professional transistor in the memory cell. F The transistor is in the ^ slot on the P-substrate. In the _-s sub-frame, the substrate is activated to high and Deactivation is low. The eighteenth figure in the middle is a schematic diagram that illustrates the character line driver 1660 and a vBBc coupling circuit 1800, which, ', and Lu's road construction. Character line driver Circuit 601 package transistor 501 and 11-channel drop transistor 503, which are connected as =-line driver 50 0 (fifth picture). Character line cry coin and Ziyuan Yufan green driving state Circuit 1 6 0 0 1 Complementary circuit of Yuyuan Line Driver 500. The gain of the complementary circuit

付係猎由置換PM0S電晶體NM〇s電晶體，以pM〇s電晶體X NMOS電晶體’以連接至^電壓供應置換連接至該L電壓供應，且以連接至Vdd電壓供應置換連接至Vss電壓供應。所/、以，除了上升與下降電晶體50!與5〇3之外，字元線驅動哭 1 6 0 0包含n-通道電晶體16〇4，p—通道電晶體l6〇2_i6〇3以。。及列位址解碼器1 6丨〇。字几線驅動器5 ο 〇之N-通道下降電晶體5 〇 3，係直接輕合至VBBS電壓產生器9 〇〇。在此實施例中，Vbbs電壓產生器 9 0 0提供一VBBS電壓，約為Vss電壓下—〇·3 v。耦合字元線°驅The pay system is replaced by a PM0S transistor NMOS transistor, a pM0s transistor X NMOS transistor 'connected to the voltage supply and connected to the L voltage supply, and connected to the Vdd voltage supply and connected to Vss Voltage supply. So, in addition to the rising and falling transistors 50! And 50, the word line drives cry 1 6 0 0 including n-channel transistor 160, p-channel transistor 16 2_i 6 0 3 . . And a column address decoder 16 16. The word table line driver 5 ο 〇 N-channel drop transistor 503 is directly connected to the VBBS voltage generator 9 〇. In this embodiment, the Vbbs voltage generator 900 provides a VBBS voltage, which is about -0.3 v at the Vss voltage. Coupling character line ° drive

548838 五、發明說明（52) 動器5 0 0之P -逋道上升電晶體5 〇1，以接收自耦合電路 1 8 0 0之V腻電壓。列位址解碼器丨6丨〇提供控制訊號& #與，其為由列位址解碼器丨5丨〇 (第五圖）提供之控制訊號& #與乂之倒轉。 j VBBC柄合電路1 8 0 0係與第七圖之耦合電路7〇〇互補。所以’如圖所示VBBC |馬合電路18〇〇包含n—通道電晶體igQi 一 1 8 0 3 ’ p-通道電晶體！ 8 〇 4與反用換流器j 8 i } 一 i 8 j 4。548838 V. Description of the invention (52) The P of the actuator 5 0-rises the transistor 5 0 1 to receive the voltage V of the self-coupling circuit 1 8 0 0. The column address decoder 丨 6 丨〇 provides the control signal &#, which is the reverse of the control signal &#and 提供 provided by the column address decoder 丨 5 丨〇 (fifth figure). j The VBBC handle circuit 1800 is complementary to the coupling circuit 700 of the seventh figure. So 'as shown in the figure, VBBC | Mahe Circuits 1800 contains n-channel transistors igQi-1 8 0 3' p-channel transistors! 8 〇 4 and inverter j 8 i} a i 8 j 4.

在活化字元線3 0 3之前，訊號XJ為高而訊號Xj為低。在這些情形下，電晶體1 6 〇 2被開啟，因而使用該Vdd供應電壓至電晶體5 0 1與5 〇 3之閘極。所以，下降電晶體5 〇 3開啟，因而提供該VBBS電壓至字元線3 〇 3。亦在此情形下，反用換々il夯1 8 11 - 1 8 1 4鏈提供一邏輯低訊號至節點n 1，因而開啟p-通迢電晶體1 8〇4。因此，該VBBC供應線係被保持於該 Vdd供應電壓。同樣地，在活化字元線3 〇 3之前，電晶體 1 8 0 2之a亥次6¾限漏損量將節點n 2拉升至電壓高於下一臨限電壓降（vt)，因而避免電晶體1801被開啟。Before activating the character line 3 03, the signal XJ is high and the signal Xj is low. In these cases, the transistor 16 2 is turned on, and thus the Vdd is used to supply a voltage to the gates of the transistors 51 and 5 03. Therefore, the falling transistor 503 is turned on, thereby supplying the VBBS voltage to the word line 303. Also in this case, the 1 8 11-1 8 1 4 chain is used to provide a logic low signal to the node n 1, so the p-pass transistor 1 804 is turned on. Therefore, the VBBC supply line is maintained at the Vdd supply voltage. Similarly, before activating the word line 3 〇3, the transistor 1 8 0 2 a 6 times limit leakage loss will pull node n 2 to a voltage higher than the next threshold voltage drop (vt), thus avoiding The transistor 1801 is turned on.

Xi #吼唬被驅動為低，且該訊號被驅動為高，以活化字，線303。在這些情形下，上升電晶體5〇1開啟，因而耦合字元線303至VBBC電壓耦合電路18〇〇。在電晶體5〇ι被開啟之後’该訊號Χ]之高狀態係經由反用換流器丨8丨丨—丨8丨4鏈傳迗，且未達節點N1。此時，p-通道電晶體丨8 〇 4持續開啟，搞合該VBBC供應線以接收該L供應電壓。亦同時，節點n 1之該低狀態將電容器耦合之電晶體18〇3之來源與排出拉至一低狀態。電晶體1 8 0 2之連接如一 MO S二極體及其閘極與排Xi #Roar is driven low and the signal is driven high to activate the word, line 303. In these cases, the rising transistor 501 is turned on, thereby coupling the word line 303 to the VBBC voltage coupling circuit 1800. After the transistor 50 is turned on, the high state of the signal X] is transmitted via the inverter 丨 8 丨丨丨 8 丨 4 chain and does not reach the node N1. At this time, the p-channel transistor 804 is continuously turned on, and the VBBC supply line is engaged to receive the L supply voltage. At the same time, the low state of node n 1 pulls the source and drain of the capacitor-coupled transistor 1803 to a low state. The connection of the transistor 1 8 0 2 is like a MO S diode and its gate and row.

第58頁 548838 五、發明說明（53) " ' 一----- 出連接至該vCCB供應線。電晶體1 8 0 2因而限制該電壓於節點 N2至不大於該八⑶電壓下之一臨限電壓（Vt )，或至潛在約等 =該V^d供應電壓。結果，電容器18〇3最初就被充電至一電壓約等於該vdd供應電壓（亦即該電壓橫過電晶體丨係約等於Vdd)。當該Xj訊號之高狀態達到節點N1，電晶^18()4· ，，因而自，vdd供應電壓終端解耦合該^⑶電壓供應線。於 2 之高電壓也造成電容器1 8 0 3，以拉升該節點N2至一包壓等於2Vdd。該節點Ν2之2Vdd電壓開啟η—通道電晶體 1801 ’因而耦合該ναΒ電壓供應線至該VBBC電壓供應線。雖然本案已利用多個實施例進行說明，但是可以理解的是^發明並不被所揭露的實施例所限制，其上可由熟知該技蟄之人士進行修飾而使用，但仍不脫離本發明之範圍。本發明之範圍如下列申請專利範圍所述。 _Page 58 548838 V. Description of the invention (53) " A ----- The output is connected to the vCCB supply line. Transistor 1 8 0 2 thus limits the voltage at node N2 to no more than a threshold voltage (Vt) under the eight CD voltage, or to a potential of approximately equal to the V ^ d supply voltage. As a result, the capacitor 1803 is initially charged to a voltage approximately equal to the vdd supply voltage (that is, the voltage across the transistor is approximately equal to Vdd). When the high state of the Xj signal reaches the node N1, the transistor ^ 18 () 4 ·, and therefore, the vdd supply voltage terminal is decoupled from the ^ CD voltage supply line. The high voltage at 2 also causes the capacitor 1 803 to pull up the node N2 to a package voltage equal to 2Vdd. The 2Vdd voltage of the node N2 turns on the n-channel transistor 1801 'and thus couples the ναB voltage supply line to the VBBC voltage supply line. Although this case has been described using multiple embodiments, it can be understood that the invention is not limited by the disclosed embodiments, and can be modified and used by those skilled in the art, but it still does not depart from the invention. range. The scope of the present invention is as described in the following patent applications. _

第59頁 548838 圖式簡單說明製作：圖’說明藉由利用-習用邏輯製程第-圖Β〜俜第：：體習所形成之用DRAM記憶胞元。 ^ /、禾一圖中該DRAM胞元之橫切剖面圖。弟一圖係一一 γ-, 包含-字元線驅動㈣一習用字元線控制電路，其锋一门勒為與一字元線電壓產生器。乐二圖 \ 传—.Τ\ Τ) * 1 案一實施例‘中+ @ t記憶胞元之概示圖，其係由根據本二_ ] T电壓來源所支援。第二圖8血第：r固厂之謂AM記憶胞元二之f根據本案不同實施例中第三圖A 寒二 /兀之检切面示意圖。胞元之i 圖係根據本案其他實施例中第三圖A該⑽^記憶迭階ί第三圖r係根據本案其他實施例中不同的製 “;t ’ —咖記憶胞元的橫切示意圖。元之粗:糸根據本案之一實施例中第三圖r之該dram胞 7G之粗略對背示意圖。造階I :圖A—第四圖J係根據本案其他實施例中不同的製 1中’一DRAM記憶胞元的橫切示意圖。造階段ΐ圖圖己=艮據本案其他實施例中不同的製 ^ ro ^ DRAM §己fe、胞元的橫切示意圖。四圖V之节回^弟四圖乂係根據本案不同實施例中，包含第胞元之陣列之對齊示意圖。回弟四圖ΑΑ係根據本案其他實施例中不同的制Page 59 548838 Schematic description of the drawing Production: Figure ′ illustrates the use of the custom logic process Figure-Figure B ~ 俜 :: DRAM memory cells formed by physical exercise. ^ /, A cross-sectional view of the DRAM cell in the first figure. This figure is a γ-, including-word line driver, a conventional word line control circuit, which is a front-to-back reference to a word line voltage generator.乐二图 \ 传 —.Τ \ Τ) * 1 A schematic diagram of the first embodiment of the ‘Medium + @ t memory cell, which is supported by a voltage source according to this II _] T. The second figure 8 is the blood cell: r solid factory, which is the AM memory cell two of f according to the third embodiment of the present embodiment of the third figure A Han Er / Wu cut-away schematic diagram. Figure i of the cell is based on the third graph A of the other embodiments of the present case. This memory sequence is used. Figure 3 r is a schematic cross-section of the memory cell according to the different systems in other examples of the present case. The thickness of the Yuan: According to the rough diagram of the dram cell 7G in the third figure r in one embodiment of the present case. Stage I: Figure A-The fourth figure J is based on different systems in other embodiments of the present case. A cross-sectional schematic diagram of a DRAM memory cell in the middle of the construction stage. Figure Schematic diagram = According to different systems in other embodiments of this case ^ ro ^ DRAM § cross-section schematic diagram of fe, cell. The fourth figure is a schematic diagram of the alignment of the array including the cells in different embodiments according to the present case. The fourth figure AA is based on different systems in other embodiments of the present case.

548838548838

548838 圖式簡單說明其係根據本案利用NMOS電晶體形成該DR AM胞元之一實施例。元件符號 1 : P-通道MOS存取電晶體 2 : p-通道MOS電晶體 3、3 0 3、4 7、4 1 2 :字元線 5、 305 :位元線 8 ： P -型基材 11 :閘極 14 、42 ^ 3011 • 17 :排出終端 18 :閘極終端 19 :輸出 21 • η- 型接觸區 40、100、3 0 0、3 0 0 0 ·· DRAM 胞元 4 1、3 0 6、3 0 1 0 : p型單晶矽基材 42 、 3111 : η-型槽區 4 4 :接觸ρ -型源極區 45、314、30 22 ··場氧化物（FOX)區 4 6 :閘極氧化物 4 7 ·多晶碎閑極電極 4 8 :氮化矽層 48A〜48C :氮化矽區 4 9 :氧化矽厚層548838 is a schematic illustration of an embodiment in which the DR AM cell is formed using an NMOS transistor according to the present case. Component symbol 1: P-channel MOS access transistor 2: p-channel MOS transistor 3, 3 0 3, 4 7, 4 1 2: word line 5, 305: bit line 8: P-type substrate 11: Gate 14, 42 ^ 3011 • 17: Discharge terminal 18: Gate terminal 19: Output 21 • η-type contact area 40, 100, 3 0 0, 3 0 0 0 ·· DRAM cell 4 1, 3 0 6, 3 0 1 0: p-type single crystal silicon substrate 42, 3111: η-type trench region 4 4: contact p-type source region 45, 314, 30 22 ·· field oxide (FOX) region 4 6: Gate oxide 4 7Polycrystalline broken electrode 4 8: Silicon nitride layer 48A ~ 48C: Silicon nitride region 4 9: Thick silicon oxide layer

第62頁 548838 圖式簡單說明 5 0、4 0 6、3 0 3 1 :多晶矽層 51 :多晶矽冠狀 5 1 A ·基礎區 51B :垂直壁 52 : ΟΝΟ結構 5 3、4 3 2 :多晶矽層 5 5 :活化Ρ +區域 5 6 A、5 6 Β、5 6 C :鈦石夕化物區域 5 7 ·多晶碎板結構 60 、 404 、 3024 :開口 2 0 0 :字元線控制電路 2 0 1 :字元線驅動器電路 211-217 > 501-502 ^ 701-703 '911 > 1001-1003 ^ 1103 、 120卜 1 2 0 2、1301、1 40 1 - 1 40 3、1 6 0 2 - 1 6 0 3、1 8 04 :p-通道電晶體 221- 229 :轉換器 231- 232 ：NAND 閘極 241 :N 0 R閘極 301 :P- 通道存取電晶體 302 :P- 通道儲存電晶體 304 • η- 摻雜槽 3 0 7、3 0 8 :薄閘極介電層 3 0 8 A :厚的閘極氧化物層 3 1 3 :上板P.62 548838 Brief description of the diagram 5 0, 4 0 6, 3 0 3 1: Polycrystalline silicon layer 51: Polycrystalline silicon crown 5 1 A · Basic area 51B: Vertical wall 52: ONO structure 5 3, 4 3 2: Polycrystalline silicon layer 5 5: Activated P + region 5 6 A, 5 6 B, 5 6 C: Titanium oxide compound region 5 7 Polycrystalline chip structure 60, 404, 3024: Opening 2 0 0: Word line control circuit 2 0 1 : Word line driver circuit 211-217 > 501-502 ^ 701-703 '911 > 1001-1003 ^ 1103, 120b 1 2 0 2, 1301, 1 40 1-1 40 3, 1 6 0 2- 1 6 0 3, 1 8 04: p-channel transistor 221-229: converter 231-223: NAND gate 241: N 0 R gate 301: P-channel access transistor 302: P-channel storage Crystal 304 • η- doped trench 3 0 7, 3 0 8: thin gate dielectric layer 3 0 8 A: thick gate oxide layer 3 1 3: upper plate

548838 圖式簡單說明 3 2 5 :絕緣側壁間隙 4 0 1 :薄氧化物層 4 0 2 :氮化矽層 4 0 3 :光阻層 4 0 5、3 0 2 5 ··凹處 406A :嵌壁式冠狀電極 4 0 6 L :基礎部分 4 0 6 S :側壁 4 0 6 U :上基礎部分 407 : p-型接觸區 408 :電容器介電層 4 0 9 :第二傳導摻雜多晶矽層 4 0 9 A :板電極 410、420、3 0 2 3、3 0 32 :光阻光罩 4 1 1 :閘極介電層 4 1 2 :傳導摻雜多晶矽閘極電極 413 、41 4 、4 1 7 、4 1 5 、4 1 6 、3 0 3 5 : {則壁間隙 4 1 8 :源極區 4 2 1 :耐熱金屬層 4 2 2、4 2 3 :金屬矽化物區 4 3 0 :接觸器 4 3 2 A :閘極電極 4 3 2 B :電容器板電極 5 0 0 :字元線驅動器548838 Brief description of the drawing 3 2 5: Insulating sidewall gap 4 0 1: Thin oxide layer 4 0 2: Silicon nitride layer 4 0 3: Photoresist layer 4 0 5, 3 0 2 5 · Recess 406A: Embedded Wall-type crown electrode 4 0 6 L: base part 4 0 6 S: side wall 4 0 6 U: upper base part 407: p-type contact region 408: capacitor dielectric layer 4 0 9: second conductive doped polycrystalline silicon layer 4 0 9 A: plate electrodes 410, 420, 3 0 2 3, 3 0 32: photoresist mask 4 1 1: gate dielectric layer 4 1 2: conductively doped polycrystalline silicon gate electrodes 413, 41 4 and 4 1 7, 4 1 5, 4 1 6, 3 0 3 5: {then wall gap 4 1 8: source region 4 2 1: heat-resistant metal layer 4 2 2, 4 2 3: metal silicide region 4 3 0: contact 4 3 2 A: Gate electrode 4 3 2 B: Capacitor plate electrode 5 0 0: Word line driver

第64頁 548838 圖式簡單說明 503-505 >704 >921 >1101-1102 >1204-1206 >1411-1414、1604、1801-1803 :n -通道電晶體 5 1 0、1 6 1 0 :位址解碼器 6 0 0 :字元線驅動器系統 7 0 0 : VSSB耦合電路 7 11 - 7 1 4、1 8 Η - 1 8 1 4 :反用換流器 800 VeeB電壓產生器 801 壞狀振動為 802 充電幫浦 803 幫浦控制器 900 vBBS電壓產生器 901 充電幫浦控制電路 911 耦合電晶體 912、9 2 2、1 0 04- 1 0 0 5、1 1 04- 1 1 0 5 :參考電流來源 1 0 0 0 : VeeB充電幫浦控制電路 I 0 2 3、1 4 3 1 :電阻器 II 0 0 : vBBS充電幫浦控制電路 1 42 1 - 1 422 : PNP兩極電晶體 1 5 0 1 :電晶體 1 6 0 0、1 7 0 0 :參考電流電路P.64 548838 Brief description of drawings 503-505 > 704 > 921 > 1101-1102 > 1204-1206 > 1411-1414, 1604, 1801-1803: n-channel transistors 5 1 0, 1 6 1 0: Address decoder 6 0 0: Word line driver system 7 0 0: VSSB coupling circuit 7 11-7 1 4, 1 8 Η-1 8 1 4: Inverter 800 VeeB voltage generator 801 The bad vibration is 802 charging pump 803 pump controller 900 vBBS voltage generator 901 charging pump control circuit 911 coupling transistor 912, 9 2 2, 1 0 04- 1 0 0 5, 1 1 04- 1 1 0 5: Reference current source 1 0 0 0: VeeB charge pump control circuit I 0 2 3, 1 4 3 1: Resistor II 0 0: vBBS charge pump control circuit 1 42 1-1 422: PNP bipolar transistor 1 5 0 1: Transistor 1 6 0 0, 1 7 0 0: Reference current circuit

第65頁 1800 VBBe耦合電路 3 0 2 1 氧化物層 3 0 2 6 電容器區 3 0 3 0 閘極介電層 548838 圖式簡單說明 3 0 3 1 A :閘極電極層 3 0 3 1 B :電容器電極 3 0 3 1 C :多晶矽部分 3 0 3 3 :輕掺雜p型沒極區 3 0 3 4 :輕摻雜p型源極區 3 0 3 6 : P+汲極區 3 0 3 7 :介電層 3 0 3 8 :矽化物阻礙光阻光罩 3039 :耐火的金屬層 3041、3042、3043 :金屬矽化物區 3 0 5 0 :接觸器 3 0 7 0 :重線 I R · 電流Page 65 1800 VBBe coupling circuit 3 0 2 1 Oxide layer 3 0 2 6 Capacitor area 3 0 3 0 Gate dielectric layer 548838 Brief description of the diagram 3 0 3 1 A: Gate electrode layer 3 0 3 1 B: Capacitor electrode 3 0 3 1 C: Polycrystalline silicon portion 3 0 3 3: Lightly doped p-type electrodeless region 3 0 3 4: Lightly doped p-type source region 3 0 3 6: P + drain region 3 0 3 7: Dielectric layer 3 0 3 8: Silicide blocking photoresist mask 3039: Refractory metal layer 3041, 3042, 3043: Metal silicide area 3 0 5 0: Contactor 3 0 7 0: Heavy line IR · Current

第66頁Page 66

Iref 、Irefni · 參考電流 N1 、N2、VN :節點 V!: :最高電壓 vbb :負極升高電壓 vbbl :負極升高偏壓電壓 vbd :分解電壓 vb_t+、vCCB :正極升高電壓 vdd 、Vss :供應電壓 Vt 、Vtp :臨限電壓 VPP :極板偏壓電壓 Vpp! :升高正極電壓 548838 圖式簡單說明 vSSB :字元線電壓第67頁Iref, IrefniReference currents N1, N2, VN: Node V! :: Highest voltage vbb: Negative boost voltage vbbl: Negative boost bias voltage vbd: Breakdown voltage vb_t +, vCCB: Positive boost voltage vdd, Vss: Supply Voltages Vt, Vtp: Threshold voltage VPP: Plate bias voltage Vpp !: Raise the positive voltage 548838 Schematic illustration vSSB: Word line voltage page 67

Claims

548838 六、申請專利範圍 1之；！形ίΠ—存取電晶體與一電容器結構之dram胞元万法该方法包含之步驟為：形成一場介電質於具有一第一莫帝中，嗲塥人+併支之一半導體基材 /亥％ "電質延伸於該半導體基材之一上表面；成：：J:，場介電質中，#中該凹處延伸於該上表形成一 ΐ 土衣面下暴露該半導體基材之-側壁部分，部電層於該半導體基材之該上表面與該侧壁形成一電極層於該第一介電層上，以及 :案化該電極層，以形成一電容導體某鉍夕〜Γ L „ 具延伸於该半少部該侧壁部分之上，_器電極至刀凹1又該+導體基材之該上表面下。 2 ·如申請專利範圍第i項中之方法，更層，以带士、分— 已b固案化该電極以形成该存取電晶體之一閘極電極。 3電ϋ ί二利f ”2項中之方法，其中該閘極電極與該 4如；：鼻j丨!!、错由該第一介電層自該半導體基材分隔。 /甲明專利範圍第3項中之方法，更包含： _ 二ΐϊ:第二介電層於該半導體基材之該上表面上，該第 —二=層具有一不同於該第一介電層之組成或厚度，及 >成該電極層於該第一介電層與該第二介電層之上，以之=匕；電極層’於該第二電極層上形成-邏輯電晶體 ^ 閘極電極。548838 6. Scope of patent application 1 Shape Π—Dram cell method for accessing a transistor and a capacitor structure The method includes the steps of: forming a field dielectric in a semiconductor substrate having a first Motif, and a parallel + The electric substance extends on the upper surface of one of the semiconductor substrates; into: J :, the field dielectric, the recess in # extends to the upper surface to form a stack, and the semiconductor substrate is exposed under the soil coat surface Material-side wall portion, an electrical layer is formed on the upper surface of the semiconductor substrate and the side wall to form an electrode layer on the first dielectric layer, and the electrode layer is formed to form a capacitor conductor of bismuth Evening ~ Γ L „has an extension above the semi-small portion and the side wall portion, the device electrode to the knife recess 1 and the + conductor substrate under the upper surface. 2 · As the method in the scope of the application for the patent i In addition, the electrode is solidified to form one of the gate electrodes of the access transistor. The method of 2 items in "2", wherein the gate electrode and The 4 is as follows: the nose is separated from the semiconductor substrate by the first dielectric layer. The method in item 3 of the Jiaming patent scope further includes: _ Er: the second dielectric layer is on the upper surface of the semiconductor substrate, and the −2 = layer has a different dielectric from the first dielectric The composition or thickness of the layer, and > the electrode layer is formed on the first dielectric layer and the second dielectric layer, with ==; the electrode layer is formed on the second electrode layer-a logic transistor ^ Gate electrode.

第68頁 1 .如申請專利範圍第1項中之方法，更包含： 548838 六、申請專利範圍形成一第二介電層於該半導體基材之該上表面上，該第二介電層具有一不同於該第一介電層之組成或厚度，形成該電極層於該第一介電層與該第二介電層之上，以及圖案化該電極層，以形成該存取電晶體之該電容器電極與一閘極電極，其中該電容器電極係位於該第一介電層上，且該閘極電極係位於該第二介電層上。 6 ·如申請專利範圍第1項中之方法，其中形成該凹處之步驟更包含：形成一光罩，其具有一開口位於該半導體基材之該侧壁部分上，經由該光罩之該開口，蝕刻該場介電質，因而形成該凹處，以及經由該光罩植入一雜質至該半導體基材中，其中該雜質調節該電容器結構之一臨限電壓。 7. 如申請專利範圍第2項中之方法，更包含：在形成該閘極電極與該電容器電極之後，進行一植入以形成一輕摻雜源極區於該閘極電極與該電容器電極之間，以及鄰近該閘極電極之一輕摻雜汲極區，以及形成一側壁間隙，其覆蓋於該輕摻雜源極區之上。 8. 如申請專利範圍第7項中之方法，更包含：形成金屬矽化物於該閘極電極上，以及避免金屬矽化物形成於該輕摻雜源極區之上。 9. 如申請專利範圍第7項中之方法，更包含：Page 68 1. The method in item 1 of the scope of patent application, further comprising: 548838 6. The scope of the patent application forms a second dielectric layer on the upper surface of the semiconductor substrate, and the second dielectric layer has A composition or thickness different from the first dielectric layer, forming the electrode layer on the first dielectric layer and the second dielectric layer, and patterning the electrode layer to form the access transistor The capacitor electrode and a gate electrode, wherein the capacitor electrode is located on the first dielectric layer, and the gate electrode is located on the second dielectric layer. 6. The method as described in item 1 of the patent application range, wherein the step of forming the recess further comprises: forming a photomask having an opening on the sidewall portion of the semiconductor substrate, and passing the photomask through the Opening, etching the field dielectric, thereby forming the recess, and implanting an impurity into the semiconductor substrate through the photomask, wherein the impurity regulates a threshold voltage of the capacitor structure. 7. The method in item 2 of the scope of patent application, further comprising: after forming the gate electrode and the capacitor electrode, performing an implantation to form a lightly doped source region between the gate electrode and the capacitor electrode And a lightly doped drain region adjacent to the gate electrode, and a sidewall gap is formed to cover the lightly doped source region. 8. The method in item 7 of the scope of patent application, further comprising: forming a metal silicide on the gate electrode, and preventing the metal silicide from forming on the lightly doped source region. 9. If the method in item 7 of the scope of patent application, further includes:

第69頁 548838 六、申請專利範圍 J f t矽化物於該閘極電極上，以及 10.如t # 物形成於該電容器電極上。在开士乾圍第7項中之方法，更包含. 在形成該側壁間隙 # _ S · 摻雜汲極區之—會狹，仃一弟二植入以形成連接該_ 、槐1 重摻雜汲極區，以及丧d 1工避免該第二棺人、去， _ 1 1如由主宙達到该輕摻雜源極區。 L如申睛專利範圍第i項中之方法，含II化石夕。 /、T邊弟一介電層包 1 2 · —種動態隨一半導舻λ!钱存記憶體（DRAM)胞元，其包含：材’其具有-第-導電型，其中具有一凹_ 了係位於該半導體基材之一上表面下，且導體基材之一=壁處延伸於該上表面下，且暴露該半與該半導體美=層，其係位於該半導體基材之該側壁部分一帝交的;! 之—相鄰上表面上，電層之下；一兩2糸位於該半導體基材中而在該電容器介上，其中該電Iΐ器閘極，其係位該該電容器介電層之一閘極^帝:器電極之一部份係延伸於該凹處中’ 一閘極電^ ^点其係該半導體基材之該上表面上；一具有第—成於該閘極介電層上；以及閘極電極與電$，型之源極區，其係位於該半導體基材中器區。扣氣極之間，其中該源極區係連接該電容 1 3 ·如申請專利已㈤第1 2項中之DRAM胞元，其中該電容器Page 69 548838 VI. Scope of patent application J f t silicide on the gate electrode, and 10. If t # is formed on the capacitor electrode. The method in item 7 of Kaishiganwei further includes. In forming the sidewall gap # _ S · doped drain region-will be narrow, and implanted to form a connection to the _, Huai 1 re-doped The miscellaneous drain region, as well as the d1, avoids the second coffin, and _11, if the light doped source region is reached by the host. The method described in item i of the patent application scope contains II fossils. /, T side brother a dielectric layer package 1 2-a kind of dynamics with half the lead λ! Money memory (DRAM) cell, which contains: material 'it has-the first-conductive type, which has a concave _ It is located under the upper surface of one of the semiconductor substrates, and one of the conductor substrates = the wall extends below the upper surface, and the half and the semiconductor beauty layer are exposed, which is located on the sidewall of the semiconductor substrate Part of the cross;!-On the adjacent upper surface, below the electrical layer; one or two 糸 is located in the semiconductor substrate and on the capacitor dielectric, wherein the gate of the electric device is located where A gate electrode of a capacitor dielectric layer: a part of the device electrode extends in the recess' a gate electrode ^ ^ is on the upper surface of the semiconductor substrate; The gate dielectric layer; and a gate electrode and a source region of the type, which are located in the semiconductor region of the semiconductor substrate. Between the degassing electrodes, where the source region is connected to the capacitor 1 3 · If the patent application has been applied to the DRAM cell in item 12 where the capacitor

548838 六、申請專利範圍介電層與該間極介電層為相同層如申請專利範圍第12項 RAM 電層與該間極介電層具有不同的組成或厚度電μ =.1如申請專利範圍第12項中之DRAM胞元’更包含第二導 i S之一沒極區，其係位於該半導體基材中與該閘極電極 1齊’該沒極區具有較該源極區更高之摻雜濃度。 1 6·如申請專利範圍第1 5項中之dram胞元，更包含金屬石夕化物’其係位於該閘極電極與該汲極區上。其中該源極區其中該電容器其中該閘極電 U·如申請專利範圍第16項中之DRAM胞元貫質上無金屬石夕化物。 18·如申請專利範圍第16項中之DRAM胞元電極實質上無金屬矽化物。 19·如申請專利範圍第12項中之DRAM胞元極與該電容器電極包含多晶矽。其中該閘極電晶碎層 20·如申請專利範圍第19項中之DRAM胞元極與5亥電谷态電極之製造，係來自同一多 ^ 2 1 · —種記憶體系統，其係因應一正極供應電壓與一接地供應電壓而運作，該記憶體系統包含：一動態隨機存取記憶體（DRAM)胞元，其具有一存取雷曰體與一電谷器結構，其中該電容器結構至少部分形成一處中’其係形成於一場介電區中，一字兀線輕合至該閘極電極，其中該字元線被活取該DRAM胞元， # 一字元線驅動器耦合至該字元線，以及548838 VI. The range of patented dielectric layer is the same layer as the interlayer dielectric layer. For example, the range of patent application No. 12 RAM dielectric layer and the interlayer dielectric layer have different compositions or thicknesses. The DRAM cell in the range item 12 further includes a non-polar region of the second conductive region, which is located in the semiconductor substrate and is aligned with the gate electrode 1. The non-polar region has a greater area than the source region. High doping concentration. 16. The dram cell in item 15 of the scope of the patent application, further comprising a metal oxide, which is located on the gate electrode and the drain region. Wherein the source region, the capacitor, and the gate electrode U. As in the DRAM cell in item 16 of the patent application, there is no metal oxide. 18. The DRAM cell electrode as described in item 16 of the scope of patent application is substantially free of metal silicide. 19. The DRAM cell and the capacitor electrode as described in item 12 of the patent application range include polycrystalline silicon. Among them, the gate electrode crystal layer 20 · As in the manufacture of the DRAM cell electrode and the 5H valley electrode in the 19th scope of the application for patent, it is from the same memory system. Operated in response to a positive supply voltage and a ground supply voltage, the memory system includes: a dynamic random access memory (DRAM) cell having an access thunder body and a valley device structure, wherein the capacitor The structure is formed at least partially in a place, which is formed in a field dielectric region, and a word line is lightly closed to the gate electrode, wherein the word line is taken from the DRAM cell, and a word line driver is coupled. To the character line, and

548838 六、申請專利範圍一正極升高電壓產生器，以提供正極升高電 J供應電壓’且小於一大於該正極供應電麼：反大於該正 =，該正極升高電壓產生器可被耦合至謗 I極體電壓 :如曱。請寻利範圍第21項，之記憶體系統，兑复驅動器。 Γ驅動器包含一p-通道電晶體耦合於該字元線、中該字元 :繼生器之間，以及1-通道電晶體升 23. 如申請專利範圍第22 極升高電壓產生器、，以提供一小上=統，更包含-負 ?高電塵，該負極升高電壓產生器係=屢之負極态。芏邊予元線驅動其中該負極一極體電壓更包含 24. 一如申請專利範圍第23項中之記憶體系統，升南電壓係小於該接地供應電壓，而降之絕對差值。 / ' ; 25·如申請專利範圍第23項中之記憶合電路’其耦合於該字元線驅動器鱼’、、，· ’更^包含一耦器之間，當該字元線首先被活化時了^負^向電壓產生接地供應電壓至該字元線驅動器，杏^ j 路係提供該至該正極供應電壓之下時，該耦合；f ::線之電壓下降極升高電壓至該字元線驅動器。。路更係用以提供該負其中該耦合 §與一提供該 26.如申請專利範圍第25項電路包含：心^體系統第一電晶體，其係耦合於該字接地供應電壓之終端間，凡、、表驅ί 第72頁 548838 々、申請專利範圍一第二電晶體，其係耦合於該字元線驅動器與該負極升南電壓產生器之間’以及一延遲鏈，其係耦合於該第一電晶體之一閘極。 2 7 ·如申請專利範圍第2 6項中之記憶體系統，更包含：一電容器，其係耦合於該延遲鏈與該第二電晶體之一閘極間，以及一二極體元件，其係耦合於該第二電晶體之該閘極與該負極升高電壓產生器之間。548838 6. Scope of patent application-a positive voltage boost generator to provide the positive voltage J supply voltage 'is less than one greater than the positive voltage supply: inversely greater than the positive =, the positive voltage boost generator can be coupled To slander I polar body voltage: such as 曱. Please find the memory range of item 21, Redeem the drive. The Γ driver includes a p-channel transistor coupled to the word line, between the word: the relay, and the 1-channel transistor. 23. For example, the 22nd pole voltage booster, In order to provide a small system, it also includes-negative-high electric dust, the negative voltage riser generator system = repeated negative state. Bianyuan Yuyuan Line Drive The negative-polarity voltage includes 24. As in the memory system in the 23rd scope of the patent application, the south voltage is smaller than the ground supply voltage, and the absolute difference is reduced. / '; 25 · If the memory circuit in item 23 of the scope of the patent application' is coupled to the character line driver fish ',,,,,,,', and more, it includes a coupler, when the character line is first activated When the negative voltage is applied, the ground supply voltage is generated to the word line driver. When the circuit is provided below the positive supply voltage, the coupling; the voltage drop of the f: line increases the voltage to the Word line driver. . The circuit is used to provide the negative wherein the coupling § and one to provide the 26. For example, the circuit in the 25th scope of the patent application includes: the first transistor of the core body system, which is coupled between the terminals of the word ground supply voltage Fan, table drive, page 72, 548838 (2), a patent application scope a second transistor, which is coupled between the word line driver and the negative south voltage generator, and a delay chain, which is coupled to A gate of the first transistor. 27. If the memory system in item 26 of the patent application scope further includes: a capacitor, which is coupled between the delay chain and a gate of the second transistor, and a diode element, which It is coupled between the gate of the second transistor and the negative boosted voltage generator.

2 8.如申請專利範圍第2 3項中之記憶體系統，更包含一耦合電路，其耦合於該η-通道電晶體與該負極升高電壓產生器之間，當該字元線被活化時，該耦合電路耦合該負極升高產生器至該η_通道電晶體，而當該字元線未被活化時，該耦合電路係用以提供該接地供應電壓至該η-通道電晶體。 2 9. —種記憶體系統，其係因應一正極供應電壓與一接地供應電壓而運作，該記憶體系統包含：一動態隨機存取記憶體（DRAM)胞元，其具有一存取電晶體與一電容器結構；其中該電容器結構至少部分形成一凹處中’其係形成於一場介電區中，2 8. The memory system in item 23 of the patent application scope further includes a coupling circuit coupled between the η-channel transistor and the negative voltage booster. When the word line is activated, At this time, the coupling circuit couples the negative boost generator to the n-channel transistor, and when the word line is not activated, the coupling circuit is used to provide the ground supply voltage to the n-channel transistor. 29. A memory system that operates in response to a positive supply voltage and a ground supply voltage. The memory system includes: a dynamic random access memory (DRAM) cell with an access transistor And a capacitor structure; wherein the capacitor structure at least partially forms a recess, which is formed in a field dielectric region,

一字元線耦合至該DRAM胞元，其中該字元線被活化以存取該DRAM胞元；一字元線驅動器耦合至該字元線；以及一負極升高電壓產生器，以提供負極升高電壓小於該接地供應電壓，且有一電壓小於二極體電壓降之絕對差值，A word line is coupled to the DRAM cell, wherein the word line is activated to access the DRAM cell; a word line driver is coupled to the word line; and a negative voltage booster is provided to provide a negative electrode. The rising voltage is less than the ground supply voltage, and there is a voltage less than the absolute difference between the diode voltage drops,

第73頁 548838 :申讀圍 " ' '〜 --- 30 ^讀負極升高電壓產生器可被耦合至該字元線驅動器。線驅H請Λ利範圍第29項中之記憶體系統’其中該字元高電康===η''通運電晶體耦合於該字元線與該負極升線。\ y主二态之間，以及一Ρ—通道電晶體耦合於該字元 3々二專之記憶體系統，更包含一正升高電塵Γ 7 Τ Γ以供一大於忒正極供應電壓之正極器。 Μ極升高電壓產生器係耦合至該字元線驅動其中該正極 -二極體電壓更包含一麵 3升2高\申上專/]範圍第31項中之記憶體系統，降之絕=於該正極供讀，而有小於· 3 3 ί電：申ϊ = = 憶體系統，$包含-搞 d，、當該字元線被活t::曰ί:::極升高電壓產生 :時，該輕合電路；當該字元線未被活巧。 “、4正極供應電壓至該Ρ-通道電晶 •如申凊專利範圍合電路，其轉合於該弟31項中之記憶體系統，更包器之間’當該字元線m驅動器與該正極升高電壓產生正極供應電覆至該字元線；=時而：耦合電路係；供該接地供應電壓之上時動；二該字元線之電壓上極“電麼至該字元線驅動;电路更係用以提供該第74頁 548838 六、申請專利範圍 3 5.如申請專利範圍第3 4項中之記憶體系統，其中該耦合電路包含：一第一電晶體，其係耦合於該字元線驅動器與一提供該正極供應電壓之終端間，一第二電晶體，其係耦合於該字元線驅動器與該正極升高電壓產生器之間，以及一延遲鏈，其係耦合於該第一電晶體之一閘極。 3 6.如申請專利範圍第3 5項中之記憶體系統，更包含：一電容器，其係耦合於該延遲鏈與該第二電晶體之一閘極間’以及一二極體元件，其係耦合於該第二電晶體之該閘極與該正極升高電壓產生器之間。Page 73 548838: Application reading " '' ~ --- 30 ^ Reading negative boost voltage generator can be coupled to the word line driver. The line driver H asks the memory system in item 29 of the scope of the above description, wherein the character Gao Diankang === η '', a transport transistor is coupled to the character line and the negative line. \ y between the main two states, and a P-channel transistor is coupled to the character 3.2 memory system, and further includes a positive rise of the electric dust Γ 7 Τ Γ for a voltage greater than the positive electrode supply voltage Positive device. The M-pole boosted voltage generator is coupled to the word line driver, wherein the positive-diode voltage further includes a side of 3 liters, 2 highs, and a memory system in item 31 of the scope, which is extremely rare. = For reading at this positive electrode, and there is less than · 3 3 ί electricity: Shen ϊ = = memory system, $ contains-engage d, when the character line is activated t :: Yue ::: pole voltage Generated: when the light-on circuit; when the word line is not active. ", 4 positive supply voltage to the P-channel transistor. If the patent application range of the circuit is combined, it is transferred to the memory system in the 31 items of this brother. The rising voltage of the positive electrode generates a positive supply voltage to the word line; = from time to time: the coupling circuit system; for moving above the ground supply voltage; the voltage of the word line is "to the word" Line drive; the circuit is also used to provide the page 74 548838 6. Application for patent scope 3 5. The memory system according to item 34 of the patent application scope, wherein the coupling circuit includes: a first transistor, which is Coupled between the word line driver and a terminal providing the positive supply voltage, a second transistor, which is coupled between the word line driver and the positive boost voltage generator, and a delay chain, which Is coupled to a gate of the first transistor. 36. The memory system according to item 35 of the scope of the patent application, further comprising: a capacitor coupled between the delay chain and a gate of the second transistor, and a diode element, which It is coupled between the gate of the second transistor and the positive boost voltage generator.

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