548802 五、發明說明（1) 發明領域： 本發明係有關於半導體DRAM電容製程，特別是指一種 利用深N W ( η型井）做為電容之一電極的製程方法。 發明背景： 電腦和電子工業不僅要求增加其整體之性能表現並且 也在乎製造整體積體電路之成本的降低。就電腦而言，無 疑的D R A Μ佔有一決定性的角色。因為D R A Μ不只是大量使 用，且也關係著電腦之輸出入的速度表現。且由於D R A Μ使 用量大，競爭者眾，因此，業者需不斷追求成本之降低， 及其高速的表現，而最為關鍵的是DRAM的微小化製程。那 怕只是減少一微影步驟，可以創造相同之密度，都是D R A Μ 製程工程師必須追求的目標之一。 嵌入式DRAM更是最近DRAM製造的一種流行趨勢。這是 因為嵌入式DRAM係將DRAM區和邏輯區同時形成於一單一晶 片之中，因此，在存取大量的資料時可以提供非常快的速 度。此夕卜，DRAM電容愈大，代表相同的再新時間下 (refresh time)，電容所保有之資料可靠度愈高。因此， 一般而言，為增加電容量，平面式電容製程僅可能在愈小 面積上往上發展，但這會面臨高深寬比值，導致蝕刻上的 困難。另一種電容則是利用溝渠式電容。溝渠式電容由於548802 V. Description of the invention (1) Field of the invention: The present invention relates to the manufacturing process of semiconductor DRAM capacitors, in particular to a manufacturing method using deep NW (n-well) as one electrode of a capacitor. BACKGROUND OF THE INVENTION The computer and electronics industries not only require increased overall performance, but also reduced the cost of manufacturing integrated circuits. As far as computers are concerned, DRMA is undoubtedly a decisive player. Because D R A M is not only used in large quantities, but also related to the speed performance of computer input and output. In addition, due to the large amount of D R A MM and the large number of competitors, the industry must continue to pursue cost reduction and high-speed performance, and the most critical is the miniaturization process of DRAM. Even if it only reduces one lithography step, it can create the same density, which is one of the goals that DRAM process engineers must pursue. Embedded DRAM is a popular trend in DRAM manufacturing recently. This is because the embedded DRAM forms the DRAM area and the logic area on a single chip at the same time, so it can provide very fast speed when accessing a large amount of data. Moreover, the larger the DRAM capacitance, the higher the reliability of the data held by the capacitance at the same refresh time. Therefore, in general, in order to increase the capacitance, the planar capacitor process can only be developed on a smaller area, but this will face high aspect ratio values, which will cause difficulties in etching. Another type of capacitor is a trench capacitor. Trench capacitor due to
第4頁 548802 五、發明說明（3) 保護層，形成於溝渠内及半導體基板的閘極氧化層上。 若是使用光阻，則可利用光罩圖案，部分曝光方式使溝渠 上角落之閘極氧化層裸露（即溝渠内接近開口部分之側壁 的閘極氧化層及溝渠上方邊緣部分），以定義電容節點。 當然，如果是以抗反射塗層做為一保護層需再形成一光阻 圖案，罩幕半導體基板上的閘極氧化層而只裸露上述溝渠 上角落之閘極氧化層。隨後，再施以回蝕刻，以蝕刻裸露 之閘極氧化層，以光阻（或以抗反射塗層）為罩幕。 在去除其餘之保護層後，回填複晶矽層於溝渠内填滿 之，並溢出半導體基板之上表面。緊接著，以光阻圖案及 蝕刻技術定義電容之底部極板及複晶閘極。隨之，施以 N L D D離子佈植以形成源/汲極區；再形成間隙壁層複晶閘 極之側壁及該電容底部極板之側壁上，該電容底部極板側 壁係露出溝渠之部分。再施以源/汲極區離子佈植。再以 退火製程活化離子。之後，沉積内連線介電層以覆蓋所有 區域；再以光阻圖案及蝕刻技術定義接觸洞於内連線介電 層之中最後回填金屬層於接觸洞内，再以光阻圖案及蝕刻 技術定義該金屬層以形成源/汲極區及電容頂部極板之連 接接觸。 發明詳細說明： 本發明之DRAM製程請參考圖一。首先以傳統製程方法Page 4 548802 V. Description of the invention (3) A protective layer is formed in the trench and on the gate oxide layer of the semiconductor substrate. If a photoresist is used, a mask pattern can be used to partially expose the gate oxide layer on the upper corner of the trench (ie, the gate oxide layer on the side wall near the opening in the trench and the upper edge of the trench) to define the capacitor node. . Of course, if an anti-reflection coating is used as a protective layer, a photoresist pattern must be formed again, and the gate oxide layer on the semiconductor substrate is covered, and only the gate oxide layer on the upper corner of the trench is exposed. Subsequently, an etch-back is performed to etch the exposed gate oxide layer, and a photoresist (or an anti-reflective coating) is used as a mask. After the remaining protective layer is removed, the backfilled polycrystalline silicon layer is filled in the trench and overflows the upper surface of the semiconductor substrate. Then, the bottom plate and the complex gate of the capacitor are defined by the photoresist pattern and the etching technology. Subsequently, N L D D ion implantation is applied to form a source / drain region; and then, a sidewall of the barrier plexer gate and a sidewall of the capacitor bottom plate are formed, and a side wall of the capacitor bottom plate exposes a trench. The source / drain region is implanted with ions. The ions are activated by an annealing process. After that, an interconnect dielectric layer is deposited to cover all areas. Then, a photoresist pattern and an etching technique are used to define a contact hole in the interconnect dielectric layer. Finally, a metal layer is backfilled in the contact hole, and then the photoresist pattern and etching are used. The technology defines the metal layer to form a connection contact between the source / drain region and the top plate of the capacitor. Detailed description of the invention: Please refer to FIG. 1 for the DRAM process of the present invention. Traditional process
第6頁 548802 五、發明說明（5) 為罩幕來完成。其中電容溝渠14 0之底部需形成於深η型井 1 3 0之中，且以隔離區1 1 0為分隔區。 請參考圖三，以高溫的熱氧化製程，例如9 0 0 - 1 0 0 0°C 形成一厚約 3 0 - 1 0 0埃的閘極氧化層1 5 0於溝渠1 4 0之側 壁、底部及半導體基板上表面。再形成一光阻16 0於該半 導體基板10 0上，並填滿電容溝渠1 4 0。隨後，利用光罩部 分曝光及顯影技術，以使電容溝渠1 4 0上角落，即接近開 口之部分侧壁的閘極氧化層及電容溝渠1 4 0上方邊緣部分 之半導體基板上的閘極氧化層1 5 0 a裸露，以定義電容節 點。本步驟也可以以底部抗反射塗層（BARC) 1 60懸塗於所 有區域並填滿電容溝渠1 4 0。隨後’利用光阻再進行回 蝕，以露出閘極氧化層1 5 0 a。 請參考圖四所示的橫載面示意圖。以濕式蝕刻法，將 外露且沒有受到B A R C或光阻1 6 0保護之閘極氧化層1 5 0 al虫 刻去除。緊接著，去除溝渠内的BARC1 60或光阻1 60，再回 填複晶矽層1 6 5於電容溝渠1 4 0内填滿之，並溢出半導體基 板1 0 0之殘餘閘極氧化層1 5 0上。此時，再施以平坦化製 程，例如化學/機械式研磨製程，以得到平坦表面。不過 此一平坦化製程，是選擇性的，可以直接跳至下一步驟。 請參考圖五所示的橫截面示意圖。再以光阻圖案及蝕刻技 術定義電容之底部極板1 8 0及複晶閘極1 7 0。利用溝渠上角 落邊緣（原裸露之閘極氧化層1 5 0 a區。請注意上述閘極氧 化層1 5 0除了提供電晶體的閘極氧化層1 5 0 b外，也提供電Page 6 548802 V. Description of the invention (5) Completed for the curtain. The bottom of the capacitor trench 140 needs to be formed in a deep n-type well 130, and the isolation region 110 is used as a separation region. Please refer to FIG. 3, using a high-temperature thermal oxidation process, for example, 9 0-1 0 0 0 ° C to form a gate oxide layer 150 having a thickness of about 3 0-1 0 0 angstroms on the side walls of the trench 1 4 0, Bottom and top surface of semiconductor substrate. A photoresist 160 is formed on the semiconductor substrate 100 and fills the capacitor trench 140. Subsequently, a photomask partial exposure and development technology is used to oxidize the gate oxide layer on the upper corner of the capacitor trench 140, that is, the gate oxide layer on the side wall near the opening and the gate substrate on the upper edge of the capacitor trench 140. Layer 150a is exposed to define the capacitor node. In this step, a bottom anti-reflection coating (BARC) 1 60 can also be used to overhang all areas and fill the capacitor trench 1 40. Subsequently, a photoresist is used to etch back to expose the gate oxide layer 150a. Please refer to the schematic diagram of the cross section shown in Figure 4. Using wet etching, the gate oxide layer 150 a, which is not exposed to B A R C or photoresist 160 protection, is removed by etching. Next, remove the BARC1 60 or photoresist 1 60 in the trench, and then backfill the polycrystalline silicon layer 1 6 5 in the capacitor trench 1 4 0 and overflow the residual gate oxide layer 1 5 of the semiconductor substrate 1 0 0 0 on. At this time, a planarization process such as a chemical / mechanical polishing process is performed to obtain a flat surface. However, this flattening process is optional, and you can skip to the next step. Please refer to the schematic diagram of the cross section shown in Figure 5. The photoresist pattern and etching technology are used to define the bottom plate 180 of the capacitor and the 170 multiplex gate. Utilize the upper corner of the trench and the falling edge (the area of the original exposed gate oxide layer 150a. Please note that the gate oxide layer 150 above provides the gate oxide layer 150b of the transistor and also provides electricity.
第8頁 548802 五、發明說明（7) 區及頂部電極的接觸位置，即第二η型井1 3 5的區域。緊接 著再施以蝕刻技術，而形成接觸洞。最後，以金屬例如鎢 填入接觸洞内並溢出至表面，再以另一光阻圖案及蝕刻技 術定義以形成源/汲極區接觸2 0 0 a及頂部電極2 0 0 b的連 接。請注意電容頂部電極係深η井區。Page 8 548802 V. Description of the invention (7) The contact position of the area and the top electrode, that is, the area of the second n-type well 135. Immediately afterwards, an etching technique is applied to form a contact hole. Finally, a metal such as tungsten is filled into the contact hole and overflows to the surface, and then another photoresist pattern and an etching technique are used to define the connection between the source / drain region contact 200a and the top electrode 200b. Note that the top electrode of the capacitor is in a deep n-well area.
以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.
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548802 圖式簡單說明 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列圖形 做更詳細的闡述： 圖一顯示半導體基板形成淺溝渠隔離區後以不同能量之離 子佈植，形成深度較淺的R型井及較深度較深之η型井。 圖二顯不形成以淺溝渠隔離區分隔之二溝渠於半導體基板 内的橫截面示意圖。 圖三顯示以高溫的熱氧化製程，形成一閘極氧化層後，再 以光阻或抗反射塗層做為一保護層，形成於溝渠内及半導 體基板的閘極氧化層上並裸露溝渠上角落之閘極氧化層的 橫截面示意圖。 圖四顯示去除裸露之閘極氧化層，接著去除保護層，然 後，再沉積複晶石夕層以填滿溝渠的橫載面示意圖。 圖五顯示以光阻及蝕刻技術定義底部電極及電晶體閘極的 橫截面示意圖。圖六顯示先佈植N L D D、形成間隙壁，再對 源/汲極區佈植，隨後退火活化離子後，再沉積内連線介 電層、與形成源/汲極區接觸及頂部電極接觸的橫截面示 意圖。 半導體基板DRAM區 100 淺溝渠隔離區 110 R型井 120 深η型井 130 第二η型井 135 電容溝渠 140 閘極敦化層 150 複晶矽層 165 沒有受到B A R C或光阻保護之閘極氧化層 150a548802 Brief description of the drawings Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures: Figure 1 shows the semiconductor substrate forming a shallow trench isolation area with different energy Ion implantation forms shallower R-type wells and deeper η-type wells. Figure 2 shows a schematic cross-sectional view of a semiconductor trench without two trenches separated by a shallow trench isolation area. Figure 3 shows a high temperature thermal oxidation process, after forming a gate oxide layer, and then using a photoresist or anti-reflective coating as a protective layer, formed in the trench and on the gate oxide layer of the semiconductor substrate and exposed on the trench. A schematic cross-sectional view of a corner gate oxide layer. Figure 4 shows a schematic cross-sectional view of removing the exposed gate oxide layer, then removing the protective layer, and then depositing a polycrystalline stone layer to fill the trench. Figure 5 shows a schematic cross-section of the bottom electrode and transistor gate using photoresist and etching techniques. Figure 6 shows the NLDD firstly planted to form a spacer, then the source / drain region is planted, and then the activated ions are annealed, and then an interconnect dielectric layer is deposited to make contact with the source / drain region and the top electrode. Schematic cross-section. Semiconductor substrate DRAM area 100 Shallow trench isolation area 110 R-type well 120 Deep η-type well 130 Second η-type well 135 Capacitor trench 140 Gate dielectric layer 150 Polycrystalline silicon layer 165 Gate oxide layer not protected by BARC or photoresist 150a
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