TW548482B

TW548482B - Structure of outer leads

Info

Publication number: TW548482B
Application number: TW92101064A
Authority: TW
Inventors: Hui-Chang Chen; Wei-Liang Chen
Original assignee: Au Optronics Corp
Priority date: 2003-01-20
Filing date: 2003-01-20
Publication date: 2003-08-21
Also published as: TW200413779A

Abstract

A structure of outer leads is formed on a substrate for outputting or inputting an electronic signal. The structure of outer leads includes a plurality of parallel conductive wires positioned along a first direction, a plurality of terminals, and an insulation layer covered on the conductive wires. Additionally, each of the terminals is located at one end of the corresponding conductive wires, and a predetermined interval is existed between the two adjacent terminals along the first direction. Furthermore, a maximum width of each terminal perpendicular to the first direction is larger than a maximum width of each conductive wire perpendicular to the first direction.

Description

548482 五、發明說明（1) 發明所屬之技術領域本發明係關於一種外引腳結構，特別是一種可增加對位精準度的外引腳結構。先前技術身又而吕’液晶顯示面板必須藉由驅動積體電路晶片的驅動’才可產生豐富亮麗的畫面。而液晶顯示面板與驅動積體電路晶片的接合方式，目前係以捲帶式晶粒接合技術（tape automated bonding, TAB)為主要技術之一’其製程分為捲帶設計、内引腳接合、封膠、與外引腳接合等步驟，其中外引腳接合便係用來電連接液晶顯示面板與驅動積體電路晶片，因此為使驅動積體電路晶片的驅動訊號得以精確地傳遞至液晶顯示面板上，外引腳結構的設計尤其重要。請參考圖一，圖一係為一液晶顯示面板之簡化示意圖。如圖一所示，一液晶顯示面板1 〇包含有一基板1 2、一 X軸印刷電路基板（X-board) 1 4、以及一 Y軸印刷電路基板（Y-board) 1 6，而X軸印刷電路基板1 4與Y軸印刷電路基板1 6係用來輸出訊號至基板1 2上，以使液晶顯示面板1〇顯示畫面。此外，液晶顯示面板1 〇另包含有複數個捲帶式封裝體（tape carrier package，TCP)18，用來電連接548482 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to an outer pin structure, especially an outer pin structure that can increase alignment accuracy. In the prior art, the liquid crystal display panel must be driven by a driving integrated circuit chip to produce a rich and beautiful picture. The bonding method of the liquid crystal display panel and the driver integrated circuit chip currently uses tape automated bonding (TAB) as one of the main technologies. Its manufacturing process is divided into tape design, internal pin bonding, Sealing, bonding with external pins, etc. The external pin bonding is used to electrically connect the liquid crystal display panel and the driving integrated circuit chip, so that the driving signals for driving the integrated circuit chip can be accurately transmitted to the liquid crystal display panel In addition, the design of the outer pin structure is particularly important. Please refer to FIG. 1, which is a simplified schematic diagram of a liquid crystal display panel. As shown in FIG. 1, a liquid crystal display panel 10 includes a substrate 1 2, an X-axis printed circuit board (X-board) 1 4, and a Y-axis printed circuit board (Y-board) 16, and the X-axis The printed circuit board 14 and the Y-axis printed circuit board 16 are used to output signals to the substrate 12 so that the liquid crystal display panel 10 displays a picture. In addition, the liquid crystal display panel 10 includes a plurality of tape carrier packages (TCP) 18 for electrical connection.

548482 五、發明說明（2) 印刷電路基板1 4與基板1 2，以及用來電連接，路基板16與基板12,且每一個捲帶式封裝體刷裳一積體電路晶片20。各封基板12上設有複數條掃描線Si〜s私及複數條資」η’而各個掃描線s r S與各個資料線D广D枸係垂: i陣Γ基板丨2上之一主動區域1〜内定義出複數個目呈車排列狀之畫素（未顯示）。此外，基板丨2另包含有— 弓1:接合區（〇uter Uacl b〇nding regi〇n)l2b，用: 谈W ^描線Sl〜S#及各個資料線D广Dn電連接至相對應的 ▼式封裝體1 8，而其詳細的電連接方式係說明如下。考圖二至圖四，圖二係為圖一所示之區域A的立四I ί圖丄圖三係為圖二之外引腳結構的上視圖，而圖一、、二，二沿切線4- 4之剖面示意圖。如圖二與圖三所 f ’、捲帶式封裝體丨8上另包含有複數個外引腳（例如：辦ts^22b、22C與22d)，用來將一電子訊號自捲帶式封裝個外^出至基板1 2，此外’端子壓著區1 2b内亦設有複數橡* +腳（例如：24a、24b、24c與24d)，用來接收來自料Γ ^封裝體1 8的電子訊號，並將該電子訊號輸入至相對應的資料線上。異=圖四所示，捲帶式封裝體1 8與基板1 2之間另設有 ,、^生‘電膜（anis〇tropic conductive film，548482 V. Description of the invention (2) The printed circuit board 14 and the substrate 12 are used to electrically connect the circuit board 16 and the substrate 12, and each tape-and-reel package is brushed with an integrated circuit chip 20. Each of the sealing substrates 12 is provided with a plurality of scanning lines Si ~ s and a plurality of data lines `` η '', and each scanning line sr S and each data line D are connected to each other: an active area on the i array Γ substrate 2 Within 1 ~, a plurality of pixels (not shown) arranged in a cart shape are defined. In addition, the substrate 丨 2 further includes — bow 1: junction area (〇uter Uacl bonding regi〇n) l2b, with: Talk about the trace lines S1 ~ S # and the various data lines D and Dn are electrically connected to the corresponding The ▼ -type package 18 is described in detail below. Consider Figures 2 to 4. Figure 2 is a stand-up I of area A shown in Figure 1. Figure 3 is a top view of the pin structure outside Figure 2. Figures 1, 2, and 2 are along the tangent line. Sectional sketch of 4--4. As shown in Figure 2 and Figure 3, the tape-and-reel package 8 also contains a plurality of external pins (for example, ts ^ 22b, 22C, and 22d), which are used to package an electronic signal from the tape-and-reel package. Each of them is out to the substrate 12, and a plurality of rubber feet (for example, 24a, 24b, 24c, and 24d) are also provided in the terminal crimping area 1 2b for receiving materials from the material Γ ^ package body 1 8 Electronic signal, and input the electronic signal to the corresponding data line. The difference is shown in FIG. 4. An anisotropic conductive film (anisotropic conductive film) is provided between the tape and reel package 18 and the substrate 12.

548482 五、發明說明（3) ACF)26，用來將各外引腳22a〜22 d電連結至相對應的各外引腳24a〜24d上。一般而言，異方性導電膜26係利用黏貼的方式貼合於捲帶式封裝體1 8與基板1 2之間，而其通常包含有一黏著劑2 6 a以及複數個導電粒子2 6 b分散於黏著劑26a中，各導電粒子26b係包含有一球狀聚合物 (polymer)、一鎳金層（n i eke 1-go 1 d )電鍍於該球狀聚合物的表面上、以及一絕緣層包覆於該鎳金層之外，而黏著劑2 6 a係由環氧樹脂（e ρ ο X y r e s i η )所構成。為因應市場的需求，液晶顯示面板1 0的晝素係日益增加，因此用來電連接捲帶式封裝體1 8與基板1 2的外引腳的數目也隨之增加，而必須縮小各外引腳的寬度（1 ead w i d t h，如圖三所示之W與W / )或各外引腳之間的間距 (lead pitch，如圖三所示之W與W2’），此將使得各外引腳容易因受熱膨脹而產生電性短路的情形。例如，在圖四所示之區域B内，理論上外引腳2 2 b應只電連接至外引腳24b，但由於受熱膨脹、或因製程與設備因素而產生對位偏移（misalignment)，均會致使導電粒子26a導通外引腳22b與2 4a，因此外引腳22b與24a之間便產生電性短路之情形，而此將影響液晶顯示面板1 〇之正常操作。發明内容本發明的目的是提供一種外引腳結構，以解決前述548482 V. Description of the invention (3) ACF) 26 is used to electrically connect the outer pins 22a to 22d to the corresponding outer pins 24a to 24d. Generally speaking, the anisotropic conductive film 26 is adhered between the tape-and-reel package 18 and the substrate 12 using an adhesive method, and usually includes an adhesive 2 6 a and a plurality of conductive particles 2 6 b. Dispersed in the adhesive 26a, each conductive particle 26b includes a spherical polymer, a nickel-gold layer (ni eke 1-go 1 d), is plated on the surface of the spherical polymer, and an insulating layer It is coated on the nickel-gold layer, and the adhesive 2 6 a is made of epoxy resin (e ρ ο X yresi η). In order to respond to the market demand, the number of daylight elements of the liquid crystal display panel 10 is increasing. Therefore, the number of external pins for electrically connecting the tape and reel package 18 and the substrate 12 also increases, and each external lead must be reduced. 1 ead width (W and W / as shown in Figure 3) or lead pitch (W and W2 'as shown in Figure 3), which will make each external lead The feet are prone to electrical shorts due to thermal expansion. For example, in the area B shown in Figure 4, theoretically the outer pin 2 2 b should be electrically connected to the outer pin 24b only, but misalignment due to thermal expansion or due to process and equipment factors Both will cause the conductive particles 26a to conduct the external pins 22b and 24a, so an electrical short circuit will occur between the external pins 22b and 24a, which will affect the normal operation of the LCD panel 10. SUMMARY OF THE INVENTION An object of the present invention is to provide an external pin structure to solve the foregoing problems.

548482 五、發明說明（4) 問題。依據本發明之目的，本種外引腳結構，該外引腳結出或輸入一電子訊號。該外一方向平行排列的導線、複覆蓋於該等導線之上，其中線之一端，任兩相鄰之該等一預定距離，且各該端子垂係大於各該導線垂直於該第由於在本發明的外引腳間隔一預定距離，且各外引較窄的導線，因此可增加外此外’由於各外引腳均具有提升了各外引腳的對位精準之間的接合良率。另一方面一抗焊劑或一保護層，因而實施方式請參考圖五，圖五係為圖。如圖五所示，一外引腳數條外引腳44設於基板40的 =明之較佳實施例係提供— 構係設於一基板上，用來輪引腳結構包含有複數條沿第數個端子、以及一絕緣層，各該端子係分別設於各該導端子於該第一方向上係間隔直於該第一方向的最大寬度一方向的最大寬度。結構中，兩相鄰之外引腳係腳均具有一較寬的端子與— 引腳結構中的外引腳數目。一較寬的端子，因此相對地度，進而增加各外引腳結構，各外引腳的導線上覆蓋有可避免產生電性短路情形。本發明之外引腳結構示意結構40包含有一基板42、複表面上、以及複數條外引腳548482 V. Description of Invention (4) Question. According to the purpose of the present invention, in the external pin structure, the external pin outputs or inputs an electronic signal. The wires arranged in parallel in the outer direction are covered on the wires, one end of the wire is any two adjacent ones of the predetermined distance, and each of the terminals is greater than each of the wires perpendicular to the first due to The outer pins of the present invention are spaced a predetermined distance apart, and each of the outer leads leads to a narrower wire, so that the outer pins can be increased. Since each outer pin has a higher joint yield, the alignment accuracy of the outer pins is improved. On the other hand, an anti-flux or a protective layer, so the implementation please refer to Figure 5, which is a diagram. As shown in FIG. 5, a plurality of outer pins 44 are provided on the substrate 40. A preferred embodiment of the invention is provided-the structure is provided on a substrate, and the wheel pin structure includes a plurality of edges. A plurality of terminals and an insulating layer are respectively provided on the lead terminals in the first direction and spaced apart from the maximum width in one direction in the first direction. In the structure, two adjacent external pin systems each have a wider terminal and — the number of external pins in the pin structure. A wider terminal, so the relative ground, and thus the structure of each outer pin is increased, and the wires of each outer pin are covered to avoid the occurrence of an electrical short circuit. Schematic diagram of the outer lead structure of the present invention. Structure 40 includes a substrate 42, a complex surface, and a plurality of outer leads.

548482548482

46插置於兩相鄰之外引腳44之間的基板40上，並且各外引腳44與各外引腳4 6均係彼此相互平行。其中，每一條外引腳44係包含有一端子44a以及一導線44b連接至端^ 44a上’而每一條外引腳46亦具有一端子46a以及一導線 46b連接至端子46a上，並且外引腳結構40乃係藉由各端子4 4a、46a而將基板42電連接至其它基板上。此外，外引腳結構40另包含有一絕緣層48覆蓋於各導線44b與46b 之上’用來避免各導線44b、46诚其他導體產生電性短路現象’以及用來保護電路。值得注意的是，在本發明 ^最佳實施例中，兩相鄰的端子44a與端子46a之間的間 $距離係為d，以使各外引腳44、46呈現差排的排列方各端子44a、46a的寬度W係大於各導線44b、、度W 4。再者’各端子4 4 a、4 6 a的形狀也可以是圓形、方形或其它非矩形的形狀。腳姅椹i ，右將外引腳結構40與圖三所示之習知的外等），由H，在外引腳寬度相同的情況下（亦即W與W 於各導!!腳結構4〇中，各端子44a的寬度 ίϊϊϊΓΓπ/46 is inserted on the substrate 40 between two adjacent outer pins 44 and each outer pin 44 and each outer pin 46 are parallel to each other. Among them, each outer pin 44 includes a terminal 44a and a wire 44b connected to the terminal 44a ', and each outer pin 46 also has a terminal 46a and a wire 46b connected to the terminal 46a, and the outer pin The structure 40 electrically connects the substrate 42 to other substrates through the terminals 44a and 46a. In addition, the outer pin structure 40 further includes an insulating layer 48 covering each of the wires 44b and 46b 'to prevent the wires 44b and 46 from being electrically short-circuited by other conductors' and to protect the circuit. It is worth noting that, in the preferred embodiment of the present invention, the distance between two adjacent terminals 44a and 46a is d, so that the outer pins 44 and 46 are arranged in a different arrangement. The widths W of the terminals 44a and 46a are larger than the respective wires 44b and W4. Furthermore, the shape of each of the terminals 4 4 a and 4 6 a may be circular, square, or other non-rectangular shapes. Pin i, the right pin structure 40 and the conventional pin shown in Figure 3, etc., from H, when the outer pin width is the same (that is, W and W are in each guide !! Foot structure 4 〇, the width of each terminal 44a ίϊϊϊΓΓπ /

係大於w i 距，亦即各端子“a與各導線46b的間短路情形2(另二一），此將I減少因受熱膨脹而產生的電’ 情況下^ 1 =方面，若在外引腳寬度與間距均相同目。纟發明之外弓丨腳結構40將具有較多的外引腳Is greater than the wi distance, that is, the short circuit between each terminal "a and each lead 46b case 2 (the other two one), this will reduce the electricity generated by thermal expansion 'case ^ 1 = aspect, if the outer pin width Both have the same purpose as the pitch. 纟 Invention of the outer arch 丨 foot structure 40 will have more outer pins

第9頁 548482 五、發明說明（6) 在本發明之較佳實施例中，基板4 2係為一可撓性基板（f 1 e X i b 1 e s u b s t r a t e )，例如：可撓性印刷電路板 (flexible printed circuit board, FPC)、可挽性平面式排線（flexible flat cable，FFC)、捲帶式封裝體所使用的基板、或薄膜覆晶（chip on f i lm，COF)技術所使用之基板等。並且，絕緣層4 8係為一抗焊劑（s 0 1 d e r resist)’例如：三聚氰胺樹脂（melamine resin)或環氧樹脂。另外，在本發明之其它實施例中，基板4 2亦可以是一液晶顯示面板之玻璃基板，此時，絕緣層4 8係為一保護層（passivation layer)，例如氮化矽（siiicori nitride)0 接下來，將說明本發明之外引腳結構之間的接合方式，以更清楚地呈現本發明之特徵。請參考圖六至圖八，圖六係為本發明之一外引腳接合結構的示意圖，圖七係為圖六沿切線7 - 7之剖面示意圖，圖八係為圖六沿切線8 - 8之剖面示意圖。如圖六所示，一外引腳接合結構 (outer lead bonding, OLB)50包含有一可撓性基板52與一玻璃基板6 2設於可撓性基板5 2之下側。其中，可撓性基板5 2的下側表面上設置有複數條相互平行且交錯的外引腳5 4與外引腳5 6，而玻璃基板6 2的上側表面上設置有複數條相互平行且交錯的外引腳6 4與外引腳6 6。並且，外引腳5 4、5 6均各具有一端子5 4 a、5 6 a以及一導線5 4 b、Page 9 548482 V. Description of the invention (6) In a preferred embodiment of the present invention, the substrate 4 2 is a flexible substrate (f 1 e X ib 1 esubstrate), such as a flexible printed circuit board ( flexible printed circuit board (FPC), flexible flat cable (FFC), substrate used in tape and reel package, or substrate used in chip on film (COF) technology Wait. In addition, the insulating layer 48 is a solder resist 'such as a melamine resin or an epoxy resin. In addition, in other embodiments of the present invention, the substrate 42 may also be a glass substrate of a liquid crystal display panel. At this time, the insulating layer 48 is a passivation layer, such as siiicori nitride. 0 Next, the bonding manner between the lead structures outside the present invention will be explained in order to present the features of the present invention more clearly. Please refer to FIGS. 6 to 8. FIG. 6 is a schematic diagram of an external pin bonding structure according to the present invention. FIG. 7 is a schematic cross-sectional view taken along the tangent line 7-7 in FIG. 6. Schematic cross-section. As shown in FIG. 6, an outer lead bonding structure (OLB) 50 includes a flexible substrate 52 and a glass substrate 62 located below the flexible substrate 52. Among them, a plurality of external pins 5 4 and 5 6 which are parallel and interlaced with each other are provided on the lower surface of the flexible substrate 52, and a plurality of parallel and mutually parallel pins are provided on the upper surface of the glass substrate 62. Interleave outer pins 6 4 and 6 6. In addition, each of the outer pins 5 4 and 5 6 has a terminal 5 4 a, 5 6 a and a wire 5 4 b,

第10頁 548482 五、發明說明（7) 56 b連接至端子54a、56a，而外引腳64、6 6均各具有一端子64a、66a以及一導線64b、66b連接至端子64a、66a，由於外引腳5 4、6 4與5 6、6 6的結構係分別與圖五之外引腳4 4與4 6相同，因此不再贅述。此外，外引腳接合結構 5 0另包含有一抗焊劑5 8，覆蓋於各導線5 4 b、5 6 b上，以及一保護層68，覆蓋於各導線64b、66b上，而抗焊劑58 與保護層6 8乃係用來避免產生電性短路的現象。另一方面，如圖七與圖八所示，外引腳接合結構5 〇另包含有一異方性導電膜7 0，黏貼於可撓性基板5 2與玻璃基板6 2之間，用來將端子5 4 a與5 6 a分別電連結至相對應的端子66a與64a上。一般而言，異方性導電膜70包含有一黏著劑7 0 a以及複數個導電粒子7 0 b分散於黏著劑7 01 之中，各導電粒子7 0 b係為異方性導電膜7 0用來導電的部分，其包含有一球狀聚合物、一鎳金層電鍍於該球狀聚合物的表面上、以及一絕緣層包覆於該鎳金層之外，而黏著劑7 0 a通常係為環氧樹脂。Page 10 548482 V. Description of the invention (7) 56b is connected to the terminals 54a, 56a, and the outer pins 64, 66 each have a terminal 64a, 66a and a wire 64b, 66b connected to the terminals 64a, 66a. The structures of the outer pins 5 4, 6 4 and 5 6, 6 6 are the same as those of the pins 4 4 and 4 6 except for FIG. 5, so they are not described again. In addition, the outer pin bonding structure 50 further includes a solder resist 5 8 covering the wires 5 4 b and 5 6 b, and a protective layer 68 covering the leads 64b and 66b, and the solder resist 58 and The protective layer 68 is used to avoid the phenomenon of electrical short circuit. On the other hand, as shown in FIG. 7 and FIG. 8, the outer pin bonding structure 5 0 further includes an anisotropic conductive film 70, which is adhered between the flexible substrate 52 and the glass substrate 62 and used for bonding The terminals 5 4 a and 5 6 a are electrically connected to the corresponding terminals 66 a and 64 a, respectively. Generally speaking, the anisotropic conductive film 70 includes an adhesive 7 0 a and a plurality of conductive particles 7 0 b dispersed in the adhesive 7 01. Each of the conductive particles 7 0 b is an anisotropic conductive film 70. The conductive part includes a spherical polymer, a nickel-gold layer electroplated on the surface of the spherical polymer, and an insulating layer covering the nickel-gold layer. The adhesive 70a is usually For epoxy.

值付注意的是，由於本發明的外引腳54、56、6 4與 66均具有較寬的端子54a、56a、64a與66a，因此相對地增加了外引腳5 4、5 6與外引腳6 6、6 4之間的可接觸面積，進而可提升外引腳5 4、5 6與外引腳6 6、6 4之間的對位精準度，並且也增加外引腳5 4、5 6與外引腳6 6、6 4之間的導電面積。另一方面，在圖七所示之區域C與區域DIt is worth noting that, since the outer pins 54, 56, 6 4 and 66 of the present invention all have wider terminals 54a, 56a, 64a, and 66a, the outer pins 5 4, 5 6 and outer pins are relatively increased. The contact area between pins 6 6, 6 4 can further improve the alignment accuracy between outer pins 5 4, 5 6 and outer pins 6 6, 6 4 and also increase outer pins 5 4 , 5 6 and the conductive area between the outer pins 6 6, 6 4. On the other hand, in areas C and D shown in FIG.

548482 五、發明說明（8) 内，由於導線56b上覆蓋有抗焊劑58，因此即使導電粒子 7Ob連接於端子66a與導線56b之間，端子66a與導線56b之間仍不會產生電性短路情形。相同地，如圖八所示之區 |域E與區域F内，由於導線66b上覆蓋有保護層68，因此可 1避免端子56a與導線66b之間產生電性短路。簡而古 |本發明之外引腳結構可避免因受熱膨脹或對位:之，成的電性短路現象。艰移所造相較於習知技術，引腳係呈一差排的排列 |的端子與一較窄的導線引腳數目。此外，由於因此相對地提升了各外 |外引腳結構之間的接合線上覆蓋有一抗焊劑或短路情形。綜合上述， |文熱膨脹或對位偏移所以上所述僅為本發 j清專利範圍所做之均等之涵蓋範圍。在本發明的外方式，且各外，因此可增加各外引腳均具引腳的對位精良率。另一方一保護層，因本發明之外引造成的電性短引腳結構φ 引腳均具L各外外引腳結構+叛寬面，各加各腳結構##生電性路現Γ避免因明之較佳實施變化與修飾， _ 548482 圖式簡單說明圖示之簡單說明：圖一係為一液晶顯示面板之簡化示意圖。圖二係為圖一所示之區域A的立體示意圖。圖三係為圖二之外引腳結構的上視圖。圖四係為圖三沿切線4 - 4之剖面示意圖。圖五係為本發明之外引腳結構示意圖。圖六係為本發明之一外引腳接合結構的示意圖。圖七係為圖六沿切線7 - 7之剖面示意圖。圖八係為圖六沿切線8 - 8之剖面示意圖。圖示之符號說明： 10 液晶顯示面板 12、4 2 基板 12a 主動區域 12b 外引腳接合區 1 4 X 軸印刷電路基板 16 Y軸印刷電路基板 18 捲帶式封裝體 20 積體電路晶片 22a、 22b、 22c、 22d、 24a、 24b、 24c、 24d、 44、 46、 54、 56、 64、 66 外引腳 2 6、7 0 異方性導電膜 2 6 a、7 0 a 黏著劑 26b、70b 導電粒子 40 外引腳結構548482 5. In the description of the invention (8), since the lead wire 56b is covered with the solder resist 58, even if the conductive particles 7Ob are connected between the terminal 66a and the wire 56b, there will be no electrical short circuit between the terminal 66a and the wire 56b . Similarly, in the area E and the area F shown in FIG. 8, since the conductive layer 66 is covered with the protective layer 68, the electrical short between the terminal 56a and the conductive line 66b can be avoided. Simple and ancient | The lead structure outside the present invention can avoid the electrical short-circuit phenomenon caused by thermal expansion or alignment. Difficult to move compared to the conventional technology, the pins are arranged in a poor row of | terminals and a narrower number of wire pins. In addition, because of this, the bonding wires between the outer and outer lead structures are relatively covered with a solder resist or short circuit. Based on the above, the thermal expansion or misalignment of the text described above is only an equivalent coverage made by the scope of this patent. In the external mode of the present invention, and each external, the alignment accuracy of each external pin can be increased. On the other side, a protective layer, the electrical short pin structure φ pins caused by the present invention are all L external pin structure + wide width surface, each plus each foot structure ## 生电性路相 Γ To avoid changes and modifications due to the better implementation of the Ming, _ 548482 is a simple illustration of the diagram: Figure 1 is a simplified schematic diagram of a liquid crystal display panel. FIG. 2 is a schematic perspective view of the area A shown in FIG. 1. Figure 3 is a top view of the pin structure other than Figure 2. Figure 4 is a schematic cross-sectional view taken along line 4-4 of Figure 3. FIG. 5 is a schematic diagram of a pin structure outside the present invention. FIG. 6 is a schematic diagram of an external pin bonding structure according to the present invention. Fig. 7 is a schematic cross-sectional view taken along line 7-7 of Fig. 6. Figure 8 is a schematic cross-sectional view taken along line 8-8 of Figure 6. Explanation of symbols: 10 LCD panel 12, 4 2 substrate 12a active area 12b outer pin bonding area 1 4 X-axis printed circuit board 16 Y-axis printed circuit board 18 Tape-and-reel package 20 Integrated circuit chip 22a, 22b, 22c, 22d, 24a, 24b, 24c, 24d, 44, 46, 54, 56, 64, 66 Outer pins 2 6, 7 0 Anisotropic conductive film 2 6 a, 7 0 a Adhesives 26b, 70b Conductive particle 40 outer pin structure

第13頁 548482 圖式簡單說明 4 4 a、4 6 a、5 4 a、5 6 a、6 4 a、6 6 a 端子 44b、46b、54b、56b、64b、66b 導線 4 8 絕緣層 50 外引腳接合結構 52 可撓性基板 58 抗焊劑 62 玻璃基板 68 保護層Page 13 548482 Brief description of drawings 4 4 a, 4 6 a, 5 4 a, 5 6 a, 6 4 a, 6 6 a Terminal 44b, 46b, 54b, 56b, 64b, 66b Conductor 4 8 Insulation layer 50 outside Pin bonding structure 52 Flexible substrate 58 Solder resist 62 Glass substrate 68 Protective layer

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Claims

六、申請專初範圍 1 · 一種外引腳結構，該外引腳結構係設於一基板上，用來輸出或輸入一電子訊號，該外引腳結構包含有：複數條沿第一方向平行排列的導線；複數個端子，分別設於各該導線之一端，任兩相鄰之該等端子於該第一方向上係間隔一預定距離，且各該端子垂直於該第一方向的最大寬度係大於各該導線垂直於該第一方向的最大寬度；以及一絕緣層，覆蓋於該等導線之上。 2 · 如申請專利範圍第1項之外引腳結構，其中該基板係為一可撓性基板（flexible substrate)。 3 · 如申請專利範圍第2項之外引腳結構，其中該絕緣層係為一抗焊劑（s〇lder resist)。 4 ·如申請專利範圍第3項之外引腳結構，其中該可撓性基板係包含一可撓性印刷電路板（f 1 e X i b 1 e p r i n t e d eir^uit board，FPC)或一可撓性平面式排線（flexible f 1 at cab 1 e，FFC)〇 1 i，I睛f利範圍第3項之外引腳結構，其中該可撓性 =f ’糸 I 捲’式封裝體（taPe carrier Package，TCP)所使用之基板。VI. Application scope 1 · An external pin structure is provided on a substrate for outputting or inputting an electronic signal. The external pin structure includes: a plurality of parallel in the first direction Arranged wires; a plurality of terminals are provided at one end of each of the wires, and any two adjacent terminals are spaced a predetermined distance in the first direction, and each terminal is perpendicular to the maximum width of the first direction Is greater than the maximum width of each of the wires perpendicular to the first direction; and an insulating layer covers the wires. 2 · If the lead structure is outside the scope of the first patent application, the substrate is a flexible substrate. 3 · If the lead structure is beyond the scope of the patent application, the insulation layer is a solder resist. 4 · If the lead structure is beyond the scope of patent application item 3, wherein the flexible substrate includes a flexible printed circuit board (f 1 e X ib 1 eprinted eir ^ uit board, FPC) or a flexible Planar cable (flexible f 1 at cab 1 e, FFC) 〇1 i, the pin structure outside the range of the third item, where the flexibility = f '糸 I roll' package (taPe carrier package (TCP).

第15頁 548482 六、申請專利範圍 6. 如申請專利範圍第3項之外引腳結構，其中該可撓性基板係為薄膜覆晶（c h i ρ ο n f i 1 m，C 0 F )技術所使用之基板。 7. 如申請專利範圍第1項之外引腳結構，其中該基板係包含有一液晶顯示面板之玻璃基板。 8. 如申請專利範圍第7項之外引腳結構，其中該絕緣層係為一保護層（passivation layer)。 9. 如申請專利範圍第7項之外引腳結構，其中該玻璃基板包含有一外引腳接合區（outer lead bonding region)，而該外引腳結構係設於該外引腳接合區内。 1 0. —種外引腳結構，該外引腳結構係設於一基板上，用來輸出或輸入一電子訊號，該外引腳結構包含有：複數個第一外引腳，該等第一外引腳係沿一第一方向平行地設置於該基板上，各該第一外引腳均係具有一第一端子、以及一第一導線連接至該第一端子，且各該第一端子垂直於該第一方向的最大寬度係大於各該第一導線垂直於該第一方向的最大寬度；複數個第二外引腳，各該第二外引腳係平行地插置於兩相鄰之該等第一外引腳之間，各該第二外引腳均係具有一第二端子、以及一第二導線連接至該第二端子，各該第Page 15 548482 6. Scope of patent application 6. For example, the lead structure outside the scope of patent application No. 3, in which the flexible substrate is a thin-film flip-chip (chi ρ ο nfi 1 m, C 0 F) technology The substrate. 7. For the lead structure other than the scope of the patent application, the substrate is a glass substrate including a liquid crystal display panel. 8. For the pin structure other than the scope of the patent application, the insulation layer is a passivation layer. 9. For example, the lead structure outside the scope of the patent application item 7, wherein the glass substrate includes an outer lead bonding region, and the outer lead structure is disposed in the outer lead bonding region. 1 0. —An external pin structure is provided on a substrate for outputting or inputting an electronic signal. The external pin structure includes: a plurality of first external pins. An external pin is disposed on the substrate in parallel along a first direction, and each of the first external pins has a first terminal and a first wire connected to the first terminal, and each of the first The maximum width of the terminal perpendicular to the first direction is greater than the maximum width of each of the first wires perpendicular to the first direction; a plurality of second outer pins, each of the second outer pins is inserted in two phases in parallel Between the adjacent first external pins, each of the second external pins has a second terminal, and a second wire is connected to the second terminal.

第16頁 548482 六、申請專利範圍 —--- 二端子垂直於該第一方向的最大寬度係大於各該第二導線垂直於該第了方向的最大寬度，且各該第一端子與各該第二端子於該第一方向上係間隔一預定距離；以及一絕緣層，覆蓋於該等第一導線與該等第二導線之上。 1 1 ·如申請專利範圍第丨〇項之外引腳結構，其中該基板係為一可撓性基板。 12 ·如申請專利範圍第11項之外引腳結構，其中該絕緣層係為一抗焊劑。 13 如申含奎直_±,| ^ a此总—1 利範圍第12項之外引腳結構’其中該可撓性暴板係包含一 7 J撓性印刷電路板或一可撓性平面式排線。 1 4 如申技東基板係為^ ί，範圍第12項之外引腳結構’其中該可撓性 ^式封裝體所使用之基板。 1 5 · 如申姓査基板係為=寻利範圍第1 2項之外引腳結構‘，其中該可撓性 “ /膜覆晶技術所使用之基板。 1 6 · 如申技々八古明專利範圍第1 〇項之外引腳結構’其中該基板係 W曰日顯示面板之玻璃基板。Page 16 548482 VI. Application scope of patents --- The maximum width of the two terminals perpendicular to the first direction is greater than the maximum width of each of the second wires perpendicular to the first direction, and each of the first terminals and each of the The second terminals are spaced a predetermined distance apart in the first direction; and an insulating layer covers the first conductive wires and the second conductive wires. 1 1 · If the lead structure is outside the scope of the patent application, the substrate is a flexible substrate. 12 · If the lead structure is beyond the scope of patent application item 11, wherein the insulation layer is a solder resist. 13 If the application contains Kui Straight _ ±, | ^ a this general — 1 range of the lead structure outside the 12th item of the lead structure 'wherein the flexible storm board includes a 7 J flexible printed circuit board or a flexible flat panel line. 1 4 If Shenjidong's substrate is ^ ί, the pin structure outside the scope of item 12 'is the substrate used in the flexible package. 1 5 · If the name of the substrate is the same as that of the pin structure outside the profit-seeking area No. 12, the substrate is used for the flexibility "/ film-on-chip technology. 1 6 · If the technology is eight The structure of the lead outside the scope of patent of the Ming patent is '10', wherein the substrate is a glass substrate of a display panel.

548482 六、申請專利範圍 1 7·如申請專利範圍第丨6項之外引腳結構，其絕緣層係為一保護層。 ' 1 8·如申請專利範圍苐丨6項之外引腳結構，其中該玻璃基板包含有一外引腳接合區，而該外引腳結構係設於該外引腳接合區内。 1 9 · 一種外引腳接合（〇 u七e r 1 e a d b ο n d i n g )結構，該外引腳接合結構包含有：一可撓性基板’且該可撓性基板的下側表面設置有複數條沿一第一方向平行排列的第一外引腳，各該第一外引腳均係具有一第一端子、以及一第一導線連接至該第一端子，任兩相鄰之該等第一端子於該第一方向上係間隔一預定距離，且各該第一端子垂直於該第一方向的最大寬度係大於各該第一導線垂直於該第一方向的最大寬度；一抗焊劑，覆蓋於該等第一導線上；一玻璃基板設於該可撓性基板的下側，該玻璃基板的上側表面設有複數條第二外引腳，各該第二外引腳係與各該第一外引腳平行相對，且各該第二外引腳均係具有一第二端子、以及一第二導線連接至該第二端子，任兩相鄰之該等第二端子於該第一方向上係間隔一預定距離，各該第二端子垂直於該第一方向的最大寬度係大於各該第二導線垂直於該第一方向的最大寬度；一保護層，覆蓋於該等第二導線上；以及548482 VI. Scope of patent application 1 7. If the pin structure outside the scope of patent application No. 丨 6, the insulation layer is a protective layer. '18. If the scope of the patent application is 6 or more, the glass substrate includes an outer pin bonding area, and the outer pin structure is disposed in the outer pin bonding area. 1 9 · An external pin bonding structure (〇u 七 er 1 eadb ο nding) structure, the external pin bonding structure includes: a flexible substrate ', and the lower surface of the flexible substrate is provided with a plurality of edges A first outer pin arranged in parallel in a first direction, and each of the first outer pins has a first terminal and a first wire connected to the first terminal, and any two adjacent first terminals A predetermined distance is spaced in the first direction, and the maximum width of each first terminal perpendicular to the first direction is greater than the maximum width of each first wire perpendicular to the first direction; a solder resist covering the On the first wires, a glass substrate is disposed on the lower side of the flexible substrate, and a plurality of second outer pins are provided on the upper surface of the glass substrate, and each of the second outer pins is connected to each of the first The outer pins are parallel to each other, and each of the second outer pins has a second terminal and a second wire connected to the second terminal, and any two adjacent second terminals are in the first direction. Are separated by a predetermined distance, each of the second terminals is perpendicular to The maximum width of each line of the first direction is larger than the maximum width of the second conductive line perpendicular to the first direction; a protective layer covers the second wire such; and

第18頁 548482 六、申請專利範圍至少一接合單元，設於該等第一外引腳與該等第二外引腳之間，用來將各該第一外引腳電連接至相對應的各該第二外引腳。 2 0 .如申請專利範圍第1 9項之外引腳接合結構，其中該抗焊劑係用來避免該等第一外引腳與該等第二外引腳產生電性短路，並保護該等第一外引腳。 m 2 1.如申請專利範圍第2 0項之外引腳接合結構，其中該保護層係用來避免該等第一外引腳與該等第二外引腳產生電性短路，並保護該等第二外引腳。 2 2.如申請專利範圍第1 9項之外引腳接合結構，其中各該接合單元係包含有一異方性導電膠（anisotropic conductive film, ACF)或一錫球結構（solder ball)。Page 18 548482 VI. At least one bonding unit for patent application is provided between the first outer pins and the second outer pins, and is used to electrically connect each of the first outer pins to a corresponding one. Each second external pin. 20. If the pin bonding structure is beyond the scope of item 19 of the patent application, the solder resist is used to avoid the electrical short circuit between the first outer pins and the second outer pins, and protect the First external pin. m 2 1. According to the pin bonding structure outside the scope of patent application No. 20, the protective layer is used to avoid the electrical short circuit between the first outer pins and the second outer pins, and to protect the Wait for the second external pin. 2 2. The pin bonding structure other than item 19 of the scope of the patent application, wherein each of the bonding units includes an anisotropic conductive film (ACF) or a solder ball structure.

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