546923 五、發明說明（/ ) 【技術領域】 本發明係關於-種頻率合成電路，特別是指一種適用 於低，考彳頻率’南頻率，及冑倍數頻率合成之 率合成電路。 ' 5【先前技術】 ίο 鎖相迴路(PLL)為頻率合成㈣路之經f使用技術， 如圖一所示。其基本架構包含相位頻率比較器_)14, 充放電式遽波器（CPF)16，電壓控制振遺器（vc〇)i8，及除 頻器(觀蜂。藉由相位頻率比較器的作用，可對電壓 控制振盪器之輸出頻率持續修正。當迴路達到鎖相狀態， -電廢控制振盈器(VC0)之輸出頻率(fVc〇)與參考信號之頻率 ㈣將滿足fVC0 = N*fref之關係；其中N為除頻器之係數。 15 對於低參考信號頻率（<1〇〇kHz)且高頻率輸出⑽ MHz)之應用而言’如：視訊傳輸系統之接收端，立必須利 用銀幕水平同步之掃描信號⑽鞭)產生高頻之時脈輸出 以作為類比數位轉換器之用，傳統式之鎖相迴路須利用古 倍數除頻(N)之除卿來達到高倍倍頻之目的，如^ 20 造成極大之相位誤差累積；此外，隨著參考信號頻率之降 低，系統之迴路頻寬亦須隨之降低，造成鎖 效抑制外部雜訊。 ".、法有 由此可見，上述習用物品仍有諸多缺失，實非 盖 之設計者，而亟待加以改良。 义° 本人鑑於上述習用頻率合成電路所衍生的各項 缺占乃亟思加以改良創新，並經多年苦心孤錯潛心研究 本纸張尺度賴t _ 546923 A7 B7 五、發明說明（2) 10 15 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 20.主 號 鎖 後，終於成功研發完成本件頻率合成電路。 【發明目的】 本發明之目的即在於提供一種頻率合成電路，利用鎖 相迴路與延遲迴路二次倍頻之作用，消除傳統鎖相迴路單 次倍頻之相位誤差累積與迪路頻寬之問題。 本發明之次一目的係在於提供一種頻率合成電路，適 用於任何可程式頻率合成器之設計應用上。對於低參考作 號頻率(〜kHz)、高頻輸出（>1〇〇ΜΗζ)之頻率合成應用亦呈 良好之效果。 /、’ 本發明之另一目的係在於提供一種頻率合成電路，盆 中之倍頻技術，可應用在視訊傳輸之時脈產生電路設^ —I»* 【技術内容】 可達成上述發明目的之頻率合成電路 電路及鎖相迴路；其中倍頻電路可將低頻之 ^倍頻 為高頻信號’以作域相迴路參考錢 〔5歲轉換 路之迴路頻寬可進而提高，藉㈣低輸^此鎖相迴 訊。 唬之抖動雜 在此’參考信叙倍頻電轉肖乡 要利用延遲迴誠㈣衫考㈣:成技術， ’並經由相位之合成達到倍頻—夕相饭輪出信 呀相學路二次倍頻的作用可降低鎖相：由延遲迴路與 導致之相位誤差累積，其倍頻倍數可 μ高倍倍頻所 路之倍頻電路與鎖相迴路之除頻 ^由_鎖 其 信 (請先閱讀背面之注意事項#.填寫本頁} •裝 訂- -線- ^^尺度適用中國國爾 546923 A7 B7 五、發明說明（令） 5 10 15 【圖式簡單說明】 附下有關本發明"'較佳實施例之詳細說明及其 =二：步瞭解本發明之技術内容及其目的功效; 有關该貫施例之附圖為： 圖一為傳統之頻率合成器架構圖； 圖二為本發明之頻率合成電路的架構圖； :三為均分一個週期的多相位輪出信號圖； 圖四為利用均分一個週期的四相位輪 頻輸出之電路架構圖； 成一七 圖五為利用均分一個週期的四相 頻輸出之信號分析圖； 輪出^號合成二倍 圖六為利用均分一週期之8相位作 Q2，與四倍_之輸出信號分㈣；、成之兩倍頻 …圖:為利用均分一週期之_位信鏡f倍倍頻相位合 成器之架構圖；以及 圖八為可程式之頻率合成電路架構圖。 【主要部分代表符號】 14相位頻率比較器 16充放電式濾波器 18電壓控制振盪器 20除頻器 41倍頻電路 42鎖相迴路 - .— (請先閱讀背面之注意事項再填寫本頁) 訂· 丨線！ 本紙張尺度3用中國。保準(CNS)A4規格(21〇^^； 546923546923 V. Description of the Invention (/) [Technical Field] The present invention relates to a frequency synthesizing circuit, and particularly to a rate synthesizing circuit suitable for low, test frequency 'south frequency, and multiple frequency synthesis. '5 [Prior art] Phase-locked loop (PLL) is a technique used in frequency synthesis circuit, as shown in Figure 1. Its basic architecture includes a phase frequency comparator_) 14, a charge-discharge type wave filter (CPF) 16, a voltage-controlled oscillator (vc0) i8, and a frequency divider (Bee Watch. By the role of the phase frequency comparator The output frequency of the voltage-controlled oscillator can be continuously corrected. When the loop reaches the phase-locked state, the output frequency (fVc〇) of the electrical waste control oscillator (VC0) and the frequency of the reference signal 满足 will satisfy fVC0 = N * fref N is the coefficient of the divider. 15 For applications with low reference signal frequency (<100kHz) and high frequency output (MHz), such as: the receiving end of a video transmission system, it must be used immediately The horizontally synchronized scanning signal of the screen is used to generate high-frequency clock output as an analog digital converter. The traditional phase-locked loop must use the division of the ancient multiples (N) to achieve the purpose of high frequency multiplication. For example, ^ 20 causes a huge phase error accumulation. In addition, as the frequency of the reference signal decreases, the loop bandwidth of the system must be reduced accordingly, causing the lock effect to suppress external noise. ". Law You can see that there are still many shortcomings in the above-mentioned custom items, which are not the designer of the cover, and need to be improved urgently. Meaning ° In view of the various shortcomings derived from the conventional frequency synthesizing circuit, I am eager to improve and innovate, and after years of hard work, I have studied the paper scale _ 546923 A7 B7 V. Description of the invention (2) 10 15 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20. After the main number lock, the frequency synthesis circuit was successfully developed. [Objective of the Invention] The purpose of the present invention is to provide a frequency synthesizing circuit that utilizes the effects of the phase-locked loop and the delay loop to double the frequency multiplication, thereby eliminating the problems of phase error accumulation and single-channel bandwidth of the traditional phase-locked loop. . A second object of the present invention is to provide a frequency synthesizing circuit suitable for the design and application of any programmable frequency synthesizer. It also shows good results for frequency synthesis applications with low reference signal frequency (~ kHz) and high-frequency output (> 100MHz). /, 'Another object of the present invention is to provide a frequency synthesizing circuit, the frequency multiplication technology in the basin, which can be applied to the clock generation circuit design of video transmission ^ —I »* [Technical Content] The above-mentioned purpose of the invention can be achieved Frequency synthesizing circuit and phase-locked loop; among them, the frequency doubling circuit can convert the low-frequency ^ frequency to high-frequency signals' as a reference for the phase-phase loop [the loop bandwidth of the 5-year-old conversion circuit can be further increased. This phase-locked response. Blind jitter is mixed here. 'Reference letter narrating the multiplication of electric frequency by Xiao Xiang to use the delay to return to the shirt to test: Cheng technology,' and through the synthesis of the phase to achieve the octave—Xi Xiangfan round out the letter. The function of frequency doubling can reduce phase locking: the phase error accumulated by the delay loop and the resulting frequency doubling factor can be divided by the frequency doubling circuit and phase locked loop of the high octave ^ by _Lock its letter (please first Read the notes on the back # .Fill in this page} • Binding--Line-^^ scale applies to China Guoer 546923 A7 B7 V. Description of the invention (order) 5 10 15 [Simplified illustration of the drawing] Attached to the present invention " 'Detailed description of the preferred embodiment and its = 2: Step by step to understand the technical content of the present invention and its purpose and effectiveness; The drawings related to this embodiment are: Figure 1 is a traditional frequency synthesizer architecture diagram; Figure 2 is this The structure diagram of the frequency synthesizing circuit of the invention; three is a multi-phase wheel output signal that is equally divided into one cycle; FIG. Four is a circuit architecture diagram that uses four-phase wheel frequency output that is equally divided into one cycle; Signal sharing of four-phase frequency output that equally divides one cycle Analyze the picture; synthesize the double with the ^ number. Figure 6 is the use of the 8 phase of the equal period to make Q2, and the output signal divided by 4 times _; twice the frequency ... _Bit signal mirror f double frequency phase synthesizer architecture diagram; and Figure 8 is a programmable frequency synthesis circuit architecture diagram. [Main part representative symbols] 14 phase frequency comparator 16 charge-discharge filter 18 voltage control oscillator 20 frequency divider 41 frequency multiplier circuit 42 phase-locked loop-.-(Please read the precautions on the back before filling this page) Order · 丨 Line! This paper size 3 is used in China. Guarantee standard (CNS) A4 specification (21〇 ^^; 546923
A7 Β7 發明說明（f) 51延遲電路 52延遲電路 53延遲電路 54延遲電路 55相位偵測器 ~ 56迴路慮波器 57相位合成器 58相位頻率比較器 59迴路濾波器 60電壓控制震盪器 61除頻器 62參考信號 63控制信號 65南頻信號 66輸出信號 67輪出信號 68輸出信號 69直流電壓 70輸出相位 71信號 81數位邏輯選擇器 .82多工器 83相位合成器 【較佳實施例】 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ----------------------^ . (請先閱讀背面之注意事項再填寫本頁) --線- 經濟部智慧財產局員工消費合作社印製 546923 Α7 __Β7 — PA010272.TWP - 7/12 五、發明說明（ 請參閱圖二，本發明所提供之頻率合成電路，主要係 由倍頻電路41和鎖相迴路42所組成；其中，倍頻電路41把 低頻輸入之參考信號62轉換成高頻之參考信號65並且提供 給鎖相迴路42作為參考信號。相位頻率比較器（pfd)58比較 5參考信號65和輸出信號67之相位與頻率差異，藉此輸出修 正信號68。輸出信號68被迴路濾、波器（CP)59轉換成實質的 直流電壓69，以進一步調整電壓控制震盪器（VC〇)60的頻 率。 電壓控制震盪器60之輸出信號66可藉由除頻器61降 10頻，其中降頻器之輸出信號67將接到相位頻率比較器58。 發明中之倍頻電路41包含延遲電路51_54、相位偵測器 55(PD)55、與迴路濾波器（CP)56。其中延遲電路51_54可由n 個延遲元件所組成，（在此延遲電路是由延遲元件51至54 所組成），延遲元件可為任何可調延遲時間之電路，其延 15遲時間由控制信號63加以控制。輸入之參考信號62經由一 連_的延遲電路可在延遲元件之輸出端得到不同相位但頻 率相同之信號。相位偵測器（PD)55可偵測最後一個延遲元 件之輸出相位70與輸入之參考信號62之相位差，藉此產生 修正信號71，此信號可經由迴路濾波器（CP)56轉成實質電 20壓之控制信號63來控制延遲電路之延遲時間。當延遲鎖相 迴路達到鎖相狀態，將可在延遲電路51-54上得到均分一 個週期、且每個延遲元件之輸出相位都相差¥的多相位 η 輸出信號，如圖三所示。 ---；-----------裝--------訂---------線 (請先閱讀背面之注音？事項再填寫本頁)A7 Β7 Description of the invention (f) 51 delay circuit 52 delay circuit 53 delay circuit 54 delay circuit 55 phase detector ~ 56 loop filter 57 phase synthesizer 58 phase frequency comparator 59 loop filter 60 voltage control oscillator 61 Frequency converter 62 reference signal 63 control signal 65 south frequency signal 66 output signal 67 wheel out signal 68 output signal 69 DC voltage 70 output phase 71 signal 81 digital logic selector. 82 multiplexer 83 phase synthesizer [preferred embodiment] This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) ---------------------- ^. (Please read the note on the back first Please fill in this page for further information) --Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 546923 Α7 __Β7 — PA010272.TWP-7/12 V. Description of the Invention It is mainly composed of frequency doubling circuit 41 and phase locked loop 42. Among them, frequency doubling circuit 41 converts low frequency input reference signal 62 into high frequency reference signal 65 and provides it to phase locked loop 42 as a reference signal. Phase frequency comparison (Pfd) 58 Compare 5 References The phase and frequency of the signal 65 and the output signal 67 are different, thereby outputting a correction signal 68. The output signal 68 is converted into a substantial DC voltage 69 by a loop filter, a wave filter (CP) 59, to further adjust the voltage-controlled oscillator (VC). ) 60. The output signal 66 of the voltage-controlled oscillator 60 can be reduced by 10 by the frequency divider 61, and the output signal 67 of the frequency reducer will be connected to the phase frequency comparator 58. The frequency doubling circuit 41 in the invention includes Delay circuit 51_54, phase detector 55 (PD) 55, and loop filter (CP) 56. Among them, delay circuit 51_54 can be composed of n delay elements (here, the delay circuit is composed of delay elements 51 to 54) The delay element can be any circuit with adjustable delay time, and its delay time is controlled by the control signal 63. The input reference signal 62 can get different phases but the same frequency at the output of the delay element through a delay circuit of _ The phase detector (PD) 55 can detect the phase difference between the output phase 70 of the last delay element and the input reference signal 62, thereby generating a correction signal 71, which can be filtered by the loop The controller (CP) 56 is converted into a control signal 63 of substantially 20 voltages to control the delay time of the delay circuit. When the delay phase locked loop reaches the phase locked state, one cycle can be divided equally on the delay circuits 51-54, and each A multi-phase η output signal whose output phases are different from each other by ¥, as shown in Figure 3. ---; ----------------------- order --- ------ Line (Please read the Zhuyin on the back? (Fill in this page again)
546923 A7546923 A7
五、發明說明（g ) 谨。:由閱圖四所7F ’此為二倍倍頻相位合成器基本架 φ，<；£)2’</)3，（^4，為延遲鎖相迴路所產生之均分 -個週期之四相位輸出信號，其間之相位差為： ' 8/12 5 10 15- 經濟部智慧財產局員工消費合作社印製 20 △Θ=27γ/4=τγ/2 、工由四相位4號之混波可在輸出 頻之信號。其簡單分析如下（請參閱圖五）： 輝igh)=(0^ = ^师削7^ Θ ❿/2) = (Δ θ 0 ^+Δ ㈧ 少 3(High)=(；r 0 $2；Γ ) = (2Δ θ $ θ $ π +2Δ θ ) ^4(High)=(3^/2^ θ ^5^/2) = (3Δ , ^ ^ ^ ^+3Δ 0) Q (High)，θ $ θ ㈣ θ) U (3Δ θ $ θ θ) -{π /2^ θ ^ n)\J (3π /2^ θ ^ 2π) =Φ lx φ 2 + ρ 3χ ρ 4 (High) = (〇^ θ ^Αθ)ϋ (2^θ ^3ΑΘ) -(0^ θ ^ π /2) U (π ^ θ ^ 3π /2) = <Μχ φ 4+φ2χ φ 3 由Q與Q’之布林函數表示式可得電流模式組之二倍 頻相位合成電路。 σ 依此觀念，利用均分一週期之η個相位輸出信號^ 為偶數），設其間之相位差△ 0 ==$，透過相位的合成將 可產生音倍頻之輸出結果。其差動輪出之一般之表示式 為： Q (High)= (Δ θ ^ ^ 2Δ Θ ) U (3Δ Θ ^ ^ 4Δ θ ) υ (請先閱讀背面之注，意事展再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） 經濟部智慧財產局員工消費合作社印製 546923 B7 ---ΡΑΰΊΰϋ/^Twp - y/ii 五、發明說明（2 ) (Δ50 ^ θ ^ 6Δ Θ ) U 〇 0 〇 〇 〇 〇 〇 〇 〇 〇 ((η-1)θ £ θ £ η/\ θ ) =Φΐχ φ 2 + φ 3χ φ 4 + φ 5χ φ6+。 。+ $ (η-1)χ ρ η Q’ (High) = (〇 ^θ^/\θ)υ(2^θ^θ $3Δ0)υ ((η-1)0 ^ θ ^ ηΑ θ) =φηχ φ1+(/>2χ φ3+φ4χ φ5+。。+ $ (η-2)χ φ (η-1) 據此，我們可將倍頻觀念推而廣之。假設有一均分 週期之η相位參考信號（η=，），透過不同相位之合成，我 1〇_們將可產生2^1，2Μ-2。。，21，之不同倍頻輸出信號。 其中，2叫倍頻之輸出信號一般式為： Q (High) = φ1χ φ2 + φ3χ φ4 + φ5χ φ6+ο ο + ρ (η-1)χ φ η -共2^1項 15 Q’（High)= φηχ φ1+φ2χ φ3+φ4χ φ5+。° + φ (η-2)χ φ (η-1) -共2λ^項 • 2Λ//_2倍頻之輸出信號一般式為： Q (High) = plx φ3+φ5χ φ7 + φ9χ pll+0 ° + φ 20 (η-3)χ ψ{ηΑ) -共2〃-2項 Q’（High) = φ (η-1 )χ φ I + φ 3χ φ 5 + φ Ίχ φ 9 + 〇。+ φ (η-5)χ φ (η-3) -共2Μ_2項 _ -9- 本紙張尺摩適用中國國家標準（CNS)A4規袼（210 χ 297公爱） ----I------------------------- (請先閱讀背面之注意事項再填寫本頁) 546923 A7 B7 五、發明說明（ PA010272.TWP - 10/12 經濟部智慧財產局員工消費合作社印製 倍頻之輸出信號一般式為： Q (High) - φ ΐχ φ (i+M-1) + φ (Μ+Μ-1) χ φ (2Μ-1 + Μ-1) -共21項 Q (High) = φ (n-M+2)x φ 1 + φ (1+ Μ-1) χ φ (Μ+Μ-1) -共21項 圖六所示為利用均分一週期之8相位信號合成之兩倍 頻Q2 ’與四倍頻Q4之輸出信號分析結果。 圖七所示為利用均分一週期之11相位信號^倍倍頻相 2 位合成器之架構。 請參閱圖八所示，此為可程式化之頻率合成電路，主 要係由倍頻電路4卜數位邏輯選擇器81、多工器82、相位 合成器83及鎖相迴路42所組成；其中該倍頻電路^產生均 分參考信號週期之多相位輸出，並配合數位邏輯選擇器Μ 選擇對應多相位參考信號輸出至多功器82再經過相位合成 器83,藉由相位合成器83之作用以合成不同之等效倍頻信 號；而相位合成器的輸出即作為鎖相迴路4?之 其中數位邏輯選擇器81可根據外部之倍頻控制信號^輸 出相位定址，再經由多工器將選定之相位輸出。以圖 例，一個8相位之參考信號可分別藉由輸出不同相位及相 20位合成而分別達到兩倍頻與四倍頻之倍頻輸出。 【特點及功效】 ' 本發明所提供之頻率合成電路，與前述引證案及 習用技術相互比較時，更具有下列之優點： >、八 10 15 表紙張尺度適种關家標準（CNS)A4規^297公f ---------------------訂--------I (請先閱讀背面之注意事項再填寫本頁) 546923 A75. Description of the Invention (g) Sincerely. : By the 7F in the picture 4 "This is the basic frame of the double frequency phase synthesizer φ, <; £) 2 '< /) 3, (^ 4, which is the equal division generated by the delay phase-locked loop-one The output signal of the four-phase period, the phase difference between them is: '8/12 5 10 15- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 20 △ Θ = 27γ / 4 = τγ / 2 The mixed signal can be a signal at the output frequency. Its simple analysis is as follows (see Figure 5): 辉 igh) = (0 ^ = ^ 师 剪 7 ^ Θ ❿ / 2) = (Δ θ 0 ^ + Δ 少 less 3 ( High) = (; r 0 $ 2; Γ) = (2Δ θ $ θ $ π + 2Δ θ) ^ 4 (High) = (3 ^ / 2 ^ θ ^ 5 ^ / 2) = (3Δ, ^ ^ ^ ^ + 3Δ 0) Q (High), θ $ θ ㈣ θ) U (3Δ θ $ θ θ)-(π / 2 ^ θ ^ n) \ J (3π / 2 ^ θ ^ 2π) = Φ lx φ 2 + ρ 3χ ρ 4 (High) = (〇 ^ θ ^ Αθ) ϋ (2 ^ θ ^ 3ΑΘ)-(0 ^ θ ^ π / 2) U (π ^ θ ^ 3π / 2) = < Μχ φ 4+ φ2χ φ 3 From the Bollinger function expressions of Q and Q ', a two-frequency phase synthesizing circuit of the current mode group can be obtained. σ According to this concept, using the η phase output signals averaging one period ^ as an even number), and setting the phase difference Δ 0 == $ between them, the phase multiplication can produce the output result of tone multiplication. The general expression of the differential wheel is: Q (High) = (Δ θ ^ ^ 2Δ Θ) U (3Δ Θ ^ ^ 4Δ θ) υ (Please read the note on the back first, and the event exhibition, then fill out this page) This paper size applies to China National Standard (CNS) A4 (21〇X 297 public love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 546923 B7 --- ΡΑΰΊΰϋ / ^ Twp-y / ii 5. Description of the invention (2) (Δ50 ^ θ ^ 6Δ Θ) U 〇0 〇〇〇〇〇〇〇〇〇 ((η-1) θ £ θ £ η / \ θ) = Φΐχ φ 2 + φ 3χ φ 4 + φ 5χ φ6 +. . + $ (η-1) χ ρ η Q '(High) = (〇 ^ θ ^ / \ θ) υ (2 ^ θ ^ θ $ 3Δ0) υ ((η-1) 0 ^ θ ^ ηΑ θ) = φηχ φ1 + (/ > 2χ φ3 + φ4χ φ5 + ... + $ (η-2) χ φ (η-1) Based on this, we can extend the concept of frequency doubling. Suppose there is an η phase reference with an equal period The signal (η =,), through the combination of different phases, we can produce 2 ^ 1, 2M-2 ..., 21, different frequency multiplied output signals. Among them, 2 is called the frequency multiplied output signal in general The formula is: Q (High) = φ1χ φ2 + φ3χ φ4 + φ5χ φ6 + ο ο + ρ (η-1) χ φ η-2 ^ 1 terms in total 15 Q '(High) = φηχ φ1 + φ2χ φ3 + φ4χ φ5 + ° + φ (η-2) χ φ (η-1)-2λ ^ terms in total • The output signal of 2Λ // _ 2 octave is generally: Q (High) = plx φ3 + φ5χ φ7 + φ9χ pll + 0 ° + φ 20 (η-3) χ ψ {ηΑ)-A total of 2〃-2 terms Q '(High) = φ (η-1) χ φ I + φ 3χ φ 5 + φ Ίχ φ 9 + 〇. + φ (η-5) χ φ (η-3)-2M_2 items in total _ -9- This paper ruler applies the Chinese National Standard (CNS) A4 Regulation (210 χ 297 public love) ---- I-- ----------------------- (Please read the precautions on the back before filling this page) 546923 A7 B7 V. Description of the invention (PA010272.TWP-10 / 12 The general formula for the output signal printed by the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is: Q (High)-φ ΐχ φ (i + M-1) + φ (Μ + Μ-1) χ φ (2Μ-1 + Μ-1)-21 items in total Q (High) = φ (n-M + 2) x φ 1 + φ (1+ Μ-1) χ φ (Μ + Μ-1)-21 items in total Shown is the analysis result of the output signal of the double frequency Q2 'and the quadruple frequency Q4 synthesized by using the 8-phase signal of the equal-divide period. The structure of the synthesizer. Please refer to Figure 8. This is a programmable frequency synthesizing circuit, which is mainly composed of a frequency doubling circuit, a digital logic selector 81, a multiplexer 82, a phase synthesizer 83, and a phase-locked loop 42. The multiplier circuit ^ generates a multi-phase output that equally divides the reference signal period, and cooperates with a digital logic selector M to select Select the corresponding multi-phase reference signal and output it to the multiplexer 82 and then pass through the phase synthesizer 83. The effect of the phase synthesizer 83 is used to synthesize different equivalent frequency doubling signals; and the output of the phase synthesizer is used as the phase-locked loop 4? Among them, the digital logic selector 81 can output the phase address according to the external frequency multiplication control signal ^, and then output the selected phase through the multiplexer. For example, an 8-phase reference signal can output different phases and 20-bit phases respectively. Combined to achieve double-frequency and quadruple-frequency output. [Features and Effects] 'The frequency synthesis circuit provided by the present invention has the following advantages when compared with the aforementioned citations and conventional technologies: > , 8 10 15 table paper standards suitable for family standards (CNS) A4 regulations 297 public f --------------------- order ------- -I (Please read the notes on the back before filling this page) 546923 A7