546787 93 59twf 1 .doc/008546787 93 59twf 1 .doc / 008
Λ7 W 經濟部智慧財產局員工消費合作社印製 爲第91Π7119號說明書修正本 修正 五、發明說明（丨） 本發明是有關於一種快閃記憶體（F1 ash Memory)的讀 取方法，且特別是有關於一種具有矽-氧化矽/氮化矽/氧化 矽-矽（SONOS)結構之快閃記憶體的讀取方法。 記憶體，顧名思義便是用以儲存資料或數據的半導體 元件。當電腦微處理器之功能越來越強，軟體所進行之程 式與運算越來越龐大時，記憶體之需求也就越來越高，爲 了製造容量大且便宜的記億體以滿足這種需求的趨勢，製 作記憶體元件之技術與製程，已成爲半導體科技持續往高 積集度挑戰之驅動力。 舉例來說，快閃記憶體元件由於具有可多次資料之存 入、讀取、抹除等動作，且存入之資料在斷電後也不會消 失之優點，所以已成爲個人電腦和電子設備所廣泛採用的 一種記憶體元件。 對快閃式記億體而言，具有遂穿氧化層之可抹除且可 程式唯讀記憶體（EPROM with Tunnel Oxide，ETOX)記憶 胞爲一種最爲普遍之記憶胞結構，墓通常篮以通道熱電子 (Channel Hot-Electron，CHE )程式化，並且通過源極旁 邊或通道區域以Fowler-Nordheim (F-N)穿|抹除。 而且，一般ETOX記憶胞係以摻雜的多晶矽製作浮置 閘極（Floating Gate)與控制閘極（Control Gate)。當記 憶體進行程式化（Program)時，注入浮置閘極的電子會均 勻分布於整個多晶矽浮置閘極餍之中。然而，當多晶矽浮 置閘極層下方的穿隧氧化層有缺陷存在時，就容易造成元 件的漏電流，影響元件的可靠度。 3 1·-------I---- ^ --------^--------丨線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規恪（210x 297公釐） 546787 9359twf 1 .doc/008 Λ7 B7 W年/〇月/ 心修正補充 經濟部智慧財產局員工消費合作社印製 爲第9 11 1 7 1 1 9號說明書修正本 修正日期:2 0 〇 2 1 〇 ^ 五、發明說明（"Z/ ) 1G·16 因此，爲了解決ETOX記憶胞漏電流（資料保存）之問 題，目前習知的一種方法是採用一電荷陷入層取代多晶砂 浮置閘極’此電荷陷入層之材質例如是氮化砂。這種氮化 矽電荷陷入層上下通常各有一層氧化矽，而形成一種具有 矽-氧化矽/氮化矽/氧化矽-砂（SONOS)結構之記憶胞。當施 加電壓於此元件之控制閘極與源極區/汲極區上以進行程 式化時’通道區中接近汲極區之處會產生熱電子而注入電 荷陷入層中。由於注入電荷陷入層之中的電子並不會均与 分布於整個電荷陷入層之中，而是集中於電荷陷入層的局 部區域上，並在通道方向上呈高斯分布，因此對於穿麗氧 化層中缺陷的敏感度較小，元件漏電流的現象較不易發 生。 然而，對於SONOS結構之記憶胞而言，注入電荷陷 入層的電子僅集中於局部的區域，而在讀取經程式化後記 憶胞之資料時造成漏電流，容易使得讀取操作時，資料之 判別錯誤。 有鑑於此，本發明的目的在於提供一種具有矽-氧化 矽/氮化矽/氧化矽-矽（SONOS)結構之快閃記憶體的讀取方 法’能夠提高記憶體元件在讀取時的操作效率。 本發明提出一種具有矽-氧化矽/氮化矽/氧化矽-矽 (SONOS)結構之快閃記憶體的讀取方法，其中具有S〇n〇s 結構之快閃記憶體是由基底、設置於基底中之P型井區、 設置於基底上的穿隧氧化層、設置穿隧氧化層上的電荷陷 入層、設置於電荷陷入層上的介電層、設置於介電層上的 4 ---— — — — — — — — — — — ·1111111 ·11111111 先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規烙（210x 297公釐） 546787 9359twfl .doc/008 Λ7 修正i 補无丨 經濟部智慧財產局員工消費合作社印製 爲第91117119號說明書修正本 修正日期：2002.1 0.16 五、發明說明（)） 閘極導體層與設置於閘極導體層兩側之基底中的源極區與 汲極區所構成，此SONOS結構之快閃記憶體之讀取方法 係對具有SONOS結構之快閃記憶體的汲極區施加一正電 壓，源極區爲浮置、P型井區接地，以產生一閘極誘導汲 極漏（Gate Induced Drain Leakage，GIDL)電流，並且於汲 極區測量閘極誘導汲極漏（GIDL)電流以讀取記憶體中之儲 存資料。 在對本發明的SONOS快閃記憶體進行讀取操作時， 對汲極區施加3伏特至5伏特之電壓、將源極區浮置、P 型井區接地，而在汲極區產生閘極誘導汲極漏電流。當鄰 接汲極區之電荷陷入層充負電（程式化），在電荷陷入層和 汲極區之間的電場較大，如此會產生一大的閘極誘導汲極 漏電流。當記憶胞沒有程式化（例如電荷陷入層沒有電子 或略具正電荷），在電荷陷入層和汲極區之間的電場較小， 而產生一小的閘極誘導汲極漏電流。故可藉由測量經過汲 極區的閘極誘導汲極漏電流的電流大小來判斷儲存於此記 憶胞中的數位資訊是「1」還是「〇」。此外，爲了提高閘 極誘導汲極漏電流，還可以對閘極導體層施加-3伏特至-5 伏特之負電壓。 由於本發明之SONOS記憶胞的穿隧氧化層之厚度（爲 20埃左右）較習知的ETOX記憶胞之穿隧氧化層之厚度（至 少爲90埃以上）爲薄，因此在使用通道熱載子注入法進行 編程或抹除時，電子能夠較容易的穿過穿隧層，進而提高 記憶體元件的操作效率。 5 J------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)Al規恪（210 x 297公釐） 546787 9359twfl .doc/008 Λ7 經濟部智慧財產局員工消費合作社印製 爲第Λ^Ι丨9 明書修正本 修正曰期：2〇〇2.10.16 發明說明（％) 而且’穿險氧化層之厚度較薄，就可以使用較低的操 作電壓進行編程或抹除的操作，因此記憶胞的尺寸能夠再 向下縮小，而達到高集積化的目的。 此外’聞極誘導汲極漏電流與穿隧氧化層之厚度有 關’隻穿隧氧化層越薄閘極誘導汲極露電流越大，舉例來 說穿隧氧化層厚度爲20埃時所量測到之閘極誘導汲極漏 電流爲穿隧氧化層厚度爲90埃時之1000倍，因此當穿險 氬北層霞度爲時，對汲極區施加正3.5伏特之偏壓、 對閘極施加負3.5伏特之偏壓，就可以使閘極誘導汲極漏 電流可能達到微安培等級，而可以準確的讀取記憶胞上之 資料。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖所繪示爲本發明較佳實施例之一種SONOS記 憶胞的剖面示意圖。 第2圖所繪示爲本發明較佳實施例之一種SON〇s記 憶胞的編程方法。 第3圖所繪示爲本發明較佳實施例之一種SONOS記 憶胞的讀取方法。 第4圖所繪示爲本發明較佳實施例之一種SONOS記 憶胞的抹除方法。 圖式之標示說明ιό I.--^----------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNSW規恪（210 x 297公釐） 546787 9359twf 1 .doc/008 Λ7 B7 ^ / ^1〇 i ί I：：] 修正補充 經濟部智慧財產局員工消費合作社印製 爲第91Π7119@說明書修正本 修正日期：2002.10.】6 五、發明說明（ί ) 100 :基底 102 :穿隧氧化層 104 :電荷陷入層 106 :介電層 108 :閘極導體層 110 :閘極結構 112 :源極區 114 :汲極區 116 :通道區 實施例 第1圖所繪示爲本發明較佳實施例之一種SONOS快 閃記憶體的剖面示意圖。 請參照第1圖，本發明較佳實施例之SONOS快閃記 憶體的結構包括基底1〇〇、Ρ型井區1〇卜穿隧氧化層102、 電荷陷入層104、介電層106、閘極導體層108、源極區112、 汲極區114以及通道區116。 基底100的材質例如是矽，並且此基底1〇〇中El形成 一 P型井區1〇1。 穿隧氧化層102係設置於基底100上，形成此穿隧氧 化層102的方法例如是熱氧化法，其厚度例如是20埃左 右。 電荷陷入層104係設置於穿隧氧化層102上，其中電 荷陷入層104的材質例如是氮化矽，形成電荷陷入層104 的方法例如是化學氣相沈積法，其厚度例如是45埃左右。 7 I------------裝---II--—訂·--------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A:1規恪（210x 297公堃） 546787Λ7 W Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs as No. 91Π7119 Amendment V. Invention Description (丨) The present invention relates to a method for reading flash memory (F1 ash memory), and in particular The invention relates to a method for reading flash memory with a silicon-silicon oxide / silicon nitride / silicon oxide-silicon (SONOS) structure. Memory, as its name implies, is a semiconductor device used to store data or data. As the functions of computer microprocessors become more and more powerful, and the programs and calculations performed by software become more and more huge, the demand for memory will become higher and higher. The trend of demand, the technology and process of making memory components, have become the driving force of semiconductor technology's continued challenge to high accumulation. For example, flash memory components have become a personal computer and electronics because they can store, read, and erase data multiple times, and the stored data will not disappear even after the power is turned off. A memory element widely used in devices. For flash memory, the erasable and programmable read-only memory (EPROM with Tunnel Oxide, ETOX) memory cell with a tunneling oxide layer is one of the most common memory cell structures. Channel Hot-Electron (CHE) is programmed and erased by Fowler-Nordheim (FN) by the source or channel area. In addition, the general ETOX memory cell line is made of doped polycrystalline silicon to make a floating gate and a control gate. When the memory is programmed, the electrons injected into the floating gate are evenly distributed throughout the polycrystalline silicon floating gate 餍. However, when there is a defect in the tunneling oxide layer under the polycrystalline silicon floating gate layer, it is easy to cause the leakage current of the element and affect the reliability of the element. 3 1 · ------- I ---- ^ -------- ^ -------- 丨 Line (Please read the precautions on the back before filling this page) This paper Standards are applicable to Chinese National Standard (CNS) A4 (210x 297 mm) 546787 9359twf 1 .doc / 008 Λ7 B7 W / O / A Correction of Supplements Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives Printed as 9 11 1 No. 7 1 1 No. 9 revision of this revision date: 2 0 〇 2 1 〇 ^ 5. Description of the invention (" Z /) 1G · 16 Therefore, in order to solve the problem of ETOX memory cell leakage current (data storage), it is currently known One method is to replace the polycrystalline sand floating gate with a charge trapping layer. The material of the charge trapping layer is, for example, nitrided sand. This silicon nitride charge trapping layer usually has a layer of silicon oxide above and below it to form a memory cell with a silicon-silicon oxide / silicon nitride / silicon oxide-sand (SONOS) structure. When a voltage is applied to the control gate and source / drain regions of the device for programming, thermal electrons are generated near the drain region in the channel region and the charge is injected into the layer. Since the electrons injected into the charge trapping layer are not evenly distributed in the entire charge trapping layer, they are concentrated in a local area of the charge trapping layer and have a Gaussian distribution in the channel direction. The sensitivity of the defects is small, and the phenomenon of component leakage current is less likely to occur. However, for a memory cell of the SONOS structure, the electrons injected into the charge trapping layer are concentrated in only a local area, and leakage of current occurs when reading the data of the programmed memory cell, which easily makes the data Judgment is wrong. In view of this, an object of the present invention is to provide a method for reading a flash memory having a silicon-silicon oxide / silicon nitride / silicon oxide-silicon (SONOS) structure, which can improve the operation of a memory element during reading. effectiveness. The invention provides a method for reading a flash memory with a silicon-silicon oxide / silicon nitride / silicon oxide-silicon (SONOS) structure. The flash memory with a Sonos structure is composed of a substrate and a substrate. A P-type well region in the substrate, a tunneling oxide layer disposed on the substrate, a charge trapping layer disposed on the tunneling oxide layer, a dielectric layer disposed on the charge trapping layer, and a 4- --—— — — — — — — — — — — · 1111111 · 11111111 Read the notes on the back before filling out this page) This paper size applies the Chinese National Standard (CNS) A4 (210x 297 mm) 546787 9359twfl .doc / 008 Λ7 Amendment No. 丨 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy as No. 91117119. Amendment date of this amendment: 2002.1 0.16 V. Description of the invention ()) Gate conductor layer and provided on the gate conductor layer The source and drain regions in the substrate on both sides are composed. The read method of the SONOS flash memory is to apply a positive voltage to the drain region of the flash memory with the SONOS structure. Grounding floating, P-type wells To generate a gate induced drain leakage (Gate Induced Drain Leakage, GIDL) current, and the drain region is measured at a gate-induced drain leakage (the GIDL) current memory to read data in the storage. When the SONOS flash memory of the present invention is read, a voltage of 3 volts to 5 volts is applied to the drain region, the source region is floated, and the P-type well region is grounded, and a gate induction is generated in the drain region. Drain leakage. When the charge trapping layer adjacent to the drain region is negatively charged (programmed), the electric field between the charge trapping layer and the drain region is relatively large, which will generate a large gate-induced drain leakage current. When the memory cell is not programmed (for example, the charge trapping layer has no electrons or is slightly positively charged), the electric field between the charge trapping layer and the drain region is small, and a small gate-induced drain leakage current is generated. Therefore, it can be judged whether the digital information stored in this memory cell is "1" or "0" by measuring the current of the gate-induced drain leakage current through the drain region. In addition, in order to increase the gate-induced drain leakage current, a negative voltage of -3 volts to -5 volts may be applied to the gate conductor layer. Since the thickness of the tunneling oxide layer of the SONOS memory cell of the present invention (about 20 angstroms) is thinner than the thickness of the tunneling oxide layer of the conventional ETOX memory cell (at least 90 angstroms), the channel heat load is used. When the sub-injection method is used for programming or erasing, electrons can easily pass through the tunneling layer, thereby improving the operating efficiency of the memory element. 5 J ------------ installation -------- order --------- line (please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) Al Regulations (210 x 297 mm) 546787 9359twfl .doc / 008 Λ7 Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as amended by ^^ 丨 丨 9 Date of amendment: 2 〇〇2.10.16 Description of the invention (%) And the thickness of the wear-resistant oxide layer is thinner, it can be programmed or erased with a lower operating voltage, so the size of the memory cell can be reduced further down to reach The purpose of high integration. In addition, the 'sense-induced drain leakage current is related to the thickness of the tunneling oxide layer'. Only the thinner the tunneling oxide layer is, the larger the gate-induced drain current is. The gate-induced drain leakage current is 1000 times the thickness of the tunneling oxide layer at 90 angstroms. Therefore, when the cross-layer argon north layer is Xia degree, a positive 3.5 volt bias is applied to the drain region, and the gate is applied to the gate electrode. With a negative bias voltage of 3.5 volts, the gate-induced drain leakage current may reach the microampere level, and the data on the memory cell can be accurately read. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1 The drawing is a schematic cross-sectional view of a SONOS memory cell according to a preferred embodiment of the present invention. FIG. 2 shows a programming method of a SONos memory cell according to a preferred embodiment of the present invention. FIG. 3 illustrates a method for reading a SONOS memory cell according to a preferred embodiment of the present invention. FIG. 4 illustrates a method for erasing a SONOS memory cell according to a preferred embodiment of the present invention. Schematic labeling instructions ιό I .-- ^ ---------- install -------- order --------- line (please read the precautions on the back first) (Fill in this page) This paper size applies Chinese national standards (CNSW regulations (210 x 297 mm) 546787 9359twf 1 .doc / 008 Λ7 B7 ^ / ^ 1〇i ί I:] Amendment to supplement the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperatives as 91Π7119 @ Instruction Manual Revised Date: 2002.10.] 6 V. Description of Invention (ί) 100: substrate 102: tunneling oxide layer 104: charge trapping layer 106: dielectric layer 108: gate conductor Layer 110: Gate structure 112: Source region 114: Drain region 116: Channel region Example 1 shows a schematic cross-sectional view of a SONOS flash memory according to a preferred embodiment of the present invention. Please refer to FIG. The structure of the SONOS flash memory in the preferred embodiment of the present invention includes a substrate 100, a P-type well region 10 tunneling oxide layer 102, a charge trapping layer 104, a dielectric layer 106, and a gate conductor layer 108. , Source region 112, drain region 114, and channel region 116. The material of the substrate 100 is, for example, silicon, and El in this substrate 100 forms a P-type well region 101. Wear The oxide layer 102 is disposed on the substrate 100, and a method for forming the tunneling oxide layer 102 is, for example, a thermal oxidation method, and the thickness thereof is, for example, about 20 angstroms. The charge trapping layer 104 is disposed on the tunneling oxide layer 102, and the charge traps therein. The material of the layer 104 is, for example, silicon nitride, and the method for forming the charge trapping layer 104 is, for example, a chemical vapor deposition method, and its thickness is, for example, about 45 angstroms. 7 I ------------ install-- -II --- Order · -------- Line (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A: 1 (210x 297 cm) 546787
Λ7 \M 修正日期：2002.1 0.1 6 93 59twf 1 .doc/008 爲第9 1 1 1 7 1 1 9號說明書修正本 五、發明說明（〔） 介電層106係設置於電荷陷入層104上，其中介電層 106的材質例如是氧化矽，形成介電層106的方法例如是 化學氣相沈積法，其厚度例如是35埃左右。 閘極導體層108係設置於介電層106上，其中閘極導 體層108的材質例如是多晶矽，形成的方法例如是化學氣 相沈積法。並且，上述的穿隧氧化層102、電荷陷入層104、 介電層106、閘極導體層108的堆疊結構係構成閘極結構 110 ° 源極區112與汲極區114設置於閘極結構110兩側的 基底100中，且部分源極區112與汲極區114延伸至閘極 結構110下方，以增加閘極誘導汲極漏電流。源極區112 與汲極區114的摻雜型態例如是η型摻雜。 通道區116係設置於閘極結構110的下方、源極區112 與汲極區114之間的基底100中。 接著請參照表一及第2圖、第3圖、第4圖，以明瞭 本發明較佳實施例之SONOS快閃記憶體之操作模式，其 係包括編程(Program，第2圖）、資料讀取(Read，第3圖）， 以及抹除(Erase，第4圖）等操作模式。 I------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 8 本紙張尺度適用中國國家標準（CNS)A4規烙（210 X 297公釐） 546787 9359twf 1 .doc/008 Λ7 補充 爲第91117119號說明書修正本 修正日期：2002.1 0 16 五、發明說明（1 ) 表一Λ7 \ M Date of revision: 2002.1 0.1 6 93 59twf 1 .doc / 008 Amends the specification No. 9 1 1 1 7 1 1 9 V. Description of the invention ([) The dielectric layer 106 is provided on the charge trapping layer 104, The material of the dielectric layer 106 is, for example, silicon oxide, and the method of forming the dielectric layer 106 is, for example, a chemical vapor deposition method, and the thickness thereof is, for example, about 35 angstroms. The gate conductor layer 108 is disposed on the dielectric layer 106. The material of the gate conductor layer 108 is, for example, polycrystalline silicon, and the formation method is, for example, a chemical vapor deposition method. In addition, the above-mentioned stacked structure of the tunneling oxide layer 102, the charge trapping layer 104, the dielectric layer 106, and the gate conductor layer 108 constitutes the gate structure 110 °. The source region 112 and the drain region 114 are disposed on the gate structure 110. In the substrate 100 on both sides, part of the source region 112 and the drain region 114 extend below the gate structure 110 to increase the gate-induced drain leakage current. The doping patterns of the source region 112 and the drain region 114 are, for example, n-type doping. The channel region 116 is disposed in the substrate 100 below the gate structure 110 and between the source region 112 and the drain region 114. Next, please refer to Table 1 and FIG. 2, FIG. 3 and FIG. 4 to understand the operation mode of the SONOS flash memory according to the preferred embodiment of the present invention, which includes programming (program, FIG. 2), and data reading. Read (Figure 3), and erase (Erase, Figure 4) and other operating modes. I ------------ install -------- order --------- line (please read the notes on the back before filling this page) Printed by the Bureau's Consumer Cooperatives 8 This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 546787 9359twf 1 .doc / 008 Λ7 Added to the specification No. 91117119 Amendment Date: 2002.1 0 16 5 Description of the invention (1) Table 1
程式化 讀取 抹除 閘極 Vcg 二 Vcc 一二 Vcg 源極區 接地 浮置 浮置 汲極區 VD Vcc 浮置 P型井區 接地 接地 VR 經濟部智慧財產局員工消費合作社印製 第2圖所繪示爲本發明較佳實施例之一種SONOS快 閃記憶體的編程方法。請參照第2圖，在對本發明的SONOS 快閃記憶體進行編程時，首先對SONOS快閃記憶體之閘 極導體層1〇8(閘極）施加一電壓Veg，並將P型井區1〇1(基 底1〇〇)接地，以打開穿隧氧化層102下方以及源極區112 與汲極區114之間的一通道區116，其中施予閘極導體層 1〇8(閘極）之電壓Veg例如是6伏特至12伏特左右。接著， 對汲極區114施加一電壓VD，施予汲極區114之電壓VD 例如是5伏特左右，並將源極區112接地。在此種偏壓情 況下，即會產生大的通道電流，其中電子係由源極區II2 端向汲極區114端移動，且在汲極區114端被高通道電場 所加速而產生熱電子，其動能足以克服穿隧氧化層之能量 阻障，再加上閘極導體層1〇8(閘極）上施加有高正偏壓， 使得熱電子從汲極區114端注入電荷陷入層104中。在編 程之後，由於電荷陷入層104帶有淨負電荷，所以會令記 憶胞之啓始電壓（VT)上升。而這些電子除非故意的將其抹 9 本纸張尺度適用中國國家標準（CNS)A4規恪（210 X 297公釐） I------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 546787 93 59twf 1 .doc/〇〇8 Λ7 摘无; 經濟部智慧財產局員工消費合作社印製 號甲明書修正本 修正曰期：2002.10.1 6 五、發明况明（召） 除，否則會在電荷陷入層104中停留一段很長的時間。 第3圖所繪示爲本發明較佳實施例之本發明較佳實施 例之一種SONOS快閃記憶體的讀取方法。本發明之SONOS 快閃記憶體的讀取操作實際上是根據在汲極區114之閘極 誘導汲極遺漏（Gate Induced Drain Leakage，GIDL)電流的情 形，而閘極誘導汲極漏電流則與電荷陷入層1〇4之電荷儲 存情形有關。閘極誘導汲極漏電流經常發生在薄閘氧化層 金氧半導體（Metal Oxide Semiconductor，MOS)元件，其係 爲汲極區與/或源極區和基底之間的電流。在元件中聞極邊 緣下方之n+摻雜區域會產生一高縱向電場，並經由電子能 帶間穿遂效應，而在閘極邊緣下方之n+摻雜區之表面形成 電洞’當電洞流入基底便形成閘極誘導汲極漏電流。由於 在汲極區上之閘極誘導汲極漏電流會流入基底中，因此可 以量測到閘極誘導汲極漏電流。 請參照第3圖，在對本發明的SONOS快閃記憶體進 行讀取操作時，對汲極區114施加一偏壓爲V。。，其例如 是3伏特至5伏特左右、對閘極導體層1〇8(閘極)施加0V 或一負偏壓VJ-3伏特至-5伏特左右）、源極區112爲浮 置、P型井區101接地。當鄰接汲極區114之電荷陷入層 106充負電(程式化），在電荷陷入層106和汲極區114之間 的電場較大，如此而產生一大的閘極誘導汲極漏電流。當 記憶胞沒有程式化(例如電荷陷入層106沒有電子或略具正 電荷），在電荷陷入層106和汲極區114之間的電場較小， 而產生一小的閘極誘導汲極漏電流。故可藉由測量經過汲 10 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNSM4規烙（210 X 297公堃） 546787 經濟部智慧財產局員工消費合作社印製 Ιΰ；^Ι^ r 9359twf 1 .doc/008 ： 爲第9m7119號說兩書修正本 ΪΓ正日期:2002.10」6 五、發明說明（q ) 極區的閘極誘導汲極漏電流的電流大小來判斷儲存於此記 憶胞中的數位資訊是「1」還是「0」。 第4圖所繪不爲本發明較佳實施例之本發明較佳實施 例之一種SONOS快閃記憶體的抹除方法。請參照第4圖， 在對本發明的SONOS快閃記憶體進行抹除時，對S0N0S 快閃記憶體之閘極導體層108(閘極）施加一電壓-Veg，其中 施予閘極導體層1〇8(閘極）之電壓-Veg例如是-5伏特左右； 對P型井區1〇1(基底100)施加一電壓VB，施加於P型井 區1〇1(基底100)之電壓VB例如是5伏特左右；將源極區 與汲極區源極區112接地，如此，即可在閘極導體層1〇8(閘 極)與P井100之間建立一個大的電場，而得以利用通道FN- 穿隧效應將電子經由穿隧氧化層從電荷陷入層106中拉出 至通道中_。 依照本發明實施例所述，由於本發明之SONOS記憶 胞的穿隧氧化層之厚度（爲2〇埃左右)較習知的ΕΤΟχ記憶 胞之穿隧氧化層之厚度（至少爲90埃以上）爲薄，因此在使 用通道熱載子注入法進行編程或抹除時，電子能夠較容易 的穿過穿隧層，進而提高記憶體元件的操作效率。 而且，穿隧氧化層之厚度較薄，就可以使用較低的操 作電壓進行編程或抹除的操作，因此記億胞的尺寸能夠再 向下縮小，而達到高集積化的目的。 此外’閘極誘導汲極漏電流與穿隧氧化層之厚度有 關，亦即穿隧氧化層越薄閘極誘導汲極胤電流越大，舉例 來說穿隧氧化層厚度爲2〇埃時所量測到之閘極誘導汲極 I------------裝----丨—訂-------丨-線 (請先閱讀背面之注意事項再填寫本頁)Programmatically read and erase the gates Vcg 2 Vcc 1 2 Vcg source area ground floating floating drain area VD Vcc floating P-type well ground ground VR Printed by Figure 2 Illustrated is a programming method of a SONOS flash memory according to a preferred embodiment of the present invention. Please refer to FIG. 2. When programming the SONOS flash memory of the present invention, first apply a voltage Veg to the gate conductor layer 108 (gate) of the SONOS flash memory, and apply a P-type well area 1 〇1 (Substrate 100) is grounded to open a channel region 116 below the tunneling oxide layer 102 and between the source region 112 and the drain region 114, in which a gate conductor layer 108 (gate) is applied The voltage Veg is, for example, about 6 volts to 12 volts. Next, a voltage VD is applied to the drain region 114, and the voltage VD applied to the drain region 114 is, for example, about 5 volts, and the source region 112 is grounded. Under this bias condition, a large channel current will be generated, in which the electron system moves from the source region II2 end to the drain region 114 end, and the drain region 114 end is accelerated by a high-channel electric field to generate hot electrons. Its kinetic energy is sufficient to overcome the energy barrier of the tunneling oxide layer, coupled with the high positive bias applied to the gate conductor layer 108 (gate), so that hot electrons are injected into the charge trapping layer 104 from the drain region 114 in. After programming, since the charge trapping layer 104 has a net negative charge, the starting voltage (VT) of the memory cell rises. And these electronics unless they are intentionally wiped 9 paper sizes are applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) I ------------ install ----- --- Order --------- line (please read the precautions on the back before filling this page) 546787 93 59twf 1 .doc / 〇〇8 Λ7 Abstract; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Amendments to the Manufacturing Code No. 1 Revised Date: 2002.10.1 6 V. The invention is clear (called), otherwise it will stay in the charge trapping layer 104 for a long time. FIG. 3 illustrates a method for reading a SONOS flash memory according to a preferred embodiment of the present invention. The read operation of the SONOS flash memory of the present invention is actually based on the gate induced drain leakage (GIDL) current in the drain region 114, and the gate induced drain leakage current is related to the gate induced drain leakage (GIDL) current. The charge storage situation of the charge trapping layer 104 is related. Gate-induced drain leakage often occurs in thin-gate oxide metal oxide semiconductor (MOS) devices, which are currents between the drain region and / or the source region and the substrate. A high longitudinal electric field is generated in the n + doped region below the edge of the electrode in the device, and a hole is formed on the surface of the n + doped region below the gate edge through the electron band tunneling effect. The substrate forms a gate-induced drain leakage. Since the gate-induced drain leakage current in the drain region flows into the substrate, the gate-induced drain leakage current can be measured. Referring to FIG. 3, when the SONOS flash memory of the present invention is read, a bias voltage of V is applied to the drain region 114. . It is, for example, about 3 volts to 5 volts, applying 0 V or a negative bias voltage VJ-3 volts to -5 volts to the gate conductor layer 108 (gate), the source region 112 is floating, P The well area 101 is grounded. When the charge trapping layer 106 adjacent to the drain region 114 is negatively charged (programmed), the electric field between the charge trapping layer 106 and the drain region 114 is relatively large, thus generating a large gate-induced drain leakage current. When the memory cell is not programmed (for example, the charge trapping layer 106 has no electrons or is slightly positively charged), the electric field between the charge trapping layer 106 and the drain region 114 is small, and a small gate-induced drain leakage current is generated. . Therefore, you can draw 10 ------------- install -------- order --------- line by measuring (please read the precautions on the back first) (Fill in this page) This paper size is in accordance with Chinese national standard (CNSM4 standard (210 X 297 gong)) 546787 Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs; ^ Ι ^ r 9359twf 1 .doc / 008: No. 9m7119 It is said that the two books amend the positive date: 2002.10 "6 V. Description of the invention (q) The current induced by the drain leakage current of the gate of the pole region to determine whether the digital information stored in this memory cell is" 1 "or" 0 " ”. FIG. 4 does not depict a method for erasing a SONOS flash memory according to a preferred embodiment of the present invention. Please refer to FIG. 4 for the SONOS flash memory of the present invention. When erasing, a voltage -Veg is applied to the gate conductor layer 108 (gate) of the S0N0S flash memory, and the voltage -Veg to the gate conductor layer 108 (gate) is, for example, about -5 volts. ; A voltage VB is applied to the P-type well region 101 (substrate 100), and the voltage VB applied to the P-type well region 101 (substrate 100) is, for example, about 5 volts; the source region and the drain The source region 112 is grounded. In this way, a large electric field can be established between the gate conductor layer 108 (gate) and the P well 100, and the electrons can be oxidized through the tunnel by using the channel FN-tunneling effect. The layer is pulled out from the charge trapping layer 106 into the channel. According to the embodiment of the present invention, the thickness of the tunneling oxide layer of the SONOS memory cell of the present invention (about 20 angstroms) is larger than that of the conventional ETOX memory cell. The thickness of the tunneling oxide layer (at least 90 angstroms) is thin, so when programming or erasing using the channel hot carrier injection method, electrons can easily pass through the tunneling layer, thereby improving the memory device's Operational efficiency. Moreover, the thickness of the tunneling oxide layer is relatively thin, so that a lower operating voltage can be used for programming or erasing operations. Therefore, the size of the memory cell can be further reduced to achieve the purpose of high accumulation. In addition, the gate induced drain leakage current is related to the thickness of the tunneling oxide layer, that is, the thinner the tunneling oxide layer is, the larger the gate induced drain current is, and the thickness of the tunneling oxide layer is 20 angstroms, for example. Gate-induced drain Pole I ------------ install ---- 丨 --order ------- 丨 -line (please read the precautions on the back before filling this page)
546787 93 59twf 1 .doc/008 Λ7 B7 ^Ί〇 // 補充 爲第91Π7119號說明書修正本 修正臼期：2002.10.1 6 五、發明說明（丨^) 漏電流爲穿隧氧化層厚度爲90埃時之1000倍，因此當穿 ，氯化層厚度爲20埃時，對汲極區施加3.5伏特之偏壓、 對閘極施加3.5伏特之偏壓，就可以使閘極誘導汲極漏電 流達到微安培等級，而可以準確的讀取記憶胞上之資料。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 12 本紙張尺度適用中國國家標準（CNS)A:1規恪（210x 297公餐） I--------------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 言546787 93 59twf 1 .doc / 008 Λ7 B7 ^ Ί〇 // Supplement to the specification No. 91Π7119 Amend this revision period: 2002.10.1 6 V. Description of the invention (丨 ^) The leakage current is the thickness of the tunneling oxide layer is 90 angstroms 1000 times the time, so when the thickness of the chloride layer is 20 angstroms, a bias voltage of 3.5 volts is applied to the drain region and a bias voltage of 3.5 volts is applied to the gate electrode. Micro amp level, and can accurately read the data on the memory cell. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 12 This paper size applies Chinese National Standard (CNS) A: 1 (210x 297 meals) I --------------- (Please read the precautions on the back before filling this page ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs