TW544984B

TW544984B - Manufacturing method for semiconductor device

Info

Publication number: TW544984B
Application number: TW091112060A
Authority: TW
Inventors: Junji Tanimura; Yoshihisa Tashiro; Shinji Abe; Nobuyuki Kasai; Harumi Nishiguchi
Original assignee: Mitsubishi Electric Corp
Priority date: 2001-06-12
Filing date: 2002-06-05
Publication date: 2003-08-01
Also published as: KR100496783B1; KR20020094931A; JP3741062B2; JP2003069155A

Abstract

A manufacturing method for a semiconductor device is provided, which includes the steps of: forming a first semiconductor layer 2 on a semiconductor substrate 1, forming a quantum well layer 180 on the first semiconductor layer 2, forming a second semiconductor layer 6 with thickness less than 500 nm on the quantum well layer 180, forming a SiO film 7 on the second semiconductor layer 6, performing an ion implant to implant Si ions from the upper side of the SiO film 7 wherein the value of Si peak concentration at the region of at least from the second semiconductor layer 6 to the quantum well layer 180 is controlled not to be over 1x10<19> cm<-3>, and performing an annealing so as to disorder part or all of the quantum well layer 180 in the thickness direction. According to this method, even a semiconductor device having arbitrary layer structure and wherein the thickness of the upper clad layer is less than 500 nm, the generation of crystal defects can be suppressed and the disorder of the quantum well layer is possible.

Description

544984 五、發明說明（1) [背景技術] 本發明係關於半導體裝置的製法，特別是關於將多重量子井層（MQW: Multi Quantum Well)無序化的方法。而此處的無序化係指利用光激發光（p h 〇 t ο 1 u m i n e s c e n c e)波長誘發30nm以上的藍色移位（blue-shift)的狀態。第8圖，係揭示於例如美國專利4，5 9 4，6 0 3號說明書中，表示習知半導體裝置的製法中的MQW層構造之無序化方法的圖，係藉由離子注入與退火來進行無序化者。如第 8圖（a)所示，係在p型GaAs基板13上，層積並形成p型GaAs 緩衝層14，p型AluGauAs下覆篕層15，無摻雜（AlAsl6/ GaAs 1 7 )的MQW層1 8，η型A1Q WauAs上覆蓋層1 9，以及η型 GaAs空隙層20，以一般的光微影技術（photolithography) 將SiN遮罩21構造圖案化後，將Si離子以375keV，1 〇14cnr2 (cnr2 : atoms/cm2)的摻入量進行離子注入。在去除光阻劑後，以6 7 5 °C的溫度進行4小時的退火，形成如第8圖（c )所示之MQW層無序化區域1 〇。此外，第8圖（b)為第8圖（a) 中’A所表示的部分的放大說明圖，Lz表示（^^層17的厚度，LB則表示A1 As層1 6的厚度。此外，第8圖（d)為第8圖 (c)中，B所表示的部分的放大說明圖。此外，第9圖為揭示於日本特開平6 — 5 3 6 〇 4號公報中的 MQW層構造的另一無序化方法的圖，係顯示藉由退火進行無序化的方法。如第9圖（a)所示，係在11型（^^基板上声積形成η型GaAs緩衝層22，r^Gafl 5lnfl 5p緩衝層23，下覆蓋層24，無摻雜（A1。a “以/光閉阻層544984 V. Description of the invention (1) [Background technology] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for disordering a multiple quantum well (MQW: Multi Quantum Well). The disorder here refers to a state in which a blue-shift of 30 nm or more is induced by using a wavelength of photoexcitation light (p h ο 1 u m i n c e c c n c e). FIG. 8 is a view showing, for example, a method for disordering the structure of an MQW layer in a conventional method for manufacturing a semiconductor device, which is disclosed in the specification of US Patent No. 4,594,603. It is performed by ion implantation and annealing. To the chaotic. As shown in FIG. 8 (a), the p-type GaAs substrate 13 is laminated and formed with a p-type GaAs buffer layer 14. The p-type AluGauAs is covered with a hafnium layer 15 and is undoped (AlAsl6 / GaAs 1 7). The MQW layer 18, the n-type A1Q WauAs overlying layer 19, and the n-type GaAs void layer 20 are patterned with a SiN mask 21 structure using a general photolithography technique, and the Si ions are patterned at 375 keV, 1 〇14cnr2 (cnr2: atoms / cm2) was implanted in an amount of ion implantation. After removing the photoresist, annealing was performed at a temperature of 675 ° C for 4 hours to form a disordered region 10 of the MQW layer as shown in FIG. 8 (c). In addition, FIG. 8 (b) is an enlarged explanatory diagram of a portion indicated by 'A in FIG. 8 (a), Lz represents (^^ layer 17 thickness, and LB represents A1 As layer 16 thickness. In addition, Fig. 8 (d) is an enlarged explanatory view of a portion indicated by B in Fig. 8 (c). In addition, Fig. 9 is an MQW layer structure disclosed in Japanese Patent Application Laid-Open No. 6-5 3 6 04 The diagram of another disordering method is shown in FIG. 9 (a). As shown in FIG. 9 (a), an n-type GaAs buffer layer 22 is formed by an acoustic product on a 11-type substrate. R ^ Gafl 5lnfl 5p buffer layer 23, lower cover layer 24, undoped (A1.

544984 五、發明説明（2) 25，無摻雜GauInuP的活性層26，無摻雜（AlQ5GaQ5)Q5ln 〇·5Ρ光閉阻層27 ’ P型八1〇.5111().5?上覆蓋層28，p型GaQ 5In〇 5P 緩衝層29 ’以及P型GaAs接觸層30，並利用光微影技術將光阻劑遮罩圖案化。之後，如第9圖（b)所示，以光阻劑8 做為遮罩以蚀刻p-GaAs接觸層30。接著如第9圖（c)所示，利用E N蒸鍍形成S1層3 1，並在以剝落法去除光阻劑8與光阻劑上的Si層31之後，如第9圖（d)所示，形成8丨〇2層32，再以8 5 0 t：的溫度將Si層31予以熱擴散，以形成無序化區域10。此時，即調整退火時間，使。層31的邊緣與以紅接觸層3 0的邊緣之間的距離形成大於1 # m的狀態，且光閉阻層25與光閉阻層27的表面形成低於表面} # m的狀態，並使 Si擴散距離變為l//m。藉此，由於可在Si擴散無法抵達 GaAs接觸層30與Gao.sIrio.sP緩衝層29的接合面的狀況下形成無序化區域10，因此可減少因GaAs接觸層30與Gamine.5卩緩衝層29的接合面上的晶袼不重合而產生的轉移。但是在美國專利4，5 9 4，6 0 3號說明書中所揭示的習知方法上’由於係將上覆蓋層19的厚度設定在5 0 0nm至2// m ’並以375keV的高能量進行Si注入，而使注入Si濃度分佈變為廣闊，而不易分析所注入的Si。但是在低於5 00nm 的薄層上覆蓋層的情況下，雖以低於1 5 0 k e V的低能量進行注入，但卻會因S i濃度分佈過於急峻之故，析出所注入之 S i而產生結晶上的缺陷。如此因析出s丨原子而產生之結晶缺陷會吸收光並產生熱，因此假設使用在半導體裝置的導波路或窗形構造時，會有降低半導體雷射裝置的可靠性，544984 V. Description of the invention (2) 25, undoped GauInuP active layer 26, undoped (AlQ5GaQ5) Q5ln 〇 · 5 light blocking layer 27 'P type eight 10.0.5111 (). 5? Overlay layer 28, a p-type GaQ 5In0P buffer layer 29 ′ and a p-type GaAs contact layer 30, and a photoresist mask is patterned using a photolithography technique. Thereafter, as shown in FIG. 9 (b), the photoresist 8 is used as a mask to etch the p-GaAs contact layer 30. Next, as shown in FIG. 9 (c), the S1 layer 31 is formed by EN evaporation, and the photoresist 8 and the Si layer 31 on the photoresist are removed by a peeling method, as shown in FIG. 9 (d). It is shown that the SiO 2 layer 32 is formed, and then the Si layer 31 is thermally diffused at a temperature of 850 t: to form the disordered region 10. At this time, the annealing time is adjusted so that. The distance between the edge of the layer 31 and the edge of the red contact layer 30 forms a state greater than 1 # m, and the surfaces of the light blocking layer 25 and the light blocking layer 27 form a state lower than the surface} # m, and The Si diffusion distance is made 1 // m. As a result, the disordered region 10 can be formed under the condition that the Si diffusion cannot reach the joint surface between the GaAs contact layer 30 and the Gao.sIrio.sP buffer layer 29, so the buffer caused by the GaAs contact layer 30 and Gamine.5 卩 can be reduced. The transfer of crystal ridges on the bonding surface of the layer 29 does not overlap. However, in the conventional method disclosed in the specification of U.S. Patent No. 4,5,9,4,603, 'because the thickness of the upper cover layer 19 is set to 500 nm to 2 // m' and a high energy of 375 keV The Si implantation is performed to make the implanted Si concentration distribution broad, and it is difficult to analyze the implanted Si. However, in the case of a thin cover layer below 500 nm, although the implantation is performed at a low energy of less than 150 ke V, the implanted Si is precipitated because the concentration distribution of Si is too severe. Defects in the crystal are generated. In this way, the crystal defects caused by the precipitation of s 丨 atoms absorb light and generate heat. Therefore, if it is used in the waveguide or window structure of a semiconductor device, the reliability of the semiconductor laser device will be reduced.

313715.ptd 第13頁 544984 五、發明說明（3) 並減低使用壽命的問題。前述習知方法由於未考慮到前述結晶缺陷，因此具有無法獲得高品質半導體裝置的問題。此外，在日本特開平6 - 5 3 6 04號公報所揭示的習知方法，係用以控制在GaAs接觸層30與Gao.5Ino.5P緩衝層29的接合面上所產生的轉移，因此具有無法適用於任何層構造的問題。本發明，係為解決上述問題而創作發明者，其目的在提供一種半導體裝置的製法，即使是在具有任意的層構造，且上覆蓋層的厚度低於500//m的情況下，也不會發生因S i析出而產生的結晶缺陷或殘存有S i，並且能夠實現量子井層的無序化。 [發明之概要] 本發明之半導體裝置的製法，係包含有：在半導體基板上設置單層或複數層的第1半導體層的步驟；在該第1半導體層上設置量子井層的步驟；在該量子井層上設置合計膜厚小於50 0 nm的單層或是複數層的第2半導體層的步驟；在該第2半導體層上設置SiO膜或是Si ON膜的步驟；以使至少由前述第2半導體層到前述量子井層為止的區域中的Si 峰值濃度值小於lx 1019cnr3的方式，進行由前述SiO膜或是 SiON膜上注入Si離子的步驟；以及在進行離子注入步驟之後進行熱退火，而將位於膜厚方向的前述量子井層的部分或是全部無序化的步驟。本發明的半導體裝置的製法，係在前述製法中，將量子井層中至少一部份的Si濃度值設定為大於lx 1018cnr3。313715.ptd Page 13 544984 V. Description of the invention (3) The problem of reducing the service life. The aforementioned conventional method has a problem that a high-quality semiconductor device cannot be obtained because the aforementioned crystal defects are not taken into consideration. In addition, the conventional method disclosed in Japanese Patent Application Laid-Open No. 6-5 3 6 04 is used to control the migration generated on the joint surface of the GaAs contact layer 30 and the Gao.5Ino.5P buffer layer 29, and therefore has Cannot be applied to any layer structure. The present invention was created by the inventor to solve the above-mentioned problems, and an object thereof is to provide a method for manufacturing a semiconductor device, even if the layer has an arbitrary layer structure and the thickness of the upper cover layer is less than 500 // m Crystal defects or S i remain due to the precipitation of S i, and the quantum well layer can be disordered. [Summary of the Invention] The method for manufacturing a semiconductor device according to the present invention includes a step of providing a single semiconductor layer or a plurality of first semiconductor layers on a semiconductor substrate; a step of providing a quantum well layer on the first semiconductor layer; A step of providing a single semiconductor layer or a plurality of second semiconductor layers with a total film thickness of less than 50 nm on the quantum well layer; a step of providing a SiO film or a Si ON film on the second semiconductor layer; Performing the step of implanting Si ions from the SiO film or the SiON film in a manner that the peak Si concentration in the region from the second semiconductor layer to the quantum well layer is less than lx 1019cnr3; and performing heat after the ion implantation step Annealing, and a step of disordering part or all of the quantum well layer located in the film thickness direction. In the method for manufacturing a semiconductor device of the present invention, in the aforementioned manufacturing method, the Si concentration value of at least a part of the quantum well layer is set to be greater than lx 1018cnr3.

313715.ptd 第14頁 544984 五、發明說明（4) 本發明的半導體裝置的製法，係在前述製法中，於進行熱退火時，將SiO膜或是SiON膜的膜厚設定為大於 1 0 0 nm 〇本發明的半導體裝置的製法，係在前述製法中，以 800 °C以上的溫度進行熱退火。本發明的半導體裝置的製法，係在前述製法中，進行 30分鐘以上的熱退火。本發明的半導體裝置的製法，係在前述製法中，以 800 °C以上的溫度進行30分鐘以上的熱退火。本發明之半導體裝置的製法，係包含有：在半導體基板上設置單層或複數層的第1半導體層的步驟；在該第1半導體層上設置量子井層的步驟；在該量子井層上設置合計膜厚小於5 0 0nro的單層或是複數層的第2半導體層的步驟；在該第2半導體層上設置SiO膜或是SiON膜的步驟；在前述 SiO膜或是Si ON膜上進行Si離子注入的步驟；在進行Si離子注入步驟之後進行熱退火，而將位於膜厚方向的前述量子井層的部分或是全部無序化的步驟；以及注入Si離子注入後將Si濃度值大於lx 1019cnr3的區域在熱退火後去除的步驟。本發明的半導體裝置的製法，係在前述製法中，於第 2半導體層與SiO膜或是Si ON膜之間，設置第3半導體層，並使注入Si離子後Si濃度值大於lx 1019cnr3的區域形成在前述第3半導體層内。本發明的半導體裝置的製法，係在前述製法中，將量313715.ptd Page 14 544984 V. Description of the invention (4) In the method for manufacturing a semiconductor device of the present invention, in the aforementioned manufacturing method, the film thickness of the SiO film or the SiON film is set to be greater than 1 0 0 during thermal annealing. nm 〇 The method for manufacturing a semiconductor device according to the present invention is a method in which thermal annealing is performed at a temperature of 800 ° C. or higher in the aforementioned method. The method for manufacturing a semiconductor device according to the present invention is performed in the above-mentioned manufacturing method, and thermal annealing is performed for 30 minutes or more. In the method for manufacturing a semiconductor device of the present invention, in the aforementioned method, thermal annealing is performed at a temperature of 800 ° C or higher for 30 minutes or more. The method for manufacturing a semiconductor device according to the present invention includes the steps of: providing a single semiconductor layer or a plurality of first semiconductor layers on a semiconductor substrate; the step of providing a quantum well layer on the first semiconductor layer; and on the quantum well layer. A step of providing a single semiconductor layer or a plurality of second semiconductor layers with a total film thickness of less than 500 nro; a step of providing a SiO film or a SiON film on the second semiconductor layer; and a step of providing the SiO film or the Si ON film A step of performing Si ion implantation; a step of performing thermal annealing after performing the Si ion implantation step, and disordering a part or all of the aforementioned quantum well layer located in the film thickness direction; and a Si concentration value after the implantation of Si ion The step of removing the area larger than lx 1019cnr3 after thermal annealing. In the method for manufacturing a semiconductor device of the present invention, in the aforementioned manufacturing method, a third semiconductor layer is provided between the second semiconductor layer and the SiO film or the Si ON film, and a region where the Si concentration value after implanting Si ions is greater than lx 1019cnr3 It is formed in the third semiconductor layer. The method for manufacturing a semiconductor device according to the present invention is based on the aforementioned manufacturing method.

313715.ptd 第15頁 544984 五、發明說明（5) 子井層的至少一部份中的Si濃度值設定為大於1χ l〇18cm_3 的值。 [實施形態] 第1實施以下利用圖面說明本發明的第1實施形態。弟1圖為用以說明本發明第1實施形態之2重量子井 (DQW : Double Quantum Well)層構造的無序化方法的圖。首先’如第1圖（a)所示，在η型GaAs基板1(半導體基板）上形成厚度為3# m的n-AlQ5Ga()5As下覆蓋層2(第1半導體層），再於該下覆蓋層2的上面，形成由：厚度為1〇11111的 AluGauAs波導層3;厚度為10nm的AluGauAs井層4;厚度為10nm的AlG.3GaQ.7As阻擋層5 ;厚度為10nm的AluGauAs 井層4 ;以及厚度為1 〇nm的AlQ 3GaQ.7As波導層3所形成的DQW 層180，接著，又在DQW層180上，利用MOCVD (Metal Organic Chemical Vapor Deposition:有機金屬化學氣相蒸鍍）法形成厚度為5〇11111的041().56&().^3上覆蓋層6(第2半導體層）。其次，如第1圖（b)所示，藉由錢射（sputter)法全面形成厚度為45 nm的SiO膜7，並塗布光阻劑8，再使用一般的光微影技術進行光阻劑的圖案化。接著，在4 0 k e V、0 · 7 x 1 〇14cm-2的條件下注入Si離子9。該情況下的注入深度與。濃度係表示於第2圖。第2圖的橫軸（注入深度）表示與上覆蓋層6表面之距離，以虛線及箭號標示的DQW層位置為 DQW層的中央位置，即阻擋層5的中央位置，相當於距離上313715.ptd Page 15 544984 V. Description of the invention (5) The Si concentration value in at least a part of the sub-well layer is set to a value greater than 1 × 1018 cm_3. [Embodiment] First Embodiment The first embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a diagram for explaining a method of disordering a double-quantum well (DQW: Double Quantum Well) layer structure according to the first embodiment of the present invention. First, as shown in FIG. 1 (a), an n-AlQ5Ga () 5As undercoat layer 2 (first semiconductor layer) having a thickness of 3 # m is formed on an n-type GaAs substrate 1 (semiconductor substrate). Above the lower cover layer 2, an AluGauAs waveguide layer 3 having a thickness of 1011111; an AluGauAs well layer 4 having a thickness of 10 nm; an AlG.3GaQ.7As barrier layer 5 having a thickness of 10 nm; an AluGauAs well layer having a thickness of 10 nm 4; and the DQW layer 180 formed by the AlQ 3GaQ.7As waveguide layer 3 with a thickness of 10 nm, and then, on the DQW layer 180, a MOCVD (Metal Organic Chemical Vapor Deposition) method is used. A cover layer 6 (second semiconductor layer) having a thickness of 041 (). 56 & (). ^ 3 having a thickness of 5011111 is formed. Secondly, as shown in FIG. 1 (b), a SiO film 7 having a thickness of 45 nm is fully formed by a sputter method, and a photoresist 8 is coated. Then, a general photolithography technique is used to perform the photoresist. Patterned. Next, Si ions 9 were implanted under the conditions of 40 k e V and 0.7 × 10 14 cm-2. The implant depth in this case is equal to. The concentration is shown in FIG. 2. The horizontal axis (injection depth) in Figure 2 represents the distance from the surface of the upper cover layer 6. The position of the DQW layer indicated by the dashed line and the arrow is the center position of the DQW layer, that is, the center position of the barrier layer 5, which is equivalent to the distance above.

313715.ptd 第16頁 544984 五、發明說明（6) 覆蓋層6表面0.075//m的位置。接著，如第1圖（c )所示，在除去光阻劑8之後，以8 0 0 °C的溫度，進行3 0分鐘的熱退火，以形成無序化區域1 0。最後再利用氟酸蝕除SiO膜7。如上述方式獲得的半導體裝置，如第2圖所示，至少在上覆蓋層6表面到DQW層為止的區域内的Si峰值濃度值係低於 lx 1019cm_3(ciir3: atoms/cm3)，且 DQW層位置的Si 濃度值顯示高於lx 1018cnr3，因此DQW層構造被無序化，且具有不會產生由S i原子的析出所導致的結晶缺陷的效果。第2 圖中，離子注入條件為40keV、0.7x 1 014cnr2。藉由將本實施形態所形成的DQW層構造的無序化後的透過電子顯微鏡像與藉由習知方法所形成者相較的結果，在習知方法上，在上覆蓋層6中，S i峰值濃度係形成大於1 X 1 019cm_3的值，此外在Si峰值濃度形成大於1 X 1 019cnr3的值的位置上存在有多數呈黑點狀的結晶缺陷，但是在本實施形態中，則可確認DQW構造係經無序化，且上覆蓋層内並未產生結晶缺陷。此外，在本實施形態中，至少在上覆蓋層6表面到DQW 層為止的區域内的Si峰值濃度值係小於lx 1019cm_3，且DQW 層位置的Si濃度值顯示大於lx 1018cnr3，因此Si離子注入條件，並不限於前述注入條件，可配合注入能量適度地控制注入量。表1係相對於40keV的Si離子9的各注入量，距離上覆蓋層6的表面的各深度中的Si濃度的總表。313715.ptd Page 16 544984 V. Description of the invention (6) 0.075 // m position on the surface of the cover layer 6. Next, as shown in FIG. 1 (c), after the photoresist 8 is removed, thermal annealing is performed at a temperature of 800 ° C. for 30 minutes to form a disordered region 10. Finally, the SiO film 7 is etched by using a hydrofluoric acid. In the semiconductor device obtained as described above, as shown in FIG. 2, at least the Si peak concentration value in a region from the surface of the upper cladding layer 6 to the DQW layer is lower than lx 1019 cm_3 (ciir3: atoms / cm3), and the DQW layer Since the Si concentration value at the position is higher than lx 1018cnr3, the structure of the DQW layer is disordered, and there is an effect that crystal defects caused by precipitation of Si atoms do not occur. In Fig. 2, the ion implantation conditions are 40 keV and 0.7 x 1 014cnr2. The result of comparing the disordered transmission electron microscope image of the structure of the DQW layer formed in this embodiment with the one formed by the conventional method. In the conventional method, in the upper cover layer 6, S The peak i concentration is a value greater than 1 X 1 019cm_3, and there are many crystal defects with black spots at the position where the peak Si concentration is greater than 1 X 1 019cnr3. However, in this embodiment, it can be confirmed that The DQW structure was disordered, and no crystal defects occurred in the upper cladding layer. In addition, in this embodiment, the Si peak concentration value at least in the area from the surface of the upper cladding layer 6 to the DQW layer is less than lx 1019cm_3, and the Si concentration value at the position of the DQW layer is greater than lx 1018cnr3, so the Si ion implantation conditions It is not limited to the aforementioned injection conditions, and the injection amount can be appropriately controlled in accordance with the injection energy. Table 1 is a summary table of the Si concentration in each depth from the surface of the upper cladding layer 6 with respect to the implanted amount of Si ions 9 at 40 keV.

313715.ptd 第17頁 544984 五、發明說明⑺ 表1 深度 (At m) 注入量（Xl〇14cnT2) 0.3 0.4 0.5 0.6 0.7 0.8 0.000 3.6X1018cm"3 4.8Xl〇18cm 3 6.0X10lW3 7.2X10lW3 8.4X10I8cm"3 9.6X10l8cm'3 0.010 3.8 X1018cm"3 5.〇Xl〇18cm 3 6.3X1018cnT3 7.5X10l8cm"3 8.8X1018cm"3 1.0X1019cm'3 0.020 3.4 X101 W3 4.6X10l8cm 3 5.7X1018cnT3 6.8X1018cm'3 8.0X10l8cm"3 9.1X10I8cm"3 0.030 2.8X10I8cm-3 3.7X1018cm"3 4.7X1018cm'3 5.6X10l8cm"3 6.5X1018cm'3 7.4X10i8cm3 0.040 2.2 X101 W3 2.9X10lW3 3.6X1018cm·3 4.3X10l8cm'3 5.0X1018cm_3 5.7X1018cm3 0.050 1.6X10lW3 2.1X1018cm"3 2.7X1018cm'3 3.2X1018cm'3 3.7X1018cm"3 4.3X1018cm·3 0.060 1.2X1018cm"3 1.6X10l8cm 3 1.9X10l8cm 3 2.3X10I8cm'3 2,7X1018crrf3 3.1 Xl〇l8cm 3 0.070 8.5X1017cttT3 1.1 Xl〇18cm 3 1.4X1018cm'3 1.7X1018cnT3 2.0X10lW3 2.3X1018cm'3 0.075 7.6X10i7cm'3 1.0X1018cm'3 1.3X1018cm·3 1.5 Xl〇l8cm 3 1.8Xl〇18cm 3 2.〇Xl〇18cm 3 由表1中得知，Si離子9注入量在〇·4至〇.7x 1014cnr2的範圍且深度在内的區域時，不會產生值大於ιχ 1019cm_3的Si濃度區域，而且由於深度為〇〇75//m的DqW位置的Si濃度可達lx 1018cnr3以上，因此注入能量為4〇 keV時，只需—要前述範圍的Si離子9注入量即可獲得相同效此外，表2係在本實施形態中，進行8讣^的Si離子時距離上覆蓋層6表面的各深度中的Si濃度相對於Si離子9的各注入量的總表。313715.ptd Page 17 544984 V. Description of the invention ⑺ Table 1 Depth (At m) Injection volume (Xl〇14cnT2) 0.3 0.4 0.5 0.6 0.7 0.8 0.000 3.6X1018cm " 3 4.8Xl〇18cm 3 6.0X10lW3 7.2X10lW3 8.4X10I8cm " 3 9.6X10l8cm'3 0.010 3.8 X1018cm " 3 5.〇Xl〇18cm 3 6.3X1018cnT3 7.5X10l8cm " 3 8.8X1018cm " 3 1.0X1019cm'3 0.020 3.4 X101 W3 4.6X10188 " 3 5.7X1018cnT3 6.8X1018cm " 3cm 3 0.030 2.8X10I8cm-3 3.7X1018cm " 3 4.7X1018cm'3 5.6X10l8cm " 3 6.5X1018cm'3 7.4X10i8cm3 0.040 2.2 X101 W3 2.9X10lW3 3.6X1018cm · 3 4.3X10l8cm'3 5.0X1018cm_3 5.7X1018cm3 3.50X1010cm3 X1018cm'3 3.2X1018cm'3 3.7X1018cm " 3 4.3X1018cm3 0.060 1.2X1018cm " 3 1.6X10l8cm 3 1.9X10l8cm 3 2.3X10I8cm'3 2,7X1018crrf3 3.1 Xl0l8cm 3 0.070 8.5X1017cttT3 1.1X10.18cm 1.7X1018cnT3 2.0X10lW3 2.3X1018cm'3 0.075 7.6X10i7cm'3 1.0X1018cm'3 1.3X1018cm · 3 1.5 X1018cm 3 1.8X1018cm 3 2.〇X1018cm 3 According to Table 1, the Si ion 9 implantation amount Between 0.4 and 〇.7x 1014cnr2 range and depth, the Si concentration region greater than ιχ 1019cm_3 will not be generated, and the Si concentration at the DqW position with a depth of 〇075 // m can reach lx 1018cnr3 or more, so the implantation When the energy is 40 keV, the same effect can be obtained only by the amount of Si ions 9 implanted in the aforementioned range. In addition, Table 2 shows the distance from the surface of the cover layer 6 when performing 8 讣 Si ions in this embodiment. A summary table of the Si concentration in each depth with respect to each implanted amount of Si ions 9.

313715.ptd 第18頁 544984 表2 五、發明說明（8) 深度注入量(X 10i4cm 2) (# m) 0.1 0.2 1.0 1.2 1.3 0.000 3.2X10l7cm"3 6.4X1017cm 3 3.2X10l8cm-3 3.5XlOl8cm'3 4.2Xl018cm—3 0.010 4.7X10I7cm"3 9.4X1017cm'3 4.7 X1018cm 3 5.2X1018cm'3 6.1 Xl〇l8cm 3 0.020 6.2X10l7cm"3 1.2X1018cm~3 6.2X10i8cnf3 6.8Xl〇I8cm 3 8.1X10l8cm"3 0.030 6.9X1017cm'3 1.4X1018cm 3 6.9X1018cm'3 7.6X1018cm'3 9.0X1018cnT3 0.040 7.6 ΧΙΟ1 W3 1.5Xl〇18cm 3 7.6X1018cm"3 8.3Xl〇18cm 3 9.9X1018cm"3 0.050 7.7X1017cm'3 1.6X10l8cm 3 7·7Χ1018〇ιΓ3 8.5Xl〇18cm 3 1.0 Xl〇19cm 3 0.060 7.8X10l7cm'3 1.6Xl〇l8cm 3 7.8X1018cm'3 8.6X1018cm—3 l.lX1019cm"3 0,070 7‘4X10i7cm-3 1.5X1018cm"3 7.4X1018cm'3 8.1X1018cm"3 9.6Xl〇18cm 3 0.075 7.2X1017cm'3 1.4X1018cnf3 7.2X1018cnf3 7.9Xl〇18cm 3 9.3X1018cm'3 由表2中得知，Si離子9注入量在〇·2至ΐ·2χ 1014cnr2的範圍且深度在0.075//m内的區域時，不會產生值大於ΐχ 1019cm_3的Si濃度區域，而且由於深度為〇〇75//m的DqW位置的Si濃度可達lx H^cnr3以上，因此注入能量為85 keV時’只需-要前述範圍的Si離子9注入量即可獲得相同效此外，在本實施形態中，退火溫度與退火時間係有所關連，在增加退火溫度時，可縮短退火時間。而加長退火時間時，則可降低退火溫度。第2實施形態第3圖為本發明之第2實施形態之dqw層構造的無序化方法說明圖。 .313715.ptd Page 18 544984 Table 2 V. Description of the invention (8) Depth injection (X 10i4cm 2) (# m) 0.1 0.2 1.0 1.2 1.3 0.000 3.2X10l7cm " 3 6.4X1017cm 3 3.2X10l8cm-3 3.5XlOl8cm'3 4.2 Xl018cm—3 0.010 4.7X10I7cm " 3 9.4X1017cm'3 4.7 X1018cm 3 5.2X1018cm'3 6.1 Xl0l8cm 3 0.020 6.2X10l7cm " 3 1.2X1018cm ~ 3 6.2X10i8cnf3 6.8Xl0I8cm 3 8.1X1030.0 cm3 " X1018cm 3 6.9X1018cm'3 7.6X1018cm'3 9.0X1018cnT3 0.040 7.6 ΧΙΟ1 W3 1.5Xl〇18cm 3 7.6X1018cm " 3 8.3Xl〇18cm 3 9.9X1018cm " 3 0.050 7.7X1017cm'3 1.6X10l8cm 3 0.7l3 × 10 × 3 18cm 3 1.0 Xl019cm 3 0.060 7.8X10l7cm'3 1.6X10l8cm 3 7.8X1018cm'3 8.6X1018cm—3 l.lX1019cm " 3 0,070 7'4X10i7cm-3 1.5X1018cm " 3 7.4X1018cm'3 8.1X1018cm " 3 9.6Xl 〇18cm 3 0.075 7.2X1017cm'3 1.4X1018cnf3 7.2X1018cnf3 7.9X1018cm 3 9.3X1018cm'3 It is known from Table 2 that the Si ion 9 implantation amount is in the range of 0.2 to ΐ2χ 1014cnr2 and the depth is 0.075 // In the region of m, no Si concentration greater than ΐχ 1019cm_3 is generated. In addition, since the Si concentration at the DqW position with a depth of 075 // m can reach more than lx H ^ cnr3, when the implantation energy is 85 keV, it is only necessary to obtain the same amount of Si ion 9 in the aforementioned range to obtain the same amount. In addition, in this embodiment, the annealing temperature is related to the annealing time. When the annealing temperature is increased, the annealing time can be shortened. Increasing the annealing time can decrease the annealing temperature. (Second Embodiment) Fig. 3 is an explanatory diagram of a method for disordering a dqw layer structure according to a second embodiment of the present invention. .

313715.ptd 第19頁 544984 五、發明說明（9) 首先，如第3圖（a)所示，在基板丨（半導體美板）上，形成厚度為3//ΙΠ的n-AlQ.5Ga().5As下覆蓋層2(第1& 導體層），再於該下覆蓋層2的上面，形成由： a a 1 r a 丄、爸。 7子 1 馬 1 Onm 的 AluGauAs波 v 層 3;厚度為 i〇nm 的 a1q iGa() 9As井層 4 ; 厚度為 10nm 的 AlQ.3GaQ.7As 阻檔層 5 ;厚度為 1〇ηπ^ A1。iGa。9 As井廣4，以及厚度為1 〇nm的a1q /心jAs波導層3所形成的 DQW層180，接著，又在該1)(^層18〇上，利用M〇CVD法形成厚度為16〇11111的？41()如().^上覆蓋層6(第2半導體層）。接著’如第3圖（b)所示，藉由濺射法全面形成厚度為 45nm的SiO膜7，並塗布光阻劑g，再使用一般的光微影技術進行光阻劑的圖案化。接著，在95keV、〇· 5x 1〇ucm_2的條件下注入S i離子9。該情況下的注入深度與s i濃度如第4 圖所示。第4圖的注入深度表示與上覆蓋層6表面之距離，以虛線及箭號標示的DQW層位置為阻擔層5的中央位置，相當於距離上覆蓋層6表面0.185//m的位置。之後，如第3圖（c )所示，在去除光阻劑8後，以濺射法形成厚度為150nm的追加Si 0膜，並將合計膜厚設定為 195 nm。之後，再進行溫度為800 °C，共30分鐘的熱退火，並如第3圖（d)所示，形成無序化區域10。最後以氟酸蝕除 SiO膜7與追加SiO膜11。另外，第3圖（e)為DQW層180的放大說明圖。如上述方式獲得的半導體裝置，如第4圖所示，至少在上覆蓋層6表面到DQW層為止的區域内的Si峰值濃度值低於lx 1019cm_3，且DQW層位置的Si濃度值亦小於lx 1018313715.ptd Page 19 544984 V. Description of the invention (9) First, as shown in FIG. 3 (a), on the substrate 丨 (semiconductor beauty plate), an n-AlQ.5Ga (three-in-thickness) is formed. ) .5As the lower cover layer 2 (the first & conductor layer), and then on the lower cover layer 2 to form: aa 1 ra 丄, dad. 7 sub 1 Ma 1 Onm AluGauAs wave layer 3; a1q iGa () 9As well layer 4 with a thickness of 10 nm; AlQ.3GaQ.7As barrier layer 5 with a thickness of 10 nm; thickness is 10 η ^ A1. iGa. 9 As well 4 and the DQW layer 180 formed by the a1q / core jAs waveguide layer 3 with a thickness of 10 nm, and then, on the 1) (18 layer), a thickness of 16 was formed by the MOCVD method. 〇11111? 41 () as (). ^ On the cover layer 6 (second semiconductor layer). Then 'as shown in Figure 3 (b), a 45nm-thick SiO film 7 is formed by sputtering, The photoresist g was coated, and then the photoresist was patterned using a general photolithography technique. Then, Si ions 9 were implanted under the conditions of 95 keV and 0.5 × 10 ucm_2. The implantation depth and The si concentration is shown in Figure 4. The injection depth in Figure 4 represents the distance from the surface of the upper cover layer 6, and the position of the DQW layer indicated by the dashed line and the arrow is the center position of the barrier layer 5, which is equivalent to the distance from the upper cover layer. 6 surface at a position of 0.185 // m. After that, as shown in FIG. 3 (c), after removing the photoresist 8, an additional Si 0 film having a thickness of 150 nm is formed by a sputtering method, and the total film thickness is set to 195 nm. Thereafter, thermal annealing was performed at a temperature of 800 ° C for a total of 30 minutes, and as shown in Fig. 3 (d), disordered regions 10 were formed. Finally, SiO was etched by hydrofluoric acid. 7 and additional SiO film 11. In addition, FIG. 3 (e) is an enlarged explanatory view of the DQW layer 180. As shown in FIG. 4, the semiconductor device obtained as described above is at least on the surface of the upper cover layer 6 to the DQW layer. The Si peak concentration value in the region is lower than lx 1019cm_3, and the Si concentration value at the DQW layer position is also less than lx 1018.

313715.ptd 第20頁 544984 五、發明說明（ίο) cm—3。由於Si峰值濃度值小於lx 10i9cm-3，因此具有不會產生由S i原子的析出所導致的結晶缺陷的效果。另一方面，由於DQW層位置的Si濃度值雖小於lx l〇18cm_3，但因追加 S i 0膜1 1之故，不僅增加了空晶格結點的供給，同時也促進了無序化，因此具有可藉由8 00 °C、30分鐘的熱退火讓 DQW層構造無序化的效果。在第4圖中，離子注入條件為 95keV、0. 5X 1014cm-2 〇此外，在本實施形態中，注入S i離子的條件並不限於前述注入條件。表3為距離上覆蓋層6表面的各深度的μ濃度相對於9 5 k e V的S i離子9的各注入量的總表。表3 深度注入量（X l〇l4cm 2) (μ m) 0.1 0.5 L0 1.4 1.5 0.000 2.1X10l7cm'3 l.lX1018cm'3 2.1 X10l8cm 3 2.6X1018cnT3 3.2X1018cm'3 0.020 4.0 Xl〇l7cm 3 2.0X10l8cm'3 4.0 xio1 W3 5.〇Xl〇18cm 3 6.lX10l8cm"3 0.040 6.〇Xl〇ncm 3 3.0X1018cm 3 6.〇Xl〇l8cm 3 7.4X1018cm·3 8.9 Xl〇18cm 3 0.060 6.5X1017crrf3 3.3X10lW3 6.5X10l8cm"3 8.1X10l8cm"3 9.8X1018cm'3 0.080 7.1 xio1 W3 3.5X10l8cm'3 7.1X1018cm'3 8.8Xl〇I8cm 3 l.lX1019cm'3 0.100 6.0X10l7cm 3 3.0X1018cm 3 6.0X1018cm'3 7.4 X101 W3 8.9X10l8cm"3 0.120 5.0X1017cnT3 2.5X1018cm'3 5.0X1018cm"3 6.2 Xl〇18cm 3 7.7X1018cnT3 0.140 3.8X1017cm·3 1.9X1018cm 3 3.8X1018cm 3 4.8 X101 W3 5.8Xl〇18cm"3 0.160 2.7X1017cm"3 1.4X10l8cm'3 2.7X1018cm'3 3.4X1018cm"3 4_lX1018cm 3 0.180 2.0X10ncm"3 9.9X1017crrf3 2.0X10l8cm"3 2.5X10l8cm'3 3.0X10l8cm 3 0.185 1.8X1017cm"3 9.0X1017cm"3 1.8X1018cm'3 2.2X1018cm'3 2.7X1018cm"3313715.ptd Page 20 544984 V. Description of the invention (ίο) cm-3. Since the peak Si concentration value is less than lx 10i9cm-3, there is an effect that crystal defects due to precipitation of Si atoms do not occur. On the other hand, although the Si concentration value at the position of the DQW layer is less than 1 × 1018 cm_3, the addition of the Si 0 film 11 not only increases the supply of empty lattice nodes, but also promotes disorder. Therefore, it has the effect of making the structure of the DQW layer disordered by thermal annealing at 800 ° C for 30 minutes. In Fig. 4, the ion implantation conditions are 95 keV and 0.5X 1014 cm-2. In this embodiment, the conditions for implanting Si ions are not limited to the aforementioned implantation conditions. Table 3 is a summary table of the µ concentration at each depth from the surface of the upper cover layer 6 with respect to each implanted amount of Si ions 9 at 5 5 k e V. Table 3 Depth injection volume (X 104 cm 2) (μm) 0.1 0.5 L0 1.4 1.5 0.000 2.1X10l7cm'3 l.lX1018cm'3 2.1 X10l8cm 3 2.6X1018cnT3 3.2X1018cm'3 0.020 4.0 Xl0l7cm 3 2.0X10l8cm'3 4.0 xio1 W3 5.0 × 1018cm 3 6.lX10l8cm " 3 0.040 6.〇Xl0ncm 3 3.0X1018cm 3 6.〇X10l8cm 3 7.4X1018cm3 8.9 Xl〇18cm 3 0.060 6.5X1017crrf3 3.3X10lW3 6.5X1018cm " 3 8.1X10l8cm " 3 9.8X1018cm'3 0.080 7.1 xio1 W3 3.5X10l8cm'3 7.1X1018cm'3 8.8Xl0I8cm 3 l.lX1019cm'3 0.100 6.0X10l7cm 3 3.0X1018cm 3 6.0X1018cm'3 7.4 X101 W3 8.9X10l8cm " 5.0X1017cnT3 2.5X1018cm'3 5.0X1018cm " 3 6.2 Xl018cm 3 7.7X1018cnT3 0.140 3.8X1017cm3 1.9X1018cm 3 3.8X1018cm 3 4.8 X101 W3 5.8Xl〇18cm " 3 0.160 2.7X1017cm " 3 1.431010cm8 3.4X1018cm " 3 4_lX1018cm 3 0.180 2.0X10ncm " 3 9.9X1017crrf3 2.0X10l8cm " 3 2.5X10l8cm'3 3.0X10l8cm 3 0.185 1.8X1017cm " 3 9.0X1017cm " 3 1.8X1018cm'3 2.2X1018cm'3

313715.ptd 第21頁 544984 五、發明說明（11) 圍内Ϊ表ΓΛ知，當Si離子9注入量在i4x i〇i4cm—2的範於lx l〇19cm'3^ •嘈洚π # ^ 卫+會產生值大的農度£域，因此在注入能量為95keV的情子，J：b外#低於前述注入量的Si離子9注入量注入Si_ 子此外右再追加層壓SiO膜u則可獲相同效果。、此外，在前述實施形態中，係在注入離子後，並在埶退火前追加層壓Sicmu，而使Si〇膜的合計膜 …、 195nm ’但是在熱退火時只要膜厚超過合計1〇〇nm，即使量子井層的S!濃度值小於lx 1〇18cm_3亦具有相第3實施开 11 政果以下使用第1圖，說明本實施形態3之DQff層構造的無序化方法。 …、首先，如第1圖（a)所示，在nSGaAs基板丨（半導體基板）上，形成厚度為3/zm的n-AiQ5GaQ5As下覆蓋層2(第導體層），再於該下覆蓋層2的上面，形成由二厚度為1〇nm 的AluGauAs波導層3 ;厚度為l〇nm的AluGauAs井層4 ; 厚度為10nm的AlG.3GaG 7As阻擋層5 ;厚度為l〇nm的AlQ1Ga0.9 As井層4，以及厚度為1〇11111的人1()368().43波導層3所形成的 DQW層180，接著，又在DQW層180上，利用M0CVD法形成厚度為1 60nm的p-AlG5GaQ 5As上覆蓋層6(第2半導體層）。接著’如第1圖（b)所示，藉由濺射法全面形成厚度為 45nm的Si 0膜7，並塗布光阻劑8，再使用一般的光微影技術進行光阻劑的圖案化。接著，在95keV、0· 5x l〇14Cnr2的條件下注入S i離子9。該情況下的注入深度與S i濃度係與313715.ptd Page 21 544984 V. Description of the invention (11) It is known that the amount of Si ion 9 implanted in i4x i〇i4cm-2 is less than lx l〇19cm'3 ^ • 洚洚 π # ^ Wei + will produce a large amount of farmland. Therefore, when implanting energy at 95keV, J: b 外 #Si ions lower than the aforementioned implantation amount. 9 Implantation amount of Si_. In addition, a SiO film is additionally laminated on the right. The same effect can be obtained. In addition, in the foregoing embodiment, after the ion implantation, Sicmu is additionally laminated before the plutonium annealing, so that the total film of the Si film is ... 195 nm ', but in the thermal annealing, as long as the film thickness exceeds a total of 100. nm, even if the S! concentration value of the quantum well layer is less than 1 × 1018 cm_3, it has the third embodiment. The following figure illustrates the method of disordering the structure of the DQff layer in the third embodiment using the first figure. …, First, as shown in FIG. 1 (a), an n-AiQ5GaQ5As lower cover layer 2 (conductor layer) having a thickness of 3 / zm is formed on the nSGaAs substrate 丨 (semiconductor substrate), and then the lower cover layer is formed. 2 above, two AluGauAs waveguide layers 3 with a thickness of 10 nm; AluGauAs well layers 4 with a thickness of 10 nm; AlG.3GaG 7As barrier layers 5 with a thickness of 10 nm; AlQ1Ga0.9 with a thickness of 10 nm As well layer 4 and person 1 () 368 (). 43 with a thickness of 1011111, a DQW layer 180 formed by the waveguide layer 3, and then, on the DQW layer 180, a pCVD layer having a thickness of 1 60 nm is formed by MOCVD. -AlG5GaQ 5As cladding layer 6 (second semiconductor layer). Next, as shown in FIG. 1 (b), a 45 nm-thick Si 0 film 7 is formed by sputtering, and a photoresist 8 is applied, and then the photoresist is patterned using a general photolithography technique. . Next, Si ions 9 were implanted under the conditions of 95 keV and 0.5 x 1014 Cnr2. The implantation depth and Si concentration in this case are the same as

313715.ptd 第 22 頁 544984313715.ptd Page 22 544984

之後，如第！ m ,、度為82(TC，60分:所不’在去除光阻劑8後，進行溫後以氟酸蝕除S i 〇膜7。、、退火以形成無序化區域1 〇。最如上述方式獲得的半導體褒詈在上覆蓋層6表面到DQW 竹如第4圖所示，至少於lx 1〇七一’且=域内之Si峰值濃度值低 cm-3。由於Si峰值ΓΛ二度值亦小於ix 1018 生Si原子析出所道又小；x i〇19cm—3，因此具有不會產置的Si濃度值雖小於lx 1〇18cm_3文果。此外，DQW層位 μ ^ r m ^^ 廿士仁因在本實施形態中，田長時間以強化熱退火之故，而促進無序此具有可使_層構造無序化的效果。丄、，、施形恶中，注入s i離子的條件，並不限於如述條件。當注入條件為951[^的注入能量時，與第2實施形態相同，當Si離子9注入量在丨.4x 1〇14cm_2的範圍内時，在深度達〇.185//m為止的區域内並不會產生值大於i X 1019cnr3的Si濃度區域，因此若以低於前述注入量的8丨離子9注入量注入S i離子，同時提高退火溫度，並加長時間來強化熱退火，即可獲得相同效果。此外，在本實施形態中，雖將退火溫度設定在8 2 〇 °C ’而將退火時間設在6 0分鐘，但若以溫度大於8 〇〇的退火溫度’或是超過3 0分鐘的退火時間等任何條件來強化熱退火，則可獲得與本實施形態相同的效果。第4實施形態After that, as the first! After the photoresist 8 is removed, the temperature is 82 (TC, 60 minutes: after removing the photoresist 8, the Si film 7 is etched with fluoric acid, and the annealing is performed to form a disordered region 10. The semiconductor 获得 obtained in the above manner is on the surface of the upper cladding layer 6 to the DQW bamboo. As shown in FIG. 4, the Si peak concentration value in the domain is at least 1 × 100.7 ′ and cm-3 is lower. Because the Si peak ΓΛ 二The degree value is also smaller than that of ix 1018. Si atom precipitation is small; xi〇19cm-3, so it has a Si concentration value that will not be produced although it is less than lx 1010cm_3. In addition, the DQW horizon μ ^ rm ^^ In this embodiment, Shi Shiren promotes disorder by enhancing the thermal annealing for a long time, which promotes disorder. This has the effect of disordering the layer structure. The conditions are not limited to the conditions described above. When the implantation condition is 951 [^ implantation energy, it is the same as the second embodiment, and when the implantation amount of Si ions 9 is within the range of .4x 1014 cm_2, the depth reaches 0. In the region up to .185 // m, there will not be a Si concentration region with a value greater than i X 1019cnr3. The same effect can be obtained by implanting Si ions at an injection amount of 9 and increasing the annealing temperature and intensifying the thermal annealing for a long time. In addition, in this embodiment, although the annealing temperature is set to 8 2 0 ° C, the annealing is performed. The time is set at 60 minutes, but the same effect as in the present embodiment can be obtained if the thermal annealing is strengthened under any conditions such as an annealing temperature greater than 800 ° or an annealing time exceeding 30 minutes. form

313715.ptd 第 23 頁 544984313715.ptd Page 23 544984

第5圖係本發明第4實施形態的DQW層構造法的說明圖。的無序化方首先、，如第5圖（a)所示，在11型（^^基板丨（半導體基板）上形成厚度為3//m的η-入1().56&().，3下覆蓋層2(第1半1 體層）’再於該下覆蓋層2的上面，形成由：厚度為1〇㈣的 Al〇.3GaG.7As波導層3 ;厚度為1 〇nm的aig /auAs井層4 ;厚度為 1 Onm 的 AlQ.3GaG.7As阻擋層 5 ;厚度為 l〇nm 的 aiq iGa。fAs 井層4 ;以及厚度為i〇nm的波導層3所形成^㈣層180，接著，又在該DQW層180上，利用M0CVD法形成厚度為50nm的p-AlQ.5GaQ.5As上覆蓋層6(第2半導體層）。接著，如第5圖（b)所示，利用M0CVD形成厚度為1〇〇nm 的p-GaAs空隙層12(第3半導體層），並藉由激射法在該 GaAs空隙層12上全面形成厚度為35nm的SiO膜7，並塗布光阻劑8，使用一般的光微影技術進行光阻劑的圖案化。接著，以85keV、2· 2x l〇i4cm-2的條件注入Si離子g。該情況下的注入深度與Si濃度係表示於第6圖中。第6圖的注入深度表示與GaAs空隙層1 2表面之距離，而以虛線及箭號標示的DQW層位置為阻擋層5的中央位置，相當於距離GaAs空隙層12表面〇.175//m的位置。之後，如第5圖（c)所示，在去除光阻劑8之後，進行 8 0 0 °C ，3 0分鐘的熱退火，以形成無序化區域丨〇。最後再以氟酸蝕除SiO膜7後，利用酒石酸、過氧化氫去除GaAs空隙層1 2。此外，第5圖U)為DqW層18〇的放大說明圖。如第6圖所示’在本實施形態中，GaAs空隙層12内的Fig. 5 is an explanatory diagram of a DQW layer structure method according to a fourth embodiment of the present invention. First, as shown in Fig. 5 (a), a η-in 1 () of a thickness of 3 // m is formed on a 11-type (^^ substrate 丨 (semiconductor substrate)). 56 & () ., 3 lower cladding layer 2 (first half 1 bulk layer) 'on top of this lower cladding layer 2 is formed of: Al0.3 GaG.7As waveguide layer 3 with a thickness of 10 ㈣; a thickness of 10 nm aig / auAs well layer 4; AlQ.3GaG.7As barrier layer 5 with a thickness of 1 Onm; aiq iGa.fAs well layer 4 with a thickness of 10 nm; and a waveguide layer 3 with a thickness of 10 nm 180. Next, on the DQW layer 180, a p-AlQ.5GaQ.5As cover layer 6 (second semiconductor layer) having a thickness of 50 nm is formed by the MOCVD method. Next, as shown in FIG. 5 (b), A 100-nm-thick p-GaAs void layer 12 (third semiconductor layer) was formed by MOCVD, and a 35 nm-thick SiO film 7 was formed on the GaAs void layer 12 by lasing, and a photoresist was applied. Agent 8 is used to pattern the photoresist using a general photolithography technique. Next, Si ions g are implanted under the conditions of 85 keV and 2.2 x 10 cm 4 cm-2. The implantation depth and Si concentration in this case are shown in Figure 6. Injection of Figure 6 The degree represents the distance from the surface of the GaAs void layer 12, and the position of the DQW layer indicated by the dashed line and the arrow is the center position of the barrier layer 5, which corresponds to a position of 0.175 // m from the surface of the GaAs void layer 12. After that, As shown in FIG. 5 (c), after removing the photoresist 8, a thermal annealing at 800 ° C for 30 minutes is performed to form a disordered region. Finally, the SiO film is etched with a fluoric acid. After 7, tartaric acid and hydrogen peroxide were used to remove the GaAs interstitial layer 12. In addition, FIG. 5 U) is an enlarged explanatory diagram of the DqW layer 18O. As shown in FIG. 6 ', in this embodiment, the

313715.ptd 第24頁 544984 五、發明說明（14)313715.ptd Page 24 544984 V. Description of the invention (14)

Si峰值濃度值雖大於1χ 1〇 i9cm-3，但是至少上覆蓋層6表面到DQW層為止的區域内的以峰值濃度值小於ΐχ 1 〇19cnr3，且 DQW層位置的Si濃度值達到ix i〇i8cm_3以上。由於Si濃度值大於1 X 1019cnr3的值的GaAs空隙層12會在最後的步驟中被去除，因此具有不會在上覆蓋層6中殘存結晶缺陷的效果。此外，由於DQW層位置的Si濃度值大於lx l〇18cm_3，因此具有可使DQW層構造無序化的效果。在第6圖中，離子注入條件為 85keV，2· 2x 1 〇14cnr2。另外，本實施形態之注入S i離子的條件並不限於前述條件。表4為距離GaAs空隙層12表面的各深度中的Si濃度相對於85keV的Si離子9的各注入量的總表。表 4 深度 (jLtm) 注入量(X l〇14cm 2) 0.7 0.8 LO 2.0 2.2 2.3 0.000 2.2X1018cm"3 2.6X10lW3 3.2Xl〇i8cm 3 6.4X1018cnT3 7.1X1018cm'3 7.4X1018cm"3 0.020 4.3X1018cm"3 5.0 Xl〇18cm 3 6.2X1018cm'3 1.2X1019cm'3 1.4 Xl〇l9cm 3 1.4X10l9cm"3 0.040 5.3 Xl〇18cm 3 6.1X1018cm"3 7.6Xl〇18cm 3 1.5Xl〇19cm 3 1.7X1019cm"3 L7X1019cm"3 0.060 5.5Xl〇l8cm 3 6.2X10 丨 8cm·3 7.8X1018cm'3 1.6X1019cm"3 1.7 Xl〇19cm 3 1.8X1019cm"3 0.080 4.9 X10l W3 5.6Xl〇l8cm 3 7.0X1018cm-3 1.4X1019cm"3 1.5 Xl〇l9cm 3 1.6Xl〇l9cm 3 0.100 3.2X10l8cm~3 3.6X1018cm"3 4.5 Xl〇18cm 3 9.0X1018cm'3 9.9 Xl〇18cm 3 l.〇Xl〇l9cm 3 0.120 2.8X1018cm'3 3.2X10i8cm"3 4.0X1018cm'3 8.0X1018cm 3 8.8X10lW3 9.2xi〇l8cm'3 0.140 2.1 X1018cm 3 2.4X1018cm"3 3.0X1018cm'3 6.0X1018cnT3 6.6 Xl〇l8cm 3 6.9X10l8cm"3 0.160 1.3X10l8cm 3 1.5X10l8cm*3 1.9X10l8cm 3 3.8X1018cm"3 4.2X10I8cm_J 4.4X10l8cm 3 0.170 1.2Xl〇l8cm 3 1.3X10l8cm 3 1.6X10l8cm 3 3.3X1018cm'3 3.6Xl〇I8cm 3 3.8X10l8cm'3 0.175 9.9X1017cm 3 1.1X10%T3 1.4X1018cm 3 2.8X1018crrT3 3.1X1018cm'3 3.2X10l8cm'3Although the peak Si concentration value is greater than 1x10i9cm-3, the peak concentration value in at least the area from the surface of the upper cover layer 6 to the DQW layer is less than ΐχ1 〇19cnr3, and the Si concentration value at the position of the DQW layer reaches ixi〇. i8cm_3 or more. Since the GaAs void layer 12 having a Si concentration value greater than a value of 1 × 1019cnr3 is removed in the last step, it has an effect that no crystal defects remain in the upper cladding layer 6. In addition, since the Si concentration value at the position of the DQW layer is larger than 1 × 1018 cm_3, it has the effect of disordering the structure of the DQW layer. In Fig. 6, the ion implantation conditions were 85 keV, 2 · 2x 1 014cnr2. The conditions for implanting Si ions in this embodiment are not limited to the aforementioned conditions. Table 4 is a summary table of the Si concentration in each depth from the surface of the GaAs void layer 12 with respect to each implanted amount of Si ions 9 of 85 keV. Table 4 Depth (jLtm) Injection amount (X l〇14cm 2) 0.7 0.8 LO 2.0 2.2 2.3 0.000 2.2X1018cm " 3 2.6X10lW3 3.2Xl〇i8cm 3 6.4X1018cnT3 7.1X1018cm'3 7.4X1018cm " 3 0.020 4.3X1018cm " 3 5.0 Xl 〇18cm 3 6.2X1018cm'3 1.2X1019cm'3 1.4 X1010cm 3 1.4X1019cm " 3 0.040 5.3 X10〇18cm 3 6.1X1018cm " 3 7.6X1018cm 3 1.5X1019cm 3 1.7X1019cm " 3 L7X1019cm " 3 0.060 5.5X 〇l8cm 3 6.2X10 丨 8cm · 3 7.8X1018cm'3 1.6X1019cm " 3 1.7 Xl〇19cm 3 1.8X1019cm " 3 0.080 4.9 X10l W3 5.6Xl〇l8cm 3 7.0X1018cm-3 1.4X1019cm " 3 1.5 X10l9cm 3 1.6Xl 〇l9cm 3 0.100 3.2X10l8cm ~ 3 3.6X1018cm " 3 4.5 Xl〇18cm 3 9.0X1018cm'3 9.9 Xl〇18cm 3 l.〇Xl〇l9cm 3 0.120 2.8X1018cm'3 3.2X10i8cm " 3 4.0X1018cm'3 8.0X1018cm 3 8.8 X10lW3 9.2xi〇l8cm'3 0.140 2.1 X1018cm 3 2.4X1018cm " 3 3.0X1018cm'3 6.0X1018cnT3 6.6 Xl〇l8cm 3 6.9X10l8cm " 3 0.160 1.3X10l8cm 3 1.5X10l8cm * 3 1.9X10l8cm 3 3.8X10cm3 " 10X1018cm " 0.170 1.2X10l8cm 3 1.3X10l8cm 3 1.6X10l8cm 3 3.3X 1018cm'3 3.6X10I8cm 3 3.8X10l8cm'3 0.175 9.9X1017cm 3 1.1X10% T3 1.4X1018cm 3 2.8X1018crrT3 3.1X1018cm'3 3.2X1018cm'3

313715.ptd 第25頁 544984 五、發明説明（15) 由表4知知’當Si離子9注入里在〇·8至2·2χ l〇14cnr2的範圍時，在深度達〇至m為止的GaAs空隙層12會產生值大於lx 1〇19cm_3的^濃度區域，而在深度達0.100至 0.175//Π1為止的區域則不會產生值大於lx 1 〇19cm-3的si濃度區域，且深度為0.175//m的DQW位置的Si濃度，達到ιχ 1 018cnr3以上的程度，因此在注入能量為85keV的情況下，可以前述範圍的Si離子9注入量注入Si離子，並在最後的步驟中將Si濃度值大於1 X 1 〇19ciir3的GaAs空隙層1 2去除，如此便可獲相同的效果。第5實施形態使用第1圖說明本實施形態5的D Q W層構造之無序化方法。首先，如第1圖（a)所示，在η型GaAs基板1(半導體基板）上，形成厚度為3//m的n-AluGauAs下覆蓋（ciad)層2 (第1半導體層），再於該下覆蓋層2的上面，形成由：^度為1〇11111的人1().3680.7人3波導層3;厚度為1〇11111的人1()1〇&()9人3井層4，厚度為ΙΟηιη的Al〇.3Ga〇7As阻擒層5，厚度為lOnuj的A1 uGauAs井層4 ;以及厚度為10nm的AluGauAs波導層3所形成的DQW層180，接著，又在DQW層180上，利用m〇CVDs 形成厚度為50ηιη的0-人1〇.56&().5人3上覆蓋層6(第2半導體層）。接著，如第1圖（b)所示，藉由濺射法全面形成厚度為 135 nm的SiO膜7，並塗布光阻劑8，再使用一般的光微術進行光阻劑的圖案化。接著，在85keV、2· 2x 1 〇ucm-2的313715.ptd Page 25 544984 V. Description of the invention (15) From Table 4, we know that when the Si ion 9 implantation is in the range of 0.8 to 2.2 x 1014cnr2, GaAs at a depth of 0 to m The void layer 12 will generate a ^ concentration region with a value greater than lx 1〇19cm_3, while a region with a depth of 0.100 to 0.175 // Π1 will not generate a si concentration region with a value greater than lx 1 〇19cm-3 and a depth of 0.175 The Si concentration at the // m DQW position is above ιχ 1 018cnr3, so when the implantation energy is 85keV, Si ions can be implanted with the Si ion 9 implantation amount in the aforementioned range, and the Si concentration is added in the final step. The GaAs void layer 1 2 having a value greater than 1 X 1 019ciir3 is removed, so that the same effect can be obtained. Fifth Embodiment A method for disordering a D Q W layer structure according to the fifth embodiment will be described with reference to FIG. 1. First, as shown in Fig. 1 (a), a layer 2 (first semiconductor layer) of n-AluGauAs is formed on the n-type GaAs substrate 1 (semiconductor substrate) to a thickness of 3 / m (first semiconductor layer). On the lower cover layer 2, a person 1 () with a degree of 1011111 (3), a waveguide layer 3 of 36.80.7 people, and a person 1 () with a thickness of 1011111 and 9 people 3 are formed. Well layer 4, AlO3Ga07As trap layer 5 with a thickness of 10 ηη, A1 uGauAs well layer 4 with a thickness of 10 Nuj; and a DQW layer 180 formed by the AluGauAs waveguide layer 3 with a thickness of 10 nm. On the layer 180, 0-person 10.56 & (5. 5) with a thickness of 50 ηm is used to form a cover layer 6 (second semiconductor layer) on the person 3. Next, as shown in FIG. 1 (b), a 135 nm-thick SiO film 7 is formed on the entire surface by a sputtering method, a photoresist 8 is applied, and then the photoresist is patterned using general photomicroscopy. Next, at 85keV, 2 · 2x 1 〇ucm-2

544984 五、發明說明（16) 條件下注入S i離子9。該情況下的注入深度與S i濃度係表示於第7圖中。第7圖的橫軸（注入深度）表示與上覆蓋層6 表面之距離，而以虛線及箭號標示的DQW層位置為阻擋層5 的中央位置’相當於距離上覆蓋層6表面0.075//m的位置。另外，雖未標示於第7圖中，但是在深度達〇至〇.135 //m為止的SiO膜7上，會產生值大於ΐχ i〇i9cffl-3的以濃度區域。在第7圖中，離子注入條件為85keV，2· 2x l〇"cm-2。之後，如第1圖（c)所示，在去除光阻劑8之後，進行 800 °C ，30分鐘的熱退火，以形成無序化區域1〇。最後再以氟酸蝕除SiO膜7。依上述方式獲得的半導體裝置，雖會在深度達〇至 0.135 //m為止的SiO膜7產生值大於ΐχ i〇i9cm-3的^濃度區域’但因該SiO膜7係在致後步驟中餘除，因此如第7圖^ 示’在上覆蓋層6内的Si峰值濃度值會小於ΐχ ΐυ9。^-3，且 DQW層位置的Si濃度值顯示大於1χ i〇i8cm_3，藉此dqw声構造被無序化，且具有不會產生析出Si原子的結晶缺陷胃的效果。此外，在本實施形態中，注入Si離子的條件並不限於前述注入條件。表5為距離上覆蓋層6表面的各深度的sut 度相對於85keV的Si離子9的各注入量的總表。又艮544984 V. Description of the invention (16) The Si ions 9 are implanted. The implantation depth and Si concentration in this case are shown in Fig. 7. The horizontal axis (injection depth) of FIG. 7 indicates the distance from the surface of the upper cover layer 6, and the position of the DQW layer indicated by the dashed line and the arrow is the center position of the barrier layer 5 'equivalent to 0.075 from the surface of the upper cover layer 6 // m's location. In addition, although not shown in FIG. 7, on the SiO film 7 having a depth of 0 to 0.135 // m, a concentration region having a value greater than ΐχioi9cffl-3 is generated. In Fig. 7, the ion implantation conditions are 85 keV, 2.2 x 10 " cm-2. After that, as shown in FIG. 1 (c), after removing the photoresist 8, thermal annealing was performed at 800 ° C. for 30 minutes to form a disordered region 10. Finally, the SiO film 7 is again etched with hydrofluoric acid. The semiconductor device obtained in the above manner, although the SiO film 7 having a depth of 0 to 0.135 // m will produce a ^ concentration region 'with a value greater than ΐχ i0i9cm-3, but the SiO film 7 is in the subsequent step. The remainder is divided, so as shown in Fig. 7 ', the peak Si concentration in the upper cladding layer 6 will be less than ΐχ ΐυ9. ^ -3, and the Si concentration value at the position of the DQW layer is shown to be greater than 1 × i0i8cm_3, whereby the dqw acoustic structure is disordered and has the effect of not producing a crystal-deficient stomach in which Si atoms are precipitated. In this embodiment, the conditions for implanting Si ions are not limited to the aforementioned implantation conditions. Table 5 is a summary table of the sut degree of each depth from the surface of the upper cover layer 6 with respect to each implanted amount of Si ions 9 of 85 keV. Again

313715.ptd 第27頁 544984 五、發明說明（17) 深度注入量(Xl〇14cnT2) (M m) 0.7 0.8 1.0 2.0 2.2 2.3 0.000 3.2 X1018cm 3 3.6X10l8cm 3 4.5 Xl〇l8cm 3 9.0X1018cm 3 9.9X1018cm'3 l.〇Xl〇19cm'J 0.010 3.0X10l8cm*3 3.4X10l8cm 3 4.3X10l8cm"3 8.5Xl〇i8cnT3 9.4Xl〇18cm 3 9.8X1018cm"3 0.020 2.8X1018cm'3 3.2X10l8cm'3 4.〇Xl〇l8cm 3 8.0X1018cm'3 8.8 Xl〇l8cm 3 9.2X1018cm3 0.030 2.5X1018cm"3 2.8X1018cm'3 3.5 Xl〇I8cm 3 7.0X1018cnT3 7.7X1018cm"3 8.1X1018cm'3 0.040 2.1 Xl〇18cm 3 2.4X10I8cm 3 3.0X10l8cm~3 6.0 Xl〇l8cm 3 6.6Xl〇18cm 3 6.9X10l8cm'3 0.050 1.7X1018cm'3 2·0Χ1018ατΓ3 2.5X1018cm'3 4.9 Xl〇18cm 3 「5.4X1018cm-3 5.7X10l8cm'3 0.060 1.3 Xl〇l8cm 3 1.5X1018cm~3 1.9X1018cm"3 3.8X1018cm'3 4.2 Xl〇18cm 3 4’.4Xl〇i8cm 3 0.070 1.2X10l8cm'3 1.3X1018cm"3 1.6Xl〇l8cm 3 3.3X10I8cm'3 3.6X1018cm'3 3.8X1018cm"j 0.075 9.9Xl〇17cm'3 LlX1018cm"3 1.4X10l8cm 3 2.8X10I8cm'3 3.1 Xl〇18cm 3 3.2Χ10%Γ3 由表5中得知，當Si離子9注入量在0.8至2.2x 1014cnr2 的範園内時，在深度達0.075//m為止的區域内並不會產生值大於lx 1019cnr3的Si濃度區域，此外深度為〇.〇75/zm的 DQW層位置的Si濃度大於lx 1 019cnr3，因此在注入能量為 85keV的情況/F，只需有前述範圍的Si離子9注入量便可獲得相同效果。另外’在前述各實施形態中，雖表示了 DQW層構造的無序化方法，但是相同的無序化方法對於與習知相同的 MQW層構造者依然有效。此外’在前述各實施形態中，雖表示下覆蓋層（第1半導體層）2，以及上覆蓋層（第2半導體層）6為單層，但以複數層構成亦無妨。313715.ptd Page 27 544984 V. Description of the invention (17) Depth injection amount (Xl014cnT2) (M m) 0.7 0.8 1.0 2.0 2.2 2.3 0.000 3.2 X1018cm 3 3.6X1018cm 3 4.5 X1018cm 3 9.0X1018cm 3 9.9X1018cm ' 3 l.〇Xl019cm'J 0.010 3.0X10l8cm * 3 3.4X10l8cm 3 4.3X10l8cm " 3 8.5Xl〇i8cnT3 9.4Xl〇18cm 3 9.8X1018cm " 3 0.020 2.8X1018cm'3 3.2X10l8cm'3 4.〇Xl0l8cm 3cm 8.0X1018cm'3 8.8 X1010cm3 9.2X1018cm3 0.030 2.5X1018cm " 3 2.8X1018cm'3 3.5 Xl〇I8cm 3 7.0X1018cnT3 7.7X1018cm " 3 8.1X1018cm'3 0.040 2.1 XlO18cm 3 2.4X10I8cm 3 3.0X10l8 ~ 〇l8cm 3 6.6X1018cm 3 6.9X10l8cm'3 0.050 1.7X1018cm'3 2.0 × 1018ατΓ3 2.5X1018cm'3 4.9 Xl018cm 3 「5.4X1018cm-3 5.7X10l8cm'3 0.060 1.3 Xl0cm8cm 3 1.5X1018cm ~ 3 1.9X1018 &; 3 3.8X1018cm'3 4.2 Xl018cm 3 4'.4Xl0i8cm 3 0.070 1.2X10l8cm'3 1.3X1018cm " 3 1.6Xl10l8cm 3 3.3X10I8cm'3 3.6X1018cm'3 3.8X1018cm " j 0.075 9.9Xl017cm ' 3 LlX1018cm " 3 1.4X10l8cm 3 2.8X10I8cm'3 3.1 Xl018cm 3 3.2 × 10% Γ3 From Table 5, when Si When the injection amount of the sub-9 is within the range of 0.8 to 2.2x 1014cnr2, the Si concentration region with a value greater than lx 1019cnr3 will not be generated in the area up to 0.075 // m, and the DQW with a depth of 0.075 / zm The Si concentration at the layer position is greater than lx 1 019cnr3, so in the case of an implantation energy of 85 keV / F, the same effect can be obtained as long as the implantation amount of Si ions 9 in the foregoing range is obtained. In addition, in each of the foregoing embodiments, the method of disordering the structure of the DQW layer is shown, but the same method of disordering is still effective for the same MQW layer constructor as the conventional one. In addition, in the foregoing embodiments, although the lower cladding layer (first semiconductor layer) 2 and the upper cladding layer (second semiconductor layer) 6 are single layers, a plurality of layers may be used.

313715.ptd 第28頁 544984 五、發明說明（18) 此外，在前述各實施形態中，雖表示在下覆蓋層（第2 半導體層）6上，形成SiO膜7，但亦可以SiON膜取代SiO膜 Ί 〇此外，在前述各實施形態中，係將DQW層的中央位置的Si濃度設定為大於lx 1018cnr3，使DQW層構造無序化，但亦可將膜厚方向中的DQW層的全部，或是DQW層其他位置中的Si濃度設定為大於lx 1018cnr3，使膜厚方向中的DQW層的全部，或其中一部份形成無序化。如上所述，由於本發明之半導體裝置的製法係進行以下步驟：在半導體基板上設置單層或複數層的第1半導體層的步驟；在該第1半導體層上設置量子井層的步驟；在該量子井層上設置合計膜厚小於50 0 nm的單層或是複數層的第2半導體層的步驟；在該第2半導體層上設置SiO膜或是SiON膜的步驟；以使至少由前述第2半導體層到前述量子井層為止的區域中的Si峰值濃度值小於lx 1019cnr3的方式，進行由前述SiO膜或是Si ON膜上注入Si離子的步驟；以及在進行離子注入步驟之後進行熱退火，而將位於膜厚方向的前述量子井層的部分或是全部加以無序化的步驟，因此可抑制因S i原子析出而產生的結晶缺陷。此外，若將本發明的半導體裝置應用在半導體雷射裝置的導波路或窗形構造上，由於幾乎不會產生吸收光的結晶缺陷，因此可提昇雷射裝置的可靠性，並提高使用壽命。本發明的半導體裝置的製法，係在前述製法中，將量子井層的至少一部份的Si濃度值設定為大於lx 1 018cm_3，313715.ptd Page 28 544984 V. Description of the invention (18) In the foregoing embodiments, although the SiO film 7 is formed on the lower cladding layer (second semiconductor layer) 6, a SiON film may be used instead of the SiO film. 〇〇 In addition, in each of the foregoing embodiments, the Si concentration in the central position of the DQW layer is set to be greater than lx 1018cnr3, so that the structure of the DQW layer is disordered, but the entire DQW layer in the film thickness direction may also be used, or The Si concentration in the other positions of the DQW layer is set to be greater than lx 1018cnr3, so that all or a part of the DQW layer in the film thickness direction is disordered. As described above, the method for manufacturing a semiconductor device according to the present invention includes the following steps: a step of providing a single or a plurality of first semiconductor layers on a semiconductor substrate; a step of providing a quantum well layer on the first semiconductor layer; A step of providing a single semiconductor layer or a plurality of second semiconductor layers with a total film thickness of less than 50 nm on the quantum well layer; a step of providing a SiO film or a SiON film on the second semiconductor layer; Performing the step of implanting Si ions from the SiO film or the Si ON film in a manner that the peak Si concentration in the region from the second semiconductor layer to the quantum well layer is less than lx 1019cnr3; and performing heat after the ion implantation step Annealing, and a step of disordering part or all of the quantum well layer located in the film thickness direction, can suppress crystal defects caused by precipitation of Si atoms. In addition, if the semiconductor device of the present invention is applied to a waveguide or a window structure of a semiconductor laser device, since crystal defects that absorb light are hardly generated, the reliability of the laser device can be improved and the service life can be improved. In the method for manufacturing a semiconductor device of the present invention, in the aforementioned manufacturing method, the Si concentration value of at least a part of the quantum well layer is set to be greater than lx 1 018 cm_3,

313715.ptd 第29頁 544984 五、發明說明（19) 以使量子井層構造無序化。本發明的半導體裝置的製法，係在前述製法中，將進行熱退火時的SiO膜或是Si ON膜的膜厚設定為超過100 run，以使量子井層構造無序化。本發明的半導體裝置的製法，係在前述製法中，因以 8 0 (TC的溫度進行熱退火，故可使量子井層構造無序化。本發明的半導體裝置的製法，係在前述製法中，因進行30分鐘以上的熱退火處理，故可使量子井層構造無序化。本發明的半導體裝置的製法，係在前述製法中，因以 8 0 0 °C以上的溫度進行3 0分鐘以上的熱退火，故可使量子井層構1造無序化。由於在本發明的半導體裝置的製法中，進行以下步驟：在半導體基板上設置單層或複數層的第1半導體層的步驟；在該第1半導體層上設置量子井層的步驟；在該量子井層上設置合計膜厚小於50 Onm的單層或是複數層的第2 半導體層的步驟；在該第2半導體層上設置SiO膜或是Si ON 膜的步驟；由前述SiO膜或是Si ON膜上注入Si離子的步驟；在進行S i離子注入後，進行熱退火，而將位於膜厚方向的前述量子井層的部分或是全部無序化的步驟；以及將注入Si離子後Si濃度值大於lx 1019cnr3的區域於熱退火處理後去除的步驟，因此可抑制因S i原子析出而產生的結晶缺陷。此外，若將本發明的半導體裝置應用在半導體雷射裝置的導波路或窗形構造上，由於幾乎不會產生吸收光的313715.ptd page 29 544984 V. Description of the invention (19) To make the structure of the quantum well layer disorder. In the method for manufacturing a semiconductor device according to the present invention, in the aforementioned manufacturing method, the film thickness of the SiO film or the Si ON film during thermal annealing is set to more than 100 run, so that the structure of the quantum well layer is disordered. The manufacturing method of the semiconductor device of the present invention is based on the aforementioned manufacturing method. Since the thermal annealing is performed at a temperature of 80 ° C., the structure of the quantum well layer can be disordered. The manufacturing method of the semiconductor device of the present invention is based on the aforementioned manufacturing method. Because the thermal annealing treatment is performed for more than 30 minutes, the structure of the quantum well layer can be disordered. The method for manufacturing the semiconductor device of the present invention is based on the aforementioned method, because it is performed at a temperature of 800 ° C or higher for 30 minutes. The above thermal annealing can make the quantum well layer structure 1 disordered. In the method for manufacturing a semiconductor device of the present invention, the following steps are performed: a step of providing a single or multiple first semiconductor layers on a semiconductor substrate A step of providing a quantum well layer on the first semiconductor layer; a step of providing a single semiconductor layer or a plurality of second semiconductor layers with a total film thickness of less than 50 Onm on the quantum well layer; on the second semiconductor layer A step of setting a SiO film or a Si ON film; a step of implanting Si ions on the aforementioned SiO film or Si ON film; and after performing Si ion implantation, thermal annealing is performed to place the quantum well layer in the film thickness direction of A step of separating or completely disordering; and a step of removing a region having a Si concentration value greater than lx 1019cnr3 after the Si ions are implanted after the thermal annealing treatment, thereby suppressing crystal defects due to precipitation of Si atoms. In addition, if When the semiconductor device of the present invention is applied to a waveguide or a window structure of a semiconductor laser device, light-absorbing

313715.ptd 第30頁 544984 五、發明說明（20) 結晶缺陷，因此可提昇雷射裝置的可靠性，並提高其使用壽命。本發明的半導體裝置的製法，係在前述製法中，於第 2半導體層與SiO膜或Si ON膜之間，設置第3半導體層，並使注入Si離子後Si濃度值大於1 X 1 019cnr3的區域形成於前述第3半導體層内，故可在熱退火後輕易地將Si濃度值大於1 X 1 019cnr3的區域予以去除，並控制因Si原子析出而產生的結晶缺陷。本發明的半導體裝置的製法，係在前述製法中，因將量子井層的至少一部份的Si濃度值設定在lx 1 018cnr3以上，故可使量子井層構造無序化。313715.ptd Page 30 544984 V. Description of the invention (20) Crystal defects, which can improve the reliability of the laser device and increase its service life. In the method for manufacturing a semiconductor device of the present invention, in the foregoing manufacturing method, a third semiconductor layer is provided between the second semiconductor layer and the SiO film or the Si ON film, and the Si concentration value after implanting Si ions is greater than 1 X 1 019cnr3. Since the region is formed in the third semiconductor layer, the region having a Si concentration value greater than 1 × 1 019cnr3 can be easily removed after thermal annealing, and the crystal defects caused by the precipitation of Si atoms can be controlled. In the method for manufacturing a semiconductor device of the present invention, in the aforementioned manufacturing method, since the Si concentration value of at least a part of the quantum well layer is set to 1x 1 018cnr3 or more, the structure of the quantum well layer can be disordered.

313715.ptd 第31頁 544984 圖式簡單說明 [圖面之簡單說明] 第 1圖（a)至（d)為本發明第1 實施形態，第3實施形態以及第 5實施形態之DQW層構造的無序化方法的說明圖；第 2圖為第1實施形態的S i離子注入深度與S i濃度的關係圖第 3圖（a)至（e)為本發明第2 實施形態之D Q W層構造的無序化方法說明圖；第 4圖為第2實施形態以及第 3實施形態的S i離子注入深度與 S i濃度的關係圖；第 5圖（a)至（d)為本發明第4 實施形態之DQW層構造的無序化方法說明圖；第 6圖為第4實施形態的Si離子注入深度與S i濃度的關係圖第 7圖為第5實施形態的S i離子注入深度與S i濃度的關係圖第 8圖（a)至（d)為習知的無序化方法的說明圖；第 9圖（a)至（d)為習知的另- -無序化方法的說明圖。 [元件符號說明] 1 η型GaAs基板 2 第1半導體層 3 波導層 4 井層 5 阻擋層 6 第2半導體層 7、 ‘ 1 1 SiO膜 8 光阻劑 9 Si離子 10 無序化區域 12 20 空隙層 13 p型GaAs基板313715.ptd Page 31 544984 Brief description of drawings [Simplified description of drawings] Figures 1 (a) to (d) show the structure of the DQW layer of the first embodiment, the third embodiment, and the fifth embodiment of the present invention. An illustration of the disordering method; Fig. 2 is a graph showing the relationship between the Si ion implantation depth and the Si concentration in the first embodiment; Figs. 3 (a) to (e) are the structure of the DQW layer in the second embodiment of the present invention; FIG. 4 is an explanatory diagram of a disordering method; FIG. 4 is a graph showing the relationship between the Si ion implantation depth and the Si concentration in the second embodiment and the third embodiment; and FIGS. 5 (a) to (d) are the fourth embodiment of the present invention. An explanatory diagram of a method for disordering a DQW layer structure according to an embodiment; FIG. 6 is a graph showing a relationship between a Si ion implantation depth and a Si concentration in a fourth embodiment; FIG. 7 is a Si ion implantation depth and a S in a fifth embodiment; Relationship diagram of i concentration Figures 8 (a) to (d) are explanatory diagrams of the conventional disordering method; Figures 9 (a) to (d) are conventional alternatives--the explanation of the disordering method Illustration. [Description of Element Symbols] 1 η-type GaAs substrate 2 First semiconductor layer 3 Waveguide layer 4 Well layer 5 Barrier layer 6 Second semiconductor layer 7 '1 1 SiO film 8 Photoresist 9 Si ion 10 Disordered region 12 20 Void layer 13 p-type GaAs substrate

313715.ptd 第32頁 544984313715.ptd Page 32 544984

313715.ptd 圖式簡單說明 14、22、23、29 緩衝層 15 ' 24 下覆蓋層 16 A 1 As 層 17 Ga As 層 18 MQW層 19 ' 28 上覆蓋層 21 SiN遮罩 25 ^ 27 光閉阻層 26 活性層 30 接觸層 31 Si層 32 SiO』 180 量子井層第33頁313715.ptd Schematic description 14, 22, 23, 29 Buffer layer 15 '24 Under cover layer 16 A 1 As layer 17 Ga As layer 18 MQW layer 19' 28 Overlay layer 21 SiN mask 25 ^ 27 Optical blocking Layer 26 Active layer 30 Contact layer 31 Si layer 32 SiO '180 Quantum well layer 第 33 页

Claims

544984 六、申請專利範圍 1. 一種半導體裝置的製法，其係包含有：在半導體基板上設置單層或複數層的第1半導體層的步驟；在該第1 半導體層上設置量子井層的步驟；在該量子井層上設置合計膜厚小於500nm的單層或是複數層的第2半導體層的步驟；在該第2半導體層上設置SiO膜或是Si ON膜的步驟；以使至少由前述第2半導體層到前述量子井層為止的區域中的Si峰值濃度值小於lx 1019cnr3的方式，進行由前述SiO膜或是SiON膜上注入Si離子的步驟；以及在進行離子注入步驟之後，進行熱退火，而將位於膜厚方向的前述量子井層的部分或是全部無序化的步驟。 2. 如申請專利範圍第1項之半導體裝置的製法，其中，係將量子井層的至少一部份的Si濃度值設定為大於lx 1 018cm-3 〇 3. 如申請專利範圍第1項之半導體裝置的製法，其中，係將熱退火時的SiO膜或是Si ON膜的膜厚設定為大於 10 0 nm 〇 4. 如申請專利範圍第1項之半導體裝置的製法，其中，係以8 0 0 °C以上的溫度進行熱退火。 5. 如申請專利範圍第1項之半導體裝置的製法，其中，係進行30分鐘以上的熱退火。 6. 如申請專利範圍第1項之半導體裝置的製法，其中，係以8 0 0 °C以上的溫度進行3 0分鐘以上的熱退火。 7. 一種半導體裝置的製法，其係包含有：在半導體基板544984 VI. Application for Patent Scope 1. A method for manufacturing a semiconductor device, comprising: a step of providing a single or multiple first semiconductor layers on a semiconductor substrate; and a step of providing a quantum well layer on the first semiconductor layer A step of providing a single semiconductor layer or a plurality of second semiconductor layers with a total film thickness of less than 500 nm on the quantum well layer; a step of providing a SiO film or a Si ON film on the second semiconductor layer; Performing the step of implanting Si ions from the SiO film or the SiON film in a manner that the peak Si concentration value in the region from the second semiconductor layer to the quantum well layer is less than lx 1019cnr3; and after performing the ion implantation step, A step of thermally annealing and disordering part or all of the quantum well layer located in the film thickness direction. 2. The method for manufacturing a semiconductor device according to item 1 of the scope of patent application, wherein the Si concentration value of at least a part of the quantum well layer is set to be greater than lx 1 018cm-3 〇3. A method for manufacturing a semiconductor device, wherein the thickness of the SiO film or the Si ON film during thermal annealing is set to be greater than 100 nm. For example, the method for manufacturing a semiconductor device according to item 1 of the patent application range is 8 Thermal annealing at temperatures above 0 0 ° C. 5. The method for manufacturing a semiconductor device according to item 1 of the patent application, wherein the thermal annealing is performed for more than 30 minutes. 6. The method for manufacturing a semiconductor device according to item 1 of the patent application, wherein the thermal annealing is performed at a temperature of 800 ° C or more for 30 minutes or more. 7. A method for manufacturing a semiconductor device, comprising: a semiconductor substrate

313715.ptd 第34頁 544984 六、申請專利範圍上設置單層或複數層的第1半導體層的步驟；在該第1 半導體層上設置量子井層的步驟；在該量子井層上設置合計膜厚小於50 0 nm的單層或是複數層的第2半導體層的步驟；在該第2半導體層上設置SiO膜或是Si ON膜的步驟；由前述SiO膜或是Si ON膜上注入Si離子的步驟；在進行S i離子注入後，進行熱退火，而將位於膜厚方向的前述量子井層的部分或是全部無序化的步驟；以及將注入Si離子後Si濃度值大於lx 1019cnr3的區域於熱退火處理後去除的步驟。 8.如申請專利範圍第7項之半導體裝置的製法，其中，係在第2半導體層與SiO膜或Si ON膜之間，設置第3半導體層，並使注入Si離子後Si濃度值大於lx 1019cnr3的區域形成於前述第3半導體層内。 9 ·如申請專利範圍第7項之半導體裝置的製法，其中，係將量子井層的至少一部份的Si濃度值設定為大於lx 1 0 18cm-3 〇313715.ptd Page 34 544984 VI. The step of setting a single or multiple first semiconductor layer on the scope of the patent application; the step of setting a quantum well layer on the first semiconductor layer; the total film on the quantum well layer A step of a single semiconductor layer or a plurality of second semiconductor layers having a thickness of less than 50 nm; a step of providing a SiO film or a Si ON film on the second semiconductor layer; and injecting Si from the aforementioned SiO film or Si ON film A step of ionizing; a step of performing thermal annealing after Si ion implantation and disordering part or all of the aforementioned quantum well layer located in the film thickness direction; and a Si concentration value after implantation of Si ions greater than lx 1019cnr3 The area is removed after the thermal annealing process. 8. The method for manufacturing a semiconductor device according to item 7 of the scope of patent application, wherein a third semiconductor layer is provided between the second semiconductor layer and the SiO film or the Si ON film, and the Si concentration value after implanting Si ions is greater than lx A region of 1019cnr3 is formed in the third semiconductor layer. 9. The method for manufacturing a semiconductor device according to item 7 of the scope of patent application, wherein the Si concentration value of at least a part of the quantum well layer is set to be greater than lx 1 0 18 cm-3.

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