TW544736B - Calculation method for RC parameters in IC design and implement thereof - Google Patents

Abstract

A calculation method for RC parameters in IC design and implement thereof are disclosed, and particularly to a calculation method for RC parameters and implement thereof in logical synthesis and physical synthesis of IC design flow. The calculation method for RC parameters comprises: providing a gate netlist; comparing a circuit-unit physical synthesis delay time of a physical synthesis delay time of the gate netlist with a circuit-unit reference delay time of a reference delay time, in order to make the circuit-unit physical synthesis delay time equal to the circuit-unit reference delay time for obtaining custom capacitance by adjusting capacitance; comparing a inter-connect physical synthesis delay time of the physical synthesis delay time with a inter-connect reference delay time of the reference delay time, in order to make the inter-connect physical synthesis delay time equal to the inter-connect reference delay time for obtaining custom resistance by utilizing the custom capacitance and adjusting resistance. By utilizing the present invention, the accurate resistance and capacitance in IC design can be provided to designer, and meanwhile the design performance is enhanced and the expendable time is decreased.

Description

544736 經濟部智迮財產局員工消費合作社印製 A7 B7 五、發明説明（） 發明領域： 本發明係有關於一種積體電路設計中電阻電容（RC)參 數的計算方法及其應用，特別是有關於在積體電路設計流 程的邏輯合成（Logical Synthesis)和實體合成（physical Synthesis)中，一種RC參數的計算方法及其應用，藉以使 得減少合成過程所耗費的時間及增加RC參數的計算準確 度。 發明背景： 隨著半導體製程技術之發展，使得線幅尺寸進人次微 米（Sub-Micro)甚至深次微米（Deep Sub-Micro)的領域。元件 在有限的空間内不斷堆疊的結果，造成在半導體元件進入 深次微米的領域時，為了使積體電路的運作效率提高和元 件彳占用面積的考量，元件的尺寸需大幅縮小，所以各種半 導體設計和製程所要求的精準度就愈來愈高。 由於積體電路設計的複雜度越來越高，設計者為了有 效率地的開發晶片，所以漸漸地從邏輯層（L 〇 g i c L e v e 1)移 到暫存器傳輸階層（Register Transfer Layer; RTL)來設計。 在由上往下的積體電路設計流程中，暫存器傳輸階層設計 是一種廣泛使用的積體電路設計描述方法，利用暫存器傳 輸階層碼（RTL Code)來描述積體電路設計。 請參考第1圖，其所繪示為習知邏輯合成之流程圖。 在習知積體電路和晶片的設計流程中，首先利用積體電路 設計的電路單元庫導線負載模型（Library Wire Load 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ----Γ ·-......费.........訂......... (請先閲讀背面之注意事項再填寫本頁) 544736 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁)544736 Printed by A7 B7 in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Field of the invention: The present invention relates to a method for calculating resistance and capacitance (RC) parameters in integrated circuit design and its application. Regarding the logical synthesis and physical synthesis of the integrated circuit design flow, a method of calculating RC parameters and its application, so as to reduce the time consumed by the synthesis process and increase the calculation accuracy of the RC parameters . Background of the Invention: With the development of semiconductor process technology, the size of line widths has entered the field of sub-micro and even deep sub-micro. As a result of the continuous stacking of components in a limited space, when semiconductor devices enter the field of deep sub-microns, in order to improve the operating efficiency of integrated circuits and the consideration of the area occupied by components, the size of components must be significantly reduced, so The accuracy required for design and manufacturing processes is increasing. Due to the increasing complexity of integrated circuit design, in order to efficiently develop the chip, the designer gradually moved from the logic layer (L 0gic Leve 1) to the register transfer layer (RTL). ) To design. In the integrated circuit design flow from top to bottom, the register transfer hierarchy design is a widely used method for describing integrated circuit designs. It uses register transfer hierarchy codes (RTL Code) to describe integrated circuit designs. Please refer to Figure 1, which shows a flowchart of conventional logic synthesis. In the process of designing integrated circuits and wafers, first use the circuit wire library circuit load model of the integrated circuit design (Library Wire Load). This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) --- -Γ · -...... Fee ......... Order ... (Please read the notes on the back before filling out this page) 544736 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page)

Model) 1 2，對此積體電路的已設計完成之rtl碼1 0進行 邏輯合成步驟14，以獲得未定位閘階層網列（Gate Net li s t)，其中電路單元庫導線負載模型主要是用以估算積 體電路設計的電容值’因為隨著積體電路設計中導線的連 接點（Fanout)增多，對應的電容值亦相應增加，所以邏輯合 成可藉由電路單元庫導線負載模型來粗略地估算電容值， 進而估算出電阻值。 接著對此未定位閘階層網列進行定位及繞線 (Placement and Routing)步驟1 6，得到已定位已繞線閘階層 網列（Placed and Routed Gate Netlist)，然後進行估算步驟 1 8，估算此已定位已繞線閘階層網列的電阻值2 0、電容值 22和因電阻電容而引起的延遲時間值（rc Delay Time)24 等資訊，及可獲得此積體電路設計之個別化導線負載模型 (Custom Wire Load Model)26。若電阻值 20、電容值 22 和 經濟部智慧財產局員工消費合作社印製 延遲時間值24等資訊，與預期有所偏差而未能達至積體電 路設計的要求時，則需利用此個別化導線負載模型2 6，對 已設計完成之RTL碼10再一次進行邏輯合成步驟14，直 至獲得符合要求的電阻值20、電容值22和延遲時間值24 等資訊。而為了得到更精確的估算結果，每個積體電路設 計都有其專屬的電路單元庫導線負載模型12，且此電路單 元庫導線負載模型1 2可由客戶提供，或由工程師推算，以 供邏輯合成之用。 請參考第2圖，其所繪示為習知利用電路單元庫導線 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 經濟部智迖財產局員工消費合作社印製 A7 B7 發明說明（） 負载模型對RTL碼進行邏輯合成後，對應導線路徑（Path) 之電容值估算的錯誤比率之曲線圖。如第2圖中之曲線100 所示’於積體電路設計中，只有約3 %的導線路徑其電容值 估算的錯誤比率為〇 %，而約5 %的導線路徑其電容值估算 的錯誤比率為-丨〇%，即表示約5%的導線路徑其估算的電容 值係比實際的電容值少約1 0%，另外約2%的導線路徑其電 容值估算的錯誤比率為1 〇%，即表示約2%的導線路徑其估 算的電容值係比實際的電容值多約1 〇%，曲線1 〇〇上的其 他標點所表示之意思亦如上所述。 請參考第3圖，其所繪示為習知利用個別化導線負載 模型對RTL碼進行邏輯合成後，對應導線路徑之電容值估 算的錯誤比率之曲線圖。如第3圖中之曲線1 〇 2所示，於 積體電路設計中，當邏輯合成後所估算的電阻電容值和延 遲時間值未符合要求時，可利用邏輯合成後所得的個別化 導線負載模型，對已完成之RTL碼再一次進行邏輯合成， 以獲得符合要求的電阻電容值和延遲時間值等電路資訊。 如第3圖中之曲線1 〇 2所示，於積體電路設計中，約5 %的 導線路徑其電容值估算的錯誤比率為〇%，而約4%的導線 路徑其電容值估算的錯誤比率為-丨0%，即表示約4%的導線 路徑其估算的電容值係比實際的電容值少約1 〇%，另外約 5%的導線路徑其電容值估算的錯誤比率為丨〇%，即表示約 5 %的導線路徑其估算的電容值係比實際的電容值多約 1 0% ’曲線丨02上的其他標點所表示之意思亦如上所述。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ...............、可......... (請先閲讀背面之注意事項再填寫本頁) A7Model) 1 2. Perform the logic synthesis step 14 of the designed rtl code 1 0 of this integrated circuit to obtain the unlocated gate-level network column (Gate Net List), in which the circuit cell library wire load model is mainly used To estimate the capacitance value of the integrated circuit design 'Because with the increase of the connection points (Fanout) of the wires in the integrated circuit design, the corresponding capacitance value also increases accordingly, the logic synthesis can be roughly calculated by the circuit unit library wire load model Estimate the capacitance value, and then the resistance value. Next, the positioning and routing of the non-positioned gate hierarchy network step 16 is performed to obtain the positioned and routed gate netlist, and then the estimation step 18 is performed to estimate this. Information such as resistance value 20, capacitance value 22, and rc Delay Time 24 due to resistance capacitance have been located in the layered grid of the wound gate, and individualized wire loads for which this integrated circuit design can be obtained Model (Custom Wire Load Model) 26. If the resistance value 20, capacitance value 22, and the delay time value 24 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs are different from the expected ones and fail to meet the requirements of the integrated circuit design, this individualization should be used. For the wire load model 26, the logic synthesis step 14 is performed again on the designed RTL code 10 until the required resistance value 20, capacitance value 22 and delay time value 24 are obtained. In order to obtain more accurate estimation results, each integrated circuit design has its own circuit cell library wire load model 12, and the circuit cell library wire load model 12 can be provided by the customer or calculated by the engineer for logic Synthetic use. Please refer to Figure 2, which shows the conventional use of circuit unit library wires. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). 544736 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. A7 B7 Invention Explanation () The load model is used to logically synthesize the RTL code, and the graph of the error ratio corresponding to the capacitance value of the conductor path is estimated. As shown by curve 100 in Figure 2 'In integrated circuit design, only about 3% of the wire paths have an error rate of estimated capacitance value of 0%, and about 5% of the wire paths have an error rate of estimated capacitance value It is-丨%, which means that the estimated capacitance value of about 5% of the wire paths is about 10% less than the actual capacitance value, and the error rate of the estimated capacitance value of the other about 2% of the wire paths is 10%. That is to say, the estimated capacitance value of about 2% of the conductor path is about 10% more than the actual capacitance value, and the meanings indicated by other punctuation points on the curve 100 are as described above. Please refer to Figure 3, which is a graph showing the error ratio of the estimated capacitance value of the conductor path after logically synthesizing the RTL code using the individualized conductor load model. As shown by curve 10 in Figure 3, in the integrated circuit design, when the estimated resistance capacitance value and delay time value after the logic synthesis do not meet the requirements, the individualized wire load obtained after the logic synthesis can be used The model synthesizes the completed RTL code again to obtain circuit information such as the resistance and capacitance value and the delay time value that meet the requirements. As shown by the curve 1 in Fig. 3, in the integrated circuit design, about 5% of the wire paths have an error rate estimation of the capacitance value of 0%, and about 4% of the wire paths have an error rate estimation of the capacitance value. The ratio is-丨 0%, which means that the estimated capacitance value of about 4% of the wire paths is about 10% less than the actual capacitance value, and the error ratio of the estimated capacitance value of the other about 5% of the wire paths is 丨 0%. That is to say, the estimated capacitance value of about 5% of the wire path is about 10% more than the actual capacitance value. The meaning of other punctuation points on the curve 02 is also as described above. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ..............., can ......... (Please read the note on the back first (Fill in this page again) A7

544736 五、發明説明（） 比較第2圖和第3圖可看出，利用個別化導線負載模 呈’對RTL碼進行邏輯合成後，所估算的電容值準確度平 均比别次的邏輯合成後所估算的電容值準確度較高，因而 、、呈由不斷進行邏輯合成，可得到符合要求的電阻值、電容 值和延遲時間值等電路資訊。 然而’當積體電路設計的複雜度不斷提升時，邏輯合 成過程所消耗的時間就越久，因而降低設計時的效率。此 外’隨著積體電路設計的複雜度越來越高，積體電路中電 阻電谷所產生的線路延遲這項因素，對於積體電路的效能 有著越來越重要的主導地位β 請參考第4圖’其所繪示為隨製程技術的發展，於積 體電路中電阻電容參數的重要性之示意圖。如第4圖所 不’於〇,5//m的半導體製程時’電阻電容參數對積體電路 的衫響僅約為3 0 %，而於〇 _ 2 5 # m的半導體製程時，電阻 電容參數對積體電路的影響約為45%，但於〇·ΐ8 # m的半 導體製程時，電阻電容參數對積體電路的影響提升至約 60% ’可見隨著半導體製程的發展，電阻電容參數對積體 電路的影響日益增加，故習知邏輯合成其所提供的準確度 已不能滿足現今的積體電路設計之需求，於是改為利用實 體合成來估算積體電路設計的相關參數。 請參考第5圖，其所繪示為習知實體合成之流程圖。 首先，利用此積體電路設計的預設電阻電容單位值202， 對此積體電路已設計完成之RTL碼200進行實體合成步驟 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) — ......變.........、玎：.......S. (請先閲讀背面之注意事項再填寫本頁) 經濟部智迖財產局員工消費合作社印製 544736 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明説明（) 204 ,以獲得經過優化及已定位閘階層網列（phced Qate Nethst) ’然後對此已定位閘階層網列進行繞線叫）步 驟2 06後’獲得已定位已繞線閘階層網列，再進行估算步 驟208，即可估算出此積體電路設計的電阻值2丨〇、電容值 2 1 2和延遲時間值2丨4。 π參考第6圖，其所繪示為習知利用預設電阻電容單 位值對RTL碼進行實體合成後，對應導線路徑之電容值估 算的錯誤比率之曲線圖。如第6圖中之第一曲線25〇所示， 於第一積體電路設計中，有約23%的導線路徑其電容值估 异的錯誤比率為〇%，而約6%的導線路徑其電容值估算的 錯誤比率為-10%，3外約12%的導線路徑其電容值估算的 錯誤比率為1 0%，且僅有少部份的導線路徑，其電容值估 算的錯誤比率多於20%或少於JO%。 另外如第6圖中之第二曲線252所示，於第二積體電 路設計中，有約19%的導線路徑其電容值估算的錯誤比率 為〇%，而約25%的導線路徑其電容值估算的錯誤比率為-20% 0 比對第3圖和第6圖，可看出實體合成比邏輯合成能 獲彳^較精確的電阻值、電容值和延遲時間值等電路資訊， 這疋由於實體合成係利用比導線負載模型準確的電阻電容 單位值來作實體合成估算。 但是，由於積體電路的積集度日益增加，特殊功能的 。又计越來越複雜，使得晶片表面無法提供足夠的面積來製 7 本紙張尺度適用中國國家標準(CNS)A4規格(2ι〇χ297公釐) ------ .... ......變.........、玎......... (請先閲讀背面之注意事項再填寫本頁) 544736 經濟部智^財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 作所需的内連線（Interconnects)，因而採用三層或以上的金 屬層來進行多重内連線（Multilevel Interconnects)製程。當 金屬層增加時，在半導體結構中各層間所產生的耦合電容 亦隨之而增加。 請參考第7圖，其所繪示為習知半導體結構之各層間 的相對位置示意圖。於第7圖之半導體結構300中，於基 材302上形成有不同方向、不同材料和不同位置的各 t 屬層和介電層，而各種金屬層和介電層之間會產生不同的 耦合電容，例如金屬層304與金屬層3〇6之間的耦合電容 314、金屬層3 04與金屬層3〇8之間的耦合電容316、金屬 層304與金屬層31〇之間的耦合電容318、金屬層304與 介電層312之間的耦合電容32〇、金屬層3〇4與基材3〇2 之間的搞合電容322等。這些耦合電容都會影響實體合成 時所估算的電阻值、電容值和延遲時間值等電路相關參 數’當積體電路越複雜，各層之間的耦合電容之影響就越 大’使得線路之延遲時間的偏離情況日益嚴重。 所以’利用電阻電容單位值或導線負載模型的習知實 體合成’其估算的電路相關參數之準確度已不足 /a ..... 心M應付深 次微米半導體製程的積體電路，而且當積體電路越複雜 進行實體合成所需的時間就越長，更甚者可能於人 、σ攻過程 中’時序無法收歛而使得設計效率大為下降。因此♦ 展一種積體電路設計的合成方法，能於深次微米 <王後的 半導體製程中，提供積體電路設計快速而又準確的合 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 、一叮_ 544736 經濟部智迖財產局員工消費合作社印製 A7 B7 五、發明説明（） 同時又可提升設計的效率。 發明目的及概述： 雲於上述之發明背景中，於積體電路設計流程中，習 知的邏輯合成和實體合成皆未能提供設計者準確的積體電 路設計之電阻值和電容值，而且隨半導體製程的快速發 展’積體電路的積集度和複雜度都迅速提升，使得積體電 路設計在進行邏輯合成和實體合成時所耗費的時間亦不斷 增加，更甚者可能於合成過程時，時序無法收歛，造成設 計時間的浪費。 本發明的主要目的為提供了 一種積體電路設計中RC 參數的計算方法及其應用’特別是於高積集度和複雜度的 積體電路設計流程中，應用本發明之RC參數的計算方法 之合成過^ ’然論在計算精確度及計算時間上都比習知邏 輯合成過程和實體合成過程更精確，適合應用在大型且複 雜的積體電路設計中。 根據以上所述之目的’本發明為提供了 一種積體電路 設計中RC參數的計算方法及其應用，特別是有關於在積 體電路設計流程的邏輯合成和實體合成中，一種參數 的計算方法及其應用。首先提供已定位已繞線閘階層網 列’且此已定位已繞線閘階層網列分別具有實體合成 時間值和參考延遲時間i ;比對實體合成延遲時間值 電路單元實體合成延遲時間值和參考延遲時間值中的 單元參考延遲時間值，藉調整電容值以使得電路單元實體 本紙張尺度適用中國國豕標準(CNS)A4規格(21 〇X 297公爱） ---------------、訂--------- (請先閱讀背面之注意事項再填寫本頁) 544736 A7 -----—-—___ 五、發明説明（） 合成延遲時間值等於電路單元參考延遲時間值，且得到個 別化電谷值（Custom Capacitance);比對實體合成延遲時間 值中的内連線實體合成延遲時間值和參考延遲時間值中的 内連線參考延遲時間值，再利用個別化電容值及藉調整電 阻值以使得内連線實體合成延遲時間值等於内連線參考延 遲時間值’且彳于到個別化電阻值（Cust〇rn Resistance)。藉由 本發明之RC參數的計算方法及其應用，可解決傳統邏輯 合成和實體合成未能提供設計者準確的積體電路設計之電 阻值和電容值的問題，同時亦可大幅提升設計效率和時 程。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述，其中： 第1圖係繪示習知邏輯合成之流程圖。 第2圖係繪示習知利用電路單元庫導線負載模型對 RTL碼進行邏輯合成後，對應導線路徑之電容值估算的錯 誤比率之曲線圖。 第3圖係繪示習知利用個別化導線負載模型對rtL碼 .... ......變.........、玎.........摹 (請先閱讀背面之注意事項再場寫本頁) 經濟部智迖財產局員工消費合作社印製 率 阻 匕 「1 \ τρίτ 誤 中 錯 路 的 電 算 體 估 積 。 值於圖 容 ，程 電展^ 之發之 徑的成 路 術。合 線 技圖體 導 程意實 應 製示知 對 隨之習 ’ 示&示 後 4要繪 成 係重係 合。圖的圖 輯圖 4 數 5 邏線第參第 行曲 容 進之 電 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（） 第6圖係繪示習知利用預設電阻電容單位值對RTL碼 進行實體合成後，對應導線路徑之電容值估算的錯誤比率 之曲線圖。 第7圖係繪示習知半導體結構之各層間的相對位置示 意圖。 第8圖係繪示本發明之一實施例的RC參數的計算方法 之流程圖。 第9圖係繪示於積體電路設計流程中，應用本發明之 一實施例對RTL碼進行實體合成後，對應導線路徑之電容 值估算的錯誤比率之曲線圖。 圖號對照說明： 10 RTL 碼 12 電路單元庫導線負載模型 14 邏輯合成步驟 16 定位及繞線步驟 18 估算步驟 20 電阻值 22 電容值 24 延遲時間值 26 個別化導線負載模型 100 曲線 102 曲線 200 R T L碼 202 預設電阻電容單位值 204 實體合成步驟 206 繞線步驟 208 估算步驟 210 電阻值 212 電容值 214 延遲時間值 250 第一曲線 252 第二曲線 300 半導體結構 11 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) .... ......费.........、玎......... (請先閲讀背面之注意事項再填寫本頁) 544736 A7 B7 五、發明説明（） 302 基 材 304 金 屬 層 306 金 屬 層 308 金 屬 層 3 10 金 屬 層 3 12 介 電 層 3 14 耦 合 電 容 3 16 耦 合 電 容 3 18 搞 合 電 容 320 搞 合 電 容 322 耦 合 電 容 500 RTL 碼 502 電 阻 電 容 單 位 值 504 導 線 負 載模型 506 合 成 和 定 位 步 驟 508 繞 線 步 驟 5 10 擷取電阻電容和延遲時間計算步驟 5 12 參考延遲時間值 5 14 電路單元參考延遲時間值 516 内連線參考延遲時間值 5 4 8 實體合成之繞線步驟 5 50 實體合成之估計繞線電阻電容值步驟 5 52 電阻電容單位值 554 實體合成延遲時間值 5 56 電路單元實體合成延遲時間值 5 5 8 内連線實體合成延遲時間值 (請先閲讀背面之注意事項再填寫本頁) 、\丟 經濟部智迖財產局員工消費合作社印製 600 比較步驟 602 調整電容值步驟 604 個別化電容值 610 比較步驟 612 調整電阻值步驟 614 個別化電阻值 700 第一曲線 702 第二曲線 發明 詳細說明： 請參考第8圖，其所繪示為本發明之一實施例的 RC 參數的計算方法之流程圖 。首先提供 已完成積體電路設計 12 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 A7 _____ 五、發明説明（) 的RTL碼5 00，然後利用電阻電容單位值5〇2或導線負載 模型504，對RTL碼5〇〇進行合成和定位步驟5〇6，以得 到對應RTL碼500的已定"階。 由於此時已定位閘階層網列尚未繞線，故對已定位閘 階層網列進行繞線步驟508，以得到已定位已繞線閘階層 網列。接著對已定位已繞線閘階層網列進行擷取電阻電容 和延遲時間計算步驟5 1 〇，以得到已定位已繞線閘階層網 列之參考延遲時間值5 1 2，其中參考延遲時間值5丨2主要 是由電路單元參考延遲時間值5丨4和内連線參考延遲時間 值5 1 6所組成。 然後’再對經由合成和定位步驟5〇6所得的已定位閘 階層網列進行實體合成之繞線步驟548，接著利用電阻電 容單位值5 5 2，對已定位已繞線閘階層網列進行實體合成 之估計繞線電阻電容值步驟5 5 〇，以得到已定位已繞線閘 階層網列之實體合成延遲時間值5 54，其中實體合成延遲 時間值554主要是由電路單元實體合成延遲時間值556和 内連線實體合成延遲時間值5 58所組成。 由於參考延遲時間值5丨2是由已定位已繞線閘階層網 列經擷取電阻電容和延遲時間計算步驟5 1 〇而獲得，所以 具有高準確度且接近設計者所要求的延遲時間，而實體人 成之估计繞線電阻電谷值步驟5 5 0係利用電阻電容單位值 5 52來估算線路的延遲時間，因此估算結果的準確度普遍 不高，故於本發明之一實施例中，是以參考延遲時間 5 1 2 13 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁) 、\呑 經濟部智迖財產局員工消費合作社印製 五 、發明說明（） 作為RTL碼500進行 、 人忐α 體5成時的參考值，妙，幺 σ成延遲時間值554 亏值然後調整實體 ”2。 吏'、接近或等於參考延遲時間值 考延:::=實5體:=時:值554’使其接近或等於參 體合成延遲時間值…後^于參考延遲時間值512和實 和電路單元實體人 早兀，考延遲時間值514 ,,,^ 〇成延遲時間值556進行比較牛驟< 例如電路單元參考 退仃比較步驟600， 遲時間值556，==Γ51:減電路單元實體合成延 於電路單元春她 、。果的化對值作為第—差值。由 的電路單元參數和電容值所旦1 H白層網列中 杳表(Look Τ 響，而電路單元參數可經由 肩。。k-up Table)等方法獲知，故為了減少第 :糟進行調整電容值步.驟6Q2，推算出合適的電容值，再 立已繞線閘階層，網列及電阻電容單位值切進行實 體二成之估計繞線電阻電容值步驟55()，可得到經過調整 電容值後的實體合成延遲時間值554。 經濟部智^財產局員工消費合作社印製 再將經過調整電容值後的實體合成延遲時間值5 之 電路早70實體合成延遲時間值5 5 6和電路單元參考延遲時 間值514進行比較步驟600，若電路單元實體合成延遲時 間值5 5 6等於或接近電路單元參考延遲時間值5 1 4時，則 此時的電容值符合設計者的要求，為個別化電容值6〇4。 若電路單元實體合成延遲時間值556不等於電路單元參考 延遲時間值5 1 4時，則再重複進行調整電容值步驟602及 14 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) 544736 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 實體合成步驟55〇,直至獲得等於或接近電路單元參考延 遲時間值514的電路單元實體合成延遲時間值556及個別 化電容值604。 接著’由於内連線實體合成延遲時間值5 5 8主要受閘 階層網列中線路的電容值和電阻值所影響，而電容值於前 述步驟中已求得為個別化電容值604，因此可藉進行調整 電阻值步驟6 1 2，推算出合適的電阻值，再與個別化電容 值6 04和已定位已繞線閘階層網列進行實體合成步驟 550 ’得到首次調整電阻值的實體合成延遲時間值554。 經濟部智毯財產局員工消費合作社印製 再將首次調整電阻值的實體合成延遲時間值5 5 4之内 連線實體合成延遲時間值5 5 8和内連線參考延遲時間值 5 1 6進行比較步驟，若内連線實體合成延遲時間值$ 5 8等 於或接近内連線參考延遲時間值5 1 6時，則此時的電阻值 符合設計者的要求，為個別化電阻值6 1 4。若内連線實體 合成延遲時間值5 5 8不等於内連線參考延遲時間值5 1 6 時’則再重複進行調整電阻值步驟6 1 2及實體合成步驟 5 5 0 ’以求獲得等於或接近内連線參考延遲時間值5 1 6的内 連線實體合成延遲時間值5 5 8及個別化電阻值6 1 4。在獲 得個別化電容值604和個別化電阻值6 1 4後，即可再次代 入實體合成步驟550中，以求付付合设计者要求的實體合 成延遲時間值5 5 4。 請參考第9圖，其所繪示為於積體電路設計流程中， 應用本發明之一實施例對RTL碼進行實體合成後，對應導 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） Λ路彳二之電谷值估鼻的錯誤比率之曲線圖。如第9圖中之 第曲700所不，於第一積體電路設計中，有約35%的導 Λ路彳二其電谷值估异的錯誤比率為，而約1 的導線路 徑其電容值估算的錯誤比率為]〇%，另㈣1〇%的導線路 ㈣電容值估算的錯誤比率為1〇%，且僅有少部份的導線 路徑，其電容值估算的錯誤比率多於2〇%或少於_2〇%。 另外如第9圖中之第二曲線702所示，於第二積體電 路叹计中’有約29%的導線路徑其電容值估算的錯誤比率 為〇%，而約17%的導線路徑其電容值估算的錯誤比率為-⑺％，約12%的導線路徑其電容值估算的錯誤比率為1〇%。 比對第6圖和第9圖，可看出應用本發明之一實施例 車乂傳統μ體合成，能獲得更精確的電阻電容值和延遲時間 值等電路資訊，這是由於本發明所提供的積體電路設計中 多數的α十异方法，係利用前次經過調整的電容值和電阻 值’代入下次電容值和電阻值的計算步驟中計算，而非利 用電阻電容單位值或導線負載模型，因此可比傳統實體合 成獲彳于更精確的電阻電容值和延遲時間值等電路資訊。 本發明的優點為提供了一種積體電路設計中RC參數 的計具方法，於本發明之計算個別化電容值和個別化電阻 值步驟中’是利用前次經過調整的電容值和電阻值，代入 下-人汁异步驟中計算’與利用導線負栽模型和電阻電容單 位值來計算個別化電容值和個別化電阻值的傳統RC參數 計算方法不同。由於每次實體合成所採用的電容值和電阻 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) f請先閲讀背面之注意事項再填寫本頁)544736 V. Description of the invention () Comparing Figure 2 and Figure 3, it can be seen that after the RTL code is logically synthesized by using the individualized wire load mode, the accuracy of the estimated capacitance value is averaged better than that of other times. The accuracy of the estimated capacitor value is relatively high. Therefore, continuous and logical synthesis is performed to obtain circuit information such as resistance value, capacitance value and delay time value that meet the requirements. However, as the complexity of the integrated circuit design continues to increase, the longer the logic synthesis process takes, thus reducing the design efficiency. In addition, as the complexity of integrated circuit design becomes higher and higher, the factor of line delay caused by the resistance valley in integrated circuits has become more and more important in the dominance of integrated circuit performance. Fig. 4 is a schematic diagram showing the importance of resistance and capacitance parameters in integrated circuits with the development of process technology. As shown in Fig. 4, the resistance of the resistance and capacitance parameters to the integrated circuit is only about 30% when the semiconductor process is less than 0,5 // m, and the resistance during the semiconductor process of 0 2 5 # m The influence of the capacitance parameter on the integrated circuit is about 45%, but in the semiconductor process of 0 · ΐ8 # m, the influence of the resistance and capacitance parameter on the integrated circuit is increased to about 60%. It can be seen that with the development of the semiconductor process, the resistance and capacitance The influence of parameters on integrated circuits is increasing. Therefore, the accuracy provided by conventional logic synthesis can no longer meet the needs of today's integrated circuit designs. Therefore, physical synthesis is used to estimate the relevant parameters of integrated circuit designs. Please refer to Fig. 5, which shows a flowchart of conventional entity synthesis. First, use the preset resistor-capacitor unit value 202 of this integrated circuit design to perform the physical synthesis step on the RTL code 200 that has been designed for this integrated circuit. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). ) — ...... change ........., 玎: ......... S. (Please read the notes on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative 544736 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the Invention () 204 to obtain an optimized and targeted gate-level network (phced Qate Nethst) Line winding is called) after step 2 06 'to obtain the positioned and wound gate hierarchical network column, and then perform the estimation step 208 to estimate the resistance value of the integrated circuit design 2 丨 〇, the capacitance value 2 1 2 and Delay time value 2 丨 4. π refers to FIG. 6, which is a graph showing the error ratio of the estimated capacitance value of the corresponding wire path after the RTL code is physically synthesized using the preset resistance-capacitance unit value. As shown in the first curve 25 in FIG. 6, in the first integrated circuit design, about 23% of the lead paths have an error ratio of estimated capacitance value of 0%, and about 6% of the lead paths have The error rate of the capacitance value estimation is -10%. The error rate of the capacitance value estimation of about 12% of the wire paths is 10%, and there are only a few wire paths. The error rate of the capacitance value estimation is more than 20% or less JO%. In addition, as shown by the second curve 252 in FIG. 6, in the second integrated circuit design, about 19% of the wire paths have an error rate estimation of the capacitance value of 0%, and about 25% of the wire paths have a capacitance The error ratio of the value estimation is -20%. Comparing Figure 3 and Figure 6, it can be seen that the physical synthesis can obtain more accurate circuit information such as resistance, capacitance, and delay time than logical synthesis. Because the physical synthesis system uses the accurate resistance and capacitance unit value than the wire load model to make the physical synthesis estimation. However, due to the increasing degree of integration of integrated circuits, special functions. It is also becoming more and more complicated, making the surface of the wafer unable to provide enough area to make 7 paper sizes that are applicable to the Chinese National Standard (CNS) A4 specification (2ι〇χ297 mm) ------ .... ... ... change ........., 玎 ......... (Please read the precautions on the back before filling out this page) 544736 Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 5. Description of the invention () Interconnects are required for multi-level interconnections, so three or more metal layers are used for the Multilevel Interconnects process. As the number of metal layers increases, the coupling capacitance between the layers in the semiconductor structure also increases. Please refer to FIG. 7, which is a schematic diagram showing the relative positions between the layers of a conventional semiconductor structure. In the semiconductor structure 300 of FIG. 7, various metal layers and dielectric layers are formed on the substrate 302 in different directions, different materials, and different positions, and different couplings between the various metal layers and the dielectric layers are generated. Capacitors, for example, the coupling capacitance 314 between the metal layer 304 and the metal layer 306, the coupling capacitance 316 between the metal layer 304 and the metal layer 308, and the coupling capacitance 318 between the metal layer 304 and the metal layer 308. , The coupling capacitance 32 between the metal layer 304 and the dielectric layer 312, the coupling capacitance 322 between the metal layer 304 and the substrate 30, and the like. These coupling capacitances will affect circuit-related parameters such as the resistance value, capacitance value and delay time value estimated during physical synthesis. 'The more complex the integrated circuit, the greater the influence of the coupling capacitance between the layers.' This makes the delay time of the line Deviations are getting worse. Therefore, the accuracy of the estimated circuit-related parameters of 'using the unit value of the resistance-capacitance unit or the conventional entity of the wire load model' is insufficient / a ..... The core M is used for integrated circuits for deep sub-micron semiconductor processes, and when The more complicated the integrated circuit is, the longer it takes to perform the physical synthesis, and even more, the timing cannot be converged during the human and σ attack process, which greatly reduces the design efficiency. Therefore ♦ Develop a synthesis method of integrated circuit design, which can provide integrated circuit design fast and accurate in the sub-micron < Queen's semiconductor manufacturing process. The paper size is applicable to China National Standard (CNS) A4 specification ( 210X297 mm) (Please read the precautions on the back before filling out this page), Yiding _ 544736 Printed by A7 B7, Employees' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention () At the same time, it can improve the efficiency of design. Purpose and summary of the invention: In the above background of the invention, in the integrated circuit design process, the conventional logic synthesis and physical synthesis failed to provide the designer with accurate resistance and capacitance values of the integrated circuit design. The rapid development of semiconductor processes 'integration and complexity of integrated circuits are rapidly increasing, making integrated circuit designs' time spent on logic synthesis and physical synthesis increasing, and even more likely during the synthesis process, Timing cannot converge, resulting in a waste of design time. The main object of the present invention is to provide a method for calculating RC parameters in integrated circuit design and its application, especially in the design process of integrated circuits with high integration and complexity, applying the method for calculating RC parameters of the present invention. The synthesis process ^ 'ran theory is more accurate in calculation accuracy and calculation time than the conventional logic synthesis process and solid synthesis process, which is suitable for application in large and complex integrated circuit designs. According to the above-mentioned purpose, the present invention provides a method for calculating RC parameters in integrated circuit design and its application, and in particular, it relates to a method for calculating parameters in logical synthesis and physical synthesis of integrated circuit design flow. And its applications. First provide the positioned and wound gate hierarchy network column, and this positioned and wound gate hierarchy network column has the physical synthesis time value and the reference delay time i respectively; compare the physical synthesis delay time value of the circuit unit physical synthesis delay time value and The unit of the reference delay time value refers to the reference delay time value. By adjusting the capacitance value, the paper size of the circuit unit entity is applicable to the Chinese National Standard (CNS) A4 specification (21 〇 297 public love) -------- ------- 、 Order --------- (Please read the notes on the back before filling out this page) 544736 A7 -----—-—___ V. Description of the invention () Synthesis delay The time value is equal to the reference delay time value of the circuit unit, and an individualized valley value (Custom Capacitance) is obtained; the internal connection of the physical synthesis delay time value and the internal connection reference of the reference delay time value are compared The delay time value, and then the individualized capacitor value and the resistance value are adjusted so that the synthesized delay time value of the interconnecting entity is equal to the reference delay time value of the interconnecting line, and is limited to the individualized resistance value (Custorn Resistance). With the calculation method and application of the RC parameters of the present invention, the problems of traditional logic synthesis and physical synthesis that cannot provide designers with accurate integrated circuit design resistance and capacitance values can be solved, and the design efficiency and time can be greatly improved. Cheng. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figure 1 shows a flowchart of conventional logic synthesis. Figure 2 is a graph showing the error ratio of the estimated capacitance value of the corresponding wire path after the logic synthesis of the RTL code using the wire load model of the circuit unit library. Figure 3 shows the conventional use of individualized wire load models to rtL codes ......................, 玎 ......... 玎 ( (Please read the precautions on the back before writing this page)) The printed rate of the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, "1 \ τρίτ Miscalculation of computer calculations. Values are shown in Figures, Cheng Dianzhan ^ The path formation method of the path. The technical guide of the line drawing should be made to show the follow-up exercises, and the following 4 will be drawn as the system. The picture of the picture is shown in Figure 4. Number 5 The paper size of Qu Rongjin's electric paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544736 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Figure 6 is a drawing It is known that the RTL code is physically synthesized by using a preset resistance and capacitance unit value, and the error rate corresponding to the estimated capacitance value of the wire path is a graph. Fig. 7 is a schematic diagram showing the relative positions of the layers of the conventional semiconductor structure. FIG. 8 is a flowchart illustrating a method for calculating RC parameters according to an embodiment of the present invention. It is shown in the integrated circuit design flow, after applying one embodiment of the present invention to physically synthesize the RTL code, the curve corresponding to the estimated error rate of the capacitance value of the conductor path. The comparison of drawing numbers: 10 RTL code 12 circuit cell library Wire load model 14 Logic synthesis step 16 Positioning and winding step 18 Estimation step 20 Resistance value 22 Capacitance value 24 Delay time value 26 Individualized wire load model 100 Curve 102 Curve 200 RTL code 202 Preset resistance capacitance unit value 204 Physical synthesis step 206 Winding step 208 Estimation step 210 Resistance value 212 Capacitance value 214 Delay time value 250 First curve 252 Second curve 300 Semiconductor structure 11 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ... ...... Fees ........., ............ (Please read the notes on the back before filling out this page) 544736 A7 B7 V. Description of the invention () 302 Base material 304 metal layer 306 metal layer 308 metal layer 3 10 metal layer 3 12 dielectric layer 3 14 coupling capacitor 3 16 coupling capacitor 3 18 coupling capacitor 320 Coupling Capacitor 322 Coupling Capacitor 500 RTL Code 502 Resistor Capacitor Unit Value 504 Wire Load Model 506 Synthesis and Positioning Step 508 Winding Step 5 10 Extracting Resistor Capacitance and Delay Time Calculation Step 5 12 Reference Delay Time Value 5 14 Circuit Unit Reference Delay Time value 516 Inner wiring reference delay time value 5 4 8 Physical composition winding step 5 50 Physical composition estimated winding resistance capacitance value step 5 52 Resistance capacitance unit value 554 Physical composition delay time value 5 56 Circuit unit physical composition delay Time value 5 5 8 Synthesis delay time value of interconnected entities (please read the precautions on the back before filling out this page), \ Lost by the Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumption Cooperative, printed 600 Comparison step 602 Adjusting capacitance value step 604 Individual Capacitance value 610 Comparison step 612 Adjusting resistance value step 614 Individualized resistance value 700 First curve 702 Second curve The invention is described in detail: Please refer to FIG. 8, which illustrates the calculation of RC parameters according to an embodiment of the present invention. Method flow chart. First provide the completed integrated circuit design. 12 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544736 A7 _____ 5. The RTL code of the invention description () is 5 00, and then the unit value of the resistance and capacitance is 5 2 Or the wire load model 504, the synthesis and positioning step 506 of the RTL code 500 is performed, so as to obtain a predetermined level corresponding to the RTL code 500. Since the positioned gate-level grid array has not been wound at this time, a winding step 508 is performed on the positioned gate-level grid array to obtain the positioned and wound gate-level grid array. Next, perform step 5 1 〇 to calculate the resistance, capacitance and delay time of the positioned and wound gate hierarchical network to obtain the referenced delay time value of the positioned and wound gate hierarchical network 5 1 2, among which the reference delay time value 5 丨 2 is mainly composed of the reference delay time value of the circuit unit 5 丨 4 and the reference delay time value of the interconnect 5 1 6. Then, perform the physical synthesis winding step 548 on the positioned gate-level grid array obtained through the synthesis and positioning step 506, and then use the resistance-capacitance unit value of 5 5 2 to perform the positioning on the already-routed gate-level grid array. Step 5 5 0 of the estimated physical winding resistance and capacitance value of the physical synthesis to obtain the physical synthetic delay time value of the already-positioned and wound gate hierarchical network column 5 54. The physical synthetic delay time value 554 is mainly composed of the circuit unit physical synthetic delay time. The value is 556 and the combined delay time value of the connected entity is 5 58. Since the reference delay time value 5 丨 2 is obtained from the positioned and wound gate hierarchy network column by taking the resistance and capacitance and the delay time calculation step 5 1 〇, it has high accuracy and is close to the delay time required by the designer. The actual artificial step of estimating the winding resistance valley value of step 5 50 is to use the unit value of resistance capacitor 5 52 to estimate the delay time of the line. Therefore, the accuracy of the estimation result is generally not high. Therefore, it is an embodiment of the present invention. Based on the reference delay time 5 1 2 13 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) Printed by the consumer cooperative V. Description of the invention () As a reference value when the RTL code 500 is used, and the human body is 50%, wonderful, 妙 σ is a delay time value of 554, and then the entity is adjusted. "2. Officials, close to or equal to Reference delay time value test delay ::: = Real 5 body: = Hour: value 554 'to make it close to or equal to the parameter body synthesis delay time value ... After the reference delay time value of 512 and the real and circuit unit entity, Take the delay time value 514 ,,, ^ 〇 into the delay time value 556 for comparison < For example, the circuit unit refers to the back-off comparison step 600, the delay time value 556, == Γ51: minus the circuit unit entity synthesis is delayed in the circuit unit. The pairing value is used as the first difference. It is determined by the circuit unit parameters and capacitance values in the 1 H white layer network column (Look T, and the circuit unit parameters can be passed through the shoulder ... k-up Table) and other methods. It is known, so in order to reduce the first step: adjust the capacitance value step. Step 6Q2, calculate the appropriate capacitance value, and then establish the winding gate level, the network column and the unit value of the resistance and capacitance are cut to estimate the physical resistance of the winding resistance and capacitance. The value of step 55 () can obtain the physical composite delay time value 554 after adjusting the capacitance value. The circuit is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the physical composite delay time value 5 after adjusting the capacitance value is 70 as early as 70. The physical synthesis delay time value 5 5 6 and the circuit unit reference delay time value 514 are compared in step 600. If the circuit unit physical synthesis delay time value 5 5 6 is equal to or close to the circuit unit reference delay time value 5 1 4 then this time The capacitance value meets the designer's requirements and is the individualized capacitance value of 60. If the circuit unit entity synthetic delay time value 556 is not equal to the circuit unit reference delay time value 5 1 4, then repeat the adjustment of the capacitance value steps 602 and 14 This paper size applies the Chinese National Standard (CNS) A4 specification (210x297 mm) 544736 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Physical synthesis step 55 until it is equal to or close to The circuit unit entity of the circuit unit reference delay time value 514 synthesizes the delay time value 556 and the individualized capacitor value 604. Then 'Because the delay time of the internal connection entity synthesis 5 5 8 is mainly affected by the capacitance and resistance values of the lines in the gate-level network column, and the capacitance value has been obtained as the individualized capacitance value 604 in the previous step, so it can be By performing step 6 1 2 to adjust the resistance value, calculate the appropriate resistance value, and then perform physical synthesis with the individualized capacitor value 6 04 and the positioned and wound gate hierarchical network column. Step 550 'Get the physical synthesis delay for the first adjustment of the resistance value Time value 554. Printed by the Consumer Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs and the Consumers' Cooperative for the first time to adjust the resistance value, and then synthesize the delay time value of the physical connection 5 5 4 within the physical connection delay time value 5 5 8 and the internal reference delay time value 5 1 6 In the comparison step, if the synthetic delay time value of the interconnected entity $ 5 8 is equal to or close to the reference delay time of the interconnected value 5 1 6, the resistance value at this time meets the designer's requirements, which is the individualized resistance value 6 1 4 . If the value of the delay time of the synthesis of the interconnected entity 5 5 8 is not equal to the value of the reference delay time of the interconnected line 5 1 6 ', then repeat the adjustment of the resistance value step 6 1 2 and the entity synthesis step 5 5 0' to obtain an equal or The combined delay time value of the interconnected entity close to the reference delay time value of 5 1 6 is 5 5 8 and the individualized resistance value is 6 1 4. After obtaining the individualized capacitor value 604 and the individualized resistance value 6 1 4, it can be substituted into the physical synthesis step 550 again to obtain the physical synthesis delay time value 5 5 4 required by the designer. Please refer to FIG. 9, which is shown in the integrated circuit design process. After applying an embodiment of the present invention to physically synthesize the RTL code, the corresponding paper size of the guide applies the Chinese National Standard (CNS) A4 specification (210X297). (Mm) 544736 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () A graph of the error rate of the esophageal trough of the road. As shown in No. 700 of Fig. 9, in the first integrated circuit design, there are about 35% of the conduction circuits. The error ratio of the estimated valley value is, and the capacitance of the wire path of about 1 has a capacitance The error rate of the estimated value is [0%], and the error rate of the estimated capacitance value is 10%, and there is only a small part of the wire path. The error rate of the estimated capacitance value is more than 2. % Or less than -20%. In addition, as shown by the second curve 702 in FIG. 9, in the second integrated circuit circuit meter, about 29% of the lead paths have an error ratio of 0%, and about 17% of the lead paths have The error rate of capacitance value estimation is -⑺%, and the error rate of capacitance value estimation of about 12% of the wire paths is 10%. Comparing FIG. 6 and FIG. 9, it can be seen that the conventional μ-body synthesis of the car according to one embodiment of the present invention can obtain more accurate circuit information such as resistance and capacitance values and delay time values. This is because the present invention provides Most of the alpha ten different methods in the integrated circuit design are calculated by using the previously adjusted capacitance value and resistance value 'into the next calculation step of the capacitance value and resistance value, instead of using the unit value of resistance and capacitance or the load of the wire Model, so it can get more accurate circuit information such as resistance capacitance value and delay time value than traditional physical synthesis. The advantage of the present invention is to provide a method for measuring the RC parameters in the integrated circuit design. In the step of calculating the individualized capacitance value and the individualized resistance value of the present invention, the capacitor value and the resistance value adjusted before are used. Substituting the calculation in the next-human juice different step is different from the traditional RC parameter calculation method that uses the wire load model and the resistance-capacitance unit value to calculate the individualized capacitance value and the individualized resistance value. Due to the capacitance and resistance used for each physical synthesis, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). F Please read the precautions on the back before filling this page)

544736 A7 B7 五、發明説明（） 值皆經過進一步調整修正後才再次進行實體合成，因此可 比傳統邏輯合成和實體合成更快速計算出準確的電容值、 電阻值和線路延遲時間等電路資訊，因此設計效率和時程 得以大幅提升。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 —— ......#.........、玎......... (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)544736 A7 B7 V. Description of the invention () The values are all adjusted after physical adjustments are made again. Therefore, accurate circuit information such as capacitance, resistance, and line delay time can be calculated faster than traditional logic synthesis and physical synthesis. Design efficiency and schedule have been greatly improved. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention Effective changes or modifications should be included in the scope of patent application described below. —— ## ............, 玎 ......... (Please read the notes on the back before filling out this page) Employee Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Printed paper sizes are applicable to China National Standard (CNS) A4 (210X297 mm)

Claims (1)

544736 A B CD 申請專利範圍 經濟部智慧財產局員工消費合作社印製 1.一種積體電路設計中RC參數的計算方法，係應用於 該積體電路設計的一已繞線設計中，其中該已繞線設計已 具有一第一實體合成延遲時間值和一參考延遲時間值，且 該第一實體合成延遲時間值至少包括複數個第一電路單元 實體合成延遲犄間值和複數個第一内連線實體合成延遲時 間值，其中影響該ϋ —電路單^實體合成延遲時間值的 參數至少包括複數個電路單元參數以及一第一〜 ^ 电各值，影 響該些第一内連線實體合成延遲時間值的參數至少包括一 第-電阻值以及該第一電容值，$參考延遲時間值則至少 包括複數個電路單元參考延遲時間值和複數個内連線參= 延遲時間值，該積體電路設計中RC參數的舛管+ J叶异方法至少 包括： 對該些第-電路單元實體合成延遲時間值和該些電路 單元參考延遲時間值進行一第一比較步驟，以々 于到一第一 差值； 藉調整該第一電容值，以減少該第一差佶尽值，並得到一 第二電容值； 對該已繞線設計進行一第一實體合成步驟， 共中該第 一實體合成步驟係利用該第二電容值和一電阻时 电各單位 值’以得到該已繞線設計之一第二實體合成延遲時間值， 其中該第二實體合成延遲時間值至少包括： 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公釐) (請先閲讀背面之注意事項再填寫本頁} -訂· 544736 六、申請專利範圍 A8 B8 C8 D8544736 AB CD Patent application scope Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 1. A calculation method of RC parameters in integrated circuit design, which is applied to a wound design of the integrated circuit design, where the wound The line design already has a first physical composition delay time value and a reference delay time value, and the first physical composition delay time value includes at least a plurality of first circuit unit physical composition delay time values and a plurality of first interconnections. The physical synthesis delay time value, wherein the parameters affecting the ϋ-circuit single ^ physical synthesis delay time value include at least a plurality of circuit unit parameters and a first ~ ^ electrical value, which affect the first interconnected physical synthesis delay time. The value parameter includes at least a first resistance value and the first capacitance value, and the $ reference delay time value includes at least a plurality of circuit unit reference delay time values and a plurality of interconnecting parameters = delay time value. The integrated circuit design The RC parameter + J-lead method in RC parameters at least includes: synthesizing delay time values for the first circuit unit entities and the circuit units Perform a first comparison step with reference to the delay time value to obtain a first difference value; adjust the first capacitor value to reduce the first difference value and obtain a second capacitor value; The winding design performs a first physical synthesis step. The first physical synthesis step uses the second capacitance value and a resistance time unit value to obtain a second physical synthesis delay time of the wound design. Value, where the second entity synthetic delay time value includes at least: This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) (Please read the precautions on the back before filling out this page}-Order · 544736 VI. Patent application scope A8 B8 C8 D8 複數個第二雷敗结_ 早凡實體合成延遲時 . 複數個第二内連魂” 一〈遲時間值，M及 運線K體合成延遲時 對該些第二電路單元举_人 &gt; 卞值， 蓋亓夫者”味“ 延遲時間值和該些電路 事：參：延遲時間值進行-第二比較步驟，當該4b第二： 路單疋貫體合成延遲時間值 Λ 電 且个寻於該些電政 時間值時，藉調整該第-帝六 '^遲 弟一私谷值，以得到複數個預設電 單元實體合成延遲時間值及一 路 丨口⑴化冤各值，其中該些 設電路單元實體合成延遲時間值 - 了间值寺於垓些電路單元參考 遲時間值； 、 對該些第二電路單元膏許人# μ π + 、租σ成I遲蚪間值和該些電路 單元參考延遲時間值進行該第二比較步驟，當誃歧 路單元實體合成延遲時間值等於該此電 ^ 寸么θ二1：路早疋參考延遲時 間值時，則該第一電谷值為該個別化電容值，以及該此第 二電路單元實體合成延遲時間值為該些預設電路單元實體 合成延遲時間值； 對該些第一内連線實體合成延遲時間值和該些内連線 參考延遲時間值進行一第三比較步驟，以得到一第二差 值； 、 利用該個別化電容值及調整該第一電阻值，以減少該 第二差值，並得到一第二電阻值； 對該已繞線設計進行一第二實體合成步驟，其中該第 二實體合成步驟係利用該第二電阻值、該個別化電容值， 以得到該已繞線3又a十之 第二實體合成延遲時間值，立中 19 本紙張尺度適用巾酬緖準(CNS)A4規格(21GX297公楚） f請先閱背面之注意事項再填寫本頁} •訂. 經濟部智慧財產局員工消費合作社印製 544736 ABCD 申請專利範圍 該第二實體合成延遲時間值至少包括： (請先閱讀背面之注意事項再填寫本頁) 複數個第三電路單元實體合成延遲時間值；以及 複數個第三内連線實體合成延遲時間值； 對該些第三内連線實體合成延遲時間值和該些内連線 參考延遲時間值進行一第四比較步驟，當該些第三内連線 實體合成延遲時間值不等於該些内連線參考延遲時間值 時’藉調整該第二電阻值，以得到複數個預設内連線實體 合成延遲時間值及一個別化電阻值，其中該些預設内連線 實體合成延遲時間值等於該些内連線參考延遲時間值；以 及 對該些第二内連線實體合成延遲時間值和該些内連線 參考延遲時間值進行該第四比較步驟，當該些第三内連線 實體合成延遲時間值等於該些内連線參考延遲時間值時， 則該第二電阻值為該個別化電阻值，以及該些第三内連線 實體合成延遲時間值等於該些預設内連線實體合成延遲時 間值。 經濟部智慧財產局員工消費合作社印製 2 ·如申請專利範圍第1項所述之方法，其中於得到該 個別化電容值和該個別化電阻值後，更包括利用該個別化 電容值和該個別化電阻值，進行一第三實體合成步驟，以 調整該積體電路設計之一已定位閘階層網列。 3 .如申請專利範圍第1項所述之方法，其中影響該些 20 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ABCD 544736 六、申請專利範圍 第一電路單元實體合成延遲時間值的參數包括複數個電路 單元參數，且該些電路單元參數係視該積體電路設計而 定。 4.如申請專利範圍第1項所述之方法，其中上述之第 一電容值是由一第一垂直方向電容值和一第一水平方向電 容值組成。 5 ·如申請專利範圍第1項所述之方法，其中上述之第 一電阻值是由一第一垂直方向電阻值和一第一水平方向電 阻值組成。 (請先閲讀背面之注意事項再填寫本頁) 個平 之水 述化 上別 中個 其一 ， 和 法值 方容 之電 述向 所方 項直 1 垂 第化 圍別 範個 利' ο 專由成 請是組 申值值 如容容 6.電電 化向 別方 個平 之水 述化 上別 中個 其 一 , 和 法值 方阻 之電 述向 所方 項直 1 垂 第化 圍 为 範個 利一。 專由成 請是組 申值值 如阻阻 7.電電 化向 別方 % 經濟部智慧財產局員工消費合作社印製 第去 之減 述值 上間 中時 其遲 ’ 延 法成 方合 之體 述實 所元 項單 1路 第電時 圍一遲 範第延 利些考 專談參 請為元 申驟單 如步路 8.較電 比些 1 該 值 間 21 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 A8Plural second thunderbolts _ When early synthesis of entities is delayed. Plural second interlinked souls "-<late time value, when M and K line body composition delays, the second circuit unit is lifted _person> Threshold value, the "coward" delay time value and these circuit matters: reference: the delay time value is performed-the second comparison step, when the 4b second: the road single body synthesis delay time value Λ electric and a When looking for the time values of the electric power, by adjusting the value of the -dijili '^ chidiyiprivate valley value, to obtain a plurality of preset electrical unit entity synthetic delay time values and all the values of ⑴ ⑴ 冤, in which The synthetic delay time values of the set circuit unit entities are the reference time delay values of the circuit units, and the second circuit unit pastes the people # μ π +, and σσ is the delay time value and The circuit unit performs the second comparison step with reference to the delay time value. When the synthetic delay time value of the 誃 manifold unit entity is equal to the voltage ^ θ 1: 1: the reference delay time value of the road early, the first power valley Value is the individualized capacitor value, and the first The second circuit unit entity synthesis delay time value is the preset circuit unit entity synthesis delay time value; a third comparison step is performed on the first interconnected entity synthesis delay time values and the interconnected reference delay time values. To obtain a second difference value; use the individualized capacitor value and adjust the first resistance value to reduce the second difference value and obtain a second resistance value; perform a second on the wound design Physical synthesis step, wherein the second physical synthesis step uses the second resistance value and the individualized capacitor value to obtain the second physical synthesis delay time value of the wound wire 3 and a, which is 19 paper sizes. Applicable towel standard (CNS) A4 specifications (21GX297). F Please read the notes on the back before filling out this page} • Order. Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 544736 ABCD Application for patent scope This second entity The synthetic delay time value includes at least: (Please read the precautions on the back before filling this page) Multiple synthetic circuit unit delay time values for the third circuit unit; and multiple third internal Synthesizing delay time values of the line entities; performing a fourth comparison step on the synthesizing delay time values of the third interconnecting entities and the reference delay time values of the interconnecting entities; When it is not equal to the reference delay time values of the interconnects, 'the second resistor value is adjusted by the adjustment to obtain a plurality of preset interconnected entity synthetic delay time values and a specific resistance value, wherein the preset interconnects The physical synthesis delay time value is equal to the interconnected reference delay time values; and the fourth comparison step is performed on the second interconnected physical synthesis delay time values and the interconnected reference delay time values. When the combined delay time values of the third interconnected entities are equal to the reference delay time values of the interconnected entities, the second resistance value is the individualized resistance value, and the synthesized delay time values of the third interconnected entities are equal to the These preset interconnected entities synthesize delay time values. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 · The method described in item 1 of the scope of patent application, wherein after obtaining the individualized capacitor value and the individualized resistance value, it further includes using the individualized capacitor value and the The resistance value is individualized, and a third physical synthesis step is performed to adjust one of the gated grids of the integrated circuit design. 3. The method as described in item 1 of the scope of patent application, in which the 20 paper sizes are affected by the Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 544736 6. The synthesis delay of the first circuit unit entity of the patent scope The parameters of the time value include a plurality of circuit unit parameters, and the circuit unit parameters are determined according to the integrated circuit design. 4. The method according to item 1 of the scope of patent application, wherein the first capacitance value is composed of a first capacitance value in a vertical direction and a first capacitance value in a horizontal direction. 5. The method according to item 1 of the scope of patent application, wherein the first resistance value is composed of a first vertical resistance value and a first horizontal resistance value. (Please read the notes on the back before filling out this page) One of the flat descriptions of the water description, and the electric description of the legal value of Fang Rong to the right, 1 vertical and vertical range of Fan Geli 'ο The specific value of the application is as follows: 6. Electricity and electricity are reported to one of the other parties, and one of the electric power is reported to the other party. For Fan Geli. Exclusive application is the group's application value such as resistance. 7. Electricity is printed to other parties.% The printed value of the deducted value printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is delayed. The report states that the yuan entry sheet 1 is the first time when the electricity is around, and the time is about one second. The special discussion is to refer to the Yuanshen order, such as walking. 8. Compared with the electricity, the value is 21. The paper size is applicable to Chinese national standards ( CNS) A4 size (210X297 mm) 544736 A8 六、申請專利範圍 9.如申請專利範圍第！項所述之方法，其中上述之第 -差值為該m路單^實體合成延遲時間值減去該些 電路單元參考延遲時間值所得之一第一絕對值。 10·如申請專利範圍第丨項所述之方法，其中上述之第 三比較步驟為該些第一内連線實體合成延遲時間值減去該 些内連線參考延遲時間值。 11 ·如申請專利範圍第1項所述之方法，其中上述之第 二差值為該些第一内連線實體合成延遲時間值減去該些内 連線參考延遲時間值所得之一第二絕對值。 12·—種積體電路設計中rC參數計算方法的應用方 法，至少包括： 提供該積體電路設計之一已定位閘階層網列； 對該已定位閘階層網列進行一繞線步驟，以得到一已 繞線設計； (請先閲讀背面之注意事項再填寫本頁) 訂· 經濟部智慧財產局員工消費合作社印製 繞少 已至 該值 到間 得時 及 以遲 以 ,¾; 驟考 值； 步參 間值 算該 時間 計中 遲時 一其 延遲 第， 考延 一值 參考 行間 元參 進時 單線 計遲 路連 設延 電内 線考 個個 繞參 數數 已一 複複 該之 對計： 設括 : 線包 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐） 544736 A B CD 六、申請專利範圍 以 驟 步 線 繞 成 合 體 實 一 行 進·’ 計 網設 層線 階繞 閘已 位成 定合 已體 該實 對一 到 得 得第 以該 ， 中 驟其 步 ’ 算值 計間 二時 第遲 一 延 行成 進合 計體 設實 線一 繞第 已一 成之 合 計 體設 實線 該繞 對已 該 到 中 其 值 間 時 遲 延 成 合 : 體 括實 包元 少單 至路 值電間一 時第 遲個 延數 成複 合 體 實 至 數 參 的 值 間 時 遲 延 成 合 體 實 元 單 路 電 1 第 些 ： 該括 響包 影少 影 中 其 值 間 時 遲 延 ; 成 數及合 參以體 元.，實 單值線 路容連 電電内 個 一 一 數第第 複一個 數 複 及 以 包 少 至 數 參 的 值 間 士&quot;r 日 遲 延 成 合 體 實 線 内 1 第 些 該 ： 響括 路 電 I 行 進 值 間 時 遲 延 及 成 以 合 ;.，體 值值實 阻容元 電電單 一 1 路 第第電 1 該 一 第 些 該 對 實 元 單 路 電 設 預及 個以 數 ·’ 複值 到容 得電 以化 &gt; »UJ. 另 驟個 步 一 整及 調值 值間 間時 時遲 遲延 延成 元合 單體 (請先閲讀背面之注意事項再填寫本頁) -、ν'ντ 經濟部智慧財產局員工消費合作社印製 線成 連合 内體 一 實 行線 進連 值内 間設 時預 遲個 延數 成複 合 到 體得 實以電 線，化 連驟別 内步個 一 整 一 第調及 些 值值 該間間 對時時 遲遲 .延延 值 阻 C R 中 tt 設 路 電 體 積 之 述 所 項 2 11 第 圍 範 利 專 請 申 如 23 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ABCD 544736 七、申請專利範圍 參數計算方法的應用方法，其中更包括提供該積體電路設 計之一閘階層網列，並對該閘階層網列進行一第一定位步 驟和一調整步驟，以得到該已定位閘階層網列。 1 4.如申請專利範圍第1 2項所述之積體電路設計中RC 參數計算方法的應用方法，其中更包括提供該積體電路設 計之一暫存器傳輸階層（RTL)設計碼，並對該暫存器傳輸階 層設計碼進行一第一實體合成步驟和一第二定位步驟，以 得到該已定位閘階層網列。 1 5 .如申請專利範圍第1 4項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第一實體合成步驟 和該第二定位步驟係藉該積體電路設計之一導線負載模型 以完成。 (請先閲讀背面之注意事項再填寫本頁) 如 請法位 申方定 算二 計第 數該 參和 專 的步 利應驟 範 用係 , 第 第法一 圍方藉 項 中 C R 中電 其 一 驟 步 。 計；f成 設合完 路體以 電實值 體一位 積第單 之之容 i4述電 所上阻 經濟部智慧財產局員工消費合作社印製 第法 圍方 範用 利應 專的 請去 如算 17計 數 參 迮已 計 亥 =0 設到 線得 繞以 已， 該驟 行 繞 之 述 所 項 2 1X ft 設 路 電 體 第 之 述 上 中 其 驟 步 算 _».Iar RC對 中為 電 取 擷 步 算 -&gt;6T 遲 延。 一 值 和間 驟時 步遲 容延 ί 考 阻參 該 之 •\ar 設 線 24 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ABCD 544736 々、申請專利範圍 1 8 .如申請專利範圍第1 2項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第二計算步驟為利 用一第二電阻電容單位值，對該實體合成已繞線設計進行 一實體合成擷取電阻電容步驟和一延遲計算步驟，以得到 該實體合成已繞線設計之該第一實體合成延遲時間值。 19.如申請專利範圍第12項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之繞線步驟為一虛擬 繞線步驟。 (請先閲讀背面之注意事項再填寫本頁) 圍 範 利 專 請 申 方 用 應 的 法 方。 如算驟 2 計步 數線 參繞 C R 中 設 路 電 體 積 之 述 所 項 2 1Χ 第 法 體 全 一 為 驟 步 線 繞 之 述 上 中 其 第法 圍方 々巳 々車 用 ί— 應 專纟* J t方。 如算驟 t+ 數線 參繞 之 述 所 項 2 C R 中 -tt 設 路 ^s 體 為 驟 步 線 繞 之 述 上 中 其 田 詳 經濟部智慧財產局員工消費合作社印製 第法 圍方 I 用 。 利應定 專的而 請法計 申方設 如算路 22計電 數體 參積 所 項 2 11 之 -&gt;ar 設 路 電 體 參 元 單 路 電 些 該 中 其 c¾ R ^ 中視 5 2 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ABCD 544736 七、申請專利範圍 23 .如申請專利範圍第1 2項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第一電容值是由一 第一垂直方向電容值和一第一水平方向電容值組成。 24.如申請專利範圍第12項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第一電阻值是由一 第一垂直方向電阻值和一第一水平方向電阻值組成。 2 5 .如申請專利範圍第1 2項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之個別化電容值是由 一個別化垂直方向電容值和一個別化水平方向電容值組 成0 (請先閱讀背面之注意事項再填寫本頁) 第法 圍方 範用 ί«應 專的 請Η t方 如算 26計 數 參 C R 中 &gt;ar 設 路 電 體 積 之 述 所 項 2 11 上 中 其 個 之 由 是 值 阻 電 化 組 值 阻 電 向 方 平 水 化 別 個 1 和 值 阻 電 向 方 直 垂 化 別 個 成 經濟部智慧財產局員工消費合作社印製 第法 圍方 範 用 利應 專的 請U 如算 2 計 數 '參 C R 中 .tt 設 路 電 體 積 之 述 所 項 2 I 為 間 時 遲 延 元 單 路 ^fril 之 述 上 中 其 路一 電第 些 一 該到 和得 值以 間 ’ 時驟 遲步 延較 成比 合 一 體第 實一 元行 單進 路值 電間 一 時 第遲 些延 步該考 整對參 調 元 值 單 括 包 少 至 驟 6 2 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736Sixth, the scope of patent application 9. If the scope of patent application is the first! The method according to the item, wherein the above-mentioned first difference is a first absolute value obtained by subtracting the reference delay time values of the circuit unit reference delay times from the m single entity synthesis delay time values. 10. The method as described in item 丨 of the patent application range, wherein the third comparison step is to synthesize the delay time values of the first interconnected entities by subtracting the reference delay time values of the interconnects. 11 · The method as described in item 1 of the scope of patent application, wherein the second difference is one of the synthetic delay time values of the first interconnected entities minus the reference delay time values of the interconnects. Absolute value. 12 · —An application method of the rC parameter calculation method in integrated circuit design includes at least: providing one of the positioned gate-level network columns of the integrated circuit design; performing a winding step on the positioned gate-level network columns to Get a winding design; (Please read the precautions on the back before filling out this page) Order · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The value of the step parameter is calculated as the delay in the time meter. The delay is the first. The value of the delay reference is based on the single-line meter delay when the line is connected. The number of winding parameters for the internal extension test has been repeated. Countermeasure: Include: The paper size of the wire package is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544736 AB CD. 6. The scope of the patent application is wound with a step line to form a solid line. The step-by-step gate has been set to form a fixed combination, and the actual pair must be obtained. The middle step is the first step. The calculation is delayed at 2 o'clock and the total delay is set. The total body is set to a solid line that should be delayed to the middle value of the time delay: the delay between the real package element and the road value is temporarily delayed for the first time into a complex real time delay. Chenghe solid single circuit power 1 The first: the delay in the value of the enclosing package shadow; the number and the combined parameters are the body element. The real single-value line is the first one in the electric power line. Counting and the value between the value and the value of the parameter are as follows: quot; r-day delay into a solid line within the solid line 1 The second should: ring road power I travel time delay between the combined value;., Volume value real resistance Yuandian Electric Single 1st Road No. 1 The first and first pairs of real Yuan single electric lines are pre-set and counted to the complex value to the capacity of electricity &gt; »UJ. Another step is to adjust and adjust the value From time to time, it has been delayed into a single unit (please read the precautions on the back before filling out this page)-, ν'ντ The Intellectual Property Bureau of the Ministry of Economic Affairs, the employee consumer cooperative printed a line into a joint inner body The value is set in advance and the delay number is compounded into a solid body. With the electric wire, the steps are adjusted one by one and the values are delayed. The delay value is CR. tt Set the item of electric power volume in the item 2 11 Fan Li specially requested to apply 23 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 544736 VII. Application method of parameter calculation method for patent scope It also includes providing a gate-level network column of the integrated circuit design, and performing a first positioning step and an adjustment step on the gate-level network column to obtain the positioned gate-level network column. 1 4. The method for applying the RC parameter calculation method in integrated circuit design as described in item 12 of the scope of patent application, which further includes providing a register transmission level (RTL) design code of one of the integrated circuit designs, and A first physical synthesis step and a second positioning step are performed on the register transmission hierarchy design code to obtain the positioned gate hierarchy network column. 15. The application method of the RC parameter calculation method in the integrated circuit design according to item 14 of the scope of the patent application, wherein the first physical synthesis step and the second positioning step are based on one of the integrated circuit designs. Wire load model to complete. (Please read the notes on the back before filling out this page) If you want the applicant to determine the number two steps in the application, please refer to CR Zhongdian in the first debit of the law. One step. F. Set up the completed road body with the capacity of one electric unit. I4 The electric power station is blocked by the Intellectual Property Bureau of the Ministry of Economic Affairs and the employee consumer co-operative society to print the law. Fan Fanli should specifically go. For example, if 17 counts have been counted, set 0 = set the line to be wound, the step of the winding is 2 1X ft, and the step is calculated in the above description. »» .Iar RC centering Calculate steps for electricity-> 6T delay. The value and time are delayed and the delay is delayed. Resistance of the problem. \ Ar Set the line 24. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 544736 々, the scope of patent application 18. The application method of the RC parameter calculation method in the integrated circuit design described in Item 12 of the scope of the patent application, wherein the second calculation step described above is to use a second resistance-capacitance unit value to perform a The physical composition captures the resistance and capacitance steps and a delay calculation step to obtain the first physical composition delay time value of the physical composition winding design. 19. The application method of the RC parameter calculation method in the integrated circuit design according to item 12 of the scope of the patent application, wherein the winding step is a virtual winding step. (Please read the notes on the back before filling out this page.) Fan Li specially asked the applicant to apply the French method. As described in step 2 above, the step counting line is connected to the CR in the description of the circuit volume. 2 1 × The first body of the body is the step line winding. Its method is used for vehicles. * J t square. For example, in the calculation of the t + number line, the item 2 C R -tt sets the road ^ s as the step line description. The details are printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. If the profit should be set, please ask the law application party to set up the 2nd of the 2nd of the calculation of the number of electrical and electronic parameters of the road 22, &gt; ar to set up the electrical parameters of the electric circuit of the single circuit. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 544736 VII. Patent application scope 23. Application method of RC parameter calculation method in integrated circuit design as described in item 12 of the patent application scope, where The first capacitance value is composed of a first capacitance value in the vertical direction and a first capacitance value in the horizontal direction. 24. The application method of the RC parameter calculation method in the integrated circuit design according to item 12 of the scope of the patent application, wherein the first resistance value is composed of a first vertical resistance value and a first horizontal resistance value . 25. The application method of the RC parameter calculation method in the integrated circuit design described in item 12 of the scope of the patent application, wherein the individualized capacitance value is composed of a specific vertical capacitance value and a specific horizontal capacitance value. The value composition is 0 (please read the precautions on the back before filling this page). Fang Fang Fan Yong uses «Should be specific, please t calculate the 26 counts, refer to the item 2 in CR &gt; ar set the circuit volume. 11 One of the reasons for the above is the value of the resistance resistance group to the Fang Ping hydration type 1 and the value resistance to the power leveling of the other. The Ministry of Economic Affairs Bureau of Intellectual Property Bureau employee consumer cooperatives printed the law of the law. Please count the 2 counts as described in the reference CR. Tt Set the item 2 in the circuit volume description as I. Time delay unit single circuit ^ fril In the description above, the circuit should be called first and the value should be between the sum and the value. '' The time delay is delayed compared to the ratio of the first real unit of a single line, and the time delay of the current unit is delayed for a short time. Applicable to China National Standard (CNS) A4 specification (210X297 mm) 544736 A B CD 中清專利範圍 差值； 藉調整該第一電容值，以減少該第-差值，益得到-第二電容值； 對該實體合成已繞線設計進行一第三實體合成步驟， ^中該第三實體合成步驟係利用該第二電容值和該電阻電 容單位值，以得到該實體合成已繞線設計之一第二實體合 成延遲時間值’其中該第二實體合成延遲時間值至少包 括： 複數個第二電路單元實體合成延遲時間值；以及 複數個第二内連線實體合成延遲時間值； 對該些第二電路單元實體合成延遲時間值和該些電路 單元參考延遲時間值進行一第二比較步驟，當該些第二電 路單疋實體合成延遲時間值不等於該些電路單元參考延遲 時間值時，藉調整該第二電容值，以得到該些預設電路單 元實體合成延遲時間值及該個別化電容值，其中該些預設 電路單元實體合成延遲時間值等於該些電路單元參考延遲 時間值；以及 (請先閲讀背面之注意事項再填寫本頁) •裝· -、τ % 經濟部智慧財產局員工消費合作社印製 路電時第體 電二遲些實 些第延該元 該些考及單 和該參以路 值當元，電 間，單值設 時驟路容預 遲步電電些 延較些化該 成比該別為 合二於個值 體第等該間 實該值為時 元行間值遲 單進時容延 路值遲電成 電間延二合 。 二時成第體值 第遲合該實間 些延體則元時 該考實，單遲 對參元時路延 元單值電成 單路間二合 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 A B CDAB CD Zhongqing patent range difference; adjust the first capacitor value to reduce the-difference value, and get-the second capacitor value; perform a third entity synthesis step on the physical synthesis wound design, ^ The third entity synthesis step uses the second capacitance value and the resistance-capacitance unit value to obtain a second entity synthesis delay time value of the physical synthesis wound design, where the second entity synthesis delay time value is at least The method includes: a plurality of second circuit unit entity synthetic delay time values; and a plurality of second interconnect unit physical synthesis delay time values; performing the second circuit unit entity synthesis delay time value and the circuit unit reference delay time values. A second comparison step, when the physical synthesis delay time values of the second circuit units are not equal to the reference delay time values of the circuit units, the second capacitor value is adjusted to obtain the physical synthesis delay times of the predetermined circuit units. The time value and the individualized capacitor value, wherein the preset delay time values of the predetermined circuit unit entities are equal to the reference delay times of the circuit units Time value; and (please read the precautions on the back before filling this page) • Installation ·-, τ% When the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the road electricity, the body electricity will be delayed later. Some considerations and the reference value of the road value yuan, electricity, single value set when the sudden path capacity is delayed, the electricity is delayed, and the ratio is equal to the value of the unit. The value is the time interval line value is delayed, the capacity delay path value is delayed, and the electricity delay is combined into the electricity delay. The second time is the body value and the second time is the real time. The extended time is the time of the real time test. The single time delay is used for the reference value of the road and the time value of the single yuan. The paper size applies the Chinese National Standard (CNS). A4 size (210X297 mm) 544736 AB CD 經濟部智慧財產局員工消費合作社印製 申請專利範圍 2 8.如申請專利範圍第27項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第二電容值是由一 第二垂直方向電容值和一第二水平方向電容值組成。 29.如申請專利範圍第27項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第一比較步驟為該 些第一電路單元實體合成延遲時間值減去該些電路單元參 考延遲時間值。 3 0.如申請專利範圍第27項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第一差值為該些第 一電路單元實體合成延遲時間值減去該些電路單元參考延 遲時間值所得之一第一絕對值。 3 1 .如申請專利範圍第1 2項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之内連線延遲時間值 調整步驟至少包括： 對該些第一内連線實體合成延遲時間值和該些内連線 參考延遲時間值進行一第三比較步驟，以得到一第二差 值； 利用該個別化電容值並調整該第一電阻值，以減少該 第二差值，並得到一第二電阻值； (請先閲讀背面之注意事項再填寫本頁) •訂· % 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 544736 A8 B8 C8 D8Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs for the application of patent scope 2 8. The application method of the RC parameter calculation method in the integrated circuit design described in item 27 of the scope of patent application, wherein the above-mentioned second capacitance value is Two vertical capacitance values and a second horizontal capacitance value are composed. 29. The application method of the RC parameter calculation method in the integrated circuit design as described in item 27 of the scope of the patent application, wherein the first comparison step described above is the synthesis delay time of the first circuit unit entities minus the circuit units Reference delay time value. 3 0. The application method of the RC parameter calculation method in the integrated circuit design as described in item 27 of the scope of the patent application, wherein the first difference is the delay time of the physical synthesis delay time of the first circuit units minus the circuits. One of the first absolute values obtained by the unit referring to the delay time value. 31. The method for applying the RC parameter calculation method in the integrated circuit design described in item 12 of the scope of the patent application, wherein the above-mentioned step of adjusting the interconnect delay time value includes at least: the first interconnect entities Perform a third comparison step between the synthesized delay time value and the reference delay time values to obtain a second difference value; use the individualized capacitor value and adjust the first resistance value to reduce the second difference value And get a second resistance value; (Please read the precautions on the back before filling this page) • Order ·% This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 544736 A8 B8 C8 D8 、申請專利範圍 對 其中該 電容值 值，其 對 參考延 實體合 時，藉 成延遲 體合成 對 參考延 實體合 則該第 實體合 間值。 第二二：已繞線設計進行一第四實體合成步驟， ，以得：：成步驟係利用該第二電阻值、該個別化 中該第-in線設計之-第三實體合成延遲時間 ^ 一實體合成延遲時間值至少包括： ^數個第二電路單元實體合成延遲時間值；以及 A :數個第三内連線實體合成延遲時間值； :二第二内連線實體合成延遲時間值 =間值進行-第四比較步驟，當該些第I: 成延遲時間值不等於該歧連 一内運線參考延遲時間值 時f二一電阻值，以得到該些預設内連線實體合 及該個別化電阻值，其中該些預設内連線實 =:間值等於該些内連線參考延遲時間值；以及 (請先閲讀背面之注意事項再場寫本頁} .訂· 經濟部智慧財產局員工消費合作社印製 專 請 申 如 中 -tt 設路 ： ^¾ -L 電駕值 體二阻 囔第電 述述方 所上平 項中水 1其二 3 ，第 第法一 和 範用值 禾應阻 的電 法向 方方 算直 計垂 數二 參第 C R 由 是 。 值成 阻，沮 29 本紙張尺度適用中國國家標準(CNS)A1 2 3 4規格(210X297公釐） 1 I;門：内連線實體合成延遲時間值和該些内連線 、B進行該第四比較步驟’當該些第三内連線 2 成延遲時間值等於該些内連線參考延料間值時，， 3 二電阻值為該個別化電阻值’以及該些第三内連線 4 成L遲時間值等於該些預設内連線實體合成延遲時 ABCD 544736 々、申請專利範圍 3 3 .如申請專利範圍第3 1項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第三比較步驟為該 些第一内連線實體合成延遲時間值減去該些内連線參考延 遲時間值。 3 4.如申請專利範圍第3 1項所述之積體電路設計中RC 參數計算方法的應用方法，其中上述之第二差值為該些該 些第一内連線實體合成延遲時間值減去該些内連線參考延 遲時間值所得之一第二絕對值。 3 5 .如申請專利範圍第1 2項所述之積體電路設計中RC 參數計算方法的應用方法，其中於得到該個別化電容值和 該個別化電阻值後，更包括利用該個別化電容值和該個別 化電阻值，進行一第五實體合成步驟，以調整該積體電路 設計之該已定位閘階層網列。 (請先閲讀背面之注意事項再填寫本頁) -、v&quot; % 經濟部智慧財產局員工消費合作社印製The scope of the patent application refers to the value of the capacitor, which is synchronized with the reference delay entity, and the delay value is used to synthesize the reference delay entity. The second step is to perform a fourth physical synthesis step for the winding design to obtain: the forming step is to use the second resistance value and the third physical synthesis delay time of the -in line design in the individualization ^ A physical composite delay time value includes at least: ^ several second circuit unit physical composite delay time values; and A: several third interconnected physical composite delay time values;: two second interconnected physical composite delay time values = Interval value-Fourth comparison step, when the first: delay time value is not equal to the reference delay time value of the inter-line transport line, the f-21 resistance value is obtained to obtain the preset interconnected entities. Combine the individualized resistance values, where the preset interconnections are equal to =: the value is equal to the reference delay time values of the interconnections; and (Please read the precautions on the back before writing this page}. Order · The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a special application for application such as -tt to set up the road: ^ ¾ -L The second value of the electric driving value body 囔 中 项 中 中 中 中 其 其 其 其 其 其 其 其 其 3 3 Yihe Fan uses the electric method to resist Calculate the vertical number of the second reference CR by Yes. The value becomes the resistance, the frustration 29 This paper size applies the Chinese National Standard (CNS) A1 2 3 4 specifications (210X297 mm) 1 I; gate: delay time for the synthesis of interconnected entities Value and the interconnects, and B performs the fourth comparison step. When the delay time values of the third interconnects are equal to the values of the reference extensions of the interconnects, the two resistance values are the individual values. The resistance value and the delay time of the third interconnects are equal to the delay time of the synthesis of the preset interconnect entities. ABCD 544736 申请, the scope of patent applications 3 3. As described in item 31 of the scope of patent applications The application method of the RC parameter calculation method in the integrated circuit design, wherein the third comparison step is the synthesis delay time values of the first interconnected entities minus the reference delay time values of the interconnects. The application method of the RC parameter calculation method in the integrated circuit design described in item 31 of the scope of the patent application, wherein the above-mentioned second difference value is a value of the synthesis delay time of the first interconnected entities minus the interconnects Line reference delay time The second absolute value. 3 5. The application method of the RC parameter calculation method in the integrated circuit design described in Item 12 of the scope of patent application, wherein after obtaining the individualized capacitor value and the individualized resistance value, the method further includes: Using the individualized capacitor value and the individualized resistance value, a fifth physical synthesis step is performed to adjust the positioned gate-level network column of the integrated circuit design. (Please read the precautions on the back before filling this page) -, V &quot;% Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)This paper size applies to China National Standard (CNS) A4 (210X 297 mm)