TW543125B - Fan-out type wafer level package and the method of the same - Google Patents

Fan-out type wafer level package and the method of the same Download PDF

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Publication number
TW543125B
TW543125B TW91110175A TW91110175A TW543125B TW 543125 B TW543125 B TW 543125B TW 91110175 A TW91110175 A TW 91110175A TW 91110175 A TW91110175 A TW 91110175A TW 543125 B TW543125 B TW 543125B
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Taiwan
Prior art keywords
conductive
substrate
patent application
type package
exposed
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TW91110175A
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Chinese (zh)
Inventor
Wen-Bin Sun
Ming-Hui Lin
Wen-Pin Yang
Wen-Kun Yang
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Advanced Chip Eng Tech Inc
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Publication of TW543125B publication Critical patent/TW543125B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention discloses a fan-out type package that includes a carrier having through holes formed therein. A conductive pattern is formed on the surface of the through holes and a portion of the surface of the carrier. A dielectric layer is formed on the carrier's surface to expose a portion of the conductive patter. A chip or die is formed on the exposed conductive pattern by using first conductive bump. A moulding material is encapsulated the chip and the dielectric layer. A second conductive bump is formed on the lower surface of the carrier and aligned to the holes.

Description

543125 五、發明說明（1) 發明領域： 本發明與一種封裝結構有關’特別是有關於一種擴散 式（fan-out type)晶圓型態（wafer-level)封裝辞構以及 其製程。 發明背景： 在極大型積體電路（ULSI)趨勢中，半導體元件的尺寸 不斷地縮小，用以不斷地提昇晶圓上元件之積集度。隨著 電子元件尺寸的縮小化後，在積體電路的製造過程上出現 許多新挑戰。此外，由於電腦以及通訊技術之蓬勃發展， 伴隨需要的是更多不同種類與應用之電子元件。例^，由 語音操作之電腦界面或其他通訊之界面均需要許多之記情 元件以及不同類型之半導體元件。是故，積體電路之趨‘ 仍然會朝向高積集度發展。然而，近幾年來高穷 =件發展階段早已進入次微米（submicr〇n )之技術範一 半導體晶片通常個別地封於塑膠或陶瓷材料之 之内。封裝體之結構必須可以保護晶片以及、^一 程中所產生之熱散出，傳統之封裝亦被用來m過 ，式時之用。料，隨著半導體技術之快速以曰，曰= 口口在輕薄短小、多功能速度快之趨勢的推動下， 的I /〇數目不但越來越多密度亦越來越高，使得 體 的引腳數亦隨之越來越多，4度的要求亦越來越快“導件致543125 V. Description of the invention (1) Field of the invention: The present invention is related to a packaging structure ', and particularly to a fan-out type wafer-level packaging morphology and its manufacturing process. Background of the Invention: In the ultra-large integrated circuit (ULSI) trend, the size of semiconductor components is continuously shrinking to continuously increase the accumulation of components on wafers. As electronic components have become smaller, many new challenges have arisen in the fabrication of integrated circuits. In addition, due to the rapid development of computers and communication technology, more and more electronic components of different types and applications are accompanying. For example, a voice-operated computer interface or other communication interface requires many memory components and different types of semiconductor components. Because of this, the trend of integrated circuits will still develop towards a high degree of integration. However, in recent years, the high-poor development stage has already entered the sub-micron technology. Semiconductor wafers are usually individually enclosed in plastic or ceramic materials. The structure of the package must be able to protect the chip and the heat generated in the process. The traditional package is also used for m-type, and is used for the formula. It is expected that with the rapid advancement of semiconductor technology, the number of I / 〇 will not only be more and more dense but also higher and higher due to the trend of light, thin, short, and multifunctional. The number of pins is increasing, and the requirement of 4 degrees is getting faster and faster.

第5頁 543125 五、發明說明（2) 元件耗功率越來越大，所以增進 ^ f要。目前，封裝也越做越小以符^目f-效果’則曰趨 是，負責I/O的引腳為球狀較導線。::裴技術的特點 距離紐且不易受損變形，衣几件之細長％腳 速度快’可符合目前及未來數=輸距離短 之/數量I/O之封裝伴隨球矩 ^ 。換言 grid array;以下簡稱BGA封裝）技術之技術（baU 因此’ iC半導體承載的封裝趨向支於^展而有所突破， 術（BGA) 1GA構裝的特點是，負；矩陣排列封裝技 線架構裝元件之細長引腳距離短且0的引腳為球狀較導 元件之電性的傳輸距離短速度快，义損f形’其封裝 系統速度的需求。 付口目刚及未來數位 目W已經有許多不同型態 種型態之封裝，絕大部分之封心：體封裝，不論是哪-在進行封裝。然而，晶圓型態為個體之後 勢，其為反其道而行係將晶粒於種趨 割。可以節省製程時間以及相對之㈣褒好後再切 的引腳配置之* < , ^ t之成本。此外，基於I /0 1 本發明之動機係提出一種擴散式 n type)晶圓型態（wafe卜level)封裝/、 發明目的及概述： 第6頁 543125 五、發明說明（3) ^啦明之目的為提供一種晶圓型態 裝結構。Page 5 543125 V. Description of the invention (2) The power consumption of the component is getting larger and larger, so it is necessary to increase it. At present, the packages are getting smaller and smaller to meet the f-effects. The trend is that the pins responsible for I / O are spherical and more conductive. :: Features of Pei technology The distance between the buttons is not easy to be deformed. The slender% feet of the clothes are fast and can meet the current and future numbers = short transmission distance / quantity I / O package with ball moment ^. In other words, grid array (hereinafter referred to as BGA package) technology (baU, so 'iC semiconductor-borne packaging tends to support and break through, and the characteristics of BGA 1GA architecture are negative; matrix array packaging technology line architecture The length of the slender pin of the component is short and the pin of 0 is spherical. The electrical transmission distance of the conductive element is short and the speed is short, which harms the f-shape's demand for the speed of its packaging system. Fu Kougang and future digital W There have been many different types of packaging, most of which are sealed: body packaging, no matter where-packaging is in progress. However, the wafer type is an individual behind, which is the opposite The die is cutting. It can save the process time and the cost of the pin configuration * < ^ t after cutting. In addition, based on I / 0 1 the motivation of the present invention is to propose a diffusion type n type) Wafer type package /, the purpose and summary of the invention: Page 6 543125 V. Description of the invention (3) The purpose of Laming is to provide a wafer type package structure.

本毛明之另一目的為提供—M ^ JtJr 4*' -P , X . 禋擴散式（fan-out type) 曰曰 圓i A(wafer—level)封裝結構及其製程。 本發 :晶圓型態封裝：以利於晶： = = = =測試 試 之測 本發明之擴散式晶圓型態 有穿孔於其中（例如_ .載體，其中具 下之罩幕層）；導電層圖幸，二:佈/、上利用微影技術留 於部分之載體上表面a;'介電刀於上述穿孔表面以及位 曝露部分之上述導以目&上表面且 接於上述被曝露之導^芦円，精由第一導電凸塊連 體，覆蓋於上述之晶ϊ 形成電形連m谬 塊，配置於上述載第二導電凸 处义r衣面且對位於上述之穿孔。 一種擴散式晶圓型態封裝之 後塗佈罩幕層（載體）於上、 $棱仏一基板，之 曝露部分該基，以及形二圖案Μ幕層：以 電圖案之上並曝露部=上圖案於罩幕層、導 I刀之上述導電圖案，以第一導電凸塊Another purpose of this Maoming is to provide —M ^ JtJr 4 * '-P, X. Fan-out type (round-A) package structure and its manufacturing process. The hair: Wafer type package: for the benefit of the crystal: = = = = test test The diffusion wafer type of the present invention has a hole in it (for example, a carrier with a cover layer under it); conductive Fortunately, two: cloth /, using the lithography technology to leave part of the upper surface of the carrier a; 'dielectric knife on the above perforated surface and the exposed part of the above guide & upper surface and connected to the above exposed The guide 円 円 is composed of a first conductive bump conjoined body, covering the above crystal ridge to form an electrically shaped continuous m block, which is arranged on the upper surface of the second conductive protrusion, and is opposite to the above-mentioned perforation. A diffusion-type wafer-type package is coated with a cover curtain layer (carrier) on the substrate, the exposed portion of the substrate, and the shape 2 pattern M curtain layer: on the electrical pattern and the exposed portion = top The above conductive pattern is patterned on the cover layer and the I-blade, with a first conductive bump

543125543125

=日日^連接於上述被曝露之導電層 接。隨之形成封裝膠體於上 成電形連 接續形成第二導雷η掄定你私、士 g 再去除上述基板。 夺^凸塊疋位於被曝露出夕μ、+、增； 及切割分離封裝H ^電圖案， 裝。 〜风上述擴散式晶圓型態封 發明詳細說明： J:明為，露一種晶圓型態封裝以及製作晶 =定第所r;;實r只做一說明非用 ^ ^ . y τ 多閱第一圖，楗供一基板（載體）2，以較 質貝二二^ 3可以採用玻璃、石英、陶瓷或均等功能之材 ^一卓，層4塗佈於上述基板2之上。就本實施例而言可 或二，，賞罩幕材質（solder mask material)作為一範例 \^樹脂或二乙烯基矽氧烷雙苯並環丁烯樹脂或聚亞醯 Μ脂。之後利用圖案化製程例如微影製程將上述之罩幕 層4圖案化用以定義出預設之圖案。可利用濺鍍形成底層 再利用光阻定義出特定區域，使用電鍍技術形成導電層6 於被光阻所曝露之區域。隨後去除光阻並蝕刻底層，如第 二圖所示。 參閱第三圖至第五圖，形成一介電層圖案8於上述罩幕層4 圖案以及導電層6之上，一般可以採用微影或印刷製程達 五、發明說明（5) 到上述目的， 於後續之製種。）丨電層圖案8將部分之導電層6曝露出以利 於上述被曝露出，，利用第導電凸塊1 〇將晶片1 2連接 電性連接。隨 V電層6區域之上方，並與導電層6形成 於基板2之上诉承如第五圖所示，塗佈封裝膠體或化合物1 4 在。 ” i蓋整個晶片1 2，標示1 6係為切割線所 下一步驟則將破 學蝕刻方式或杯/土板去除，可以採用物理研磨或是化 基於上述之步驟可已知之技術達到’參閱第六圖。因此， 露以形成電性接觸：：罩幕：4圖案下側之導電層6將被曝 放導體球之區域。兴1杏=電路被暴露之區域為預定來置 層6可以做為輪出二之貝二而/二上述曝露之導電電路 裝（BGA)做為輸出^曝入路//電層6用U形成球矩陣排列封 =用重新配置於罩幕層表 上成或合金，較佳為利用 排列）將部分第-導電凸塊之;塊（第二球矩陣 凸塊使用-錫膏罩幕遮住電路：：擴2封裝。上述導電 電路特定之區域，—印刷樂央任、，彖且錫貧罩幕暴露 上】Si;=上述特定之區域 凸塊也可以採用錫凸塊、金凸合 第9頁 543125 五、發明說明（6) =然後：用熱流過程將錫膏變成 利用已知之製程溫度，半導體晶^流之溫度可以 錫球可以利用已知的BGA技術加以轉合於上述之錫球， 為一陣列排列，錫球連接上述之踗卞，較佳之錫球分佈 因而建立電性連接。 之後’將上述封裝體翻轉，—膠帶⑼ 1 4表面’以利於切割後封裝單體排 ^敕附於封裝膝體 後封裝體散置。可以利用習知技術之貼性以避免切割 一般而言係採用藍膠帶（Mue t 技術加以附著， 割技術以上述標示16之切割線所 ^利用 剝除藍膠帶20以分離個別之封裝U進行切割，再 第九圖’基於本發明係可以應用於晶圓=== 於將端點擴散配合實際之應用因此本、^ 1 % 值付庄思的疋，在切割之前可以進行S κ夕、目 =傳送至晶圓型態測試裝置中進行晶圓型;二如 朋應測試（burn-in)，完成晶圓型態測示之後，然 ^ 切割用以分離個別之晶粒。切割過程主要沿著切、割道切^ 而得到擴散式晶片尺寸封裝（chip scale package . CSPj。上述擴散式晶圓型態封裝包含：_載體（錫膏罩幕 材質；solder mask material)，其中具有穿孔於其中. 導電層圖案’分佈於上述穿孔表面以及位於部分之載體上 表面；介電層’配置於該載體之上表面且曝露部分之上述 導電層圖案；晶片，藉由第一導電凸塊連接於上^被曝露 543125 五、發明說明（7) 之導電層圖案用以形成電形連接；封裝膠體，覆蓋於上述 之晶片以及上述介電層之上；第二導電凸塊，配置於上述 載體之下表面且對位於上述之穿孔。 本發明以較佳實施例說明如上，而熟悉此領域技藝，在不 脫離本發明之精神範圍内，當可作些許更動潤飾，其專利 保護範圍更當視後附之申請專利範圍及其等同領域而定。= Day to Day ^ Connect to the exposed conductive layer. Then, the encapsulation gel is formed on the electrical connection, and then a second lead η is formed, and then the substrate is removed. The bumps 疋 are located at the exposed positions μ, +, and Z; and the cut and package H ^ electrical patterns are assembled. ~ Wind The above-mentioned diffusion type wafer type sealing invention is explained in detail: J: Mingwei, revealing a wafer type package and making crystals = fixed first place; real r is only used to explain non-use ^ ^. Y τ more As shown in the first figure, a substrate (carrier) 2 is provided, and glass, quartz, ceramic, or an equivalent material can be used for the better quality. The layer 4 is coated on the above substrate 2. In this embodiment, it may be two or more. As an example, a mask material is a resin or a divinylsiloxane bisbenzocyclobutene resin or a polyurethane resin. Then, the above-mentioned mask layer 4 is patterned by a patterning process such as a lithography process to define a preset pattern. The bottom layer can be formed by sputtering, and a specific area is defined by a photoresist, and a conductive layer 6 is formed using an electroplating technique on the area exposed by the photoresist. The photoresist is then removed and the bottom layer is etched, as shown in the second figure. Referring to the third to fifth figures, a dielectric layer pattern 8 is formed on the mask layer 4 pattern and the conductive layer 6 described above. Generally, a lithography or printing process can be used. V. Description of the invention (5) to the above purpose. For subsequent seed production. ) 丨 The electrical layer pattern 8 exposes a part of the conductive layer 6 to facilitate the above exposure. The chip 12 is electrically connected with the second conductive bump 10. As shown in the fifth figure, the appeal of the formation of the conductive layer 6 above the region of the V electrical layer 6 and the conductive layer 6 on the substrate 2 is coated with a compound or compound 1 4. ”I cover the entire wafer 12 and mark 16 as the cutting line. The next step is to remove the etch method or the cup / soil plate, which can be physically ground or chemically based on known techniques based on the above steps. Figure 6. Therefore, exposed to form electrical contact :: mask: 4 area where the conductive layer 6 on the lower side of the pattern will be exposed to the conductive ball. Xing 1 apricot = the area where the circuit is exposed is predetermined. Layer 6 can be made. For the second and second rounds, the second exposed conductive circuit device (BGA) is used as the output. ^ The exposure path // the electrical layer 6 is formed by a U-shaped ball matrix seal. = It is re-arranged on the surface of the cover layer to form or Alloy, preferably using an arrangement) to partially part of the first conductive bump; block (second ball matrix bump use-solder paste mask to cover the circuit :: expand 2 package. Specific area of the above conductive circuit, printed music Yang Ren, Xi, and the tin-poor mask is exposed on the surface] Si; = The bumps in the above specific areas can also be tin bumps, gold bumps. Page 9 543125 V. Description of the invention (6) = Then: The solder paste is heat-processed. Using a known process temperature, the temperature of the semiconductor crystal stream can be solder balls It can be transferred to the above-mentioned solder balls using known BGA technology. The solder balls are arranged in an array, and the solder balls are connected to the ridges. The better solder ball distribution thus establishes an electrical connection. ⑼ 1 4 surface to facilitate the packaging of individual cells after cutting ^ 敕 attached to the packaging knee after the package is scattered. You can use the familiarity of the technology to avoid cutting. Generally speaking, blue tape (Mue t technology is used to attach The cutting technology uses the cutting line labeled 16 above to remove the blue tape 20 to separate individual packages U for cutting, and then the ninth picture 'based on the present invention can be applied to the wafer === the end diffusion For practical applications, the value of ^ 1% is worth paying to Zhuang Si. Before cutting, S can be carried out, and the screen can be transferred to the wafer type test device for wafer type. Second, the burn-in ), After the wafer type measurement is completed, then ^ cutting is used to separate individual dies. The dicing process is mainly cut along the cutting and cutting lines ^ to obtain a diffusion chip scale package (CSPj. The above diffusion type Wafer Type Seal Including: _ carrier (solder mask material; solder mask material), which has perforations therein. The conductive layer pattern is 'distributed on the perforated surface and part of the upper surface of the carrier; the dielectric layer' is disposed on the upper surface of the carrier And the above-mentioned conductive layer pattern of the exposed part; the wafer is connected to the upper part through the first conductive bump; 543125 is exposed. 5. The conductive layer pattern of the invention description (7) is used to form an electrical connection; the encapsulation gel covers the above Above the wafer and the above-mentioned dielectric layer; the second conductive bump is arranged on the lower surface of the above-mentioned carrier and opposite to the above-mentioned perforation. The present invention has been described above with reference to the preferred embodiment, and is familiar with the art in this field without departing from the present invention. Within the scope of the spirit, it can be modified slightly, and the scope of its patent protection depends on the scope of the attached patent application and its equivalent.

第11頁 543125 圖式簡單說明 本發明的較佳實施例將於往後之說明文字中輔以下列圖形 做更詳細的闡述： 第一圖一所顯示為本發明形成罩幕層於基板上之截面圖。 第二圖所顯示為本發明形成導電層之截面圖。 第三圖所顯示為本發明形成介電層之截面圖。 第四圖所顯示接合晶片之截面圖。 第五圖所顯示為本發明塗佈封裝膠體之截面圖。 第六圖所顯示為本發明去除基板之截面圖。 第七圖所顯示為本發明植入導電凸塊之截面圖。Page 543125 Schematic illustration of the preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows the formation of the mask layer on the substrate Sectional view. The second figure shows a cross-sectional view of the conductive layer formed in the present invention. The third figure shows a cross-sectional view of a dielectric layer formed in the present invention. A cross-sectional view of the bonded wafer is shown in the fourth figure. The fifth figure shows a cross-sectional view of the coated encapsulant of the present invention. The sixth figure shows a cross-sectional view of the substrate removed in the present invention. The seventh figure shows a cross-sectional view of the implanted conductive bump of the present invention.

第八圖所顯示為本發明切割單體之截面圖。 第九圖所顯示為本發明切割後封裝單體之截面圖。The eighth figure is a cross-sectional view of a cutting unit according to the present invention. The ninth figure is a cross-sectional view of the packaged monomer after cutting according to the present invention.

元件符號對照 基板2 罩幕層4 導電層6 介電層圖案8 第一導電凸塊10 晶片1 2 封裝膠體1 4 切割線1 6 第二導電凸塊1 8 膠帶20Comparison of component symbols Substrate 2 Cover layer 4 Conductive layer 6 Dielectric layer pattern 8 First conductive bump 10 Wafer 1 2 Encapsulant 1 4 Cutting line 1 6 Second conductive bump 1 8 Tape 20

第12頁Page 12

Claims (1)

^^125^^ 125 • 種擴散式晶圓型態封裝包含·· 一載體，其中具有穿孔於其中； 導電層圖案，分佈於上述穿孔 體上表面； & 面 以及位於部分 介電層 電層圖案； 配置於該載體之上表 面且曝露部分之上 曰^，藉由第—導電凸塊連 圖案用以形成電形連接； 4饭曝路之導 封裝膠體，覆蓋於上述之晶 篦-道日巧以及上述介電声之 第一 V電凸塊，配置於上述載 电盾之 述之穿孔。 戟媸之下表面且對位 2·如申睛專利範圍第1項之擴耑 材暫勺人雜烏fu t放式日日圓型態封裝， 材貝包含錫貧罩幕材料或環 衣 並環丁烯樹脂或聚亞醯胺谢&二，曰或一乙烯遵 載體 雙苯並環丁烯樹脂或聚亞醯胺 3第如：：專利範圍第1項之擴散式晶 弟一導電凸塊包含錫球或金凸塊或其合^•全。封凌， 4·如申請專利範圍第1項之擴耑★、曰 5 · 一種擴散式晶圓型態封裝之制# 裝之製程包含： 衣耘，該擴散式晶 之載 述導 電層 上； 於上 ?該 氧烷 r該 7該 態封 543125 :、申請專利範圍 提供一基板； '塗佈罩幕層於上述基板之上； 圖案化該罩幕層用以曝露部分該基板； 形成導電圖案於部分罩幕層圖案上以及該 上； 曝輅之基板 形成介電層圖案於該罩幕層、該導電圖 部分之上述導電圖案； 〃上並曝露 電Γί將晶片連接於上述被曝露之導 案用以形成電形連接； 形成封裝膠體於上述晶片之上； 剝除上述基板； ， 形成第二導電凸塊定 電層圖 及 裝 位於被曝露出之上述導電圖案; 切割分離封裝單體， 用以形成上述擴散式晶 圓型態封 6·如申請專利範圍第5項之擴 其中該基板包含破螭。 ’、月式晶圓型態封裝之製程， 7·如申請專利範圍第5項之擴 。 其中該基板包含陶瓷。 、月式晶圓型態封裝之製程， 之製程， 8其二專Λ?/。5項之擴散式晶圓型態封裝 543125 六、申請專利範圍 · 9 ·如申請專利範圍第5項之擴散式晶圓型態封裝之製程， 其中該罩幕層材質包含錫膏罩幕材料所組成。 / I 0.如申請專利範圍第5項之擴散式晶圓型態封裝之製程， 其中該第一導電凸塊包含錫球或金凸塊或其合金。 II ·如申請專利範圍第5項之擴散式晶圓型態封裝之製程， 其中該第二導電凸塊包含錫球或金凸塊或其合金。• A diffused wafer type package includes a carrier with perforations therein; a conductive layer pattern distributed on the upper surface of the perforated body; a & surface and a portion of the dielectric layer electrical layer pattern; disposed on the carrier On the upper surface and the exposed part, ^, the first conductive bump is connected to the pattern to form an electrical connection; 4 the conductive packaging gel of the exposed circuit is covered with the above-mentioned crystalline silicon-Dao Riqiao and the above dielectric Acoustic first V electric bumps are arranged in the perforations described in the aforementioned electric shield. The lower surface of the halberd owl and the counterpoint 2 · The extension of the material in the scope of the patent application No. 1 of the patent application is temporarily packaged in a Japanese yen type package. The material contains tin curtain material or a ring and a ring. Butene resin or polyimide resin & two or one ethylene conforming carrier bisbenzocyclobutene resin or polyimide 3 Example: Diffusion type crystal brother conductive bump of item 1 of patent scope Contains solder balls or gold bumps or a combination of them. Feng Ling, 4 · If the scope of the application for the scope of the patent application is expanded to 1 or 5; a manufacturing method of a diffused wafer type package # The manufacturing process includes: clothing, the conductive layer on the diffused crystal; On the oxane r the 7 the state seal 543125 :, a substrate is provided to apply for a patent; 'coating a curtain layer on the substrate; patterning the mask layer to expose a part of the substrate; forming a conductive pattern On the part of the mask layer pattern and above; the exposed substrate forms a dielectric layer pattern on the mask layer and the above conductive pattern of the conductive pattern part; and on the exposed substrate is exposed to electricity to connect the chip to the exposed conductor. To form an electrical connection; to form an encapsulation gel on the wafer; to strip the substrate; to form a second conductive bump fixed layer pattern and to place the above-mentioned conductive pattern on the exposed substrate; In order to form the above-mentioned diffusion-type wafer, the substrate 6 may be broken as described in the fifth item of the patent application. ′ 、 The manufacturing process of the monthly wafer type package. 7. If the scope of the patent application is expanded in item 5. Wherein the substrate comprises ceramic. 2. The manufacturing process of the monthly wafer type package. Diffusion wafer type package of 5 items 543125 VI. Patent application scope · 9 · If the process of diffusion type wafer type package of item 5 of the patent application process, the material of the mask layer includes the solder paste mask material composition. / I 0. According to the manufacturing process of the diffused wafer type package in item 5 of the patent application scope, wherein the first conductive bump includes a solder ball or a gold bump or an alloy thereof. II. The process of diffusion wafer type package according to item 5 of the patent application process, wherein the second conductive bump comprises a solder ball or a gold bump or an alloy thereof. 第15頁Page 15
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196408B2 (en) 2003-12-03 2007-03-27 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US7489037B2 (en) 2005-04-11 2009-02-10 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
US7514767B2 (en) 2003-12-03 2009-04-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US8895368B2 (en) 2013-04-25 2014-11-25 Chipmos Technologies Inc. Method for manufacturing chip package structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196408B2 (en) 2003-12-03 2007-03-27 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US7459781B2 (en) 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
US7514767B2 (en) 2003-12-03 2009-04-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7557437B2 (en) 2003-12-03 2009-07-07 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7667318B2 (en) 2003-12-03 2010-02-23 Advanced Chip Engineering Technology Inc. Fan out type wafer level package structure and method of the same
US7489037B2 (en) 2005-04-11 2009-02-10 Siliconware Precision Industries Co., Ltd. Semiconductor device and fabrication method thereof
US8895368B2 (en) 2013-04-25 2014-11-25 Chipmos Technologies Inc. Method for manufacturing chip package structure

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