TW538594B - Clock switching architecture and clock switching method thereof - Google Patents
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538594 4226twf.doc/005 A 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（I ) 本發明係關於一種可運用在使用多重時脈系統裝置 內的時脈切換架構，特別係有關於一'種可運用在使用多重 時脈系統裝置內，而具有最少的缺陷（Glitch)發生的時脈切 換架構。 對於多重時脈信號作切換的電路，在目前的科技發展 中具有相當重要的應用。例如在電腦系統中即具備有許多 不同時脈操作速度的記憶體，而此時脈切換電路即可運用 在這些不同操作速率的記憶體中，讀取記憶體內資料的時 脈切換。而另一種較明顯的運用，即是例如在目前電腦系 統常用到的操作模式（Operating Mode)與閒置模式（idle Mode)。在操作模式下，當然會以較高頻率的時脈來讀取 或寫入資料，但是若是在閒置模式下，則可降低操作頻 率，來節省功率的消耗。而這樣的切換，則必須運用到操 作時脈的切換，也就是必須運用此時脈切換架構來達成此 目的。 傳統的時脈切換架構，例如第1A圖所示，此時脈切 換架構100包括一個多工器(MUX)l 10與一個切換控制裝 置120。此切換控制裝置120藉由輸出到多工器11〇的選 擇信號來達到多工器110切換輸出不同時脈信號的目的。 此多工器110的複雜度係與所要切換的時脈信號個數平方 成正比，因此在硬體上較爲複雜，成本也較高，例如，以 對四個時脈信號Clk—A、Clk_B、Clk—C及ClkJD的切換而 言，此多工器110係藉由切換控制裝置120的選擇信號 (SJJiS。)來對多工器中所對應的輸入埠切換選擇輸出。 3 (請先閱讀背面之注意事項寫本頁) •1: -裝· 訂 線 本纸浪尺度適用中國國家標準（CNS ) A4規格（210X 297公慶） 538594 4226twf doc/005 ^ 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（/) 如在第1A圖所示之時脈信號cik_A、Clk_B、Clk__C 及Clk_D分別接到多工器110的輸入埠（oooi)、（0100)、 (0111)、（1101)。而切換控制裝置120係接收一個具有多位 元的時脈選擇信號（Clk_Sel)與一取樣時脈（Sample_Clk)信 號。在接收到時脈選擇信號Clk_Sel後，此切換控制裝置 120會根據取樣時脈Sample_Clk來變換輸出之選擇信號 (SJjj。），而在多工器110接收到此選擇信號（SsSjjo) 後，會根據其値來輸出一輸出時脈（Out_Clk)。而其對應的 輸出値如第1B圖所示，如在選擇信號（SJAjdKOOOl)， 則輸出時脈 〇ut_Clk=Clk_A，如在選擇信號 (SJASjyOlOO)，則輸出時脈Out—Clk=ClkJB，如在選擇 信號（S^ASg^KOIII)，則輸出時脈 Out_Clk=Clk_C，如在 選擇信號（SJASd^llOl)，則輸出時脈Out_Clk=Clk_D。 另外，在習知的時脈切換架構中，需要額外的取樣時 脈時脈Sample_Clk信號。而且，對於選擇適當的取樣時脈 Sample_Clk，必須考慮一個限制，即其頻率必須高於所要 切換的所有時脈信號頻率。如在第2圖所示，即爲另一種 對於兩個時脈X〇_clk與xl__dk作切換的時脈切換架構 200。此時脈切換架構包括一個四階多工器(MUX4)210、一 切換控制裝置220。 而對於所要切換的兩個時脈x〇_clk與Xl_clk中， x0_dk時脈具有較高的頻率。因此，所採用的取樣時脈 Sample__Clk的頻率最少不得低於xOjlk時脈的頻率。並在 第2圖中顯示有pre_x0_clk與pre_xl_clk係分別經由取樣 4 ^浪尺度適用中國國家標i(CNS ) A4規格( 210X 297公釐了 (請先閱讀背面之注意事項寫本頁) .裝· 訂 -線 538594 4226twf.doc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（$ ) 時脈Sample_Clk經過兩個D型正反器230與240對兩個 時脈xO jlk與xl_d的輸出値。在此假設，若是 pre—xn—clk=xn—elk，n^O 或 1，則表示 xn_clk 時脈位準 (duration of level)的時間夠長。而切換控制裝置220除了 接收用來取樣的取樣時脈Sample_Clk之外，還接收另一個 切換致能信號（Swith_H)。在切換致能信號Swith_H爲高位 準(即邏輯1)時，即經由輸出的選擇信號（S1，S0)進行切換 的操作，如第2圖所示，（S1，S0)在等於(0,0)、（0，1)、（1，〇) 或(1，1)時輸出信號out一elk分另[J爲x0_clk、0、1與xl—C卜 對於第2圖所示的時脈切換架構200的操作時脈圖， 如第3A-3B與4A-4B圖所示。在第3A圖中，顯示將從較 高頻率的時脈x〇_clk轉換爲較低頻率的xl_clk，在切換致 能信號Swith_H爲高位準（High)時(即時間爲tO)，開始作 切換操作。在取樣時脈Sample_Clk上升邊緣的時間t2時， 所得的xO_clk時脈値與對應於前一個Sampk_Clk上升邊 緣的時間tl時，所得的pre_x0_dk時脈値相等（皆爲低位 準）。此時，選擇信號（S1，S0)即由（0,0)轉爲（1，0)，此時， 輸出信號〇ut_clk即轉爲高位準，並在時間t3時，選擇信 號(S1，S0)即由（1，0)轉爲（1，1)，而輸出信號out__clk即轉爲 與xl_clk時脈同步。 而在第3B圖中，一樣顯示從較高頻率的時脈x〇_clk 轉換爲較低頻率的xl_clk，在切換致能信號Swith_H爲高 位準（High)時（即時間爲t0)，開始作切換操作。在取樣時 脈Sample__Clk上升邊緣的時間t2時，所得的x0__clk時脈 5 本紙?長尺度適用中國國家標準（CNS ) A4規格（2丨0X 297公釐） (請先閱讀背面之注意事項I®?寫本頁) -裝· 訂 線 538594 4226twf.doc/005 ^ B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（…） 〜 値與對應於前一個Sample—Clk上升邊緣的時間t~l時，所 得的pre—x〇_clk時脈値相等，所不同的是此兩個値皆爲高 位準。在t2時，選擇信號（S1，S0)即由（0,0)轉爲（〇，1)，此時， 輸出信號out—elk即轉爲低位準，並在時間t3時，選擇信 號(S1，S0)即由（〇，1)轉爲（1，1)，而輸出信號out—Clk即轉胃 與xl_clk時脈同步。 在第4A圖中，顯示將從較低頻率的xi__cik轉換爲較 高頻率的時脈x〇—elk，在切換致能信號Swith_H爲高位準 (High)時（即時間爲tO)開始作切換操作。取樣時月辰 Sample_Clk上升邊緣的時間t2時，所得的χΐ—cik時脈値 與對應於前一個Sample—Clk上升邊緣的時間ti時，所得 的pre_xO__clk時脈値相等（皆爲高位準）。此時，選擇信號 (S1，S0)即由（1，1)轉爲（0，1)，此時，輸出信號ollt—clk即轉 爲低位準。在接著的Sample—Clk上升邊緣時間t3與t4時， 所得的x〇_clk時脈値皆爲高位準，而目前的輸出信號 out一elk爲低位準，因此無法同步。在接著下一個 Sample—Clk上升邊緣時間t5時，x〇_dk時脈値爲低位準， 因此，選擇信號（S1，S0)即由（0，1)轉爲（〇,〇)，而輸出信號 out一elk即轉爲與x〇_clk時脈同步。 與第4A圖類似，在第4B圖中，顯示將從較低頻率 的x]_clk轉換爲較高頻率的時脈x〇_clk，在切換致能信號 Swith_H爲高位準（High)時（即時間爲tO)開始作切換操 作。取樣時脈Sample_Clk上升邊緣的時間t2時，所得的 xl_clk時脈値與對應於前一個Sainple_Clk上升邊緣的時 6 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項^►寫本頁} -壯衣- T -、^• -線 538594 6twf.doc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（Γ) 間tl時，所得的pre一xO一elk時脈値相等，不同的是皆爲低 位準。此時，選擇信號（S1，S0)即由（1，1)轉爲（ι，〇)，此時， 輸出信號out_clk即轉爲高位準。在接著的Sample—Clk上 升邊緣時間t3時，所得的x0_cik時脈値爲低位準，而目 前的輸出信號out-clk爲高位準，因此無法同步。在接著 下一個Sample_Clk上升邊緣時間t4時，x〇-Cik時脈値爲 高位準，因此，選擇信號（S1，S0)即由（1，0)轉爲（〇,〇)，而輸 出號〇ut_clk即轉爲與x〇_cik時脈同步。 上述兩種習知的時脈切換架構中，多工器的複雜度係 與所要切換的時脈信號個數平方成正比，因此在硬體上較 爲複雜，成本也較高。另外，在取樣時脈的選擇上有較多 的限制。 因此，本發明的目的在於提供一種時脈切換架構，其 多工器的複雜度係與所要切換的時脈信號個數成正比，可 大量地簡化電路的複雜度，降低製造之成本。 本發明的另一目的，在於提供另一種時脈切換架構， 其取樣時脈係採用在所欲選擇的時脈信號中，最高頻率的 時脈’可避免需要額外的取樣時脈，其頻率小於所欲選擇 時脈的問題。 爲達上述之目的，本發明係提供一種時脈切換架構， 用以接收一時脈匯流排信號與一時脈選擇信號，其中此時 脈匯流排信號據以至少第一時脈信號與.第二時脈信號，而 時脈切換架構用以選擇性地輸出該時脈匯流排信號中該 第一時脈信號與該第二時脈信號兩者之一。此時脈切換架 7 (請先閲讀背面之注意事項 裝-- :寫本頁) 訂 線_ 本紙張尺度適用中國國家標準（CNS )八4規格（加乂 297公產） 538594 4226twfdoc/005 A7 B7 五、發明説明（匕） 構包括一切換控制裝置、一第一多工器、一或閘、一反及 閘、一第一閂鎖裝置、一第二閂鎖裝置、一第二多工器、 以及一第三多工器。 此切換控制裝置用以接收第一時脈信號、第二時脈信 號、切換致能信號與取樣時脈信號，並根據切換致能信號 之驅動，輸出一第一選擇信號與第二選擇信號。第一多工 器用以接收第一選擇信號與第二選擇信號，並根據第一與 第二選擇信號之値而選擇性地輸出與之耦接之第一時脈 信號或第二時脈信號。或（OR)閘係用以接收第一選擇信號 與第二選擇信號，並對第一與第二選擇信號做一或(0R)之 邏輯處理後輸出一第一時脈寫入信號。反及(NAND)閘係用 以接收第一選擇信號與第二選擇信號，並對第一與第二選 擇信號做一反及（NAND)之邏輯處理後輸出一第二時脈寫 入信號。而第一閂鎖裝置係用以接收時脈選擇信號、第一 時脈寫入信號與取樣時脈信號，並根據第一時脈寫入信號 與取樣時脈信號，對時脈選擇信號轉換輸出一第一時脈選 擇信號。第二閂鎖裝置係用以接收時脈選擇信號、第二時 脈寫入信號與取樣時脈信號，並根據第二時脈寫入信號與 取樣時脈信號，對時脈選擇信號轉換輸出一第二時脈選擇 信號。第二多工器係耦接到第一多工器，用以接收時脈匯 流排信號與第一時脈選擇信號，並根據第一時脈選擇信號 而輸出第一時脈信號至第一多工器。第三多工器係耦接到 第一多工器，用以接收時脈匯流排信號與第二時脈選擇信 號，並根據第二時脈選擇信號而輸出第二時脈信號至第一 8538594 4226twf.doc / 005 A 7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (I) The present invention relates to a clock switching architecture that can be used in devices using multiple clock systems. Regarding a clock switching architecture which can be applied in a device using multiple clock systems with the least occurrence of glitches. The circuit for switching multiple clock signals has a very important application in the current development of science and technology. For example, in a computer system, there are many memories with different clock operating speeds, and the clock switching circuit can be used in these memories with different operating speeds to read the clock of the data in the memory. Another more obvious application is, for example, the operating mode and idle mode commonly used in current computer systems. In the operating mode, of course, data is read or written at a higher frequency, but in the idle mode, the operating frequency can be reduced to save power consumption. And this kind of switching must use the switching of the operating clock, that is, the clock switching architecture must be used to achieve this purpose. A conventional clock switching architecture is shown in FIG. 1A. At this time, the clock switching architecture 100 includes a multiplexer (MUX) 110 and a switching control device 120. The switching control device 120 achieves the purpose of switching and outputting different clock signals by the multiplexer 110 by selecting signals output to the multiplexer 110. The complexity of the multiplexer 110 is proportional to the square of the number of clock signals to be switched, so it is more complicated in hardware and the cost is higher. For example, for the four clock signals Clk_A, Clk_B For switching between Clk-C and ClkJD, the multiplexer 110 selects and outputs corresponding input ports in the multiplexer by selecting signals (SJJiS.) Of the switching control device 120. 3 (Please read the notes on the back first to write this page) • 1:-The paper size of the binding and binding paper is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 public holiday) 538594 4226twf doc / 005 ^ 7 B7 Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives V. Invention Description (/) The clock signals cik_A, Clk_B, Clk__C, and Clk_D shown in Figure 1A are connected to the input ports (oooi), (0100) of the multiplexer 110, respectively. , (0111), (1101). The switching control device 120 receives a clock selection signal (Clk_Sel) with multiple bits and a sample clock (Sample_Clk) signal. After receiving the clock selection signal Clk_Sel, the switching control device 120 converts the output selection signal (SJjj.) According to the sampling clock Sample_Clk. After receiving the selection signal (SsSjjo), the multiplexer 110 It outputs an output clock (Out_Clk). And its corresponding output: as shown in Figure 1B, if the selection signal (SJAjdKOOOl), the output clock 〇ut_Clk = Clk_A, if the selection signal (SJASjyOlOO), the output clock Out—Clk = ClkJB Select the signal (S ^ ASg ^ KOIII), then output the clock Out_Clk = Clk_C. If you select the signal (SJASd ^ llOl), output the clock Out_Clk = Clk_D. In addition, in the conventional clock switching architecture, an additional sample clock clock Sample_Clk signal is required. Furthermore, for selecting the appropriate sampling clock Sample_Clk, a limitation must be considered, that is, its frequency must be higher than all clock signal frequencies to be switched. As shown in Fig. 2, it is another clock switching architecture 200 for switching between two clocks X〇_clk and xl__dk. The clock switching architecture includes a fourth-order multiplexer (MUX4) 210 and a switching control device 220. For the two clocks x0_clk and Xl_clk to be switched, the x0_dk clock has a higher frequency. Therefore, the frequency of the sampling clock Sample__Clk used must be at least lower than the frequency of the xOjlk clock. And in the second figure, it shows that pre_x0_clk and pre_xl_clk are sampled 4 ^ wave scales are applicable to China National Standard i (CNS) A4 specifications (210X 297 mm (please read the precautions on the back to write this page). Order-line 538594 4226twf.doc / 005 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention ($) Clock Sample_Clk passes two D-type flip-flops 230 and 240 to two clocks xO jlk and The output of xl_d is 値. It is assumed here that if pre_xn_clk = xn_elk, n ^ O or 1, it means that the duration of level of the xn_clk clock is long enough. The switch control device 220 is In addition to the sampling clock Sample_Clk used for sampling, it also receives another switching enable signal (Swith_H). When the switching enable signal Swith_H is at a high level (ie, logic 1), it is via the output selection signals (S1, S0) Perform the switching operation, as shown in Figure 2. When (S1, S0) is equal to (0,0), (0,1), (1, 〇) or (1,1), the output signal out is elk points. [J is the operation clock diagram of x0_clk, 0, 1, and x1-C. For the clock switching architecture 200 shown in FIG. 2, Figures 3A-3B and 4A-4B are shown. In Figure 3A, the clock from the higher frequency x0_clk to the lower frequency xl_clk is displayed, and the switch enable signal Swith_H is at a high level. Time (that is, time t0), the switching operation is started. At the time t2 of the rising edge of the sample clock Sample_Clk, the obtained xO_clk clock 値 and the time t1 corresponding to the rising edge of the previous Sampk_Clk are obtained. Equal (all low level). At this time, the selection signal (S1, S0) is changed from (0,0) to (1,0). At this time, the output signal OUT_clk is turned to the high level, and at time t3 At this time, the selection signal (S1, S0) is changed from (1, 0) to (1, 1), and the output signal out__clk is synchronized with the xl_clk clock. In Figure 3B, the same is displayed from the higher frequency The clock x〇_clk is converted to a lower frequency xl_clk. When the switch enable signal Swith_H is at a high level (that is, time t0), the switching operation is started. At the time t2 when the rising edge of the sample clock Sample__Clk rises Time, the obtained x0__clk clock pulse 5 paper? The long scale applies the Chinese National Standard (CNS) A4 specification (2 丨 0 X 297 mm) (Please read the note on the back I®? Write this page)-Binding · 538594 4226twf.doc / 005 ^ B7 Printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs 5. Description of the invention (…) ~ 値 and the time t ~ l corresponding to the rising edge of the previous Sample-Clk, the resulting pre-x0_clk clock 値 is equal, except that both 此 are high. At t2, the selection signal (S1, S0) is changed from (0,0) to (0,1). At this time, the output signal out_elk is turned to a low level, and at time t3, the selection signal (S1 , S0) is changed from (0,1) to (1,1), and the output signal out-Clk is turned to the stomach and synchronized with the xl_clk clock. In FIG. 4A, the clock x0-elk converted from the lower frequency xi__cik to the higher frequency is shown, and the switching operation is started when the switching enable signal Swith_H is at a high level (that is, time is tO). . At the time t2 of the rising edge of Sample_Clk at the time of sampling, the obtained χΐ-cik clock 値 is equal to the time ti corresponding to the rising edge of the previous Sample_Clk (the high level). At this time, the selection signals (S1, S0) are changed from (1, 1) to (0, 1). At this time, the output signal ollt-clk is turned to a low level. At the following Sample_Clk rising edge times t3 and t4, the obtained x0_clk clock pulses are all high levels, and the current output signal out-elk is low levels, so it cannot be synchronized. At the next Sample_Clk rising edge time t5, the x〇_dk clock 値 is at a low level, so the selection signal (S1, S0) is changed from (0, 1) to (〇, 〇) and output The signal out elk is synchronized with the x〇_clk clock. Similar to FIG. 4A, in FIG. 4B, the clock x0_clk that is converted from the lower frequency x] _clk to the higher frequency is displayed. When the switching enable signal Swith_H is at a high level (that is, The time is tO). Sampling clock Sample_Clk rising edge time t2, the resulting xl_clk clock 値 and the time corresponding to the previous Sainple_Clk rising edge 6 This paper size applies to China National Standard (CNS) A4 (210X 297 mm) (please first Read the notes on the back ^ ►Write this page} -Zhuang Yi-T-, ^ • -Line 538594 6twf.doc / 005 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The obtained pre-xO-elk clock pulses are equal, except that they are all low level. At this time, the selection signal (S1, S0) is changed from (1, 1) to (ι, 〇), and at this time, the output The signal out_clk is turned to the high level. At the next Sample-Clk rising edge time t3, the obtained x0_cik clock is at the low level, and the current output signal out-clk is at the high level, so it cannot be synchronized. At the rising edge time t4 of Sample_Clk, x〇-Cik clock 値 is high, so the selection signal (S1, S0) is changed from (1, 0) to (〇, 〇), and the output number 〇ut_clk is Synchronized with x〇_cik clock. In the above two conventional clock switching architectures, The complexity of the multiplexer is proportional to the square of the number of clock signals to be switched, so it is more complicated in hardware and the cost is higher. In addition, there are more restrictions on the selection of the sampling clock. Therefore The object of the present invention is to provide a clock switching architecture, the complexity of the multiplexer is directly proportional to the number of clock signals to be switched, which can greatly simplify the complexity of the circuit and reduce the cost of manufacturing. Another object is to provide another clock switching architecture. The sampling clock system uses the clock with the highest frequency among the clock signals to be selected, which can avoid the need for additional sampling clocks, whose frequency is less than the one selected. In order to achieve the above-mentioned object, the present invention provides a clock switching architecture for receiving a clock bus signal and a clock selection signal, where the clock bus signal is based on at least the first clock signal. And. The second clock signal, and the clock switching architecture is used to selectively output one of the first clock signal and the second clock signal in the clock bus signal. Switching frame 7 (please read the precautions on the back first --- write this page) Thread setting _ This paper size is applicable to China National Standard (CNS) 8-4 specifications (plus 297 products) 538594 4226twfdoc / 005 A7 B7 V. Invention Description (Dagger) structure includes a switching control device, a first multiplexer, an OR gate, a reverse gate, a first latch device, a second latch device, a second multiplexer, and a The third multiplexer is used to receive the first clock signal, the second clock signal, the switching enable signal and the sampling clock signal, and output a first selection signal according to the driving of the switching enable signal. With the second selection signal. The first multiplexer is configured to receive the first selection signal and the second selection signal, and selectively output the first clock signal or the second clock signal coupled to the first selection signal and the second selection signal. The OR gate is used to receive the first selection signal and the second selection signal, and perform an OR processing on the first and second selection signals to output a first clock write signal. The inverse (NAND) gate system is used for receiving the first selection signal and the second selection signal, and performing a logical inverse (NAND) processing on the first and second selection signals, and outputting a second clock write signal. The first latch device is used to receive the clock selection signal, the first clock write signal, and the sampling clock signal, and convert and output the clock selection signal according to the first clock write signal and the sampling clock signal. A first clock selection signal. The second latch device is used for receiving the clock selection signal, the second clock write signal and the sampling clock signal, and converting and outputting a clock selection signal according to the second clock write signal and the sampling clock signal. Second clock selection signal. The second multiplexer is coupled to the first multiplexer for receiving the clock bus signal and the first clock selection signal, and outputting the first clock signal to the first multiple according to the first clock selection signal. Worker. The third multiplexer is coupled to the first multiplexer for receiving the clock bus signal and the second clock selection signal, and outputting the second clock signal to the first 8 according to the second clock selection signal.
(請先閱讀背面之注意事項A 裝-- r本頁) 訂 經濟部智慧財產局員工消費合作社印製 表紙浪尺度適用中國國家標準（CNS ) A*4規格（21〇Χ 297公釐） 538594 4226twf.doc/005 A 7 _ B7 五、發明説明（7) 多工器，藉以使得第一多工器可選擇性地輸出第一時脈信 號或第二時脈信號，第一多工器的控制如傳統時脈及一取 樣時脈的控制方法。 在上述的時脈切換架構中之第一閂鎖器包括一第一 二階多工器與一第一暫存器。其中，第一二階多工器係用 以接收時脈選擇信號與第一時脈寫入信號，並根據第一時 脈寫入信號之驅動而輸出時脈選擇信號。第一暫存器係用 以接收取樣時脈信號與經由第一二階多工器所輸出之時 脈選擇信號，並根據取樣時脈信號閂鎖時脈選擇信號，並 輸出第一時脈選擇信號。 在上述的時脈切換架構中之第二閂鎖器包括一二階 多工器與一第二暫存器。其中，此二階多工器，用以接收 時脈選擇信號與第二時脈寫入信號，並根據第二時脈寫入 信號之驅動而輸出時脈選擇信號。此第二暫存器係用以接 收取樣時脈信號與經由二階多工器所輸出之時脈選擇信 號，並根據取樣時脈信號閂鎖時脈選擇信號，並輸出第二 時脈選擇信號。 爲達上述之目的，本發明提供一種時脈切換架構，用 以接收一時脈匯流排信號與一時脈選擇信號。此時脈匯流 排信號至少具有一第一時脈信號與一第二時脈信號。此時 脈切換架構用以選擇性地輸出時脈匯流排信號中之第一 時脈信號或第二時脈信號。而此時脈切換架構包括一切換 控制裝置、一第一多工器、一第一閂鎖裝置、一第二閂鎖 裝置、一第二多工器與一第三多工器。切換控制裝置係用 9 (請先閲讀背面之注意事項寫本頁) r(Please read the precautions on the back of this page. A --- r page) Order the printed paper size for the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to apply the Chinese National Standard (CNS) A * 4 specification (21〇 × 297 mm) 538594 4226twf.doc / 005 A 7 _ B7 V. Description of the invention (7) Multiplexer, so that the first multiplexer can selectively output the first clock signal or the second clock signal. Control methods such as traditional clocks and a sampling clock. The first latch in the above clock switching architecture includes a first second-order multiplexer and a first register. The first second-order multiplexer is used to receive the clock selection signal and the first clock write signal, and output the clock selection signal according to the driving of the first clock write signal. The first register is used to receive the sampling clock signal and the clock selection signal output by the first second-order multiplexer, latch the clock selection signal according to the sampling clock signal, and output the first clock selection signal. The second latch in the above-mentioned clock switching architecture includes a second-order multiplexer and a second register. The second-order multiplexer is used to receive the clock selection signal and the second clock write signal, and output the clock selection signal according to the driving of the second clock write signal. The second register is used to receive the sampling clock signal and the clock selection signal output by the second-order multiplexer, latch the clock selection signal according to the sampling clock signal, and output the second clock selection signal. To achieve the above object, the present invention provides a clock switching architecture for receiving a clock bus signal and a clock selection signal. At this time, the bus signal has at least a first clock signal and a second clock signal. The clock switching architecture is used to selectively output the first clock signal or the second clock signal of the clock bus signals. The clock switching architecture includes a switching control device, a first multiplexer, a first latch device, a second latch device, a second multiplexer, and a third multiplexer. Switch control device 9 (Please read the precautions on the back to write this page) r
I 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 538594 4226twf doc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（又） 以接收第一時脈信號、第二時脈信號、切換致能信號與取 樣時脈信號，並根據切換致能信號之驅動，輸出第一選擇 信號與第二選擇信號。第一多工器係用以接收第一選擇信 號與第二選擇信號，並根據第一與第二選擇信號之値而選 擇性地輸出與之耦接之第一時脈信號或第二時脈信號。第 一閂鎖裝置係用以接收時脈選擇信號、第一時脈信號、第 二時脈信號與取樣時脈信號，並根據第一時脈信號、第二 時脈信號與取樣時脈信號，對時脈選擇信號轉換輸出一第 一時脈選擇信號。第—^問鎖裝置係用以接收時脈選擇fe 號、第—時脈信號、第二時脈信號與取樣時脈信號，並根 據第一時脈信號、第二時脈信號與取樣時脈信號，對時脈 選擇信號轉換輸出一第二時脈選擇信號。第二多工器，耦 接到第一多工器，用以接收時脈匯流排信號與第一時脈選 擇信號，並根據第一時脈選擇信號而輸出第一時脈信號至 第一多工器。第三多工器耦接到第一多工器，係用以接收 時脈匯流排信號與第二時脈選擇信號，並根據第二時脈選 擇信號而輸出第二時脈信號至第二多工器，藉以使得第一 多工器可選擇性地輸出第一時脈信號或第二時脈信號。 對於數個時脈的切換系統，本發明提供一種時脈切換 架構，以兩個時脈來說明，可接收一第一時脈信號與一第 二時脈信號，其中第一時脈信號之頻率高於該第二時脈信 號。此時脈切換架構用以選擇性地輸出第一時脈信號或第 二時脈信號。此時脈切換架構包括一切換控制裝置與一第 一多工器。此切換控制裝置係用以接收第一時脈信號、第 10 本纸張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）I Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economy This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 538594 4226twf doc / 005 A7 B7 Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Also) receiving the first clock signal, the second clock signal, the switching enable signal and the sampling clock signal, and outputting the first selection signal and the second selection signal according to the driving of the switching enable signal. The first multiplexer is used to receive the first selection signal and the second selection signal, and selectively output the first clock signal or the second clock coupled thereto according to the first of the first and second selection signals. signal. The first latch device is used to receive a clock selection signal, a first clock signal, a second clock signal, and a sampling clock signal, and according to the first clock signal, the second clock signal, and the sampling clock signal, The clock selection signal is converted and output a first clock selection signal. The ^ th interrogation device is used to receive the clock selection fe number, the first clock signal, the second clock signal, and the sampling clock signal, and according to the first clock signal, the second clock signal, and the sampling clock Signal, converts to the clock selection signal and outputs a second clock selection signal. The second multiplexer is coupled to the first multiplexer, and is used for receiving the clock bus signal and the first clock selection signal, and outputting the first clock signal to the first multiple according to the first clock selection signal. Worker. The third multiplexer is coupled to the first multiplexer, and is used for receiving the clock bus signal and the second clock selection signal, and outputting the second clock signal to the second clock according to the second clock selection signal. The multiplexer enables the first multiplexer to selectively output the first clock signal or the second clock signal. For several clock switching systems, the present invention provides a clock switching architecture, which is illustrated by two clocks, and can receive a first clock signal and a second clock signal, wherein the frequency of the first clock signal is Above the second clock signal. The clock switching architecture is used to selectively output the first clock signal or the second clock signal. The clock switching architecture includes a switching control device and a first multiplexer. This switching control device is used to receive the first clock signal, the 10th paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm)
(請先閱讀背面之注意事項H •裝-- ，寫本頁) 、?τ 線 538594 4226twf.doc/005 A7 經濟部智慧財產局員工消費合作社印製 ________B7 五、發明説明（f ) ^' 二時脈信號、一切換致能信號與一取樣時脈信號，其中， 此取樣時脈信號係爲第一時脈信號。此切換控制裝置根據 切換致能信號與取樣時脈信號而輸出一第一選擇信號與 一第二選擇信號。第一多工器係耦接到切換控制裝置，並 用以接收第一時脈信號、第二時脈信號、第一選擇信號與 第二選擇信號，而第一多工器係根據所接收的第一與第二 選擇信號之値，選擇性地輸出第一時脈信號及該第二時脈 信號兩者之一。 爲達上述之目的，本發明提出一種時脈切換架構，用 以接收複數個時脈信號，其中最高頻率時脈信號爲〜第— 時脈信號。此時脈切換架構用以選擇性地輸出這些時脈信 號之一。此時脈切換架構主要包括一切換控制裝置與〜第 一多工器。而此切換控制裝置係用以接收這些時脈信號、 切換致能信號與取樣時脈信號，其中此取樣時脈信號係即 爲第一時脈信號。此切換控制裝置根據切換致能信號與取 樣時脈信號而輸出複數個選擇信號。而第一多工器係耦接 到切換控制裝置，用以接收這些時脈信號與選擇信號，而 第一多工器係根據所接收的這些選擇信號之値，選擇性地 輸出其中之一時脈信號。 爲達上述之目的’本發明提供一種時脈切換方法，適 用於根據一取樣時脈信號，將一輸出時脈信號從原來的一 第一時脈信號切換爲一第二時脈信號，其中第一時脈信號 之頻率高於該第二時脈信號。此時脈切換方法包括選擇此 取樣時脈信號等於第一時脈信號，並接著在取樣時脈信號 (請先閲讀背面之注意事項λ -裝I— ί寫本頁) -訂 -線- 538594 4226twfdoc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（β ) 上升邊緣時，將輸出時脈信號暫時轉爲高位準，而後在接 著的下一個取樣時脈信號上升邊緣時，偵測第二時脈信號 之位準，若第二時脈信號爲高位準時，即將可將輸出時脈 信號切換爲第二時脈信號輸出。 爲達上述之目的，本發明提供一種時脈切換方法，適 用於根據一^取樣時脈信號，將一輸出時脈信號從原來的一 第二時脈信號切換爲一第一時脈信號，其中第一時脈信號 之頻率高於該第二時脈信號。此時脈切換方法包括先選擇 取樣時脈信號等於第一時脈信號。在第一時間時，根據取 樣時脈信號上升邊緣時的第二時脈信號値，以及在前一個 取樣時脈脈波時的第二時脈信號値是否相同，據以判斷第 二時脈信號之位準是否能切換，其中若兩個位準都相同表 示可以開始切換。接著判斷在第一時間時的第二時脈信號 値，若是低位準，則暫時地將輸出信號固定輸出高位準， 並在下一個週期之取樣時脈信號上升時，直接將該輸出信 號轉爲低位準，並以此第一時脈信號輸出。而若是在第一 時間時的該第二時脈信號値爲高位準，則暫時地將輸出信 號固定輸出低位準，而接著在下一個週期之取樣時脈信號 下降時暫時地將輸出信號固定轉換輸出高位準，接著在下 一個取樣時脈信號下降時，直接將該輸出時脈信號選擇切 換爲第一時脈信號輸出。 爲達上述之目的，本發明提供一種時脈切換方法，適 用於根據一取樣時脈信號，將一輸出時脈信號從原來的一 第二時脈信號切換爲一第一時脈信號，其中此第一時脈信 12 (請先閲讀背面之注意事項HI寫本頁) -裝·(Please read the precautions on the back H • Install-, write this page),? Τ line 538594 4226twf.doc / 005 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ________B7 V. Description of Invention (f) ^ ' Two clock signals, a switching enable signal, and a sampling clock signal, where the sampling clock signal is a first clock signal. The switching control device outputs a first selection signal and a second selection signal according to the switching enable signal and the sampling clock signal. The first multiplexer is coupled to the switching control device and is used to receive the first clock signal, the second clock signal, the first selection signal and the second selection signal, and the first multiplexer is based on the received first One of the first and second selection signals selectively outputs one of the first clock signal and the second clock signal. In order to achieve the above object, the present invention proposes a clock switching architecture for receiving a plurality of clock signals, wherein the highest frequency clock signal is the first clock signal. The clock switching architecture is used to selectively output one of these clock signals. The clock switching architecture mainly includes a switching control device and a first multiplexer. The switching control device is used to receive these clock signals, switch enable signals, and sampling clock signals, where the sampling clock signal is the first clock signal. The switching control device outputs a plurality of selection signals according to the switching enable signal and the sampling clock signal. The first multiplexer is coupled to the switching control device to receive the clock signals and the selection signals. The first multiplexer selectively outputs one of the clocks according to the received selection signals. signal. To achieve the above object, the present invention provides a clock switching method, which is applicable to switch an output clock signal from an original first clock signal to a second clock signal according to a sampled clock signal. The frequency of one clock signal is higher than the second clock signal. The clock switching method includes selecting this sampling clock signal to be equal to the first clock signal, and then sampling the clock signal (please read the precaution on the back first λ-装 I— ί write this page) -Order -line-538594 4226twfdoc / 005 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (β) When the rising edge, temporarily output the clock signal to a high level, and then when the next sampling clock signal rises the edge. To detect the level of the second clock signal. If the second clock signal is at a high level, the output clock signal can be switched to the second clock signal output. To achieve the above object, the present invention provides a clock switching method, which is applicable to switch an output clock signal from an original second clock signal to a first clock signal according to a sampling clock signal, wherein The frequency of the first clock signal is higher than the second clock signal. The clock switching method includes first selecting a sampling clock signal equal to the first clock signal. At the first time, it is judged based on whether the second clock signal 边缘 at the rising edge of the sampling clock signal and the second clock signal 时 at the previous sampling clock wave are the same. Whether the level can be switched. If both levels are the same, it can be switched. Then judge the second clock signal 値 at the first time. If it is the low level, temporarily fix the output signal to the high level temporarily, and when the sampling clock signal of the next cycle rises, directly turn the output signal to the low level. And output the first clock signal. If the second clock signal 値 is at the high level at the first time, the output signal is temporarily fixed to the low level, and then the output signal is temporarily converted and output when the sampling clock signal of the next cycle falls. High level, then when the next sampling clock signal drops, directly select the output clock signal to switch to the first clock signal output. To achieve the above object, the present invention provides a clock switching method, which is suitable for switching an output clock signal from an original second clock signal to a first clock signal according to a sampled clock signal. First Clock Letter 12 (Please read the note on the back first to write this page)
、1T 線_ 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 538594 4226twf.d〇c/〇〇5 A7 經濟部智慧財產局員工消費合作社印製 _____ _B7_— _ 五、發明説明（"） 號之頻率高於第二時脈信號。此時脈切換方法包括選擇取 樣時脈信號等於第一時脈信號，並接著在第一時間時’根 據取樣時脈信號下降邊緣時的第二時脈信號値’以及在前 一個取樣時脈脈波時的第二時脈信號値是否相同’據以判 斷第二時脈信號之位準是否能切換，其中若兩個位準都相 同表示可以開始切換。接著判斷在第一時間的第二時脈信 號値，若是低位準，則暫時地將輸出信號固定輸出高位 準，而在下一個週期之取樣時脈信號下降時，直接將輸出 信號轉爲低位準，而切換爲以第一時脈信號輸出。而若是 在第一時間時的第二時脈信號値爲高位準，則暫時地將輸 出信號固定輸出低位準，而接著在下一個週期之取樣時脈 信號下降時暫時地將輸出信號固定轉換輸出高位準，接著 在下一個取樣時脈信號下降時，直接將輸出時脈信號選擇 切換爲該第一時脈信號輸出。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖係繪7Γ；傳統的一種時脈切換架構。 第1B圖係繪示根據第1A圖中的傳統時脈切換架構 之選擇信號與其對應的多工器輸出値。 第2圖係繪示另一種傳統的時脈切換架構。 第3A與3B圖係顯示在第2圖之傳統時脈切換架構 中’從較高頻率時脈切換到較低頻率時脈之時序圖。 (請先閲讀背面之注意事項I®!寫本頁) -裝·Line 1T _ This paper wave scale is applicable to China National Standard (CNS) A4 specifications (210X 297 mm) 538594 4226twf.d〇c / 〇〇5 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _____ _B7__ _ V. The frequency of the invention note is higher than the second clock signal. The clock switching method includes selecting the sampling clock signal equal to the first clock signal, and then 'according to the sampling clock signal at the falling edge of the second clock signal 値' at the first time and the previous sampling clock Whether the second clock signal 値 of the wave time is the same 'is used to determine whether the level of the second clock signal can be switched, and if both levels are the same, it can be switched. Then judge the second clock signal 値 at the first time, if it is the low level, temporarily fix the output signal to the high level temporarily, and when the sampling clock signal of the next cycle drops, directly turn the output signal to the low level, And switch to output with the first clock signal. If the second clock signal 値 is at the high level at the first time, the output signal is temporarily fixed to the low level, and then the output signal is temporarily converted to the output high level when the sampling clock signal of the next cycle falls. When the next sampling clock signal falls, the output clock signal is directly switched to the first clock signal output. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A Department 7Γ; a traditional clock switching architecture. Figure 1B shows the selection signal and its corresponding multiplexer output 値 according to the traditional clock switching architecture in Figure 1A. Figure 2 shows another traditional clock switching architecture. Figures 3A and 3B are timing diagrams of switching from a higher frequency clock to a lower frequency clock in the traditional clock switching architecture of Figure 2. (Please read the Precautions I® on the back first! Write this page)
、1T 線 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公慶） 538594 4226twf.doc/005 A7 B7 五、發明説明（/ y) 第4A與4B圖係顯示在第2圖之傳統時脈切換架構 中，從較低頻率時脈切換到較高頻率時脈之時序圖。 (請先閱讀背面之注意事項寫本頁) 第5圖係說明本發明一較佳實施例之時脈切換架 構。 第6圖係說明在第5圖之時脈切換架構中，從時脈 xO_dk轉換爲時脈xl_clk之操作時序圖。 第7圖係說明在第5圖之時脈切換架構中，從時脈 xO_clk轉換爲時脈xl_clk之操作時脈圖。 第8圖係說明在第5圖之時脈切換架構中，從時脈 xl_clk轉換爲時脈x〇_clk之操作時脈圖。 第9圖係說明在第5圖之時脈切換架構中，從時脈 xl_clk轉換爲時脈x〇_clk之操作時脈圖。 第10圖係說明在第5圖之時脈切換架構之操作流 程。 第11圖係說明本發明另一較佳實施例之一時脈切換 架構。 第12圖係說明在第11圖之時脈切換架構中，時脈從 時脈xO_clk切換到時脈xl_clk之時序圖。 經濟部智慧財產局員工消費合作社印製 第13圖係說明在第11圖之時脈切換架構中，從時脈 xl_clk切換到時脈χθ—clk之時序圖。 第14圖係說明在第11圖之時脈切換架構中，從時脈 xl_clk切換到時脈x0_clk之時序圖。 第圖係說明在第11圖本發明另一較佳實施例之時 脈切換架構之操作流程圖。 14 本紙張尺度適用中國國家標準（CNS ) A4規格（2!0'乂297公釐) 五 經濟部智慧財產局員工消費合作社印製 538594 4226twfdoc/005 B7 、發明説明（/夕） 圖號之簡單說明： 時脈切換架構100 多工器（MUX)llO 切換控制裝置120。 時脈切換架構200 四階多工器（MUX4)2 10 切換控制裝置220 時脈切換架構500 多工器(MUX)510 切換控制電路520 多工器（MUX A)530 多工器（MUX B)540 一閂鎖裝置531 多工器（MUX 2)532 暫存器(REGA)534 閂鎖裝置541 多工器(MUX 2)542 暫存器(REGB)544 第一邏輯運算裝置560 第二邏輯運算裝置570 第一實施例 以下係介紹按照本發明應用之較佳實施例’並以附圖 說明。根據所附之圖示中，相同之元件以相同之標號表 示，不在贅述。 本纸張尺度適用中國國家標準（CNS )八4規格（210X 297公釐） (請先閱讀背面之注意事項寫本頁) •裝- 訂 538594 4226twf.doc/005 A7 B7 i_I_ 經濟部智慧財產局員工消費合作社印製 發明説明（f/) 請參照第5圖，係說明本發明一較佳實施例之時脈切 換架構500。此時脈切換架構500主要包括一個用來輸出 的多工器（MUX)5 10、一切換控制電路520、以及用來選擇 輸入時脈的多工器（MUX A)530與多工器（MUX B)540。此 多工器5 1 0係爲一四階的多工器，接收由切換控制電路520 輸出的選擇信號（S1，S0)，對應其値（0,0)、（〇，；[)、（1，〇)、〇，υ 分別輸出四個信號xO_clk、0、1、xl_clk。 而多工器530係接收要切換的時脈匯流排（Bus of Clocks)信號clk_xn與時脈選擇信號clk_sel經由一閂鎖裝 置531，包括多工器(MUX 2)532與暫存器(REGA)534，閂 鎖作用後之時脈選擇信號muxa_sel。根據時脈選擇信號 muxa_sel，此多工器530將會選擇信號x〇_clk輸出。而此 多工器（MUX 2)532係根據暫存器寫入驅動信號 (rega_wi*_H)的値來輸出。而暫存器534係經由取樣時脈 sample_clk來閂鎖（Latch)時脈選擇信號Clk_sel並藉以控 制多工器530。此暫存器寫入驅動信號rega_Wr_H是經由 第5圖右側的選擇信號（S1，S0)，經過一第一邏輯運算裝置 560之一第一^邏輯運算後所得的信號，在此之第一邏輯運 算裝置560以或閘（OR) 560爲例，而第一邏輯運算則爲或 (〇R)邏輯運算。 多工器540也用來接收要切換的時脈匯流排(Bus of Clocks)信號dk_xn與經由一閂鎖裝置541之多工器(MUX 2)542與暫存器（REGB)544作用之時脈選擇信號 muxb^sel ◦根據時脈選擇信號muxb_se卜此多工器540將 16 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐）1. The paper size of the 1T line is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 public holiday) 538594 4226twf.doc / 005 A7 B7 V. Description of the invention (/ y) The 4A and 4B drawings are shown in the tradition of Figure 2 In the clock switching architecture, the timing diagram of switching from a lower frequency clock to a higher frequency clock. (Please read the notes on the back to write this page first) Figure 5 illustrates the clock switching architecture of a preferred embodiment of the present invention. FIG. 6 is a timing diagram illustrating the operation from clock xO_dk to clock xl_clk in the clock switching architecture of FIG. 5. FIG. 7 is an operation clock diagram illustrating the operation from the clock xO_clk to the clock xl_clk in the clock switching architecture of FIG. 5. FIG. 8 illustrates the operation clock diagram of the clock xl_clk to clock x0_clk conversion in the clock switching architecture of FIG. 5. FIG. 9 is a diagram illustrating the operation of the clock switching architecture in FIG. 5 from clock xl_clk to clock x0_clk. Figure 10 illustrates the operation flow of the clock switching architecture in Figure 5. FIG. 11 illustrates a clock switching architecture according to another preferred embodiment of the present invention. Fig. 12 is a timing diagram illustrating the clock switching from the clock xO_clk to the clock xl_clk in the clock switching architecture of Fig. 11. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 13 illustrates the timing diagram for switching from clock xl_clk to clock χθ-clk in the clock switching architecture in Figure 11. FIG. 14 is a timing diagram illustrating switching from the clock xl_clk to the clock x0_clk in the clock switching architecture of FIG. 11. Figure 11 is a flowchart illustrating the operation of the clock switching architecture of Figure 11 in accordance with another preferred embodiment of the present invention. 14 This paper size applies the Chinese National Standard (CNS) A4 specification (2! 0 '乂 297 mm) 5. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 538594 4226twfdoc / 005 B7, the description of the invention (/) Description: Clock switching architecture 100 multiplexer (MUX) 110 switching control device 120. Clock switching architecture 200 Fourth-order multiplexer (MUX4) 2 10 Switching control device 220 Clock switching architecture 500 Multiplexer (MUX) 510 Switching control circuit 520 Multiplexer (MUX A) 530 Multiplexer (MUX B) 540 a latch device 531 multiplexer (MUX 2) 532 register (REGA) 534 latch device 541 multiplexer (MUX 2) 542 register (REGB) 544 first logic operation device 560 second logic operation The first embodiment of the device 570 is described below with reference to the preferred embodiment of the application according to the present invention and is illustrated with the accompanying drawings. According to the attached drawings, the same components are denoted by the same reference numerals, and will not be described in detail. This paper size applies to China National Standard (CNS) 8-4 specifications (210X 297 mm) (Please read the notes on the back to write this page) • Binding-538594 4226twf.doc / 005 A7 B7 i_I_ Intellectual Property Bureau, Ministry of Economic Affairs Employee Consumer Cooperative Cooperative Prints the Invention Description (f /) Please refer to FIG. 5, which illustrates a clock switching architecture 500 according to a preferred embodiment of the present invention. The clock switching architecture 500 mainly includes a multiplexer (MUX) 5 10 for output, a switching control circuit 520, and a multiplexer (MUX A) 530 and a multiplexer (MUX) for selecting an input clock. B) 540. This multiplexer 5 1 0 is a fourth-order multiplexer, and receives a selection signal (S1, S0) output by the switching control circuit 520, corresponding to 値 (0,0), (〇 ,; [), ( 1, 0), 0, υ respectively output four signals xO_clk, 0, 1, xl_clk. The multiplexer 530 receives the bus of clocks signal clk_xn and the clock selection signal clk_sel via a latch device 531, including a multiplexer (MUX 2) 532 and a register (REGA). 534. Clock selection signal muxa_sel after the latch is applied. According to the clock selection signal muxa_sel, the multiplexer 530 will select the signal x〇_clk for output. The multiplexer (MUX 2) 532 is output according to the 値 of the register write drive signal (rega_wi * _H). The register 534 latches the clock selection signal Clk_sel and controls the multiplexer 530 through the sample clock sample_clk. This register write driving signal rega_Wr_H is a signal obtained after the first logical operation of a first logical operation device 560 via the selection signals (S1, S0) on the right side of FIG. 5, and the first logic here The arithmetic device 560 uses an OR gate 560 as an example, and the first logical operation is an OR (OR) logical operation. The multiplexer 540 is also used to receive the clock of the to-be-switched Bus of Clocks signal dk_xn and the timing of the multiplexer (MUX 2) 542 and the register (REGB) 544 via a latching device 541. Selection signal muxb ^ sel ◦ According to the clock selection signal muxb_se, this multiplexer 540 will apply 16 paper sizes to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)
(請先閱讀背面之注意事項H —裝-- >寫本頁) 訂 線 538594 4226twf.doc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（i f) 會選擇信號xl—elk輸出。而此多工器(MUX 2)542係根據 閂鎖裝置之暫存器寫入驅動信號（regb-wr-H)的値來輸 出。而暫存器544係經由取樣時脈sample—elk來閂鎖（Latch) 時脈選擇信號clk_sd並藉以控制多工器540。此暫存器寫 入驅動信號regb_wr—Η是經由第5圖右側的選擇信號 (S1，S0)，經過一第二邏輯運算裝置570之一第二邏輯運算 後所得的信號，在此之第二邏輯運算裝置570以反及 (NAND)閘爲例，而第二邏輯運算則爲反及(NAND)邏輯運 算。 而對於何時開始作切換’則由切換控制電路520所接 收的切換致能信號switch_H所控制。在本實施例中，此切 換致能信號switch_H係由時脈選擇信號muxa_sel與 muxb_sel經過比較器（CMP)550做一比較，若是A端的輸 入値(即時脈選擇信號muxb_sel)與B端的輸入値（即時脈 選擇信號muxa_sel)相同，則輸出爲0，若不同則輸出1。 g靑參照第6圖’係說明關於弟5圖之時脈切換架構 500從時脈x0_clk轉換爲時脈xl_clk之操作時脈圖。在時 間tl時，時脈選擇信號muxb_Sel改變，於是驅動多工器 540輸出時脈xl_clk，在此同時，經過比較器550輸出的 切換致能信號switch_H轉換爲高位準，於是在下一個取樣 時脈samPle__Clk上升邊緣，也就是時間t2，偵測出時脈 xO_clk的輸出爲低位準，而時脈x〇_clk的前一個値亦爲低 位準，表示此位準的時間夠長，可做切換動作。切換控制 電路520輸出的選擇信號（S1，S0)値在此時轉換爲（1，0)，於 (請先閲讀背面之注意事寫本頁) 項 -裝- 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 538594 4226twf doc/005 A 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（) 是輸出信號〇ut_clk即轉爲高位準，而在接著的取樣時脈 Sample_Clk上升邊緣皆會對時脈Xl_clk作偵測，直到時間 t3時，時脈xl_clk轉爲高位準，切換控制電路520所輸出 的選擇信號（S1，S0)値即轉換爲（1，1)，輸出信號out_clk即 切換爲與時脈xl__clk问步。 請參照第7圖，也是說明關於第5圖之時脈切換架構 5〇〇從時脈x0_clk轉換爲時脈xl_clk之操作時脈圖。在時 間tl時，時脈選擇信號muxb_sel改變，於是驅動多工器 540輸出時脈xl_clk，在此同時，經過比較器550輸出的 切換致能信號switch_H轉換爲高位準，於是在下一個取樣 時脈sample_clk上升邊緣，也就是時間t2，與第6圖不同 之處，在於偵測出時脈x0_dk的輸出爲高位準，而時脈 x0_clk的前一個値亦爲高位準，表示此位準的時間夠長， 可做切換動作。切換控制電路520輸出的選擇信號（S1，S0) 値在此時轉換爲（0，1)，於是輸出信號〇iit_clk即轉爲低位 準，而在接著的取樣時脈sample_Clk上升邊緣，也就是時 間t3時，偵測出時脈xl_clk爲高位準，切換控制電路520 所輸出的選擇信號（S1，S0)値即轉換爲（1，1)，輸出信號 oiU_clk即切換爲與時脈xl_dk同步。 請參照第8圖，係說明關於第5圖之時脈切換架構 5〇〇從時脈xl__clk轉換爲時脈x0_clk之操作時脈圖。在時 間tl時，時脈選擇信號miixa_Sel改變，於是驅動多工器 530輸出時脈x〇_clk，在此同時，經過比較器550輸出的 切換致能信號switch_H轉換爲高位準，於是在下一個取樣 18 (請先閱讀背面之注意事項纖寫本頁) -裝. 訂 線_ 本紙?良尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 538594 4226twfdoc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（/ ?) 時脈sample_clk上升邊緣，也就是時間t2，偵測出時脈 xl_dk的輸出爲高位準，而時脈xl_clk的前一個値亦爲高 位準，表示此位準的時間夠長，可做切換動作。切換控制 電路520輸出的選擇信號（S1，S0)値在此時轉換爲（0，1)，於 是輸出信號〇ut_clk即轉爲低位準，而在接著的取樣時脈 sample_Clk上升邊緣皆會對時脈x〇_clk作偵測，直到時間 t3時，時脈x0_clk轉爲低位準，切換控制電路520所輸出 的選擇信號（S1，S0)値即轉換爲（〇,〇)，輸出信號〇ut_clk即 切換爲與時脈x〇_clk同步。 請參照第9圖，也是說明關於第5圖之時脈切換架構 500從時脈xl_clk轉換爲時脈x0_clk之操作時脈圖。在時 間tl時，時脈選擇信號muxa_sel改變，於是驅動多工器 530輸出時脈x0_clk，在此同時，經過比較器550輸出的 切換致能信號switch_H轉換爲高位準，於是在下一個取樣 時脈sample_clk上升邊緣，也就是時間t2，與第8圖不同 之處，在於偵測出時脈xl_clk的輸出爲低位準，而時脈 xl_clk的前一個値亦爲低位準，表示此位準的時間夠長， 可做切換動作。切換控制電路520輸出的選擇信號（S1，S0) 値在此時轉換爲（1，〇)，於是輸出信號〇ut_dk即轉爲高位 準，而在接著的取樣時脈sample_clk上升邊緣，也就是時 間t3時，偵測出時脈X〇__clk爲高位準，切換控制電路520 所輸出的選擇信號（S1，S0)値即轉換爲（0,0)，輸出信號 out—elk即切換爲與時脈χθ—dk同步。 關於第5圖之時脈切換架構500之操作流程，如第1〇 19 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閱讀背面之注意事項HI寫本頁) -裝· 、?τ 線· 538594 4226twf.doc/005 A 7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（β) 圖所示，在步驟1000中，判斷目前多工器MUX 510所選 擇輸出的時脈爲x〇_clk或是xl_clk。若是xl_clk時脈， 則暫存器REG B 544並未寫入新的clk_sel値，而暫存器 REG A 534則寫入新的clk_sel値。接著步驟1020，多工 器5 10選擇一個適當的固定値（即所謂高位準或低位準）輸 出，接著步驟1030，多工器510選擇時脈x〇_clk輸出。 在步驟1000中，判斷目前多工器MUX 510所選擇輸 出的時脈若是xl_clk，則接著步驟1040,暫存器REG A534 並未寫入新的elk—sel値，而暫存器REG B 544則寫入新 的clk_sel値。接著步驟1〇5〇，多工器510選擇一個適當 的固定値GP所謂高位準或低位準)輸出，接著步驟1〇60， 多工益5 1 0選擇時脈Xl_clk輸出。 根據上述本發明較佳實施例之時脈切換架構，係運用 暫存器與低階的多工器，對於時脈選擇信號做一閂鎖作 用’以控制所輸出的時脈信號，其在多工器與切換控制電 路上的硬體複雜度係與所要切換的時脈信號個數成正 比，可大量地簡化電路的複雜度，降低製造之成本。 請參照第π圖，係說明本發明另一較佳實施例之一 時脈切換架構1100，此時脈切換架構H00主要包括一多 工器mo與一切換控制裝置1120。而切換控制裝置U2〇 用以接收時脈x〇_clk、時脈xl—Clk、取樣時脈sample_clk、 以及切換致能信號switch—Η，並輸出選擇信號（S1，S0)，其 中取樣時脈sample—Clk係採用所欲切換時脈x0_clk或 ___ 20 用中CNS) A4規格（21GX 297公產）(Please read the note H on the back first-installation-> write this page) Booking line 538594 4226twf.doc / 005 A7 B7 Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (if) will select the signal xl —Elk output. The multiplexer (MUX 2) 542 is output according to the register write drive signal (regb-wr-H) of the latch device. The register 544 latches the clock selection signal clk_sd via the sampling clock sample_elk and controls the multiplexer 540. This register write drive signal regb_wr—Η is a signal obtained through a second logic operation of a second logic operation device 570 via the selection signals (S1, S0) on the right side of FIG. The logic operation device 570 uses an inverse (NAND) gate as an example, and the second logic operation is an inverse (NAND) logic operation. And when to start switching is controlled by the switching enable signal switch_H received by the switching control circuit 520. In this embodiment, the switch enable signal switch_H is compared by the clock selection signal muxa_sel and muxb_sel through a comparator (CMP) 550. If it is the input of the A terminal (the real-time pulse selection signal muxb_sel) and the input of the B terminal ( If the instantaneous pulse selection signal muxa_sel) is the same, the output is 0. If it is different, the output is 1. g. Referring to FIG. 6 ', the operation clock diagram of the clock switching architecture 500 from the clock 5 to the clock x0_clk is explained. At time t1, the clock selection signal muxb_Sel changes, so the multiplexer 540 is driven to output the clock xl_clk. At the same time, the switch enable signal switch_H outputted by the comparator 550 is converted to a high level, so the next sampling clock samPle__Clk The rising edge, that is, time t2, detects that the output of the clock xO_clk is at a low level, and the previous 値 of the clock x0_clk is also at a low level, which indicates that the time at this level is long enough to perform a switching action. The selection signal (S1, S0) output by the switching control circuit 520 is converted to (1, 0) at this time, in (Please read the caution on the back first and write this page) Item-Binding-Binding This paper size applies to China Standard (CNS) A4 specification (210X 297 mm) 538594 4226twf doc / 005 A 7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () is the output signal ut_clk is turned to a high level, and then The rising edge of the sampling clock Sample_Clk will detect the clock Xl_clk. Until time t3, the clock xl_clk goes to a high level, and the selection signal (S1, S0) output by the switching control circuit 520 is converted into (1 , 1), the output signal out_clk is switched to step with the clock xl__clk. Please refer to Fig. 7, which also explains the operation clock diagram of the clock switching architecture 5 in Fig. 5. The clock x0_clk is converted to the clock xl_clk. At time t1, the clock selection signal muxb_sel changes, so the multiplexer 540 is driven to output the clock xl_clk. At the same time, the switch enable signal switch_H outputted by the comparator 550 is converted to a high level, so the next sample clock sample_clk The rising edge, that is, time t2, is different from Figure 6 in that the output of the clock x0_dk is detected to be high, and the previous 値 of the clock x0_clk is also high, indicating that the time at this level is long enough. , Can do switching action. The selection signal (S1, S0) output by the switching control circuit 520 is converted to (0, 1) at this time, so the output signal 〇iit_clk is turned to a low level, and the rising edge of the sample_Clk is the time, which is the time. At t3, it is detected that the clock xl_clk is at a high level, the selection signal (S1, S0) output by the switching control circuit 520 is converted into (1, 1), and the output signal oiU_clk is switched to synchronize with the clock xl_dk. Please refer to Fig. 8 for the operation clock diagram of the clock switching architecture 5 in Fig. 5 for converting from clock xl__clk to clock x0_clk. At time t1, the clock selection signal miixa_Sel changes, so the multiplexer 530 is driven to output the clock x〇_clk. At the same time, the switch enable signal switch_H outputted by the comparator 550 is converted to a high level, so the next sample 18 (Please read the precautions on the back of this page to write this page first)-Binding. Thread_ This paper is a good standard for China National Standard (CNS) A4 (210X 297 mm) 538594 4226twfdoc / 005 A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative V. Description of the invention (/?) The rising edge of the clock sample_clk, that is, time t2, detects that the output of the clock xl_dk is at a high level, and the previous 値 of the clock xl_clk is also at a high level, indicating This level is long enough to switch. The selection signal (S1, S0) 输出 output by the switching control circuit 520 is converted to (0, 1) at this time, so the output signal OUT_clk is turned to a low level, and the rising edge of the next sampling clock sample_Clk will be equal to the time. The pulse x0_clk is detected. Until time t3, the clock x0_clk turns to a low level, and the selection signal (S1, S0) output by the switching control circuit 520 is converted into (〇, 〇), and the output signal 〇ut_clk That is, it is switched to synchronize with the clock x〇_clk. Please refer to FIG. 9, which also explains the operation clock diagram of the clock switching architecture 500 of FIG. 5 from clock xl_clk to clock x0_clk. At time t1, the clock selection signal muxa_sel changes, so the multiplexer 530 is driven to output the clock x0_clk. At the same time, the switch enable signal switch_H output by the comparator 550 is converted to a high level, so the next sample clock sample_clk The rising edge, that is, time t2, differs from Figure 8 in that the output of the clock xl_clk is detected as a low level, and the previous 値 of the clock xl_clk is also a low level, indicating that the time at this level is long enough. , Can do switching action. The selection signal (S1, S0) output by the switching control circuit 520 is converted to (1, 0) at this time, so the output signal ut_dk is turned to a high level, and the rising edge of sample_clk, which is time At t3, it is detected that the clock X〇__clk is at a high level, the selection signal (S1, S0) output by the switching control circuit 520 is converted into (0,0), and the output signal out_elk is switched to the current time. Pulse χθ-dk synchronization. Regarding the operation flow of the clock switching architecture 500 in Figure 5, such as No. 1019, this paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the note on the back first to write this page) -Installation · · τ line · 538594 4226twf.doc / 005 A 7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (β) As shown in the figure, in step 1000, determine the current multiplexer MUX 510 The selected output clock is x〇_clk or xl_clk. If it is the xl_clk clock, the register REG B 544 is not written to the new clk_sel 値, and the register REG A 534 is written to the new clk_sel 値. Following step 1020, the multiplexer 5 10 selects an appropriate fixed chirp (the so-called high level or low level) output, and then at step 1030, the multiplexer 510 selects the clock x0_clk output. In step 1000, it is judged that if the current output clock selected by the multiplexer MUX 510 is xl_clk, then step 1040, the register REG A534 is not written into the new elk_sel 値, and the register REG B 544 is Write new clk_sel 値. Then in step 1050, the multiplexer 510 selects an appropriate fixed (GP (so-called high or low level) output), and in step 1060, the multiplexer 5 10 selects the clock Xl_clk output. According to the clock switching architecture of the above-mentioned preferred embodiment of the present invention, a register and a low-order multiplexer are used to perform a latching action on the clock selection signal to control the output clock signal. The hardware complexity of the controller and the switching control circuit is proportional to the number of clock signals to be switched, which can greatly simplify the complexity of the circuit and reduce the manufacturing cost. Please refer to FIG. Π, which illustrates one of the clock switching architecture 1100 according to another preferred embodiment of the present invention. At this time, the clock switching architecture H00 mainly includes a multiplexer mo and a switching control device 1120. The switching control device U20 is configured to receive the clock x0_clk, the clock x1-Clk, the sampling clock sample_clk, and the switching enable signal switch_Η, and output a selection signal (S1, S0), among which the clock is sampled. sample-Clk adopts the desired switching clock x0_clk or ___ 20 CNS in use) A4 specification (21GX 297)
(請先閱讀背面之注意事項I -裝-- —寫本頁) 、?! 線· 538594 4226twf doc/005 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（β ) xl_dk兩者頻率最高者，在此假設時脈xO_dk的頻率高於 時脈xl_clk的頻率，因此，取樣時脈sample_Clk即等於時 脈 xO—elk 〇 而第11圖中的時脈切換架構1100操作時序圖，則如 第12圖所示，爲時脈切換從時脈x0_clk切換到時脈 xl_dk。在時間tl時，切換致能信號switch_H變成高位準， 即開始切換時脈，此時，在下一個取樣時脈sample_clk上 升邊緣，也就是時間t2時，選擇信號（S1，S0)可直接由原來 的(〇,〇)轉爲（1，〇)，也就是輸出信號out_clk暫時轉爲高位 準，而不需判斷x0_clk前一個時脈是高或低位準，也就是 不用判斷此位準時間是否夠長。再接著的下一個取樣時脈 sample_Clk上升邊緣，也就是時間t3時，偵測出時脈xi_clk 爲高位準，於是，可將輸出信號〇ut_clk直接轉會爲與時 脈xl_clk同步，達成時脈切換的動作。 而第13圖所示，爲本實施例中之時脈切換架構11〇〇 從時脈xljlk切換到時脈x〇_clk之操作時序圖。在時間 tl時’切換致能信號switchJH變成高位準，即開始切換時 脈’此時’在下一個取樣時脈sample_clk上升邊緣，也就 是時間t2時，偵測出xl_clk時脈爲低位準，並判斷xl_clk 前一個時脈也是低位準，也就是判斷此位準時間是否夠 長’選擇信號（S1，S0)可直接由原來的（1，1)轉爲（1，0)，也就 是輸出信號out_clk暫時轉爲高位準。再接著的下一個取 樣時脈sample__cik上升邊緣，也就是時間t3時，取樣時脈 sample—elk與時脈x〇_cik相同，因此時脈x〇_ciic也是在上 (請先閲讀背面之注意事項HI寫本頁) 裝· 訂 線· 本紙張尺度適用中國國家檩準（CNS ) A4規格（21〇χ 297公慶） 538594 4226twf.doc/005 ρ^η --- Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（w ) 升邊緣’而此時的輸出信號out_clk又位於高位準，則無 法同步地上升。因此，爲了能同步時脈，所以必須先將輸 出信號〇m_cik轉爲低位準，也就是選擇信號（si，S2)轉爲 (〇，1) 〇而在下一個取樣時脈sample，上升邊緣，也就是 時間t4時，即可將輸出信號〇ut_clk直接轉爲與時脈x〇_cik 同步，達成時脈切換的動作。 而第14圖所示，爲本實施例中之時脈切換架構11〇〇 從時脈xl_clk切換到時脈x〇_clk之操作時序圖。在時間 tl時，切換致能·信號switch_H變成高位準，即開始切換時 脈，此時，在下一個取樣時脈Sample_Clk上升邊緣，也就 '是時間t2時，偵測出xi_clk時脈爲高位準並判斷xl_clk 前一個時脈也是高位準，也就是判斷此位準時間是否夠 長，選擇信號（S1，S0)可直接由原來的（1，1)轉爲（0，1)，也就 是輸出信號〇ut_clk暫時轉爲低位準，因此時間夠長。再 接著的下一個取樣時脈sample_clk上升邊緣，也就是時間 t3時，取樣時脈sample_clk與時脈x0_clk相同，因此時脈 xO_clk也是在上升邊緣，而此時的輸出信號out_clk又位 於低位準，因此可將輸出信號〇ut_dk直接轉爲與時脈 xO_clk同步，達成時脈切換的動作。 關於第13與14圖中的時序圖，因爲係利用取樣時脈 sampk_clk(也就是時脈x0_dk)的上升邊緣作爲判斷的依 據，因此，在時脈xl_clk切換到時脈x〇_dk時，若是將 輸出信號〇ut_clk暫時轉爲高位準（也就是選擇信號 Sl，S0=l，〇)，則需要再轉爲低位準之後再同步。因爲在此 22 ^^^度適用中國國家標準（^奶）八4規格（210';< 297公釐） (請先閲讀背面之注意事 I寫本頁) •裝_ 、11 -線 538594 經濟部智慧財產局員工消費合作社印製 4226twf.doc/005 A7 _______ B7_ 五、發明説明（>| ) 實施例係採用所要切換的時脈中，最高頰率的時脈作爲取 fee時脈。因此’在由低頻轉到此最筒頻率的時脈時，^以 上升邊緣爲基準，則必須先將輸出信號〇u匕clk轉爲低位 準。當然，本實施例的取樣時脈基準逝非居限於上升邊 緣。若是以下降邊緣爲基準，則同樣地若是輸出信號 out一elk信號位於低位準，則必須先將其轉換爲高位準之 後，才能作同步的切換。 本實施例的操作流程圖如第15圖所示，爲以取樣時 脈基準之上升邊緣爲切換依據的時脈切換流程。在步驟 1510時，先判斷是哪一個時脈被選擇。若是要切換到最高 頻之時脈，則進行步驟1512，若是要由最高頻率切換到其 他時脈，則進行步驟1542。 請先參照要切換到最高頻時脈之步驟1512,若是開 始切換時，則接著進行步驟1514，判斷現在的時脈位準是 否夠久，在本實施例中揭露一種利用取樣時脈上升時的原 時脈値與前一個取樣時脈脈波上升的値是否相同來判 斷’然並不限定僅用此方法來完成。接著步驟15 Μ，判斷 時脈位準之値，若是0，則進行步驟1518，使多工器選擇 固定値1輸出，並接著步驟1520讓多工器變動選擇0輸 出·’而若是1，則進行步驟1522，讓多工器選擇0輸出。 在步驟15 18到1520中對多工器多出一次的切換，係因爲 在取樣時脈上升邊緣時要切換輸出時脈，而取樣時脈即爲 最高頻率之時脈，因此，必須將輸出先切換爲〇，才能在 取樣時脈上升邊緣完成切換。接著步驟1524，多工器在此 23 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） (請先閲讀背面之注意事項ιρί寫本頁) •裝· 、訂 線· 538594 4226twfdoc/005 A7 _________B7 ____ 五、發明説明（·〆） 時則可選擇最高頻率的時脈輸出，此時即接著步驟1550 完成切換動作，而沒有任何切換的缺陷（Glitch)產生。 請接著參照要由最高頻率切換到其他時脈的步驟 1542，在決定切換後，則先讓多工器選擇固定値i輸出。 接著步驟1546,判斷所欲切換的時脈位準是否爲丨，若是， 則進行步驟1548，讓多工器直接輸出”被選擇時脈”。此 時，即完成切換時脈的動作。 在本實施例中，提供了一種切換時脈架構，其取樣時 脈係採用在所欲選擇的時脈信號中，最高頻率的時脈。其 優點如上所顯示，不論是其他頻率時脈切換到最高頻率的 時脈，或是由最高頻率的時脈切換到其他頻率的時脈，都 可以較簡化且較快的流程完成時脈切換。因此，可避免取 樣時脈頻率小於所欲選擇時脈所產生的問題。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閲讀背面之注意事 裝-- :寫本頁)(Please read the precautions on the back I-install --- write this page first),?! Line · 538594 4226twf doc / 005 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (β) xl_dk Both For the highest frequency, it is assumed here that the frequency of the clock xO_dk is higher than the frequency of the clock xl_clk. Therefore, the sampling clock sample_Clk is equal to the clock xO_elk 〇 and the clock switching architecture 1100 operation timing diagram in Figure 11 is, As shown in Fig. 12, the clock is switched from the clock x0_clk to the clock xl_dk. At time t1, the switch enable signal switch_H becomes high, that is, the switching clock is started. At this time, at the next sampling clock sample_clk rising edge, that is, at time t2, the selection signals (S1, S0) can be directly changed from the original (〇, 〇) turns to (1, 〇), that is, the output signal out_clk is temporarily turned to a high level, without judging whether the previous clock of x0_clk is high or low, that is, it is not necessary to judge whether the time of this level is long enough. . Then the next sampling clock sample_Clk rising edge, that is, at time t3, it is detected that the clock xi_clk is at a high level, so the output signal OUT_clk can be directly transferred to synchronize with the clock xl_clk to achieve clock switching Actions. FIG. 13 is a timing diagram of the operation of switching the clock from the clock xljlk to the clock x0_clk in this embodiment. At time t1, the 'switch enable signal switchJH becomes high level, that is, the switching clock is started. At this time, at the next sampling clock sample_clk rising edge, that is, at time t2, the xl_clk clock is detected as a low level, and judged xl_clk The previous clock is also a low level, that is, to determine whether the time of this level is long enough. The selection signal (S1, S0) can be directly changed from the original (1, 1) to (1, 0), which is the output signal out_clk Turn to high level temporarily. Then the next sampling clock sample__cik rising edge, that is, at time t3, the sampling clock sample_elk is the same as the clock x〇_cik, so the clock x〇_ciic is also on top (please read the note on the back first) Matters HI write on this page) Binding · Binding · This paper size is applicable to China National Standard (CNS) A4 (21〇χ 297 public holiday) 538594 4226twf.doc / 005 ρ ^ η --- Β7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the Employee Consumption Cooperative V. Invention Description (w) Rising edge ', and at this time the output signal out_clk is at a high level, it cannot rise synchronously. Therefore, in order to be able to synchronize the clock, the output signal om_cik must be turned to a low level, that is, the selection signal (si, S2) is turned to (0, 1) 〇 and the next sampling clock sample, rising edge, also That is, at time t4, the output signal 〇ut_clk can be directly converted into synchronization with the clock x〇_cik to achieve the action of clock switching. FIG. 14 is a timing diagram of the operation of switching the clock from the clock x1_clk to the clock x0_clk in this embodiment. At time t1, the switch enable signal “switch_H” becomes high, that is, the switching clock is started. At this time, at the rising edge of the next sample clock Sample_Clk, that is, at time t2, the xi_clk clock is detected to be high. And judge that the previous clock of xl_clk is also a high level, that is, to determine whether the time of this level is long enough, the selection signal (S1, S0) can be directly changed from the original (1, 1) to (0, 1), which is the output The signal 〇ut_clk goes to a low level temporarily, so the time is long enough. Then the next sampling clock sample_clk rising edge, that is, at time t3, the sampling clock sample_clk is the same as clock x0_clk, so the clock xO_clk is also on the rising edge, and the output signal out_clk at this time is at a low level, so The output signal OUT_dk can be directly converted into synchronization with the clock xO_clk to achieve the operation of clock switching. Regarding the timing diagrams in Figures 13 and 14, because the rising edge of the sampling clock sampk_clk (that is, clock x0_dk) is used as the basis for judgment, when the clock xl_clk is switched to the clock x〇_dk, if it is If the output signal OUT_clk is temporarily turned to a high level (that is, the selection signal S1, S0 = 1, 0), it needs to be turned to a low level and then synchronized. Because here 22 ^^^ degrees apply Chinese national standard (^ milk) 8 4 specifications (210 '; 297 mm) (please read the note on the back first to write this page) • equipment _, 11-line 538594 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4226twf.doc / 005 A7 _______ B7_ V. Description of Invention (> |) The embodiment uses the clock with the highest buccal rate among the clocks to be switched as the fee clock. Therefore, when 'from the low frequency to the clock of this most barrel frequency, ^ is based on the rising edge, then the output signal 〇klk must be turned to a low level. Of course, the sampling clock reference elapsed in this embodiment is limited to the rising edge. If the falling edge is used as a reference, then if the output signal out-elk signal is at a low level, it must be converted to a high level before switching synchronously. The operation flowchart of this embodiment is shown in FIG. 15 and is a clock switching process based on the rising edge of the sampling clock reference. At step 1510, first determine which clock is selected. If it is to switch to the clock with the highest frequency, go to step 1512, if it is to switch to the clock with the highest frequency, go to step 1542. Please refer to step 1512 to switch to the highest frequency clock first. If the switch is started, then step 1514 is performed to determine whether the current clock level is long enough. In this embodiment, a method using the sampling clock rising time is disclosed. It is not limited to use only this method to determine whether the original time pulse is the same as the time when the pulse wave rises during the previous sampling. Then step 15M, determine the clock level, if it is 0, go to step 1518, so that the multiplexer selects a fixed 値 1 output, and then step 1520 let the multiplexer change to choose 0 output · 'and if it is 1, then Go to step 1522 and let the multiplexer select 0 output. The switching of the multiplexer in steps 15 18 to 1520 is because the output clock is switched when the sampling clock rises, and the sampling clock is the clock with the highest frequency. Therefore, the output must be switched first. Switch to 0 to complete the switch at the rising edge of the sampling clock. Then step 1524, here the multiplexer 23 Chinese paper standard (CNS) A4 specifications (210X 297 mm) (please read the precautions on the back first to write this page) • Installation, Threading · 538594 4226twfdoc / 005 A7 _________B7 ____ 5. In the description of the invention (· 〆), the clock output with the highest frequency can be selected. At this time, the switching operation is completed after step 1550 without any switching defect (Glitch). Please refer to step 1542 to switch from the highest frequency to another clock. After deciding to switch, first let the multiplexer select the fixed 値 i output. Following step 1546, it is determined whether the clock level to be switched is 丨, and if so, step 1548 is performed to allow the multiplexer to directly output "selected clock". At this time, the action of switching clocks is completed. In this embodiment, a switching clock architecture is provided. The sampling clock is the clock with the highest frequency among the clock signals to be selected. Its advantages are as shown above. Whether it is the clock of other frequencies switched to the clock of the highest frequency, or the clock of the highest frequency switched to the clock of other frequencies, the clock switching can be completed in a simpler and faster process. Therefore, the problem that the sampling clock frequency is lower than the desired clock can be avoided. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back first ----write this page)
、1T 線 經濟部智慧財產局員工消費合作社印製 24 本紙張尺度適用中國國家檩準（CNS ) A4規格（210X 297公釐）Line 1T Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 24 This paper size applies to China National Standard (CNS) A4 (210X 297 mm)
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| TW88105286A TW538594B (en) | 1999-04-02 | 1999-04-02 | Clock switching architecture and clock switching method thereof |
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| TW88105286A TW538594B (en) | 1999-04-02 | 1999-04-02 | Clock switching architecture and clock switching method thereof |
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