TW538492B

TW538492B - Burn-in test for memories in a wafer

Info

Publication number: TW538492B
Application number: TW91107141A
Authority: TW
Inventors: Noty Tseng; John Liu
Original assignee: Chipmos Technologies Inc
Priority date: 2002-04-08
Filing date: 2002-04-08
Publication date: 2003-06-21

Abstract

A burn-in test for memories in a wafer is provided. A provided wafer has a plurality of electrodes and burn-in electrodes on one surface. During burn-in test, a burn-in contact board fully contacts all electrodes and burn-in electrodes of the wafer for respectively burning in the peripheral circuits and the memory cells.

Description

538492 五、發明說明（l) 【發明領域】本發明係有關於晶圓級預燒測試〔wafer level burn-in test〕技術，特別係有關於一種包含有記憶體之晶圓之預燒試驗方法。【先前技術】在包含有§己憶體之積體電路產品之製造過程中，預燒試驗〔burn in test〕係確保產品信賴度之必要步驟，特別疋在多晶片模組〔m u 1 t i c h i p m 〇 d u 1 e〕或晶片在基板上〔chip 〇n board〕型態等之半導體產品。若不預先以預燒試驗事先剔除容易損壞之晶片，只要一個晶片損壞將導致其它良好晶片無法被使用，故預燒試驗係為老化試驗。 ^為了提昇預燒之效率及達到製程之一貫化，預燒試驗係在半導體晶圓之製造後執行，即晶圓級預燒〔㈣f e r level burn-in test〕，以取代先前針對個別之晶片封裝結構之預燒步驟，並在預燒整個晶圓後係進行電性測試，以分辨出耐用之已知良好晶片〔Kn〇wn G0〇d Die， KGD 〕。 ’ 在中華民國發明專利第455 9 78號「一種晶圓崩應測試方法」中，揭露一種晶圓預燒〔即崩應〕測試方法，其係先提供具有凸塊之晶圓，並設計一具有焊墊之帶狀自動接合捲帶，而後將該捲帶之焊墊電氣接觸晶圓之凸塊，然後對該帶狀自動接合捲帶輪入複數個電壓與複數個電流，以進打測試，但是當此一晶圓級預燒過程運用於記憶體之預538492 V. Description of the Invention (l) [Field of the Invention] The present invention relates to a wafer level burn-in test technology, and particularly relates to a burn-in test method for a wafer containing a memory. . [Previous technology] In the manufacturing process of integrated circuit products containing § memory, burn-in test is a necessary step to ensure product reliability, especially for multi-chip modules [mu 1 tichipm 〇 du 1 e] or a semiconductor product such as a chip on a board. If the vulnerable wafers are not removed in advance by the burn-in test, as long as one wafer is damaged, other good wafers cannot be used, so the burn-in test is an aging test. ^ In order to improve the efficiency of burn-in and achieve the consistency of the process, burn-in test is performed after the semiconductor wafer is manufactured, that is, wafer level burn-in test, to replace the previous individual wafers. The package structure is pre-fired, and the electrical test is performed after the entire wafer is pre-fired to distinguish the durable and known good wafer [Knwn G0d Die, KGD]. '' In the Republic of China Invention Patent No. 455 9 78 "A wafer collapse test method", a wafer burn-in (ie collapse) test method is disclosed, which first provides a wafer with bumps and designs a wafer A strip-shaped automatic bonding reel with solder pads is then electrically contacted with the bumps of the wafer, and then a plurality of voltages and currents are applied to the strip-shaped automatic bonding reel wheel for testing. , But when this wafer-level burn-in process is applied to the memory

538492 五、發明說明（2) 燒時，輸入之電壓除了經由晶片之凸塊尚需經過晶片之周邊電路〔peripheral circuits〕，如緩衝器〔buffer〕與解碼器〔decoder〕，並需要由行或列之解碼器逐一打開記憶體區塊〔memory cell array〕之文字線〔word 1 i n e〕或位元線〔b i t 1 i n e〕，每一片晶圓預燒時間約在 24至72小時，甚至隨著記載體容量不同可達數天之久。 h538492 V. Description of the invention (2) When burning, the input voltage needs to pass through the peripheral circuits of the chip in addition to the bumps of the chip, such as buffers and decoders. The decoders in the row open the word line (word 1 ine) or bit line (bit 1 ine) of the memory cell array one by one. The burn-in time of each wafer is about 24 to 72 hours. The recorded body volume can be up to several days. h

在美國專利公告第2001/0033183號「積體電路之晶圓級預燒與測試之方法與裝置」中，揭示一種較快速之晶圓級預燒測試流程，如第1圖所示，在「開始」步驟6 0 2係將一晶圓放置於一半導體預燒設備内，而後執行「提供電源至晶片」步驟6 0 4，其係提供電源至晶圓上之所有晶片，以進行預燒，並在「穩定晶片」步驟606中穩定晶片之電壓’在「確認」步驟6 08確認所有晶片係為穩定後，執秄一「探測晶片」之步驟6 1 〇，即習知之半導體電性測試，在「確認已測試過全部晶片」6 1 2之後，執行「報告測試結果」步驟614，以供修補或分類，最後「結束」616該預燒測試流程，其中在「提供電源至晶片」之步驟6 〇4，其晶片之電路連接係如弟2圖所示，晶圓上之每一晶片2 〇〇係預先设計有一預燒電路3 0 0，該預燒電路3 〇〇係可被一外部電源供應器5 0 0啟動’如以一外部時序訊號5 〇 6開啟，該外部電源供應器500並具有一正電壓502與一負電壓504，連接至在晶圓邊緣之延伸導接墊1 〇 6，該晶圓另包含有連接導接墊106之環形導線202、切割道導線2〇4與晶片導線20 8，以電性導通至晶片2 0 0之預燒電路3 〇〇，預燒電路3 〇〇具有In U.S. Patent Publication No. 2001/0033183 "Method and Device for Wafer-Level Burn-In and Testing of Integrated Circuits", a faster wafer-level burn-in test process is disclosed. As shown in Figure 1, "Start" step 602 is to place a wafer in a semiconductor burn-in device, and then execute "Supply Power to the Chip" step 604, which provides power to all wafers on the wafer for burn-in. And in the "stabilizing wafer" step 606, stabilize the voltage of the wafer. "After confirming that all the wafers are stable in step 6 08, perform a" probing wafer "step 6 1 0, which is a conventional semiconductor electrical test. After “confirming that all chips have been tested” 6 1 2, execute the “report test results” step 614 for repair or classification, and finally “end” 616 the burn-in test process, of which the step of “providing power to the chip” The circuit connection of the wafer is as shown in Figure 2. Each wafer on the wafer is pre-designed with a burn-in circuit 300. The burn-in circuit 300 can be External power supply 5 0 0 start 'If turned on with an external timing signal 5 06, the external power supply 500 has a positive voltage 502 and a negative voltage 504, and is connected to the extension pad 10 on the edge of the wafer. The wafer additionally contains There are a ring-shaped wire 202, a dicing track wire 204, and a chip wire 208 connected to the conductive pad 106, and the chip 200 is electrically connected to the chip 200, and the chip 3 has a burn-in circuit.

第5頁 538492 五、發明說明一内部振盪電路3 0 2，齡人％咕」n 9 t、，也 t^40 3 ^2 #qnn S ~八一 # μ 至而不品要經過解碼器，預燒電路3 0 0另匕3預L顯示裝置40 0，其連接至一晶片焊塾 4(H，以檢測被儲存之預煥次邻。田卜要1日日片知墊測試流程係能不經由解1貝° & ^ 在一晶圓級預燒，一解碼益而一次預燒晶圓上所有晶片之電路4〇3〕’僅需要數十秒即可完成整片晶圓之預燒1而此—晶圓級預燒燒到晶片之記憶體區塊，無法完全測試到晶片之周Μ 路，故晶片若因周邊電路之缺陷係無法利用此一預燒方法加以剔除’這般測試得到的預燒結果並不能確保晶片是否具有良好之信賴性。Page 5 538492 V. Description of the invention-An internal oscillation circuit 3 02, %% of the old people "n 9 t, and also t ^ 40 3 ^ 2 #qnn S ~ 八一 # μ To the bad product, go through the decoder, The burn-in circuit 3 0 0 and the 3 L display device 4 0 0 are connected to a wafer welding pad 4 (H, to detect the stored pre-gray next neighbor. Tian Bu will be able to test the performance of the film on the 1st day. The circuit of all wafers on the wafer is burned at a wafer level without decoding. 1) It only takes tens of seconds to complete the entire wafer pre-burning. Burn 1 and this—wafer-level pre-burning burns to the memory block of the wafer, and cannot fully test the peripheral circuit of the wafer. Therefore, if the wafer cannot be removed by this pre-burning method due to defects in peripheral circuits The burn-in result obtained by the test does not ensure whether the wafer has good reliability.

【發明目的及概要】 ^本發明之主要目的在於提供一種在晶圓上記憶體之預燒試驗，利用在預燒過程中完全接觸一晶圓上所有之電極端與預燒電極端，經由該預燒電極端係能預燒該晶圓之記憶體區塊’而經由該電極端係能預燒該晶圓之周邊電路，如解碼器〔d e c 〇 d e r〕、編碼器〔e n c 〇 d e r〕或緩衝器〔bu f f er〕，以達到有效率地完整預燒該晶圓。[Objective and Summary of the Invention] ^ The main purpose of the present invention is to provide a burn-in test for memory on a wafer, which uses all contacts on the wafer and all burn-in electrode ends during the burn-in process. The burn-in electrode terminal is capable of pre-burning the memory block of the wafer, and the electrode terminal system is capable of pre-burning peripheral circuits of the wafer, such as a decoder [dec 〇der], an encoder [enc 〇der] or Buffer [bu ff er] to achieve complete burn-in of the wafer efficiently.

依本發明之在晶圓上記憶體之預燒試驗，其係提供一曰曰圓’ d亥晶圓之一表面具有電極端與預燒電極端，在預燒試驗時，以一預燒接觸板電性接觸該晶圓之全部電極端與預燒電極端，經由接觸該些預燒電極端，而施加電壓於該複數個晶片之記憶體區塊，用以預燒記憶體區塊，且經由該些電極端而施加電壓於周邊電路，以預燒該周邊電路，According to the present invention, the burn-in test on the memory on the wafer is provided with an electrode terminal and a burn-in electrode terminal on one surface of the wafer, and during the burn-in test, a burn-in contact is used. The board electrically contacts all electrode terminals and burn-in electrode terminals of the wafer, and applies voltage to the memory blocks of the plurality of wafers by contacting the burn-in electrode terminals to burn-in the memory blocks, and Applying a voltage to the peripheral circuit through the electrode terminals to pre-burn the peripheral circuit,

第6頁 538492Page 6 538492

其預燒溫度約在100 °c至150 °C維持四至七小時，藉以完整預燒遠晶圓’較佳地’該晶圓另包含有備用記憶體區塊〔redundancy memory cell array〕、第二預燒電極端及第二預燒電路，經由第二預燒電極端與第二預燒電路，以預燒該備用記憶體區塊。【發明詳細說明】請參閱所附圖式，本發明將列舉以下之實施例說明：依本發明之在晶圓上記憶體之預燒試驗，一晶圓之預燒試驗與電性測試流程係如第3圖所示，其主要包含之步驟計有：「提供晶圓」1 1、「進行預燒試驗」1 2、「電性測試」1 3、「雷射修補」1 4、「電性測試」1 5、「形成凸塊」1 6及「切割晶圓」1 7等，其詳述如後。首先，在「提供晶圓」之步驟1 1中，如第4及5圖所示，所提供之晶圓20係一體成型包含有複數個〔約數百至上千之數〕晶片21 ，每一晶片21之主動面〔active surf ace〕具有複數個電極端22與預燒電極端23，如焊整〔bond pad〕或凸塊〔bump〕，如第6圖所示，該複數個電極端22係經由周邊電路〔peripheral circuits〕連接至記憶體區塊31 〔memory cell array〕，周邊電路係為行解碼/編碼器3 2〔 c ο 1 u m n d e c 〇 d e r / e n c 〇 d e r〕、列解石馬/ 編碼器33〔row decoder/encoder〕、行與列緩衝器34 〔column & row buffer〕以及輸入/輸出緩衝器〔In put/Out put buffer〕〔圖未繪出〕等等，而預燒電極端23係經由預燒電路35〔 burn-in circuits〕，而直接Its burn-in temperature is maintained at about 100 ° C to 150 ° C for four to seven hours, so that the complete burn-in far wafer is 'preferably'. The wafer also contains a spare memory block (redundancy memory cell array), a second The burn-in electrode terminal and the second burn-in circuit pass through the second burn-in electrode terminal and the second burn-in circuit to burn the spare memory block. [Detailed description of the invention] Please refer to the attached drawings. The present invention will list the following examples: According to the present invention, the burn-in test on the wafer memory, a wafer burn-in test and electrical test flow are As shown in Figure 3, the main steps include: "provide wafers" 1 1. "Perform burn-in test" 1 2. "Electrical test" 1 3. "Laser repair" 1 4. "Electrical "Testing" 15, "forming bumps" 16 and "dicing wafers" 17 etc. The details are as follows. First, in step 11 of “providing a wafer”, as shown in FIGS. 4 and 5, the provided wafer 20 is integrally formed and includes a plurality of (about several hundreds to several thousands) wafers 21. The active surface of the wafer 21 has a plurality of electrode terminals 22 and burn-in electrode terminals 23, such as a bond pad or bump. As shown in FIG. 6, the plurality of electrode terminals 22 It is connected to memory block 31 [memory cell array] via peripheral circuits. The peripheral circuits are row decoder / encoder 3 2 [c ο 1 umndec 〇der / enc 〇der], column calcite horse / Encoder 33 [row decoder / encoder], row and column buffer 34 [column & row buffer] and input / output buffer [In put / Out put buffer] [not shown], etc. Extreme 23 is directly through burn-in circuits 35

第7頁 538492Page 7 538492

五、發明說明（5) 連接至記憶體區塊31〔memory cell array〕，不經過$ 邊電路，通常記憶體區塊3 1係包含複數條縱向之文字線〔word line〕與橫向之位元線〔bit line〕〔圖未繪出〕，在文字線與位元線之交錯處係為記憶體胞室〔memory ce 1 1 s〕，利用該預燒電路35係能不需要通過周邊電路之行解碼器3 2與列碼器3 3而能直接打開並輸入訊號至記憶體區塊3 1，關於這種内置型預燒電路3 5於晶片之設計已有多種習知之構造，如美國專利第5, 936, 9 1 0號與美又國專利第5，9 5 6，2 7 9號’故不再贅述，該些預燒電極端2 3 係分佈於晶片21之正面〔act ive surf ace〕，或者該些預燒電極端23係分佈於晶圓20之無晶片區域〔圖未繪出f，以連接所有之晶片2 1之記憶體區塊3 1。V. Description of the invention (5) Connected to memory block 31 (memory cell array), without passing through the $ side circuit, usually the memory block 31 contains a plurality of vertical word lines and horizontal bits Line [bit line] (not shown in the figure), the memory cell [memory ce 1 1 s] at the intersection of the text line and the bit line, using the burn-in circuit 35 series can pass through the peripheral circuit The row decoder 32 and the column code 33 can directly open and input signals to the memory block 31. There are many conventional structures for the design of this built-in burn-in circuit 35 in the chip, such as the US patent No. 5, 936, 9 1 0 and U.S. Patent No. 5, 9 5 6, 2 7 9 'so it will not be repeated, these burn-in electrode terminals 2 3 are distributed on the front side of the wafer 21 [act ive surf ace], or the burn-in electrode terminals 23 are distributed in the waferless area of the wafer 20 [f is not shown in the figure, so as to connect all the memory blocks 31 of the wafer 21.

之後’在「進行預燒試驗」之步驟丨2中，係將該晶圓 20放置於一種全接觸晶圓〔fully wafer contact〕之預燒設備，其中一種可行設備之型號為 TEL(Vendor), WAX- 220 0 Aehr Test Systems, FOX system，如第7圖所示，其包含有一預燒接觸板4〇〔burn-in contact board〕，該預燒接觸板4〇之探觸端 41〔 contact tip〕係能電性接觸晶圓2〇之全部電極端22 與預燒電極端23，經由接觸晶圓2〇之預燒電極端23與預燒電路35而直接施加電壓於該複數個晶片21之多個記憶體區塊3 1，由於不需要通過周邊電路之行解碼器3 2與列碼器 33，故能同時預燒所有晶片21之記憶體區塊31，+需要逐 -打開文字線或位元線，僅需要3()謂秒即可預燒到晶圓Afterwards, in step 2 of "Perform a burn-in test", the wafer 20 is placed in a fully-wafered pre-burning device, and one of the feasible devices is TEL (Vendor). WAX- 220 0 Aehr Test Systems, FOX system, as shown in FIG. 7, it includes a burn-in contact board 40 (burn-in contact board), and the probe 41 of the burn-in contact board 40 [contact tip ] It is capable of electrically contacting all the electrode terminals 22 and the burn-in electrode terminals 23 of the wafer 20, and directly applying a voltage to the plurality of wafers 21 through the burn-in electrode terminals 23 and the burn-in circuit 35 of the wafer 20. Multiple memory blocks 31, because it is not necessary to pass the peripheral decoders 3 2 and the column code 33, it can pre-burn the memory blocks 31 of all chips 21 at the same time, + need to open the text line or Bit line, only need 3 () seconds to burn-in to wafer

^38492 五、發明說明（6) 2 0上所有晶片2 1之記憶體區塊3 1，在此一預燒過程中，預繞溫度約在100 t至150 °C，其預燒熱量係由預燒設備之烤箱傳導至該晶圓20 ;並且經由接觸晶片21之電極端22，而施加一適當電壓於周邊電路，如行解碼/編碼器32、列解碼/編碼器3 3、行與列緩衝器3 4及輸入/輸出緩衝器等等，而在此一預燒晶片2 1周邊電路之過程，不需要等待記憶體區塊31之預燒，事實上，記憶體區塊31已完成預燒，&此 —預燒時間係約在四至七小時即可完成，故兩種不同之預燒路徑係藉由同一預燒設備完成，減少搬移與儲放步驟。'^ 38492 V. Description of the invention (6) The memory block 31 of all the chips 21 on 2 0. During this burn-in process, the pre-winding temperature is about 100 t to 150 ° C. The oven of the burn-in equipment is conducted to the wafer 20; and by contacting the electrode terminal 22 of the wafer 21, an appropriate voltage is applied to the peripheral circuits, such as row decoder / encoder 32, column decoder / encoder 3 3, rows and columns Buffer 34, input / output buffer, etc., and in this process of burning the peripheral circuit of the chip 21, there is no need to wait for the burn-in of the memory block 31. In fact, the memory block 31 has completed the burn-in. Burning, & this—The burn-in time can be completed in about four to seven hours, so two different burn-in paths are completed by the same burn-in equipment, reducing the steps of moving and storing. '

在完成預燒試驗後，進行「電性測試」1 3之步驟，即所謂的修補前之測試〔pre-repa i r test〕，其係將該曰圓20放置於一半導體測試機台，以其探測卡〔pr〇be曰 card〕探觸晶片21之電極端22，以取得測試結果，通a上半導體測試機台係連接有一記憶體修補分析裝置〔After the burn-in test is completed, the "electrical test" step 13 is performed, the so-called pre-repa ir test, which is to place the circle 20 on a semiconductor test machine, and The probe card [pr0be card] touches the electrode terminal 22 of the chip 21 to obtain the test result. A memory repair analysis device is connected to the semiconductor test machine on the a

Repair Analysis apparatus，MRA apparatus〕，當、、則 J 結果傳輸至記憶體修補分析裝置時，可計算與分析為右。式之修補 > 料，以供雷射修補。而在「雷射修補」丨4 2沭用係依據先前測試與分析的資料以雷射裝置照射晶圓2〇 =驟當位置之熔絲〔fuse〕，以修補晶片。適修補後之晶圓係能直接進行^切割晶圓」i 7之牛以製備良好之裸晶片〔K G D〕，但較完整的製程係在射修補」1 4之後進行第二次「電性測試」丨5，以確雷修補之品質，以避免因分析錯誤或雷射照射不良造‘'射誤，此外，若晶片21係被要求為覆晶接合〔fHp chi ^錯Repair Analysis apparatus, MRA apparatus], when J, then J results are transferred to the memory repair analysis device, the calculation and analysis are right. Repair > material for laser repair. In the "laser repair", 4 2 is used to irradiate the wafer with a laser device at 20 = sudden position fuse according to the data of previous testing and analysis to repair the wafer. After repairing, the wafer can be directly ^ cut wafer "i 7 bull to prepare a good bare wafer [KGD], but a more complete process is the second" electrical test "after the shot repair 14 "5, in order to confirm the quality of lightning repair, to avoid errors caused by analysis errors or poor laser irradiation. In addition, if the wafer 21 is required to be flip-chip bonding [fHp chi ^ wrong

538492 五、發明說明（7) 型態、供捲V承載封裝〔Tape Carrier Package〕或覆晶薄膜封裝〔Chip 〇n Film〕之用，則可執行「形成凸塊」 1 6 t步驟’其係可在「雷射修補」H之後形成複數個凸塊於該些晶片之電極端〔圖未繪出〕，例如以電鍍〔plating〕、印刷〔printing〕或蒸鑛〔evaporation〕等技術形成凸塊，最後再「切割晶圓」1 7，以形成單離之具凸塊之晶片’此外，本發明之晶圓之預燒測試流程亦可適用於製造晶圓級晶片尺寸封裝〔wafer ievel chip scale package〕，其係在「形成凸塊」16之前先在晶圓 2〇表面形成一封膠層，如聚亞醯胺或苯環丁烯〔Benez〇 Cyclobutene〕，以製備晶片尺寸封裝結構。因此，本發明之晶圓之預燒測試流程係以完全接觸晶圓之晶圓級預燒方式提供已知良好晶片〔Kn〇wn G〇〇d Die，KGD〕之完整解決方案，有效率地預燒晶片體區：與周邊電路，此外，較佳地，在「提供晶圓」n之步 =，如第6圖所示，晶圓20係另包含有備用記憶體區塊 36〔redundancy memory cen array〕、第二預燒電 38及第二預燒電路37，當預燒接觸板4〇電性接觸晶圓⑸之電極端22與預燒電極賴時，同時電性接觸該第二g _ 極端38，經由第二預燒電極端38與第二預燒電路π，：燒該備用記憶體區塊36，以提供完整而呈預燒方案。扠仏70 1而具效率之晶圓級預故本發月之保遵辄圍當視後附之申請專者為準，任何熟知此項技蓺軏圍所界夂貝筏π者，在不脫離本發明之精神和538492 V. Description of the invention (7) Type, for roll carrier package [Tape Carrier Package] or chip on film package [Chip On Film], you can perform "forming bumps" 1 6 t step 'system After the "laser repair" H, a plurality of bumps can be formed on the electrode terminals of the wafers (not shown), for example, the bumps can be formed by techniques such as plating, printing, or evaporation. Finally, “cut the wafer” 17 again to form a single-off wafer with bumps. In addition, the burn-in test process of the wafer of the present invention can also be applied to the manufacture of wafer-level wafer-size packages [wafer ievel chip scale package], which forms an adhesive layer on the surface of the wafer 20, such as polyimide or benzocyclobutene [Beenez Cyclobutene], before the "bump formation" 16 to prepare a wafer-size package structure. Therefore, the wafer burn-in test process of the present invention provides a complete solution of a known good wafer [Kn〇wn God Die, KGD] in a wafer-level burn-in method that fully contacts the wafer, efficiently Pre-burned wafer body area: and peripheral circuits. In addition, preferably, at the step of “providing the wafer” n =, as shown in FIG. 6, the wafer 20 further includes a spare memory block 36 [redundancy memory cen array], the second burn-in electricity 38 and the second burn-in circuit 37, when the burn-in contact plate 40 electrically contacts the electrode terminal 22 of the wafer ⑸ and the burn-in electrode, it also electrically contacts the second g _ Extreme 38, through the second burn-in electrode terminal 38 and the second burn-in circuit π :: Burn the spare memory block 36 to provide a complete and burn-in scheme. Fork 70 1 and efficient wafer-level pre-determined warranty compliance this month will be subject to the attached application. Anyone who is familiar with the technical boundaries of this technology will not be affected. Deviate from the spirit of the invention and

538492 五、發明說明（8) 範圍内所作之任何變化與修改，均屬於本發明之保護範圍。 Φ ΙΪΗΪ 第11頁 538492 圖式簡單說明【圖式說明】第1圖：在美國專利圓級預燒與燒測試流程在美國專利圓級預燒與之電路連接依本發明之之預燒與測依本發明之晶圓之正面依本發明之晶圓之部份第2圖第3圖第4圖第5圖第6圖第7圖公告2 0 0 1 / 0 0 3 3 1 8 3號「積體測試之方法與裝置」中，一圖；公告2 0 0 1 / 〇〇 3 3 1 8 3號「積體測試之方法與裝置」中，晶不意圖；在晶圓上記憶體之預燒試驗试流程圖；在晶圓上記憶體之預燒試驗，所提供示意圖；電路之晶晶圓級預電路之晶圓級預燒曰a 圓在晶圓上記憶體之晶片局部放大示意依本發明之在晶圓上記憶體之上其中一晶片之電路連接示意 :本發明之在晶圓上記憶體之 k接觸板電性接觸其中一晶片預燒試驗圖；預燒試驗圖；及預燒試驗之全部電，所提供，在晶圓，以一預極端之截538492 V. Any changes and modifications made within the scope of the description of the invention (8) belong to the protection scope of the present invention. Φ ΙΪΗΪ Page 11 538492 Brief description of the drawings [Illustration of the drawings] Figure 1: The test process of round burn-in and burn test in the US patent Round burn-in and circuit connection in the US patent Round burn-in and test according to the present invention The front side of the wafer according to the present invention. Part of the wafer according to the present invention. Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Announcement 2 0 0 1/0 0 3 3 1 8 3 " In the method and device for integrated test ", a picture; in the announcement" Method and device for integrated test "No. 2 01/00 03 3 183, the crystal is not intended; the pre-memory of the memory on the wafer Burn test test flow chart; burn-in test of the memory on the wafer, the schematic diagram provided; the crystal of the circuit wafer-level pre-circuit of the wafer-level burn-in The circuit connection diagram of one of the wafers on the memory on the wafer of the present invention: the k-contact board of the on-wafer memory of the present invention electrically contacts one of the wafers; a burn-in test chart; a burn-in test chart; and All of the electricity for the burn test is provided on the wafer with a pre-cut extreme

面示意圖〇【圖號說明】 11 提供晶圓 12 14 雷射修補 15 16 形成凸塊 17 20 晶圓 21 23 預燒電極端進行預燒試驗1 3 第二次電性測試切割晶圓晶片 2 2 電性測試電極端Schematic drawing 〇 [Illustration of drawing number] 11 Provide wafer 12 14 Laser repair 15 16 Form bump 17 20 Wafer 21 23 Burn-in electrode terminal for burn-in test 1 3 Second electrical test dicing wafer 2 2 Electrical test electrode terminal

第12頁 538492 圖式簡單說明 31 記憶體區塊 32 33 列解碼/編碼器34 35 預燒電路 36 37 第二預燒電路 38 40 預燒接觸板 41 1 0 6 導接墊 200 晶片 208晶片導線 3 0 0預燒線路 4 0 0預燒顯示裝置 404晶片焊墊 5 0 0外部電源供應器 502 正電壓 5 0 6 外部時序訊號 602 開始 6 0 6 穩定晶片 6 1 0探測晶片 6 1 4 報告測試結果行解碼/編碼器行與列緩衝器備用記憶體區塊第二預燒電極端探觸端 2 0 2 環形導線 2 0 4 切割道導線 302内部振盪電路 4 0 2訊號 4 0 3晶片電路 5 0 4負電壓 6 0 4 提供電源至晶片 6 0 8 確認晶片是否穩定 6 1 2 確認是否已測試過全部晶片 6 1 6 結束 i!」Page 12 538492 Brief description of the diagram 31 Memory block 32 33 column decoder / encoder 34 35 Burn-in circuit 36 37 Second burn-in circuit 38 40 Burn-in contact plate 41 1 0 6 Lead pad 200 Chip 208 Chip wire 3 0 0 burn-in circuit 4 0 0 burn-in display device 404 chip pad 5 0 0 external power supply 502 positive voltage 5 0 6 external timing signal 602 start 6 0 6 stabilize the chip 6 1 0 detect the chip 6 1 4 report test Result row decode / encoder row and column buffer spare memory block second burn-in electrode end probe end 2 0 2 ring wire 2 0 4 cut wire 302 internal oscillation circuit 4 0 2 signal 4 0 3 chip circuit 5 0 4 Negative voltage 6 0 4 Supply power to the chip 6 0 8 Check whether the chip is stable 6 1 2 Check whether all chips have been tested 6 1 6 End i! ''

第13頁Page 13

Claims

538492538492

、一種在晶提供一晶預燒電路、些電極端係而該些預燒體區塊；及進行預燒之全部之電電路，而施預燒記憶體電路，以預圓上記憶體之預燒圓，该晶圓包含有複數個電極端及複經由該周邊電路電電極端係經由該預試驗，其係以預極端與預燒電極端加電壓於該複數個區塊，且經由該些燒該周邊電路。試驗方法’其步驟包含：記憶體區塊、周邊電路、數個預燒電極端，其_今性連接至該記憶體區塊，燒電路電性連接至該記憶燒接觸板電性接觸該晶圓 ’經由預燒電極端與預燒晶片之記憶體區塊，用$ 電極端而施加電壓於周二如申請專利範圍第1項所述之在晶圓上記憶體之預择試驗方法，其另包含：電性測試該晶圓，以分几預燒試驗之記憶體。斤出通過、如申請專利範圍第1項所述之在晶圓上記憶體之預声試驗方法，其中預燒試驗之溢度係維持在1 0 0 °c至1 5 〇 ^ 之間。、如申請專利範圍第1項所述之在晶圓上記憶體之預燒試驗方法，其中預燒時間係在四至七小時之間。〜、如申請專利範圍第1項所述之在晶圓上記憶體之預燒試驗方法，其中該晶圓另包含有備用記憶體區塊、第= 預燒電極端及第二預燒電路’經由第二預燒電極端與第一預燒電路，以預燒該備伟私憶體區塊。A method of providing a crystal burn-in circuit on the crystal, and some electrode terminals are connected to the burn-in block; and all the electrical circuits for burn-in, and the burn-in memory circuit is applied to pre-circulate the memory on the circle. The wafer is burned, and the wafer includes a plurality of electrode terminals and an electrical electrode terminal through the peripheral circuit. The pre-test is performed by applying a voltage to the plurality of blocks by using a pre-extreme and a burn-in electrode terminal. The peripheral circuit. The test method includes the steps of: a memory block, a peripheral circuit, and several burn-in electrode terminals, which are connected to the memory block, and the burn circuit is electrically connected to the memory burn contact plate to electrically contact the crystal. The circle 'passes through the burned electrode terminal and the memory block of the burned wafer, and uses the $ electrode terminal to apply a voltage to the pre-selected test method of the memory on the wafer as described in item 1 of the patent application on Tuesday. Including: Electrically testing the wafer to burn-in test memory. The test method for pre-sounding of memory on a wafer as described in item 1 of the scope of patent application is passed. The pre-burn test overflow is maintained between 100 ° C and 150 ° C. The burn-in test method for memory on a wafer as described in item 1 of the scope of the patent application, wherein the burn-in time is between four and seven hours. ~ The burn-in test method for memory on a wafer as described in item 1 of the scope of the patent application, wherein the wafer further includes a spare memory block, a first burn-in electrode terminal, and a second burn-in circuit. The second burn-in electrode terminal and the first burn-in circuit are used to burn-in the Weiwei private memory block.