TW536755B

TW536755B - Method for removing surface copper particle of copper layer

Info

Publication number: TW536755B
Application number: TW91113938A
Authority: TW
Inventors: Jia-Liang Chiue; Rung-Liang Jian; Shr-Ming Wang
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-06-25
Filing date: 2002-06-25
Publication date: 2003-06-11

Abstract

The method of the present invention can prevent the copper surface particle interfering the defect inspection during chemical electro-plating process. First, define damascene pattern in the dielectric layer on the semiconductor substrate. Then put the substrate into the electro-plating tank of the electro-plating tool to conduct the copper electro-plating step and form a copper layer on the upper surface of the dielectric layer. The damascene patterns are filled up as well. At the same time, the copper particles will be generated on the copper layer surface to interfere the defect inspection. Second, put the substrate in the edge-cleaning tank to proceed the edge clean step to remove the copper layer on the wafer edge. Then transfer the substrate into the spray clean type spin tank and perform highly pure DI water cleaning procedure. After the cleaning, proceed a chemical solution cleaning procedure in the same tank to remove the copper particle on the copper surface. Finally spin dry the substrate with high rotation speed.

Description

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五、發明說明（l) 發明領域：本發明與一種在化學電鑛程序中避免銅層表面銅微粒干擾缺陷檢測之方法有關’特別是一種在高純度去離^水清洗程序後，於同一喷洗式旋轉槽中施以化學藥劑清洗程序以移除銅微粒之相關方法。 / & 發明背景：V. Description of the invention (l) Field of the invention: The present invention relates to a method for avoiding the interference detection of copper particles on the surface of a copper layer in a chemical power ore process, particularly a high-purity deionization water cleaning process, in the same spray A method for removing the copper particles by applying a chemical cleaning procedure in the washing type rotating tank. / & Background of the Invention:

隨著半導體工業持續的進展，在超大型積體電路 ⑶LSI)的開發與設計中’為了符合高密度積體電路之設計趨勢，各式元件之尺寸皆降至次微米以下。並且由於元件不斷的縮小，也導致在進行相關半導體製程時，往往遭遇工前所未有之難題，且製程複雜程度亦不斷提高。一般而 δ ’積體電路包括在晶圓上某特定區域中，形成數以百萬计的元件，以及用來連接這些元件的電子連結結構，以便執行所需之特定功能。因此積體電路的性能，除了依靠所含元件之性能及可靠度外，更需要無數精密細微的金屬内連線’以便能有效傳遞元件間的電子訊號。特別是隨著積體電路尺寸持續的縮小，當前的積體電路設計，已朝著多重金屬内連線發展。With the continuous progress of the semiconductor industry, in the development and design of very large integrated circuits (CDLSI), in order to meet the design trend of high-density integrated circuits, the size of various components has been reduced to sub-micron. And due to the continuous shrinking of components, it has often led to unprecedented difficulties in the related semiconductor manufacturing process, and the complexity of the process has also increased. Generally, a δ 'integrated circuit includes millions of components formed in a specific area on a wafer, and an electronic connection structure for connecting these components in order to perform a specific function required. Therefore, in addition to the performance and reliability of the contained components, the performance of the integrated circuit also requires countless precise and fine metal interconnections' in order to effectively transfer the electronic signals between the components. Especially as the size of integrated circuits continues to shrink, current integrated circuit designs have evolved toward multi-metal interconnects.

^ 然而在多重金屬内連線的相關製程中，由於受制於微 ^解析度的限制、曝光聚焦（Focus)的誤差、影像傳遞的 ^，度與解析度（Reso lut ion)與可使用空間的縮小，導致肷製程（damascene process)的相關技術，受到廣泛的 &展與運用。並且，藉著使用單一鑲嵌製程（singU^ However, in the related process of multi-metal interconnects, due to the limitation of micro ^ resolution, the error of exposure focus (Focus), the image transfer, the resolution and resolution (Reso lut ion) and the available space. The shrinkage has led to the widespread use of & technologies related to the damascene process. And, by using a single mosaic process (singU

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五、發明說明（2) damascene)或是雙重鑲嵌製程（dual技術，可以更精確細緻的製造多重金屬内連線（mu丨t丨p j e inter-connectlons)，因此被大量的應用於大型積内連線之製程中。、 ’链金屬材料往往成為業界隨著半導體元件的積集度不線接觸結構，亦遭遇了極多 ’紹原子容易與矽底材發生，而產生’'尖峰現象”，並導前的半導體工業中，往往試低的銅金屬，來取代傳統大降低電阻-電容遲滯效應。電致遷移率，是以可應用於且，由於金屬有機氣相沉積可有效的提供銅製程極佳連線製作之課題，獲得了廣對傳統的半導體製程而言優先考慮的導線材料。然而，斷上昇，使用金屬鋁來作為連的困難。例如，在高溫環境中交互擴散（inter-di f fusion): 致紹線接觸不良。因此，在目著使用導電性較高且電阻率較量使用之鋁金屬，以便進一步特別是由於銅金屬具有較低的半導體製程中之連線結構。並法（M0CVD)與電鍍沉積等方法的階梯覆蓋性，也使得有關銅泛的研究與運用。，銅金屬的沈積是利用化 (electrochemical lectroless plating )，換反應或氧化還原反應，而沈積於半導體中之方一般說來，在半導體製程中學電鍍程序所形成的。化學電鍍 Plating)，又稱為無電電鍍& 疋種不使用電氣法，而利用置，金屬，鹽水溶液的金屬離子析出 536755 五、發明說明（3) )不用通電即可得到均一的電鍍層；（2)電鍍層與底材之間孔隙發生的機率較小，且其密著性、耐蝕性與对磨耗性亦較好；（3 )操作不如電艘程序複雜。V. Description of the invention (2) damascene) or dual damascene process (dual technology), which can manufacture multiple metal interconnects (mu 丨 t 丨 pje inter-connectlons) more accurately, so it is widely used in large-scale interconnects. In the manufacturing process of wire, "chain metal materials often become the industry's non-linear contact structure with the accumulation of semiconductor components, and also encounter a lot of" Shao atoms easily occur with silicon substrates, and produce "spikes", and In the leading semiconductor industry, low copper metal is often used to replace the traditional large reduction of the resistance-capacitance hysteresis effect. Electromobility is applicable and, because metal organic vapor deposition can effectively provide copper process electrodes The problem of good connection manufacturing has obtained wire materials that are widely considered as a priority for traditional semiconductor processes. However, it is difficult to use aluminum as the connection when the break rises. For example, inter-diffusion in high temperature environments (inter-di f fusion): Causes poor contact between the wires. Therefore, the purpose is to use aluminum metal with higher conductivity and resistivity, in order to further Metal has a lower wiring structure in the semiconductor process. The step coverage of methods such as M0CVD and electroplating deposition has also made the research and application of copper pan. The deposition of copper metal is electrochemical lectroless plating ), Exchange reaction or redox reaction, and the side deposited in the semiconductor is generally formed by the plating process in the semiconductor process. Chemical plating), also known as electroless plating & this type does not use electrical methods, and Precipitation of metal ions using metal, salt, and saline solution 536755 V. Description of the invention (3)) Uniform plating layer can be obtained without electricity; (2) The probability of occurrence of pores between the plating layer and the substrate is small, and its denseness It also has better adhesion, corrosion resistance and abrasion resistance; (3) the operation is not as complicated as the electric boat procedure.

當對已形成鑲嵌圖案於半導體底材上方之介電層中之半導體進行完化學電鍍程序時，會在其上表面形成二銅層，且填充於鑲嵌圖案中。其中，在此銅層之表面會具有各種缺陷。請參閱第一圖，此圖揭露了不同的缺陷及其產生之機率。如圖所示，這些缺陷包括了 7〇%的銅微粒（Cu ball) 、10%的火山口（crater) 、6%的連續狀銅微粒 (Cu bead) 、4°/。的銅缺失（Cu i〇ss) 、4%的污染微粒掉落（fall on) 、2% 的化學污染（chemicai stain) 、2% 的點線（dotline)以及2%的未知（unkn0Wn)缺陷。由圖中可以發現，銅微粒產生的機率佔所有缺陷產生機率的 7 0 %。但值得注意的疋，雖然銅微粒並不會造成製程的良率下降，但卻會干擾真正影響製程良率之重要缺陷的檢义測’因此本發明揭露了一種移除位於鋼層表面之銅微粒，進而有效檢測缺陷並加以移除，以增進製程良率之方法。發明目的及概述：本赉明之主要目的為提供一種對半導體進行化學電鍍程序時，避免銅層表面銅微粒干擾缺陷檢測之方法。又本叙明之另一目的為提供一種對半導體進行化學電錢程序時，於高純度去離子水清洗程序後，在同一喷洗式^When the electroless plating process is performed on a semiconductor in which a damascene pattern has been formed on a dielectric layer over a semiconductor substrate, a copper layer is formed on its upper surface and filled in the damascene pattern. Among them, the surface of the copper layer may have various defects. Please refer to the first picture, which reveals the different defects and their probability. As shown in the figure, these defects include 70% of copper particles (Cu ball), 10% of crater, 6% of continuous copper particles (Cu bead), 4 ° /. Cu Ioss, 4% fall on polluted particles, 2% chemicai stain, 2% dotline, and 2% unknown (unkn0Wn) defects. It can be found from the figure that the probability of copper particles generation is 70% of the probability of all defects. However, it is worth noting that although copper particles do not cause a decrease in the yield of the process, they will interfere with the detection of important defects that really affect the yield of the process. Therefore, the present invention discloses a method for removing copper on the surface of a steel layer. A method to effectively detect and remove defects to improve process yield. OBJECTS AND SUMMARY OF THE INVENTION: The main purpose of the present invention is to provide a method for preventing copper particles on the surface of the copper layer from interfering with defect detection when performing a chemical plating process on a semiconductor. Another purpose of this description is to provide a method for chemical electrochemistry of semiconductors, after the high-purity deionized water cleaning process, in the same spray cleaning method ^

第6頁 536755 五、發明說明（4) 轉槽中施以化學藥劑清洗程序，以移除銅微粒之方法本散明之再一目的為提供一種對半導體進行化學電鍍程序時，於高純度去離子水清洗程序後，纟同-喷洗式旋轉槽中以稀釋之洗邊溶液接著進行清洗程序，以移除銅微粒之方法。Page 6 536755 V. Description of the invention (4) A chemical cleaning procedure is applied to the rotor to remove copper particles. Another purpose of this disclosure is to provide a high-purity deionization process for the chemical plating process of semiconductors. After the water cleaning process, the same method is used to remove the copper particles by using a diluted edge cleaning solution in a spray-wash rotating tank.

、一種在化學電鍍程序中避免銅層表面銅微粒干擾缺陷檢測之方法三首先，定義鑲嵌圖案於半導體底材上方之介電層中，接著將其置於化學電鑛機台之電鑛槽中進行電鑛銅程序，而形成銅層於介電層之上表面，且填充於鑲嵌圖案中。其中，在此銅層之上表面會產生干擾缺陷檢測之銅微粒。隨後將此半導體底材置於晶圓邊緣清洗槽中，利用約含有22 %硫酸、1.1 %過氧化氫與76 9 %高純度去離子水之洗邊溶液進行洗邊程序’用以移除位於半導體底材邊緣之銅層，士在移除之後將半導體底材移入喷洗式旋轉槽中，並施以高純度去離子水清洗程序。接著，#此清洗完之半導體底材，置於喷洗式旋轉槽中利用已稀釋6〜12倍之洗邊溶液進行清洗程序約4秒鐘，以移除位於銅層表面之銅微粒。最後，利用高轉速旋乾半導體底材。發明詳細說明· -種在化學電It程序中避免銅層表A method to prevent copper particles on the surface of the copper layer from interfering with the defect detection in the process of chemical plating. First, define the mosaic pattern in the dielectric layer above the semiconductor substrate, and then place it in the electric ore tank of the chemical electric machine. A copper ore process is performed to form a copper layer on the upper surface of the dielectric layer and fill it in the mosaic pattern. Among them, copper particles on the surface of the copper layer that interfere with defect detection will be generated. This semiconductor substrate was then placed in a wafer edge cleaning bath and an edge cleaning process was performed using an edge cleaning solution containing approximately 22% sulfuric acid, 1.1% hydrogen peroxide, and 76 9% high-purity deionized water to remove the After the copper layer on the edge of the semiconductor substrate is removed, the semiconductor substrate is moved into a spray-washing rotating tank and subjected to a high-purity deionized water cleaning procedure. Next, # this cleaned semiconductor substrate is placed in a spray-washing rotating tank using a 6 to 12-fold diluted edge cleaning solution for about 4 seconds to remove copper particles on the surface of the copper layer. Finally, the semiconductor substrate is spin-dried using a high speed. Detailed description of the invention ·-a way to avoid the copper layer surface in the chemical electricity It program

第7頁 536755Page 7 536755

底材50令。此半導體底材5〇可為一 <100〉或<111〉晶向之單Substrate 50 reams. The semiconductor substrate 50 may be a single crystal of < 100> or < 111> crystal orientation.

曰曰夕ί疋位於絕緣層上之石夕基底（siHcon on insulator， S〇I)等二且在形成介電層52以前，半導體底材5〇上已製作了積體電路所需之各式主動元件、被動元件、肖週圍電路等等（未標示於圖中）。換言之，在此半導體底材5〇的表面^ ’已具有各式所需之功能層與材料層。至於介電層52 ^製作，則可由氧化矽或氮化矽來形成。例如，利用化學虱，沈積法（CVD)以四乙基矽酸鹽（TE〇s)可形成氧化矽。或著，可在大約4〇〇至45 0。C的爐中通入反應氣體SiH4， N20及NH3/而^形成氮化矽。另外，亦可以化學氣相沉積法 (LPCVD)开y成氣；5夕玻璃（[Μ)或未摻雜石夕玻璃（usg)，來構成上述之介電層52。口接著仍請參照第二圖，對介電層52施以微影蝕刻製耘，在介電層52中形成鑲嵌圖案54，且曝露出半導體底材 50之部分上表面。一般而言，在定義上述鑲嵌圖案“時，可先在介電層52上先形成光阻層，繼而轉移光罩上之鑲嵌圖案至光阻層中。接著，利用此光阻層作為蝕刻罩冪，對介電層52進行蝕刻程序，而定義鑲嵌圖案54於其中。Before the formation of the dielectric layer 52, the semiconductor substrate 50 has produced various formulas required for integrated circuits, such as siHcon on insulator (SOI), etc. on the insulating layer. Active components, passive components, circuits around Xiao, etc. (not shown in the figure). In other words, the surface of the semiconductor substrate 50 already has various functional layers and material layers required. As for the fabrication of the dielectric layer 52, it can be formed of silicon oxide or silicon nitride. For example, using chemical lice, deposition (CVD) with tetraethyl silicate (TE0s) can form silicon oxide. Alternatively, it can range from about 400 to 450. In the furnace of C, the reaction gases SiH4, N20, and NH3 / are passed to form silicon nitride. In addition, chemical vapor deposition (LPCVD) can also be used to form y gas; 5X glass ([M]) or undoped Shix glass (usg) to form the above-mentioned dielectric layer 52. Still referring to the second figure, the lithographic etching process is performed on the dielectric layer 52 to form a mosaic pattern 54 in the dielectric layer 52, and a part of the upper surface of the semiconductor substrate 50 is exposed. In general, when defining the above mosaic pattern, a photoresist layer may be first formed on the dielectric layer 52, and then the mosaic pattern on the photomask is transferred to the photoresist layer. Then, the photoresist layer is used as an etching mask. Power, the dielectric layer 52 is subjected to an etching process, and a mosaic pattern 54 is defined therein.

w參閱第二圖，此圖揭示了化學電鍍機台9 〇内之流程槽。當鑲嵌圖案54定義完成後，接著將此半導體底材5〇置於電鍍槽1〇〇中進行電鍍銅之程序，以沈積銅層56於介電層52上’且填充於鑲嵌圖案54中（如第四圖所示）。值得注意的是，在將半導體底材5〇置於化學電鍍機台内之電鍍槽中進行電鍍銅程序之前，會先形成阻障層於鑲嵌圖案^ 536755 五、發明說明（6) 之側壁與所曝露之半導體底材50上表面，以防止後續製作之銅層56，與介電層52及半導體底材5〇間發生擴散現象，而產生尖峰效應（spiking effect)。一般而言，形成阻障層之材質可選擇鈦（T i )、鈕（T a )、氮化鈦（τ丨n )、氮化叙 (T a N )或其它適當的材料組合。在阻障層（圖中未表示；沒有標號）形成之後，可接續形成銅晶種層（Cu seeding layer)(圖中未表示；沒有標號）於阻障層之表面。在一較佳實施例中，此銅晶種層^ 使用熟知技術，諸如物理氣相沉積法（physical vap〇r deposition; PVD)、濺鍍法等類似製程而形成，且豆 2f°?15°〇埃之間。接著，將此半導體底材5(Γ置於又 Ϊί Ϊ = ΐ之電鍍槽中進行電鍍銅反應，以形成銅層56 丄且填充於鑲嵌圖案54之中。藉著將銅晶 “進行還原反應電：ί Ξ極，使位於硫酸銅溶液中之銅著進行電铲r庠心 /儿積於銅晶種層之表面，亦即，藉所需的銅層56。一 =子;:：，晶種層表面，並形成鑲嵌圖案54後，仍會持續的，，；白、：層56在填充完整個中，在并錮I Γ 而覆蓋住介電層52。其 d f 1 1 / 表面會產生干擾缺陷（copper defects )檢測之銅微粒（銅曰㈧〇PPer 於第一圖）。 U位之電子顯微鏡圖已顯示隨後將此半導體底材5 〇置於、 (如第三圖所示），利用含有約2; 清洗槽110中氫與76. 9 %高純度去離子水。，丨L S文、1. 1 %過氧化于水之洗邊溶液進行洗邊程序，用第9頁 536755 五、發明說明（7) 以移除位於半導體底材50邊緣之銅層56。此洗邊程序具有些優點· （1)在電鍍過程中，會在半導體底材5〇之邊、、彖上方放置接觸環（contact ring)，此接觸環上具有接觸腳，用以將電性連結至半導體底材5 〇之表面，而使銅金屬能均勻的鍍在半導體底材5 0之表面，但由於接觸腳與半導體底材接觸的地方，電鍍出來的銅層其均勻度差，容易造成後續製程良率的下降，因此，在電鍍完成後增加一道洗邊程序，可以解決上述之問題；（2 )提升製程以及半導體底材50之整合（integration)，並避免電弧 _ $ Plasma arc )效應之產生。電弧效應為一種物理學上之大知放電原理。當半導體底材之表面被電弧所電擊時，在被電擊之區域膜層會遭到破壞，且產生膜層碎屑，這樣的結果，導致半導體底材表面上被電擊之區域，其製程良率w Refer to the second figure, which illustrates the flow cell in the electroless plating machine 90. After the definition of the mosaic pattern 54 is completed, the semiconductor substrate 50 is then placed in a plating bath 100 to perform a copper plating process to deposit a copper layer 56 on the dielectric layer 52 'and fill the mosaic pattern 54 ( (As shown in the fourth figure). It is worth noting that, before the semiconductor substrate 50 is placed in a plating bath in a chemical plating machine, and a copper plating process is performed, a barrier layer is first formed in the damascene pattern 536 755 5. The sidewall of the invention description (6) and The exposed upper surface of the semiconductor substrate 50 prevents a diffusion phenomenon between the copper layer 56 and the dielectric layer 52 and the semiconductor substrate 50 produced in the subsequent production, thereby generating a spiking effect. Generally speaking, the material for forming the barrier layer can be selected from titanium (Ti), button (Ta), titanium nitride (τ 丨 n), nitride nitride (TaN), or other suitable material combinations. After the barrier layer (not shown in the figure; no label) is formed, a Cu seeding layer (not shown in the figure; no label) can be successively formed on the surface of the barrier layer. In a preferred embodiment, the copper seed layer ^ is formed using a well-known technique, such as physical vapor deposition (PVD), sputtering, or the like, and the beans are 2f ° to 15 ° 〇Angel. Next, this semiconductor substrate 5 (Γ is placed in an electroplating bath of Ϊ Ϊ = ΐ) to perform a copper plating reaction to form a copper layer 56 丄 and fill the damascene pattern 54. By “reducing the copper crystal” Electricity: Ξ Ξ electrode, the copper located in the copper sulfate solution for electric shovel r 庠 heart / child accumulated on the surface of the copper seed layer, that is, the required copper layer 56. 一 = 子; ::, After the surface of the seed layer and the mosaic pattern 54 are formed, it will continue, and the white layer: the layer 56 covers the dielectric layer 52 in the complete filling, and the df 1 1 / surface will Copper particles (copper ㈧PPer is shown in the first picture) that detect interference defects (copper is shown in the first picture). The electron microscope image of the U-position has shown that this semiconductor substrate 50 is then placed in (as shown in the third picture) , Using about 2; hydrogen in the cleaning tank 110 and 76.9% high-purity deionized water. 丨 LS paper, 1.1% peroxidized with water edge cleaning solution for edge cleaning procedures, using page 9 536755 five Description of the invention (7) to remove the copper layer 56 on the edge of the semiconductor substrate 50. This edge cleaning procedure has some advantages. (1) in During the plating process, a contact ring is placed on the edge of the semiconductor substrate 50 and above the substrate. The contact ring has contact pins for electrically connecting the surface of the semiconductor substrate 50 to the substrate. Copper metal can be evenly plated on the surface of the semiconductor substrate 50. However, because the contact layer is in contact with the semiconductor substrate, the plated copper layer has poor uniformity, which easily causes the subsequent process yield to decrease. After completion, an edge cleaning procedure can be added to solve the above-mentioned problems; (2) Improve the process and integration of the semiconductor substrate 50, and avoid the occurrence of the arc_ $ Plasma arc effect. The arc effect is a physical problem The principle of discharge. When the surface of a semiconductor substrate is shocked by an electric arc, the film layer will be damaged in the area that is struck, and film debris will be generated. As a result, the area that is electrically shocked on the surface of the semiconductor substrate , Its process yield

下卩牛，此外，亦會使未被電擊之區域受到電擊產生之膜層碎屑的污染。 S 洗邊程序完成後，接著於喷洗式旋轉槽（sp丄n r」nser/dryer chamber， SRD chamber ) 12〇中施以第一次咼、、、屯度去離子水π洗程序，以移除洗邊溶液以及殘留於半導體底材表面之硫酸銅溶液。之後，將此清洗完之半導體底材50，置於同一喷洗式旋轉槽12〇中進行化學藥劑清洗程序約4秒鐘，以移除位於銅層56上之銅微粒，其中此化學藥劑為稀釋6〜12倍之洗邊溶液。接著，再施^第二次高，度去離子水清洗程序，以除去位於半導體底材上一之化學藥劑。最後，利用高轉速旋乾半導體底材5〇。Lowering a yak will also contaminate areas that have not been shocked by film debris from the shock. S After the edge-washing process is completed, the first rinse process of deionized water in a spray-wash spin bath (sp 丄 nr 」nser / dryer chamber, SRD chamber) 120 is performed to remove Remove the edge cleaning solution and the copper sulfate solution remaining on the surface of the semiconductor substrate. After that, the cleaned semiconductor substrate 50 is placed in the same spray-washing rotating tank 12 for a chemical cleaning process for about 4 seconds to remove copper particles on the copper layer 56. The chemical is Dilute the edge washing solution 6 to 12 times. Then, a second high-degree deionized water cleaning procedure is performed to remove a chemical agent located on the semiconductor substrate. Finally, the semiconductor substrate 50 is spin-dried using a high speed.

536755 五、發明說明（8) 在本發明中，利用已經過稀釋之洗邊溶液除去位於銅層表面之銅微粒，可使得在後續的製程中，能夠有效的將影響製程良率的重要缺陷，利用公司名稱為KLA或是型號為C Ο Μ P A S S之缺陷檢測儀將其檢驗出來，並將其移除，進而有效增加製程良率。 _ 本發明雖以一較佳實例闡明如上，然其並非用以限定本發明精神與發明實體，僅止於此一實施例爾。是以，在不脫離本發明之精神與範圍内所作之修改，均應包含在下述之申請專利範圍内。 _536755 V. Description of the invention (8) In the present invention, the use of the diluted edge cleaning solution to remove copper particles on the surface of the copper layer can effectively affect important defects that affect the yield of the process in subsequent processes. Use a defect detector with the company name KLA or model C OM PASS to check it out and remove it, thereby effectively increasing the process yield. _ Although the present invention is explained above with a preferred example, it is not intended to limit the spirit and the inventive substance of the present invention, but only to this embodiment. Therefore, all modifications made without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. _

第11頁 536755 圖式簡單說明圖式簡單說明：藉由以下詳細之描述結合所附圖示，將可輕易的了解上述内容及此項發明之諸多優點，其中：第一圖為各種製程中所產生缺陷之電子顯微鏡圖及其機率。第二圖為半導體晶圓之截面圖，顯示根據目前業界技術製作鑲嵌圖案之步驟；第三圖為化學機械研磨機台之側視與部分截面圖，顯示根據目前業界技術化學電鍍之流程槽；以及第四圖為半導體晶圓之截面圖，顯示根據目前業界技術形成銅層之步驟。圖號對照表：半導體底材5 0 鑲嵌圖案54 化學電鍍機台9 0 晶圓邊緣清洗槽11 0 介電層5 2 銅層5 6 電鍍槽1 0 0 喷洗式旋轉槽1 2 0Page 536755 Simple illustrations Simple illustrations: With the following detailed description combined with the attached drawings, the above content and the many advantages of this invention can be easily understood, of which: The first picture is used in various processes Electron microscope image of defects and its probability. The second figure is a cross-sectional view of a semiconductor wafer, showing the steps of making a mosaic pattern according to the current industry technology; the third figure is a side view and a partial cross-sectional view of a chemical mechanical polishing machine, showing the chemical plating process tank according to the current industry technology; And the fourth figure is a cross-sectional view of a semiconductor wafer, showing the steps of forming a copper layer according to the current industry technology. Drawing number comparison table: Semiconductor substrate 5 0 Mosaic pattern 54 Chemical plating machine 9 0 Wafer edge cleaning tank 11 0 Dielectric layer 5 2 Copper layer 5 6 Plating tank 1 0 0 Spray-type rotating tank 1 2 0

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Claims

536755 六、申請專利範圍 1· 一種在化學電鍍程序中避免銅層表面銅微粒干擾缺陷檢測之方法，該方法至少包含下列步驟·· A·將基材置於化學電鍍機台之電鍍槽中進行電鍍銅程序，以形成該銅層於該基材上表面，其中在該銅層之上表面會產生干擾缺陷檢測之該銅微粒；以及 B ·將该基材置於晶圓邊緣清洗槽中進行洗邊程序，以移除位於該基材邊緣之該銅層’且在移除之後將該基材移入喷洗式旋轉槽中，並施以高純度去離子水清洗程著旋乾該基材； _ 其特徵在於：在該南純度去離子水清洗程序後，於同一該噴洗式旋轉槽中、、fe、、、貞進行化學藥劑清洗程序以移除該銅微粒。 2體i ::專利乾圍第1項之方法，其中上述之基材為半導 3鑛圍Γ項之方法，其中更包括於進行該電序之刖’形成介電層於基材上表面。 4.如申請專利範圍第3 其中案於該介電層中。貝之方汝旯匕括疋義鑲嵌圖536755 6. Scope of patent application1. A method for preventing copper particles from interfering with defect detection on the surface of a copper layer in a chemical plating process. The method includes at least the following steps: A. Place the substrate in a plating bath on a chemical plating machine Copper plating process to form the copper layer on the upper surface of the substrate, wherein the copper particles that interfere with defect detection will be generated on the upper surface of the copper layer; and B. The substrate is placed in a wafer edge cleaning bath. An edge washing process to remove the copper layer at the edge of the substrate, and after the removal, the substrate is moved into a spray-wash spin bath, and the substrate is spin-dried with a high-purity deionized water cleaning process _ It is characterized in that: after the cleaning process of the South-purity deionized water, a chemical cleaning process is performed in the same spray-washing rotating tank to remove the copper particles. 2-body i :: method of patent dry enveloping item 1, in which the above-mentioned substrate is a semiconducting three-ore enclosing method of item Γ, which further includes forming a dielectric layer on the upper surface of the substrate when performing the electrical sequence. . 4. If the scope of patent application is the third one in the dielectric layer. Bei Zhi Fang Ru

536755 六、申請專利範圍 %高純度去離子水之洗邊溶浪，以移除位於該半導體底材邊緣之該銅層。 6 ·如申請專利範圍第1項之方法’其中上述之化學藥劑為稀釋6〜1 2倍之該洗邊溶液。 7.如申請專利範圍第1項之方法，其中進行該化學藥劑清洗程序之時間約為2〜6秒。 8 ·如申請專利範圍第1項之方法’其中在完成上述之化學藥劑清洗程序後，再利用轉速為1 5 0〜4 〇 0 rpm之轉速旋乾該半導體底材。 9 · 一種在化學電鍍程序中避免銅層表面銅微粒干擾缺陷檢測之方法，該方法至少包含下列步驟·· A·將基材置於化學電鍍機台之電鍍槽中進行電鍍銅程序，以形成該銅層於該基材上表面，其中在該銅層之上表面會產生干擾缺陷檢測之該銅微粒；以及 B·將該基材置於晶圓邊緣清洗槽中進行洗邊程序，以移除位於該基材邊緣之該銅層，且在移除之後將該基材移入喷洗式旋轉槽中，並施以高純度去離子水清洗程序，接著旋乾該基材；其特徵在於：536755 6. Scope of patent application: The high-purity deionized water washes and dissolved to remove the copper layer on the edge of the semiconductor substrate. 6. The method according to item 1 of the scope of patent application, wherein the above-mentioned chemical agent is the edge washing solution diluted 6 to 12 times. 7. The method according to item 1 of the scope of patent application, wherein the cleaning time of the chemical agent is about 2 to 6 seconds. 8. The method according to item 1 of the scope of patent application, wherein the semiconductor substrate is spin-dried using a rotation speed of 150 to 400 rpm after completing the above-mentioned chemical agent cleaning procedure. 9 · A method for preventing copper particles from interfering with defect detection on the surface of a copper layer in a chemical plating process, the method includes at least the following steps: · A · Place the substrate in a plating bath of a chemical plating machine to perform a copper plating process to form The copper layer is on the upper surface of the substrate, and the copper particles on the upper surface of the copper layer will interfere with defect detection; and B. The substrate is placed in a wafer edge cleaning tank to perform an edge cleaning process to remove the substrate. After removing the copper layer located on the edge of the substrate, the substrate is moved into a spray-washing rotating tank after removal, and a high-purity deionized water cleaning procedure is performed, followed by spin-drying the substrate;

第14頁六、申凊專利範圍在該高純度去離轉槽中進行化學藥 :，洗程序後，於同一該喷洗式旋學藥劑為稀釋之洗邊ς液程序以移除該銅微粒，其令該化 10·如申請專利範圍體底材间乐9項之方法，其中上述之基材為半導 11 ·如申凊專利範圍第9 鍍銅程序之前，形成介電層：法，其中更包括於進行該電基材上表面更包括定義鑲嵌 1 3 ·如申請專利範圍第9 項之方法，其中上述之洗邊程序係利用含有1 5〜2 4 %石奋舱、η 〇， ~#丄胁 ·8〜%過氧化氫以及75〜85 同純度去離子水之洗邊溶液，以移除位於該半導體底材邊緣之該銅層。 1 4 ·如申明專利範圍苐9項之方法，其中進行該化學藥劑清洗程序之時間約為2〜6秒。 ° 1 5 ·如申請專利範圍第9項之方法，其中在完成上述之化學藥劑清洗程序後，再利用轉速為150〜40 0 rpm之轉速旋乾該半導體底材。Page 14 VI. The scope of Shenying's patent: Chemical treatment in the high-purity deionization tank: After the washing process, use the same spray-washing spinner as the diluted edge-washing solution to remove the copper particles. It makes this method 10 · The method of applying for patent 9 range of substrates and substrates, among which the above-mentioned substrate is semiconducting 11 · The method of applying dielectric layer before the copper plating procedure of method 9 of the scope of patent application: It also includes defining the inlay 1 3 on the upper surface of the electrical base material. · The method of item 9 in the scope of the patent application, wherein the above-mentioned edge-washing procedure is to use 15 to 24% of Shifen cabin, η 〇, ~ # 丄丄 · 8 ~% hydrogen peroxide and 75 ~ 85 deionized water of the same purity as the edge washing solution to remove the copper layer on the edge of the semiconductor substrate. 14 · The method as stated in the scope of item 9 of the patent, wherein the cleaning time of the chemical agent is about 2 to 6 seconds. ° 1 5 · The method according to item 9 of the scope of patent application, wherein the semiconductor substrate is spin-dried using a rotation speed of 150 to 40 rpm after completing the above-mentioned chemical cleaning procedure.

第15頁 536755 16· —種在化學電鑛程序中避务徊s ^ ^ ^ β t , &充銅層表面銅微粒干擾缺陷檢測之方法’该方法至少包含下列步驟· A·將基材置於化學電鍍機△締祕序，以形成該銅層於該基材上；：電；：中進行電鑛銅程面會產生干擾缺陷檢測之該銅；：；#中在該銅層之上表移晶圓邊緣清洗槽中進行洗邊程序，以移除位於该基材邊緣之該錮屛， -V ^ Μ M rb 9 在移除之後將該基材移入噴冼式奴轉槽中，並絲古及 I她以问純度去離子水清洗程序·，以 C·將4基材置於同一該喷洗式旋轉槽中，藥劑清洗程序，以移除哕銦料抑 f由# 進仃化干 R彳9 _夕除4銅斂粒，其中该化學藥劑為稀釋 6〜1 2倍之洗邊溶液。卞 17.如申請專利範圍第16項之方法，材導體底材。 r上述之基材為半二申Λ專利，目第16項之方法，其中更包括於進行該電鍍銅私序之前，形成介電層於基材上表面。 1 9.如申請專利範圍第丨8項之方法中圖案於該介電層中。 υ更包括疋義鑲肷 20.如申請專利範圍第16項之方法，其中上述之洗邊程序 536755 六、申請專利範圍係利用含有1 5〜2 4 %硫酸、0 · 8〜1 · 2 %過氧化氫以及7 5〜 8 5 %高純度去離子水之洗邊溶液，以移除位於該半導體底材邊緣之該銅層。 2 1 ·如申請專利範圍第1 6項之方法，其中進行該化學藥劑清洗程序之時間約為2〜6秒。 2 2.如申請專利範圍第1 6項之方法，其中在完成上述之化學藥劑清洗程序後，再利用轉速為1 5 0〜4 0 0 r p m之轉速旋乾該半導體底材。Page 15 536755 16 · —A method for avoiding s ^ ^ ^ β t, & method for detecting defects of copper particles on the surface of the copper-filled layer in the process of chemical power mining 'This method includes at least the following steps: A. Substrate Placed on a chemical electroplating machine △ associated secret sequence to form the copper layer on the substrate ;: electricity ;: the copper on the copper surface of the electric ore mine will cause interference defect detection ;; #; in the copper layer The above table is moved to a wafer edge cleaning tank to perform an edge cleaning process to remove the ridge located on the edge of the substrate. -V ^ Μ M rb 9 After the removal, the substrate is moved into a spray slave tank. And Sigu and I used the purity purity deionized water cleaning procedure to place the 4 substrates in the same spray-washing rotary tank with C ·, and a pharmaceutical cleaning procedure to remove the indium indium material. Xuanhuagan R 彳 9 _ Xizhu 4 copper agglomerates, in which the chemical is a 6 to 12 times diluted edge washing solution.卞 17. According to the method of claim 16 of the scope of patent application, the material is a conductive substrate. r The above-mentioned substrate is a semi-second patent, the method of item 16, which further includes forming a dielectric layer on the upper surface of the substrate before performing the electroplated copper private sequence. 1 9. The pattern in the method of claim 8 is patterned in the dielectric layer. υ also includes 疋 yi inlay 如 20. If the method of the scope of patent application No. 16, in which the above-mentioned edge-washing procedure 536755 Six, the scope of patent application is the use of containing 15 ~ 2 4% sulfuric acid, 0 · 8 ~ 1 · 2% An edge cleaning solution of hydrogen peroxide and 75 ~ 85% high-purity deionized water to remove the copper layer on the edge of the semiconductor substrate. 2 1 · The method according to item 16 of the scope of patent application, wherein the time for performing the cleaning process of the chemical agent is about 2 to 6 seconds. 2 2. The method according to item 16 of the scope of patent application, wherein the semiconductor substrate is spin-dried with a rotation speed of 150 to 400 r p m after completing the cleaning process of the chemical agent described above.

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