經濟部智慧財產局員工消費合作社印製 533420 A7 B7__ 五、發明說明（） 發明領域： 本發明係有關於一種記憶體讀取測試之方法，特別是 有關於應用在快閃記憶體（Flash Memory)的讀取測試之方 法’藉以有效地測試每一個記憶胞的可靠度，提升產品的 良率。 發明背景： 快閃ό己憶體是一種非揮發性（N〇nv〇iatiie)的記憶體，藉 由其結構中與外界隔離的懸浮閘（Floating Gate)儲存電荷 的原理’可長時間保存資訊内容。隨著半導體技術的快速 發展’快閃記憶體最初只應用於電腦的BIOS記憶體，現已 廣泛地應用於行動電話、數位相機等電子產品中，且由於 快閃記憶體具有電可擦栻（Erase)及可程式化（program)的 能力，因此用途越趨多樣化。 請參考第1圖’其所繪示為習知快閃記憶體陣列結構 之示意圖。於第i圖之快閃記憶體陣列結構1 〇中，每兩個 記憶胞1 5共用一條源極線（s〇urce Une)2〇電性連接至接地 端（未繪示），藉由施加電壓於適當的字元線25(w〇rd Line：) 和位元線（Bit Line)30，以啟動對應的記憶胞，經由感測放 本紙張又度適用中國國家標準（CNS)A4規格（210 X 297公餐） n I— n II ·υ D n fl«l —ϋ mMamm emMmw MM9 · n m 1 an ϋ 11 n ^ 4 m ·1· nv I amemm i l I 言 矣 (請先閱讀背面之注意事項再填寫本頁) 533420 Λ7 B7 五、發明說明（） 大器（Sense Amplifier)(未緣示）對流出的電流進行量測比 較’得知記憶胞儲存的資訊。 請參考第2圖，其所繪示為習知快閃記憶體陣列結構 之記憶胞組的電路示意圖。於第2圖中，係在第1圖所示 之快閃記憶體陣列結構中之同一字元線上’以3 2個記憶胞 作為一個擁有32Bits的記憶胞組1 00，所以記憶胞組} QQ 中各個記憶胞1 02的閘極和汲極，皆分別與字元線1 〇4和 位元線1 06作電性連接，每個記憶胞組1 〇〇中各個記憶跑 102之源極，亦與源極線丨〇8作電性連接。另外，如第2 圖所示，源極線1 0 8亦與金屬線1 1 0作並聯的電性連接至 接地端1 1 2。 經濟部智慧財產局員工消費合作社印製 在快閃記憶體中，由於每個記憶胞所儲存的資訊不 同，因此每個記憶胞所處的狀態亦不相同’大致可分為擦 拭狀態和程式化狀態兩種。程式化狀態為利用通道熱栽子 注入（CHEI)，或高電場下的FN穿隧（FN Tunneling)等電子 注入方法，將適當的電子注入記憶胞的浮動閘，使得記憶 胞儲存，而且當記憶胞為程式化狀態時，記憶胞呈現非導 通狀態，電流沒法隨意流通。擦拭狀態則為利用與程式化 時相反的高電場下之FN穿隧，使電子從記憶胞的浮動閘射 出，記憶胞因而沒有儲存負電荷，而且當記憶胞為擦拭狀 態時，記憶胞呈現導通狀態，電流可以流通。 本紙張尺度適用中國國家標準（CNS)A4規烙（210 x 297公t ) 533420 Α7 Β7 五、發明說明（ 請參考第3圖，其所繪示為根據第2圖之習知快閃記 憶體中記憶胞組於理想讀取情況時進行讀取測試的電路示 意圖，其中記憶胞200處於讀取狀態。在快閃記憶體的測 試過程中，需要對快閃記憶體中每一個記憶胞進行不同的 存取動作，以測試該記憶胞的動作正常與否。而第3圖所 示之電路示意圖，係當字元線1 04和位元線202被施壓， 啟動記憶胞組100中的記憶胞200，並對記憶胞200進行 讀取時之電路示意圖。由於記憶胞2 0 0被選取，因此連接 記憶胞200的位元線202切換至感測放大器204，以對記 憶胞200流出的電流206進行量測比較。而其他未被選取 的5己憶胞丨〇 2 ’跟其〉及極電性連接的位疋線1 0 6 ’則電性連 接至接地端114。 ------------費--------訂i (請先閱讀背面之沒意事項再填寫本頁> 經濟部智.€財產局員工消費合作社印製 在 係先對 使得記 然後才 應的記 中所有 態，因 動記憶 如第3 對快閃記憶體的記憶胞200進行讀取測試時，—般 此記憶胞2 0 0所屬的記憶胞組1 〇 〇進行擦拭動作， 憶胞組1 00中每一個記憶胞1 02都處於擦拭狀態， 施壓於適當的字元線104和位元線202，以啟動對 憶胞200進行讀取測試。然而，由於記憶胞組1 % 的記憶胞1 02皆處於擦拭狀態，亦即呈現導通狀 此當施壓於第3圖之字元線104和位元線202，啟 胞200時，記憶胞200所流出的電流206，除了可 圖之路徑2 1 0，沿源極線1 0 8至金屬線1 1 〇，再流到 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 533420 Λ7 B7 五、發明說明（） (請先閱讀背面之注意事項再填寫本頁) 接地端1 1 2外’亦可如路徑2 1 2所示’沿記憶胞組1 〇〇中 其他處於擦拭狀態的記憶胞1 02流至接地端丨1 4，所以此 時3己憶胞200所流出的電流206擁有多條流動路徑至接地 端。而電流206沿記憶胞1 02流至接地端1 1 4的路徑2 1 2， 一般可稱為寄生傳導路徑（Parasitic Conduction path)。 由於記憶胞2 0 0所流出的電流2 0 6擁有多條路徑流動 至接地端，使得記憶胞2 0 0的源極電壓趨於低準位，又由 於記憶胞200流出電流206的大小，跟記憶胞200的閘極 和源極之間的電位差成正比關係，亦即閘極和源極之間的 電位差越大，記憶胞200流出的電流2〇6越大，反之亦然。 因此當記憶胞2 0 0的閘極電壓固定’而源極電壓趨於低準 位時，閘極和源極之間的電位差即隨之增加，記憶胞2 0 〇 流出的電流206隨之增加，使得感測放大器204能輕易對 此電流2 0 6作量測和比較，得到準確的資訊。 經濟部智慧財產局員工消費合作社印制代 然而，記憶胞組1 〇〇中每一個記憶胞1 02都處於擦拭 狀態（即呈現導通狀態）時，只是快閃記憶體的最佳讀取情 況。在實際操作時，由於快閃記憶體記載著資料，所以快 閃記憶體中每個記憶胞所處的狀態皆不盡相同’一些記憶 胞處於擦拭狀態（即呈現導通狀態）’另一些記憶胞則可能 處於程式化狀態（即呈現非導通狀態）。因此，當對§己憶皰 進行讀取時，記憶胞所流出的電流’並未如第3圖之記憶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 533420Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 533420 A7 B7__ V. Description of the Invention () Field of the Invention: The present invention relates to a method for reading and testing a memory, and in particular, it is applied to flash memory. The method of reading test is used to effectively test the reliability of each memory cell and improve the yield of the product. Background of the invention: Flash memory is a non-volatile (non-volatile) memory that uses a floating gate that is isolated from the outside in its structure to store charge. content. With the rapid development of semiconductor technology, flash memory was originally only used in the computer's BIOS memory, and is now widely used in mobile phones, digital cameras and other electronic products. Because flash memory is electrically erasable ( Erase) and the ability to be programmed, so the use is becoming more diverse. Please refer to FIG. 1 'for a schematic diagram of a conventional flash memory array structure. In the flash memory array structure 10 in FIG. I, every two memory cells 15 share a source line (source Une) 20 electrically connected to a ground terminal (not shown) by applying The voltage is applied to the appropriate word line 25 (bit line :) and bit line 30 (bit line) 30 to activate the corresponding memory cell. The paper is again applied to the Chinese National Standard (CNS) A4 specification through sensing ( 210 X 297 meals) n I— n II · υ D n fl «l —ϋ mMamm emMmw MM9 · nm 1 an ϋ 11 n ^ 4 m · 1 · nv I amemm il I (Please read the note on the back first Please fill in this page again for details) 533420 Λ7 B7 V. Description of the invention () A Sense Amplifier (not shown) measures and compares the current flowing out to learn the information stored in the memory cell. Please refer to FIG. 2, which shows a circuit diagram of a memory cell group of a conventional flash memory array structure. In the second figure, it is on the same character line in the flash memory array structure shown in the first figure. 'Thirty-two memory cells are used as a memory cell group with a 32Bits of 100, so the memory cell group} QQ The gate and drain of each memory cell 102 are electrically connected to the word line 104 and the bit line 106 respectively. Each memory cell in each memory cell group 100 runs the source of 102, It is also electrically connected to the source line. In addition, as shown in FIG. 2, the source line 108 is also electrically connected in parallel with the metal line 1 10 to the ground terminal 1 12. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is printed in flash memory. Because each memory cell stores different information, the state of each memory cell is also different. It can be roughly divided into wiped state and stylized Two states. The stylized state is to use electron injection methods such as channel hot plant injection (CHEI) or FN tunneling under high electric field to inject appropriate electrons into the floating gate of the memory cell, so that the memory cell is stored, and when the memory is stored, When the cell is in a stylized state, the memory cell is in a non-conducting state, and current cannot flow freely. The wiping state is to use the FN tunneling under the high electric field opposite to the stylization, so that the electrons are ejected from the floating gate of the memory cell, so the memory cell does not store a negative charge, and when the memory cell is in the wiping state, the memory cell appears conductive State, current can flow. This paper size is applicable to Chinese National Standard (CNS) A4 (210 x 297 g) 533420 Α7 Β7 V. Description of the invention (please refer to Figure 3, which shows the flash memory according to the conventional figure 2) The circuit diagram of the middle memory cell group to perform a reading test under ideal reading conditions, in which the memory cell 200 is in the reading state. During the flash memory test process, each memory cell in the flash memory needs to be different. To test the memory cell's normal operation. The circuit diagram shown in Figure 3 is when the word line 104 and the bit line 202 are pressed to start the memory in the memory cell group 100. Schematic diagram of the cell 200 and reading the memory cell 200. Since the memory cell 200 is selected, the bit line 202 connected to the memory cell 200 is switched to the sense amplifier 204, so that the current flowing out of the memory cell 200 206 for measurement and comparison. The other 5 cells that have not been selected 丨 〇2 'follow it> and the bit line 1 0 6' which is electrically connected are electrically connected to the ground terminal 114. ----- ------- Fees -------- Order i (Please read the unintentional matter on the back before Write this page> The Ministry of Economic Affairs, the Ministry of Economic Affairs, the Consumers' Cooperatives of the Property Bureau printed all the states in the record before making the record, and the dynamic memory is the third one to read the flash memory cell 200. During the test, the memory cell group 100, to which this memory cell 200 belongs, performs a wiping action. Each memory cell 102 in the memory cell group 100 is in a wiping state, and pressure is applied to the appropriate word line 104 and The bit line 202 is used to start the reading test on the memory cell 200. However, since 1% of the memory cell group 102 is in the wiping state, that is to say, it is conductive, so when the pressure is applied to the characters in Figure 3 Line 104 and bit line 202. When the cell 200 is activated, the current 206 flowing out of the memory cell 200, in addition to the graphable path 2 10, follows the source line 108 to the metal line 1 10, and then flows to the linebook. Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297g t) 533420 Λ7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Grounding terminal 1 1 2 Outside 'can also be used as Path 2 1 2 shows the other memory cells 1 02 along the memory cell group 100. To the ground terminal 丨 4, so at this time the current 206 flowing out of the memory cell 200 has multiple flow paths to the ground terminal. The current 206 flows along the memory cell 102 to the ground terminal 1 1 4 and the path 2 1 2. Generally referred to as the Parasitic Conduction Path. Because the current flowing out of the memory cell 2 0 6 has multiple paths flowing to the ground, the source voltage of the memory cell 2 0 tends to a low level Because the magnitude of the current 206 flowing out of the memory cell 200 is proportional to the potential difference between the gate and the source of the memory cell 200, that is, the larger the potential difference between the gate and the source, the larger the current flowing out of the memory cell 200. The larger 206 is, and vice versa. Therefore, when the gate voltage of the memory cell 200 is fixed and the source voltage tends to a low level, the potential difference between the gate and the source will increase accordingly, and the current 206 flowing out of the memory cell 200 will also increase. , So that the sense amplifier 204 can easily measure and compare this current 206 to obtain accurate information. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs However, when each memory cell 102 in the memory cell group 100 is in the wiping state (ie, it is in a conducting state), it is only the best read condition of the flash memory. In actual operation, since the flash memory records data, the state of each memory cell in the flash memory is different. 'Some memory cells are in a wiping state (ie, they are in a conducting state)' Other memory cells It may be stylized (ie non-conducting). Therefore, when reading the § self-membrane, the current flowing out of the memory cell is not as memorized in Figure 3. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 g t) 533420
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 胞200所流出之電流206，祐女印a ^ 擁有眾多的寄生傳導路徑流至 接地端，因為一些記憶胞虛t ^ ^ 肥處於非導通狀態，使得部份的寄 生傳導路徑呈開路狀態，所 π Μ在實際操作時，被啟動的記 憶胞所流出的電流，其擁有的、六&妨^ ^ ^ $的流動路徑的數量，將比最佳 讀取情況時少。 清參考第4圖’其所繪示為根據第2圖之習知快閃記 憶體中記憶胞組於實際讀取情況時進行讀取測試的電路示 意圖，其中記憶胞3GG處於讀取狀態。由於寄生傳導路徑 的數目減少，因此經由字元、線1〇4和位元線3〇4啟動的記 憶胞3GG，其源極之電璧比理想讀取情況時記憶㉟2〇()的 源極之電壓高’使得記憶胞3⑼的閘極和源極之間的電位 差變小，所以記憶胞3 00流出的電流3〇2亦變小，造成感 測放大器204的量測困難。 請參考第5圖，其所繪示為根據第2圖之習知快閃記 憶體中記憶胞組於最壞讀取情況時進行讀取測試的電路示 思圖，其中s己憶胞4 0 0處於讀取狀態。當記憶胞組丨〇 〇中 全部的記憶胞1 02皆為程式化狀態時（即呈現非導通狀 態）’因寄生傳導路從皆已開路’被字元線1 〇 4和位元線4 〇 4 所啟動的記憶胞4 0 0流出的電流4 0 2，，只能沿源極線1 〇 8 到金屬線1 1 0再流至接地端1 1 2的路徑2 1 0流動，因此， 記憶胞400的源極之電壓，比實際讀取情況時記憶胞的源 6 本紙張又度適用中國國家標準（CNS)A4規格（210 X 297公t ) --------------------訂---------^ (AW (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 533420 A7 B7 五、發明說明（） 極之電壓更高，使得記憶胞400的閘極和源極之間的電位 差越趨微小，所以記憶胞400流出的電流402亦變得更小， 感測放大器204對此微小的電流402作量測比較就更為困 難，量測的準確度因而降低，使得讀取的可靠度亦隨之降 低。 由於一般的快閃記憶體讀取測試，是在理想讀取情況 下進行，故未能對快閃記憶體於實際讀取情況或最壞讀取 情況進行讀取時，提供足夠的讀取可靠度，因而影響快閃 記憶體的產品良率。 另外，若要利用習知快閃記憶體的讀取測試方法，對 處於最壞讀取情況時的快閃記憶體進行讀取測試時，首先 需對記憶胞組進行擦拭動作，使每個記憶胞處於擦拭狀 態，然後按測試設計的順序，對非啟動的記憶胞進行程式 化動作，使記憶胞組内除待測記憶胞外其他的記憶胞皆處 於程式化狀態，寄生傳導路徑呈開路狀態，模擬出最壞讀 取情況，再進行讀取測試。 可是，由於記憶胞組中含有眾多記憶胞，若要在每一 個記憶胞進行讀取測試時，模擬出最壞讀取情況，則需要 反覆進行多次擦拭動作和程式化動作。例如，第2圖之記 憶胞組100中含有3 2個記憶胞102，則至少需要進行3 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） ------I----I --------訂 -------I (請先閱讀背面之注意事項再填寫本頁) 533420 Λ7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 次的擦拭動作以及程式化動 而且，在快閃記憶體中，含 最壞讀取情況以對每個記憶 試時間難以估計。因此急需 測試效率及同時能提高產品 方法。 發明目的及概述： 雲於上述之發明背景中 方法’疋對處於理想讀取情 胞的讀取測試，因而未能提 品良率。另外若要在每個記 最壞讀取情況，則需要反覆 動作，測試時間因而耗費不 本發明的主要目的為提 法’特別是有關於應用在快 號提供至每個記憶胞的汲極 皆呈開路狀態，如此不需反 化動作’即可模擬出快閃記 進行記憶胞的讀取測試時， 提供產品優良的可靠度。 作，測試時間因而耗費不少。 有眾夕的記憶胞組，若要模擬 胞進行凟取測試，則所需之測 一種具有縮短測試時間，提升 可靠度的快閃記憶體讀取測試 ’習知快閃記憶體的讀取測試 況下的兄憶胞組進行每個記憶 供足夠的讀取可靠度，影響產 憶胞進行讀取測試時，模擬出 進行多次的擦拭動作和程式化 少’使彳寸產品成本上升。 供了一種記憶體讀取測試之方 閃記憶體上。藉由將高阻抗信 之接地端，使得寄生傳導路徑 覆進行多次的擦拭動作和程式 憶體的最壞讀取情況，所以在 能大大地縮短測試時間，以及 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） ------------黌--------tr---------線Φ (請先閱讀背面之注意事項再填寫本頁) 533420 經濟部智慧財產局員工消費合作社印製 A： B7_ 五、發明說明（） 根據以上所述之目的，提供了一種記憶體讀取測試之 方法，特別是有關於應用在快閃記憶體上。藉由將高阻抗 信號提供至每個記憶胞的汲極之接地端，使得每個記憶胞 無論處於擦拭狀態或程式化狀態時，其寄生傳導路徑皆呈 開路狀態，因此當待測記憶胞被啟動後，其流出的電流只 能沿單一路徑流至金屬線的接地端，此時快閃記憶體的讀 取測試則是在最壞讀取情況下進行，而且對不同的記憶胞 進行讀取測試時，並不需要反覆進行多次的擦拭動作和程 式化動作，如此可更有效地測試每一個記憶胞的可靠度， 節省測試時間，提升產品的良率，且有助於設計人員對快 閃記憶體的電路設計作適當的改良，提供快閃記憶體理想 的操作環境。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述，其中： 第1圖係繪示習知快閃記憶體陣列結構之示意圖。 第2圖係繪示習知快閃記憶體陣列結構之記憶胞組的, 電路示意圖。 第3圖係繪示根據第2圖之習知快閃記憶體中記憶胞 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) (請先閱讀背面之注意事項再填寫本頁) # 訂---------線· 經濟部智慧財產局員工消費合作社印製 533420 __B7_ 五、發明說明（） 組於理想讀取情況時進行讀取測試的電路示意圖。 第4圖係繪示根據第2圖之習知快閃記憶體中記憶胞 組於實際讀取情況時進行讀取測試的電路示意圖。 第5圖係繪示根據第2圖之習知快閃記憶體中記憶胞 組於最壞讀取情況時進行讀取測試的電路示意圖。 第6圖係繪示於本發明之一實施例中快閃記憶體的記 憶胞組於讀取測試時的電路示意圖。 第7圖係繪示根據第6圖的本發明之一實施例中的狀 態選擇模組之一電路示意圖。 圖號對照說明： 10 陣 列 結構 15 記 憶 胞 20 源 極 線 25 字 元 線 30 位 元 線 100 記 憶 胞組 102 記 憶 胞 104 字 元 線 106 位 元 線 108 源 極 線 1 10 金 屬 線 1 12 接 地 端 114 接 地 端 200 記 憶 胞 202 位 元 線 204 感 測 放大器 206 電 流 210 路 徑 212 路 徑 300 記 憶 胞 302 電 流 304 位 元 線 10 本紙張&度適用中國國家標準（CNS)A4規格（210 X 297公f ) m n el· ^iv 1 emml Hi n n an n · i n flflfl n If a— n ^ ^ f n· He iv n flu «ϋ ϋ I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 533420 A7 B7 五、發明說明（） 400 記憶胞 402 電流 404 位元線 500 記憶胞組 502 記憶胞 504 字元線 506 位元線 508 源極線 510 金屬線 5 12 接地端 514 記憶胞 516 狀態選擇模組 518 感測放大器 520 電流 522 路徑 524 位元線 600 反相器 602 及閘 604 輸入端 606 輸入端 608 輸出端 610 輸入端 612 輸出端 發明詳細說明： 請參考第6圖，其所繪示為於本發明之一實施例中快 閃記憶體的記憶胞組於讀取測試時的電路示意圖，其中記 憶胞514處於讀取狀態。為了模擬出最壞讀取情況，如第6 圖所示，以狀態選擇模組5 1 6電性連接至與記憶胞組5 00 中每個記憶胞502的汲極相連的位元線’506。於記憶胞組 500進行讀取測試時，狀態選擇模組5 1 6提供高阻抗信號， 然後字元線504和位元線524被施壓，以啟動記憶胞5 14， 且位元線5 06自與狀態選擇模組5 1 6電性連接的狀態，切 π 本紙張尺度適用中國國家標準（CNSM4規恪（210 X 297公釐） ,--------訂---------線Φ (請先閱讀背面之注意事項再填冩本頁) 533420 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 換至與感測放大器5 1 8電性連接的狀態。 由於除了記憶胞5 1 4，其他的記憶胞5 02皆透過位元線 5 0 6電性連接至狀態選擇模組5 1 6，且此時狀態選擇模組 5 1 6提供高阻抗信號，所以自源極線508往記憶胞502至 位元線方向的寄生傳導路徑形同開路，使得當記憶胞5 i 4 被啟動而流出電流5 2 0時，電流5 2 0沒法沿其他的記憶胞 5 02之寄生傳導路徑流動，而只能沿路徑522，自源極線 5 0 8到金屬線5 1 0流至接地端5 1 2。因此，記憶胞5 1 4的源 極和閘極之間的電位差變小，使得記憶胞5丨4所流出的電 流5 2 0亦變小。如此就可測試出感測放大器5 1 8於最壞讀 取情況、記憶胞5 1 4流出微小的電流5 2 0時，所能提供的 量測準確度。 當需要測試記憶胞組5 0 0中其他的記憶胞5 0 2時，並 不需要進行擦拭動作和程式化動作，因記憶胞5 0 2無論是 處於擦拭狀態或程式化狀態，由於電性連接至位元線5 0 6 的狀態選擇模組5 1 6提供高阻抗信號，使得寄生傳導路徑 形同開路，故測試時記憶胞5 0 2所流出的電流，亦只能沿 源極線5 0 8到金屬線5 1 0流至接地端5 1 2。 請參考第7圖，其所繪示為根據第6圖的本發明之一 實施例中的狀態選擇模組之一電路示意圖。第6圖中之狀 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ’ I 11 ---I----訂·--------^« (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 533420 Λ； B7 五、發明說明（） 態選擇模組5 16，可由反相器600和及閘602組成，及閘 602的輸入端604為測試模式的輸入，當需以最壞讀取情 況進行讀取測試時，以高準位或“ 1 ”的信號輸入至及閘 602的輸入端604，否則則以低準位或“ 0”的信號輸入至 輸入端604 ;而及閘的輸入端606則為第6圖之感測放大 器的啟動輸入，當感測放大器需要啟動以量測記憶胞的電 流信號時，則以高準位或“ 1 ”的信號輸入至及閘602的輸 入端606，其餘情況則以低準位或“ 0”的信號輸入至及閘 602的輸入端606。 當及閘602的輸出端608輸出低準位或“ 0”的信號至 反相器6 0 0時，反相器6 0 0將根據從輸入端6 1 0所輸入的 信號，以輸出適當的信號至第6圖中與各記憶胞電性連接 的位元線。例如，當高準位或“ Γ 的信號輸入反相器600 的輸入端610時，反相器600的輸出端612輸出低準位的 信號，使得第6圖之各記憶胞透過位元線電性連接至狀態 選擇模組時，形同電性連接至接地端，此時的快閃記憶體 讀取情況為一般的實際讀取情況；當低準位或“ 0”的信號 輸入至輸入端610時，反相器600的輸出端612則輸出高 準位的信號。 另外，當需以最壞讀取情況進行讀取測試時，高準位 或“ Γ 的信號會輸入至及閘602的輸入端604，而且由於 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------1 « .1— HI i·— In ·ϋ fl— sl« 一 - a m m n n an 11 I (請先閱讀背面之注意事項再填寫本頁) 533420 經濟部智慧財產局員工消費合作社印製 Λ7 B7 五、發明說明（） 感測放大器的啟動，所以高準位或“ 1，，的信號亦會輸入至 及閘602的輸入端606，因此及閘602的輸出端608輸出 高準位或“ Γ的信號至反相器600。 當反相器600接收到來自及閘602的高準位信號時， 則無論是高準位信號或低準位信號輸入至反相器6〇〇的輸 入端610，反相器600的輸出端612皆輸出高阻抗信號， 從而使得跟狀態選擇模組電性連接的各位元線形同開路， 因此寄生傳導路徑亦形同開路’使得第6圖之記憶胞組在 最壞讀取情況進行讀取測試。 由於被字元線5 0 4啟動的待測記憶胞5 1 4，其位元線 5 2 4會自動切換至與感測放大器5 1 8電性連接，而其他的 §己憶胞5 0 2無論是處於擦拭狀態或程式化狀態，寄生傳導 路徑已經開路，因此利用本發明之記憶體讀取測試的方 法’並不需要考慮記憶胞所處的狀態，就能直接以最壞讀 取情況對記憶胞進行讀取測試，而且不需要反覆對記憶胞 進行多次的擦拭動作或程式化動作，大大減少測試時間。 本發明之優點為提供了/種記憶體讀取測試之方法， 特別是有關於應用在快閃記憶體的讀取測試之方法。藉由 於讀取測試的模式中，以高阻抗與快閃記憶體中每一個記 憶胞電性連接，使得每一個記憶胞呈開路狀態，再啟動需 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------^---------^ (請先閱讀背面之注意事項再填寫本頁) 533420 A7 _B7_ 五、發明說明（） 要測試的記憶胞，模擬出快閃記憶體於最壞讀取情況時， 對每一個記憶胞進行讀取測試，如此可更有效地測試每一 個記憶胞的可靠度，提升產品的良率，且有助於設計人員 對快閃記憶體的電路設計作適當的改良，提供快閃記憶體 理想的操作環境。 如熟悉此技術之人員所瞭解的，以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消曹合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f )Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () The current 206 flowing from the cell 200, the daughter of the girl a ^ has a lot of parasitic conduction paths to the ground, because some memory cells are empty t ^ ^ The non-conducting state makes part of the parasitic conduction paths open. Therefore, in actual operation, the current flowing out of the activated memory cell, the number of flow paths it possesses. Will be less than in the best read case. Refer to FIG. 4 ′, which shows the circuit diagram of the memory cell group in FIG. 2 performing a reading test according to the conventional flash memory in FIG. 2, in which the memory cell 3GG is in the reading state. Because the number of parasitic conduction paths is reduced, the source cell of the memory cell 3GG activated via the character, line 104, and bit line 304 has a source voltage that is more than the source of the memory (20) in the ideal reading condition. The higher the voltage, the smaller the potential difference between the gate and the source of the memory cell 3, so the current 300 flowing out of the memory cell 300 also becomes smaller, which makes the measurement of the sense amplifier 204 difficult. Please refer to FIG. 5, which shows a circuit diagram of the memory cell group in the conventional flash memory according to FIG. 2 to perform a reading test at the worst reading condition, in which s has a memory cell 4 0 0 is in read state. When all the memory cells 102 in the memory cell group 00 are in a stylized state (that is, they are in a non-conducting state), 'the parasitic conduction paths have all been opened,' the word line 1 04 and the bit line 4 〇 4 The activated current 4 2 of the memory cell 4 0 2 can only flow along the path 2 1 0 from the source line 108 to the metal line 1 1 0 and then to the ground terminal 1 1 2. Therefore, the memory The voltage of the source of the cell 400 is higher than the source of the memory cell when it is actually read. 6 This paper is again applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male t) ----------- --------- Order --------- ^ (AW (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 533420 A7 B7 V. Description of the invention The higher the voltage of the () pole, the smaller the potential difference between the gate and the source of the memory cell 400, so the current 402 flowing out of the memory cell 400 also becomes smaller. It is more difficult to compare and measure the current 402, and the accuracy of the measurement is reduced, which reduces the reliability of reading. Because the general flash memory reads and measures The test is performed under ideal reading conditions, so when the flash memory cannot be read in the actual reading situation or the worst reading situation, it provides sufficient reading reliability, which affects the flash memory. Product yield. In addition, if you want to use the conventional flash memory read test method to perform a flash test on the worst-case flash memory, you must first wipe the memory cell group. Each memory cell is in a wiping state, and then the non-activated memory cells are programmed according to the sequence of the test design, so that all memory cells in the memory cell group except the memory cell to be tested are in a programmed state, and parasitic conduction The path is open, and the worst reading situation is simulated, and then the reading test is performed. However, since the memory cell group contains many memory cells, if each memory cell is to perform a reading test, the worst reading is simulated. In this case, it is necessary to repeatedly perform multiple wiping actions and stylized actions. For example, if the memory cell group 100 in FIG. 2 contains 32 memory cells 102, then at least 3 2 With China National Standard (CNS) A4 specification (210 X 297 meals) ------ I ---- I -------- Order ----- I (Please read the back first Please pay attention to this page and fill in this page again) 533420 Λ7 B7 V. Description of the invention (the wiping action and the stylized action printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs) and, in the flash memory, the worst-case reading is included. It is difficult to estimate the time for each memory test. Therefore, the test efficiency is urgently needed and the product method can be improved at the same time. Purpose and summary of the invention: The method in the above-mentioned background of the invention '疋 read test in an ideal reading cell, so failed Yield yield. In addition, if you want to read the worst case in each record, you need to repeat the action, so the test time is not consumed. The main purpose of the present invention is to refer to 'especially the application of the fast number provided to each drain cell of the memory cell. It is in an open circuit state, so that no flashback action is needed to simulate the flash memory to perform a memory cell reading test, which provides excellent product reliability. As a result, the test time takes a lot of time. There is a memory cell group of Zhongxi. If you want to simulate a cell for a grab test, you need a flash memory read test with a shortened test time and improved reliability. Known flash memory read test Under the circumstances, the memory cell group performs each memory for sufficient reading reliability, which affects the memory cell to perform a reading test, simulating multiple wiping actions and less programming, which increases the cost of the product. A memory read test is provided on the flash memory. By connecting the ground terminal of the high-impedance signal, the parasitic conduction path is covered by multiple wiping actions and the worst-case reading of the program memory, so the test time can be greatly shortened, and 8 paper sizes are applicable to Chinese national standards ( CNS) A4 size (210 x 297 mm) ------------ 黉 -------- tr --------- line Φ (Please read the Note: Please fill in this page again.) 533420 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A: B7_ V. Description of the invention () According to the purpose mentioned above, a method of memory reading test is provided, especially for application On flash memory. By providing a high-impedance signal to the ground terminal of the drain of each memory cell, the parasitic conduction path of each memory cell is open regardless of whether it is in a wiped or programmed state. After startup, the current can only flow to the ground of the metal wire along a single path. At this time, the flash memory read test is performed under the worst read condition, and different memory cells are read. During the test, there is no need to repeatedly perform wiping actions and stylized actions. This can more effectively test the reliability of each memory cell, save testing time, improve product yield, and help designers to quickly The circuit design of the flash memory is appropriately modified to provide an ideal operating environment for the flash memory. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, wherein: FIG. 1 is a schematic diagram showing the structure of a conventional flash memory array. FIG. 2 is a schematic circuit diagram showing a memory cell group of a conventional flash memory array structure. Figure 3 shows the memory cell paper size in the conventional flash memory according to Figure 2. The paper size of the Chinese national standard (CNS) A4 (210 X 297 g) is applicable (please read the precautions on the back before filling in this Page) # Order --------- line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 533420 __B7_ V. Description of the invention () Circuit diagram for reading test in the ideal reading condition. FIG. 4 is a schematic circuit diagram of a memory cell in a conventional flash memory according to FIG. 2 to perform a reading test during actual reading. FIG. 5 is a schematic circuit diagram of the memory cell in the conventional flash memory according to FIG. 2 to perform a read test in the worst case. FIG. 6 is a circuit diagram of a memory cell group of a flash memory in a read test according to an embodiment of the present invention. FIG. 7 is a schematic circuit diagram of a state selection module according to an embodiment of the present invention according to FIG. 6. Explanation of drawing numbers: 10 array structure 15 memory cell 20 source line 25 character line 30 bit line 100 memory cell group 102 memory cell 104 word line 106 bit line 108 source line 1 10 metal line 1 12 ground 114 Ground 200 memory cell 202 bit line 204 sense amplifier 206 current 210 path 212 path 300 memory cell 302 current 304 bit line 10 This paper & degree applies to China National Standard (CNS) A4 specifications (210 X 297 male f ) mn el · ^ iv 1 emml Hi nn an n · in flflfl n If a— n ^ ^ fn · He iv n flu «ϋ ϋ I (Please read the notes on the back before filling this page) Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 533420 A7 B7 V. Description of the invention () 400 memory cell 402 current 404 bit line 500 memory cell group 502 memory cell 504 word line 506 bit line 508 source line 510 metal line 5 12 ground terminal 514 Memory cell 516 state selection module 518 sense amplifier 520 current 522 path 524 bit line 600 inverter 602 and gate 604 input terminal 606 input terminal 608 output terminal 610 input terminal 612 output terminal invention detailed description: Please refer to FIG. 6, which is a schematic circuit diagram of a memory cell group of a flash memory in a read test according to an embodiment of the present invention, where the memory cell is 514 Reading. In order to simulate the worst-case read condition, as shown in FIG. 6, the state selection module 5 1 6 is electrically connected to the bit line '506 connected to the drain of each memory cell 502 in the memory cell group 5 00. . When the memory cell group 500 performs a read test, the state selection module 5 1 6 provides a high impedance signal, and then the word line 504 and the bit line 524 are pressed to activate the memory cell 5 14 and the bit line 5 06 Self-connected to the state selection module 5 1 6 The state of the electrical connection, cut π This paper size applies Chinese national standards (CNSM4 regulations (210 X 297 mm), -------- Order ----- ---- Line Φ (Please read the precautions on the back before filling out this page) 533420 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Switch to and sense amplifier 5 1 8 Electrical The connection status. Since all memory cells 5 02 are electrically connected to the state selection module 5 1 6 through the bit line 5 0 6, and the state selection module 5 1 6 provides high Impedance signal, so the parasitic conduction path from the source line 508 to the memory cell 502 to the bit line forms an open circuit, so that when the memory cell 5 i 4 is activated and the current 5 2 0 flows, the current 5 2 0 cannot follow The other parasitic conduction paths of the other memory cells 5 02 can only flow along the path 522 from the source line 5 0 8 to the metal line 5 1 0. Terminal 5 1 2. Therefore, the potential difference between the source and gate of the memory cell 5 1 4 becomes smaller, so that the current 5 2 0 flowing out of the memory cell 5 丨 4 becomes smaller. In this way, the sense amplifier can be tested 5 1 8 The measurement accuracy that can be provided when the memory cell 5 1 4 flows out a small current 5 2 0 in the worst reading situation. When it is necessary to test the other memory cells in the memory cell group 5 0 0 5 2 At this time, there is no need to perform a wiping action and a stylized action. Because the memory cell 5 0 2 is in a wiping state or a stylized state, the state selection module 5 1 6 is electrically connected to the bit line 5 0 6 to provide high The impedance signal makes the parasitic conduction path open circuit, so the current flowing from the memory cell 5 2 can only flow from the source line 5 0 8 to the metal line 5 1 0 to the ground terminal 5 1 2 during the test. Please refer to Fig. 7 is a schematic diagram showing a circuit of a state selection module according to an embodiment of the present invention according to Fig. 6. State in Fig. 12 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 'I 11 --- I ---- Order · -------- ^ «(Please read the precautions on the back first (Write this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 533420 Λ; B7 V. Description of the invention () State selection module 5 16 can be composed of inverter 600 and gate 602, and the input terminal 604 of gate 602 is In the test mode input, when the worst-case reading test is required, a high level or "1" signal is input to the input 604 of the AND gate 602; otherwise, a low level or "0" The signal is input to the input terminal 604; and the input terminal 606 of the gate is the start-up input of the sense amplifier in Fig. 6. When the sense amplifier needs to be started to measure the current signal of the memory cell, a high level or " A “1” signal is input to the input terminal 606 of the AND gate 602, and in other cases, a low level or “0” signal is input to the input terminal 606 of the AND gate 602. When the output terminal 608 of the AND gate 602 outputs a low level or "0" signal to the inverter 6 0 0, the inverter 6 0 0 will output an appropriate signal according to the signal input from the input 6 1 0 The signal is to the bit line electrically connected to each memory cell in FIG. 6. For example, when a high-level or “Γ” signal is input to the input terminal 610 of the inverter 600, the output terminal 612 of the inverter 600 outputs a low-level signal, so that each memory cell in FIG. 6 passes the bit line voltage. When connected to the status selection module, it is electrically connected to the ground terminal. At this time, the flash memory reading situation is the general actual reading situation; when a low level or "0" signal is input to the input terminal At 610, the output terminal 612 of the inverter 600 outputs a high-level signal. In addition, when the worst-case reading condition is required for a reading test, a high-level or "Γ" signal is input to the AND gate 602. Input 604, and because 13 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------ 1 «.1— HI i · — In · ϋ fl— sl «a-ammnn an 11 I (please read the precautions on the back before filling out this page) 533420 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 B7 V. Description of the invention The signal of level or “1,” will also be input to the input 606 of the AND gate 602, so the AND gate 60 The output terminal 608 of 2 outputs a high-level or “Γ” signal to the inverter 600. When the inverter 600 receives the high-level signal from the AND gate 602, either the high-level signal or the low-level signal is input to the input terminal 610 of the inverter 600, and the output terminal of the inverter 600 612 all output high-impedance signals, so that each element line electrically connected to the state selection module is in the same open circuit, so the parasitic conduction path is also in the same open circuit, so that the memory cell group in FIG. 6 is read in the worst reading condition. test. Since the memory cell 5 1 4 to be activated is activated by the character line 5 0 4, its bit line 5 2 4 is automatically switched to be electrically connected to the sense amplifier 5 1 8, and the other § memory cells 5 0 2 Regardless of whether it is in a wiping state or a stylized state, the parasitic conduction path is already open. Therefore, the method for reading and testing the memory according to the present invention does not need to consider the state of the memory cell, and can directly analyze the worst-case reading condition. The memory cell is tested for reading, and it is not necessary to repeatedly wipe or stylize the memory cell repeatedly, which greatly reduces the test time. An advantage of the present invention is to provide a method for reading a memory test, and more particularly to a method for reading a test applied to a flash memory. Because in the reading test mode, each memory cell in the flash memory is electrically connected with a high impedance, so that each memory cell is in an open state. Restarting requires this paper to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------------- ^ --------- ^ (Please read the notes on the back before filling this page ) 533420 A7 _B7_ V. Description of the invention () The memory cell to be tested simulates the flash memory in the worst-case reading condition, and each memory cell is tested for reading, so that each memory cell can be tested more effectively Reliability, improve product yield, and help designers make appropriate improvements to the flash memory circuit design, providing the ideal operating environment for flash memory. As will be understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all others completed without departing from the spirit disclosed by the present invention Effective changes or modifications should be included in the scope of patent application described below. (Please read the precautions on the back before filling out this page) Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 gf)