TW530375B

TW530375B - Method to improve the spacer loss

Info

Publication number: TW530375B
Application number: TW91105556A
Authority: TW
Inventors: Hun-Jan Tao; Yung-Hung Chiu
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-03-22
Filing date: 2002-03-22
Publication date: 2003-05-01

Abstract

The present invention provides a method to improve the spacer loss. Firstly, a substrate which has an isolation Structure is provided, a conductive layer and a mask layer are formed on the substrate; then the conductive layer and a blocking layer are etched on the isolation structure to form the gate, and the mask layer is remained on the gate; a spacer on the sidewall of the gate and the mask layer are formed, and the mask layeris removed.

Description

530375530375

淺溝槽隔離區（shallow trench is〇lati〇n)製程 g 來頗受重視的半導體製造技術，傳統上係利用化學氣^ 積（CVD)程序形成一介電層以填入基底的溝槽中，但隨著匕積體電路密度不斷提高而元件尺寸日漸縮小的發展，沈積技術並不易將介電層完全填滿溝槽，導致元件雜效果受到影響。離間隙壁（spacer )是一種以絕緣材料形成在閘極周圍之基底上以用來避免閘極與源/汲極導通而造成漏電流的絕緣層裝置，間隙壁的高度與閘極的高度相同是一種較佳的設計，可有效避免閘極與源/汲極導通。但是因為不平整的基底，例如因為製造隔離區時所形t 成之溝槽，此溝槽因為未被沉積介電層時所填滿而造成的Shallow trench isolatlon process is a highly regarded semiconductor manufacturing technology that traditionally uses a chemical vapor deposition (CVD) process to form a dielectric layer to fill the trenches of the substrate. However, with the continuous increase of the circuit density of the dimmer product and the development of the shrinking component size, it is not easy for the deposition technology to completely fill the trench with the dielectric layer, which will affect the device's heterogeneous effect. A spacer is an insulating layer device formed on the substrate surrounding the gate with an insulating material to avoid leakage current caused by the gate and source / drain conduction. The height of the spacer is the same as the height of the gate It is a better design that can effectively prevent the gate and source / drain from being conducted. However, because of an uneven substrate, such as a trench formed during the manufacture of the isolation region, the trench was caused by being filled when the dielectric layer was not deposited.

530375 五、發明說明（2) 凹陷區域’在介電層上形成絕緣層時，絕緣層會填入此凹陷區域中。請參考第1(a)-1(g)圖，第1(a)-1(g)圖係習知之形成間隙壁及去除凹陷區内殘留物質的方法之剖面示意圖。如第1(a)圖所示，首先，在形成有隔離區1〇之基底11 上依序沉積一導電層12及一遮蔽層13，且隔離區1〇與基底 11之間形成有凹陷區11 a ;凹陷區1 1 a的深度大約為丨〇〇 A 至1 0 0 0 A之間。其中，沉積的方法例如化學氣相沉積；而導電層1 2的材料例如是多晶矽；遮蔽層丨3係一定義圖案層’例如為有機底反射層（button anti-reflection coating，BARC)，有機介反射層（dielectric anti-reflection coating，DARC)或硬罩幕（hardmask); 其中，硬罩幕的材料如氮化矽、氮氧化矽、氧化物或複合材料等；隔離區1 〇則例如是淺溝槽隔離區（sha丨丨〇w trench isolation， STI)。一請參考第Kb)圖，光源透過光罩到達遮蔽層13，以將光罩上之圖案轉移至遮蔽層13，使遮蔽層13形成圖案化遮請^考第l(c〇 ® ’接著’以圖案化遮蔽層l3a為罩幕二二導電層12，使圖案化遮蔽層13的圖案有效轉移到導電層12上’使位於隔離區10上之導電層12形成間極。導 12a“其中，蝕刻的方法為濕蝕刻。隨著製程，、、極連線12a的高度會改變；例如在q13㈣銅晶片製程之問極連線南度為1.8KA ’〇.1〇//_晶片製程之閘極連線高度530375 V. Description of the invention (2) Recessed area 'When an insulating layer is formed on a dielectric layer, the insulating layer will fill the recessed area. Please refer to Figures 1 (a) -1 (g). Figures 1 (a) -1 (g) are schematic cross-sectional views of the conventional method for forming a partition wall and removing residual substances in the depression area. As shown in FIG. 1 (a), first, a conductive layer 12 and a shielding layer 13 are sequentially deposited on the substrate 11 on which the isolation region 10 is formed, and a recessed region is formed between the isolation region 10 and the substrate 11. 11 a; the depth of the recessed area 11 a is approximately between 100 A and 100 A. Among them, the deposition method is, for example, chemical vapor deposition; and the material of the conductive layer 12 is, for example, polycrystalline silicon; the shielding layer, 3, is a defined pattern layer, for example, an organic anti-reflection coating (BARC), Reflective layer (dielectric anti-reflection coating (DARC) or hardmask); Among them, the material of the hardmask is silicon nitride, silicon oxynitride, oxide or composite material, etc .; the isolation area 10 is, for example, shallow Trench isolation region (STI). First, please refer to Figure Kb), the light source passes through the mask to the shielding layer 13 to transfer the pattern on the mask to the shielding layer 13 so that the shielding layer 13 forms a patterned mask. The patterned masking layer 13a is used as the mask 22 and the conductive layer 12 to effectively transfer the pattern of the patterned masking layer 13 to the conductive layer 12 'so that the conductive layer 12 on the isolation region 10 forms a pole. Guide 12a "wherein, The etching method is wet etching. With the process, the height of the electrode connection 12a will change; for example, the south of the electrode connection in the Q13㈣ copper wafer process is 1.8KA '〇.1〇 // _ the gate of the wafer process Pole connection height

530375 五、發明說明（3) 為 1·5ΚΑ，0·〇7 //m 銅晶 κ 制 < 請參考第u I1程之閘極連線高度為1.MA。 13a移除，其中，移；荦進行微影製程後之圖案化遮蔽層有機溶液的濕餘刻^的方法可以是利用异行括士 i A以電聚去除的乾餘刻；同時，不論評t ^ 日因為去除®案化遮蔽層13a的動作而使凹區11a加深約200-300 A，成為凹陷區m。間極第1(:)Λ’去除圖案化遮蔽層13a後，接著在積形成ί二二4木面之隔離區1 〇及基底11上順應性沉 1 1 i开H缝^ ! 4 L當在閘極連線1 2a、隔離區1 0及基底 =成、、邑緣層14時，由於隔離區1()與基底u之間具有凹 = lla，因此絕緣層14亦會形成於凹陷區ιι&中。直中，料=層14的材料例如氮化石夕、氮氧化石夕、氧化物或複合材 =考第1⑴圖’然後，對絕緣層14進行 ^閉極連線12a之側壁形成與閉極連線心等 : ?極連線12a的頂部亦會略為被餘刻而 Γ ^ 貝，同蚪，因為絕緣層1 4會填入隔離區1 0與基氏π之間的凹陷區11&内，且凹陷區lla之寬度較窄，凹陷之絕緣層14無法被完全去除，因此會在凹陷區lla 内形成殘留絕緣層1 6。如第1(g)圖所示，為了將凹陷區lla内之 16徹底清除，在蝕刻絕緣層14以形成間隙壁之後，、必須曰再進行蝕過蝕刻（over etch)的步驟，以將凹陷區na内形成的殘留絕緣層16完全清除。雖然過蝕刻的動作可以將凹陷 0503-7094TWF(N) ; TSMC200M012 ； Claire.ptd 第6頁 530375 五、發明說明（4) 區11a内的殘留絕緣層16徹底清除，然而，過蝕隙壁1 5損失，而使原本與閑極連線1 ^ 曰曰成高度低於間極連線i 2a的間的間隙壁1 5變壞間極連線…的頂部而造成=失，時，過㈣會破在進行後續之自我對準金屬矽化物製程的高度較閘極連線12a的高度為低，容易使閘極^530375 V. Description of the invention (3) is 1.5kA, 0 · 〇7 // m copper crystal κ system < Please refer to the gate connection height of uA1 is 1.MA. 13a is removed, wherein, the method of wet etching of the organic solution of the patterning masking layer after the lithography process is performed may be a dry etching that is removed by electropolymerization using an isotropic bracket i A; at the same time, regardless of the evaluation At t ^, the recessed area 11a is deepened by about 200-300 A due to the action of removing the masking layer 13a, and becomes the recessed area m. After the first (:) Λ ′ of the pole is removed from the patterned masking layer 13a, it is then formed on the isolation region 10 and the substrate 11 to conform to the conformation of the substrate 11 and the gap 11! When the gate line 12a, the isolation area 10, and the base = Cheng, Yi margin layer 14, because there is a recess = lla between the isolation area 1 () and the base u, the insulating layer 14 will also be formed in the recessed area ιι & in. In the straight material, the material of the layer 14 is, for example, nitride stone, oxynitride, oxide, or composite material = see Figure 1 below. Then, the insulating layer 14 is formed with the side wall of the closed electrode connection 12a and connected to the closed electrode. Line center, etc .: The top of the pole connection 12a will also be slightly engraved and Γ ^, the same, because the insulating layer 14 will fill the recessed area 11 & between the isolation area 10 and the Ki π, and The recessed area 11a has a narrow width, and the recessed insulating layer 14 cannot be completely removed, so a residual insulating layer 16 will be formed in the recessed area 11a. As shown in FIG. 1 (g), in order to completely remove 16 in the recessed area 11a, after the insulating layer 14 is etched to form a gap wall, an over etch step must be performed to dent the recess. The residual insulating layer 16 formed in the region na is completely removed. Although the over-etching action can completely remove the recesses 0503-7094TWF (N); TSMC200M012; Claire.ptd Page 6 530375 V. Description of the invention (4) The residual insulating layer 16 in the area 11a is completely removed, however, the over-etched gap wall 1 5 Loss, and the original connection with the idle pole 1 ^ said that the height is lower than the gap between the inter pole connection i 2a 15 and the top of the inter pole connection ... The height of the subsequent self-aligned metal silicide process is lower than the height of the gate connection 12a, which makes it easy to make the gate ^

Ue^ka形成在基底U内之源/ ;及極（未顯示）短路而有漏電流 (leakage current)產生，嚴重影響產品的可 (reliability)。罪又有鑑於此，本發明之目的在於提供一種改善間隙壁中= 以徹底清除因為形成隔離區所造成的凹陷區 = 但是會減少對閘極連線與間隙壁的傷害。本^ ^ t +知a杈供種改善間隙壁損失的方 ί ·，=?步Γ提供一基底’其中基底具有-隔離結 υίΐΐϊ 一導電層及一遮蔽層；蝕刻位於隔上：遮蔽層及導電層以形成閘#，並保留閘極上之層，输及遮蔽層之側壁形成一間隙壁；及去除遮根二土述目的’本發明更提供一種改善間隙壁損失的底且右匕兔:列步驟·提供一半導體基底，其中半導體基淺溝槽隔離結構；於具有淺溝槽隔離結構之半導及；^墓依序形成一多晶石夕層及—硬罩幕；餘刻多晶石夕層 m令卩於淺溝槽隔離結構上形成一閉極連線，並於閘極連線上保留硬罩幕；&閘極連線及硬罩幕之側壁形成一 0503-7094TWF(N) ； TSMC20〇M〇i2 ； Claire.ptd 530375 五、發明說明（5) 間隙壁；及去除硬罩幕。實施例：凊參考第2(a)-2(b)圖，第2(a) -2(f)圖係本發明之形成間隙壁及去除凹陷區内殘留物質的方法之剖面示意圖。如第2(a)圖所示，首先，在形成有隔離區2〇之基底21 上依序沉積一導電層22及一遮蔽層23，且隔離區20與基底 21之間形成有凹陷區21a ;凹陷區21a的深度大約為100A 至1 0 0 0 A之間。其中，沉積的方法例如化學氣相沉積；而導電層22的材料例如是多晶矽；遮蔽層23係一定義圖案層’例如為有機底反射層（button anti-reflection coating，BARC)，有機介反射層（dielectric anti reflection coating，DARC)或硬罩幕（hardmask)，厚度約200A-1000A ;其中，硬罩幕的材料如氮化矽、氮氧化矽、氧化物或複合材料等；隔離區2〇則例如是淺溝槽隔離區（shallow trench isolation， STI)。請參考第2(b)圖，光源（未顯示）透過光罩（未顯示）到達遮蔽層23，以將光罩上之圖案轉移至遮蔽層23，使遮蔽層23形成圖案化遮蔽層23a。請參考第2(c)圖，接著，以圖案化遮蔽層23a為罩幕，蝕刻導電層2 2，使圖案化遮蔽層2 3的圖案有效轉移到導電層22上，使位於隔離區20上之導電層22形成閘極連線 2 2a，接著，並於閘極22a的側面及基底21的表面上形成保護層（未顯示）；其中，蝕刻的方法為濕蝕刻。隨著製程的、不同’閘極連線22a的高度會改變；例如在〇·丨3 Am銅晶Ue ^ ka forms a source /; inside the substrate U; and a pole (not shown) is short-circuited and a leakage current is generated, which seriously affects the reliability of the product. In view of this, the object of the present invention is to provide an improvement in the gap wall = to completely remove the recessed area caused by the formation of the isolation zone = but to reduce the damage to the gate connection and the gap wall. This article provides a method for improving the loss of the gap wall. Step 1: Provide a substrate, where the substrate has an isolation junction, a conductive layer and a shielding layer; the etching is located on the partition: the shielding layer and The conductive layer forms a gate #, and the layer on the gate electrode is retained, and the side wall of the transmission and shielding layer forms a gap wall; and the purpose of removing the two roots of the covering soil is described. The present invention further provides a bottom and right dagger that improves the loss of the gap wall: Steps: Provide a semiconductor substrate, in which a semiconductor-based shallow trench isolation structure; a semiconductor having a shallow trench isolation structure; and ^ a polycrystalline stone layer and a hard mask are sequentially formed in the tomb; The Shi Xi layer m makes a closed-gate connection formed on the shallow trench isolation structure, and a hard cover is retained on the gate connection; & the gate connection and the side wall of the hard cover form a 0503-7094TWF ( N); TSMC200M0i2; Claire.ptd 530375 V. Description of the invention (5) Partition wall; and removing the hard cover. Examples: 凊 Refer to Figures 2 (a) -2 (b). Figures 2 (a) -2 (f) are schematic cross-sectional views of the method of forming a partition wall and removing residual substances in a recessed area according to the present invention. As shown in FIG. 2 (a), first, a conductive layer 22 and a shielding layer 23 are sequentially deposited on the substrate 21 on which the isolation region 20 is formed, and a recessed region 21a is formed between the isolation region 20 and the substrate 21. ; The depth of the recessed area 21a is about 100A to 100 A. Among them, the deposition method is, for example, chemical vapor deposition; and the material of the conductive layer 22 is, for example, polycrystalline silicon; the shielding layer 23 is a defined pattern layer, for example, an organic anti-reflection coating (BARC), or an organic dielectric reflection layer. (Dielectric anti reflection coating (DARC) or hardmask) with a thickness of about 200A-1000A; among them, the material of the hardmask is silicon nitride, silicon oxynitride, oxide, or composite materials, etc .; For example, it is a shallow trench isolation (STI). Referring to FIG. 2 (b), the light source (not shown) reaches the masking layer 23 through the mask (not shown) to transfer the pattern on the mask to the masking layer 23, so that the masking layer 23 forms a patterned masking layer 23a. Please refer to FIG. 2 (c). Next, using the patterned masking layer 23a as a mask, the conductive layer 22 is etched to effectively transfer the pattern of the patterned masking layer 23 to the conductive layer 22 so as to be located on the isolation region 20. The conductive layer 22 forms a gate connection 22a, and then a protective layer (not shown) is formed on the side surface of the gate 22a and the surface of the substrate 21; the etching method is wet etching. Depending on the process, the height of the gate gate 22a will change; for example, at 0 · 丨 3 Am copper

530375 五、發明說明（6) · ------530375 V. Description of the invention (6) · ------

Sd’ ΐ連線高度為i 8κα，〇·1〇㈣銅晶片製程之閘極呵又為1· 5KA，〇· 07 銅晶片製程之閘極連線高度丄· Z K A 〇 ^ 请參考第2(d)圖，接著在圖案化遮蔽層23a、閘極連、露出表面之隔離區2〇及基底21上順應性沉積形成絕緣層24。當在閘極連線22a、隔離區2〇及基底21上形成絕緣層24時，由於隔離區2〇與基底21之間具有凹陷區 21 a，因此絕緣層24亦會形成於凹陷區2 i a中。其中，絕緣 f 24的材料例如氮化矽、氮氧化矽、氧化物或複合材料' 等。請參考第2(e)圖，對絕緣層24進行蝕刻，，以在隔離區 20上方之閘極連線22a及圖案化遮蔽層23a之側壁形成與圖案化遮蔽層23a頂部等高度之間隙壁25，此時圖案化遮蔽‘ 層23a的厚度約會減少至2〇〇 a —600 a的厚度。同時，因為絕緣層24會填入隔離區20與基底21之間的凹陷區21a内， ^凹陷區2 la之寬度較窄，凹陷區21a内之絕緣層24無法被 70全去除，因此會在凹陷區2ia内形成殘留絕緣層26。其中，餘刻絕緣層2 4的方法為乾餘刻，即在5 χ 1 〇_3至1 5 〇_3拢耳（torr)的壓力下利用氟烷氣體以1〇cm3/miris8〇⑽3/ min的速率蝕刻絕緣層24 ;氟烷氣體例如是一氟甲烷 (CHsF)、二氟甲烷（CHJ2)、三氟甲烷（CHF3)或四氟化碳 (CF4)。請參考第2(f)圖，最後，將圖案化遮蔽層23a移除，其中’移除圖案化遮蔽層2 3 a的方法可以是利用有機溶液The connection height of Sd '为 is i 8κα, 〇 · １０㈣ The gate height of the copper wafer process is 1.5KA, 〇07 The connection height of the gate of the copper wafer process 丄 · ZKA 〇 ^ Please refer to Section 2 ( d), and then an insulating layer 24 is formed on the patterned masking layer 23a, the gate electrode, the isolation region 20 exposed on the surface, and the substrate 21 by compliant deposition. When the insulating layer 24 is formed on the gate line 22a, the isolation region 20, and the substrate 21, the insulating layer 24 will also be formed in the recessed region 2 because there is a recessed region 21a between the isolation region 20 and the substrate 21. in. Among them, the material of the insulating f 24 is, for example, silicon nitride, silicon oxynitride, oxide, or composite material. Referring to FIG. 2 (e), the insulating layer 24 is etched to form a barrier wall at the same height as the top of the patterned shielding layer 23a on the sidewalls of the gate lines 22a and the patterned shielding layer 23a above the isolation region 20. 25, the thickness of the patterned masking layer 23a at this time is reduced to a thickness of 200a to 600a. At the same time, because the insulating layer 24 fills the recessed area 21a between the isolation region 20 and the substrate 21, the width of the recessed area 21a is narrow, and the insulating layer 24 in the recessed area 21a cannot be completely removed by 70, so A residual insulating layer 26 is formed in the recessed area 2ia. Among them, the method of etching the insulating layer 24 is dry etch, that is, under the pressure of 5 × 1 〇_3 to 15 〇_3 torr, using a halothane gas at 10cm3 / miris8〇⑽3 / The insulating layer 24 is etched at a rate of min; the fluoroalkane gas is, for example, monofluoromethane (CHsF), difluoromethane (CHJ2), trifluoromethane (CHF3), or carbon tetrafluoride (CF4). Please refer to FIG. 2 (f). Finally, the patterned masking layer 23a is removed. The method of removing the patterned masking layer 2a may be to use an organic solution.

530375 五、發明說明（7) 濕蝕刻’或以電漿去除的乾蝕刻；同時，不論是何 …都會因為去除圖案化遮蔽層23a的動作 = 緣層26被去除；且閘極連線22a之頂部僅 t發明所提供之改善間隙壁損失的方法主間二:，[㈣00,00 A厚度的圖案化遮蔽層= 且高度會超過閘極連線… :二ΐ:面於閘極連線…的緣故，因此在以蝕刻的方法 Π; 蔽層_ ’可以有效徹底清除凹陷區…内 tlS緣層26;同時’因為在移除圖案化遮蔽層…之成間隙壁25的關係，在移除圖案化遮蔽層23a時亦 "X到部分的間隙壁25，使得間隙壁25略為減少，變成與閘極連線22a相同高度之間隙壁25a。取也因為不需要進行過蝕刻以去除殘留絕緣層26的 ^此本發明所提供之方法不會使閘極連線仏的頂部大1損失，亦不會使凹陷區21a的深度變深。而且，間隙壁25a的高度與閘極連線22a的高度相同，所以使閘極連線22a與形成在基底21内之源/汲極（未顯示）不容易笋生紐路而有漏電流產生，因此不會影響產品的可靠度久 (reliability)。如此一來，本發明除了比習知所採用的方法施行較的步驟，達到降低成本的目的之外，更能確保產品之可、度。罪 0503-7094TWF(N) ; TSMC200M012 ; Claire.ptd 第10頁 530375 五、發明說明（8) 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。530375 V. Description of the invention (7) Wet etching or dry etching with plasma removal; at the same time, no matter what ... it will be because the action of removing the patterned masking layer 23a = the edge layer 26 is removed; and the gate connection 22a The top part is only the method provided by the invention for improving the loss of the spacer. The main part is: [㈣00,00 A thickness of the patterned shielding layer = and the height will exceed the gate connection ...: Two: The surface is connected to the gate ... Because of this, the etching method Π; the mask layer _ 'can effectively and completely remove the recessed area ... within the tlS edge layer 26; at the same time' because the patterned mask layer is removed ... When the shielding layer 23a is patterned, "X" to a part of the gap wall 25, so that the gap wall 25 is slightly reduced, and becomes a gap wall 25a having the same height as the gate line 22a. This is because the over-etching is not required to remove the remaining insulating layer 26. The method provided by the present invention does not cause the top of the gate line 仏 to be lost by one, nor does it deepen the depth of the recessed region 21a. Moreover, the height of the spacer 25a is the same as the height of the gate connection 22a, so that it is not easy for the gate connection 22a to form a source / drain (not shown) formed in the substrate 21 and a leakage current is generated. , So it does not affect the reliability of the product (reliability). In this way, in addition to performing more steps than the conventional method, the present invention achieves the purpose of reducing costs, and can more ensure the availability of the product. Crime 0503-7094TWF (N); TSMC200M012; Claire.ptd Page 10 530375 V. Description of the Invention (8) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art Changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

0503-7094TWF(N) ； TSMC200M012 ； Claire.ptd 第11頁 530375 圖式簡單說明為使本發明之上述和其他目的、特徵及優點能更明顯易懂’下文特舉出較佳實施例，並配合圖式作詳細說明如下：第1 (a ) -1 ( g )圖係習知之形成間隙壁及去除凹陷區内殘留物質的方法之剖面示意圖。第2 (a)-2(f)圖係本發明之形成間隙壁及去除凹陷區内殘留物質的方法之剖面示意圖。符號說明： 1 0〜隔離區； 1 la〜凹陷區 12〜導電層 1 3〜遮蔽層 1 4〜絕緣層 1 6〜殘留絕緣層 21〜基底； 2 2〜金屬層 2 3〜遮蔽層 2 4〜絕緣層 2 6〜殘留絕緣層 11〜基底； 11 b〜凹陷區； 1 2 a〜閘極連線； 13a〜圖案化遮蔽層 1 5〜間隙壁； 2 0〜隔離區； 2 la〜凹陷區； 2 2 a〜閘極； 23a〜圖案化遮蔽層 2 5〜間隙壁；0503-7094TWF (N); TSMC200M012; Claire.ptd p. 11 530375 The diagram briefly illustrates the above and other objects, features, and advantages of the present invention to make it more obvious and easier to understand. The drawings are explained in detail as follows: Figures 1 (a) to 1 (g) are cross-sectional schematic diagrams of a conventional method for forming a partition wall and removing residual substances in a recessed area. Figures 2 (a) -2 (f) are schematic cross-sectional views of the method of forming a partition wall and removing residual substances in a recessed area according to the present invention. Explanation of symbols: 1 0 ~ isolated area; 1 la ~ recessed area 12 ~ conductive layer 1 3 ~ shielding layer 1 4 ~ insulating layer 16 ~ remaining insulating layer 21 ~ base; 2 2 ~ metal layer 2 3 ~ shielding layer 2 4 ~ Insulating layer 2 6 ~ Residual insulating layer 11 ~ Base; 11 b ~ Depression area; 1 2 a ~ Gate connection; 13a ~ Patterned shielding layer 15 ~ Spacer wall; 2 0 ~ Isolation area; 2 la ~ Depression Area; 2 2 a ~ gate electrode; 23 a ~ patterned shielding layer 2 5 ~ gap wall;

0503-7094TWF(N) ； TSMC2001-1012 ； Claire.ptd 第12頁0503-7094TWF (N); TSMC2001-1012; Claire.ptd page 12

Claims

530375 六、申請專利範圍一種改善間隙壁損失的方法，包括下列步驟：提供一基底，其中該基底具有一隔離結構；於A基底上依序形成一導電層及一遮蔽層；餘刻位於該隔離結構上之該遮蔽層及該導電層以形成閘極，並保留該閘極上之該遮蔽層； 9 ^ 於該閘極及該遮蔽層之側壁形成一間隙壁；及去除該遮蔽層。、2·如申請專利範圍第1項所述之改善間隙壁損失的方法’其中在形成該間隙壁之前更包括下列步驟：該閘極及該遮蔽層之側壁形成一保護層。 3 ·如申請專利範圍第2項所述之改善間隙壁損失的方法，其中該保護層為墊氧化層。 4 ·如申請專利範圍第1項所述之改善間隙壁損失的方法，其中該閘極為閘極連線。 5 ·如申請專利範圍第1項所述之改善間隙壁損失的方法’其中該導電層之材料為多晶矽。，6 ·如申請專利範圍第1項所述之改善間隙壁損失的方法’其中該遮蔽層為有機底反射層。 7 ·如申請專利範圍第1項所述之改善間隙壁損失的方法’其中該遮蔽層為有機介反射層。 8 ·如申請專利範圍第1項所述之改善間隙壁損失的方法，其中該遮蔽層為硬罩幕層。 9 ·如申請專利範圍第1項所述之改善間隙壁損失的方法’其中該遮蔽層的厚度為2〇〇至1000A。530375 VI. Scope of Patent Application A method for improving the loss of a spacer comprises the following steps: providing a substrate, wherein the substrate has an isolation structure; sequentially forming a conductive layer and a shielding layer on the A substrate; and the rest is located at the isolation The shielding layer and the conductive layer on the structure form a gate, and the shielding layer on the gate is retained; a gap is formed on the gate and a sidewall of the shielding layer; and the shielding layer is removed. 2. The method for improving the loss of the spacer according to item 1 of the scope of the patent application, wherein the method further includes the following steps before forming the spacer: the gate and the side wall of the shielding layer form a protective layer. 3. The method of improving the barrier wall loss as described in item 2 of the patent application scope, wherein the protective layer is a pad oxide layer. 4 · The method for improving the loss of the partition wall as described in item 1 of the scope of patent application, wherein the gate is connected to the gate. 5. The method for improving the loss of the spacer as described in item 1 of the scope of the patent application, wherein the material of the conductive layer is polycrystalline silicon. 6. The method for improving the loss of the partition wall as described in item 1 of the scope of the patent application, wherein the shielding layer is an organic bottom reflection layer. 7-The method for improving the loss of the partition wall according to item 1 of the scope of the patent application, wherein the shielding layer is an organic dielectric reflection layer. 8. The method for improving the loss of the partition wall as described in item 1 of the scope of the patent application, wherein the shielding layer is a hard cover curtain layer. 9 · The method for improving the loss of the partition wall according to item 1 of the scope of the patent application ', wherein the thickness of the shielding layer is 200 to 1000A.

0503-7094TWF(N) ； TSMC200M012 ； Claire.ptd 第 13 頁 530375 六、申請專利範圍、1 〇·如申請專利範圍第1項所述之改善間去其中该遮蔽層為選自氮化砍、氮氧化硬合材料其中之一。、11 ·如申請專利範圍第1項所述之改善間茂法’其中該間隙壁為選自氮化石夕、氮氧化石夕、合材料其中之一。 1 2 · —種改善間隙壁損失的方法，包括下^ 提供一半導體基底，其中該半導體基底且隔離結構；一於具有該淺溝槽隔離結構之該半導體基底一多晶矽層及一硬罩幕；餘刻該多晶矽層及該硬罩幕以於該淺溝槽形成一閘極連線，並於該閘極連線上保留該硬於該閘極連線及該硬罩幕之侧壁形成一間去除該硬罩幕。 1 3 ·如申請專利範圍第丨2項所述之改善間p 方法，其中該硬罩幕選自氮化矽、氮氧化矽、合材料其中之一。 1 4 ·如申請專利範圍第1 2項所述之改善間方法，其中該硬罩幕之厚度為2〇〇至1000A。 1 5 ·如申請專利範圍第丨2項所述之改善間P 方法，其中該間隙壁為氮化石夕、氮氧化矽、氧材料。〔壁損失的方氧化層及複壁損失的方氧化層及複 4步驟：有一淺溝槽上依序形成隔離結構上罩幕；隙壁；及 ί壁損失的氧化層及複 R壁損失的 R壁損失的化層及複合0503-7094TWF (N); TSMC200M012; Claire.ptd Page 13 530375 VI. Application scope, 1 〇 · Improvement as described in item 1 of the scope of patent application where the shielding layer is selected from the group consisting of nitrided nitrogen, nitrogen One of oxidized hardened materials. 11. The improvement method according to item 1 of the scope of patent application, wherein the partition wall is one selected from the group consisting of nitride stone, oxynitride, and composite materials. 1 2 · A method for improving loss of a spacer, including providing a semiconductor substrate, wherein the semiconductor substrate and an isolation structure; a polycrystalline silicon layer and a hard mask on the semiconductor substrate having the shallow trench isolation structure; The polycrystalline silicon layer and the hard mask form a gate connection in the shallow trench at a time, and the hard connection between the gate connection and the side wall of the hard mask is formed on the gate connection to form a gate connection. Remove the hard hood. 1 3 · The improved method as described in item 2 of the patent application scope, wherein the hard mask is selected from one of silicon nitride, silicon oxynitride, and composite materials. 1 4 · The improvement method as described in item 12 of the scope of patent application, wherein the thickness of the hard cover is 200 to 1000A. 15 · The improved P method as described in the item 2 of the scope of the patent application, wherein the partition wall is made of nitride nitride, silicon oxynitride, and oxygen materials. [Square oxide layer lost by the wall and square oxide layer lost by the double wall and compound 4 steps: A shallow trench is sequentially formed with an upper cover of the isolation structure; the gap wall; and the oxide layer lost by the wall and the compound R wall is lost Chemical layer and compound of R wall loss

0503-7094TW(N) ； TSMC20〇M〇i2 ； Claire.ptd 第14頁0503-7094TW (N); TSMC20〇Moi2; Claire.ptd Page 14