TW527840B

TW527840B - Synchronization of a low power oscillator with a reference oscillator in a wireless communication device utilizing slotted paging

Info

Publication number: TW527840B
Application number: TW088113890A
Authority: TW
Inventors: Mbrian K Butler; Kenneth D Easton; Nicholas K Yu
Original assignee: Qualcomm Inc
Priority date: 1998-08-14
Filing date: 2000-10-24
Publication date: 2003-04-11
Also published as: US6333939B1; AU5563599A; KR20010072500A; CN1130096C; WO2000010354A1; EP1106027A1; KR100577545B1; JP2002523936A; AR024828A1; HK1040872B; CA2340446A1; BR9912991A; JP4481495B2; CN1323494A; HK1040872A1

Abstract

A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock (224) for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit (208) for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator (217) for measuring an estimated low frequency clock error; and a sleep controller (222) for removing power from the clock signal generator (202) for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

Description

527840 五、發明說明（1) 發明背景 I .發明領域「本發明係關於無線通訊裝置之時脈信號產生。特別本發明係關於一種新穎及改良之於無線通訊裝置利用分時呼叫同步化低功率振盪器與參考振盪器之方法及電。 II.相關技術之說明典型無線通訊系統中，分時呼叫被用以延長行動站待機時間，因而延長電池壽命。行動站例如為蜂巢式或P C S電話或無線當地回路（W L L)手機。例如於美國專利第 5，3 9 2，2 8 7號名稱「於行動接收機減少功率消耗之裝置及方法」1 9 9 5年2月2 1日獲頒且讓與本發明之受讓人，併述於此以供參考，敘述之無線電話系統中，揭示一種分時呼叫系統。前述專利案中，敘述一種於具有發送機及一或多部接收機的通訊系統中減少接收機的功率消耗之系統，其中來自發送機至接收機的定期訊息被排程於「時槽」。各接收機於監視傳輸時被指定一時槽。發送機唯有於指定的時槽發送訊息至該接收機。接收機於其指定的時槽處於「激活態」。如果訊息要求接收機執行額外動作，則接收機於其指定時槽之後可保持激活態。此種激活態常稱作「叫醒」態。於「鈍化態」期間，此乃連續指定的時槽出現間的時間間期，接收機可能執行任何無須與發送機協調的動作。此段期間藉由由一或多個組件去除功率例如監視傳輸的組件527840 V. Description of the invention (1) Background of the invention I. Field of invention "The present invention relates to the generation of clock signals for wireless communication devices. In particular, the present invention relates to a novel and improved wireless communication device using time-sharing to synchronize low power Method and electricity of oscillator and reference oscillator. II. Description of related technology In a typical wireless communication system, time-sharing calling is used to extend the standby time of a mobile station, thereby extending battery life. Mobile stations are, for example, cellular or PCS phones or A wireless local loop (WLL) mobile phone. For example, it was awarded on February 21, 1995, under the name "Apparatus and Method for Reducing Power Consumption in Mobile Receivers" in US Patent Nos. 5, 3, 9 and 2, 87. A time-sharing call system is disclosed in the wireless telephone system described herein for the assignee of the present invention and described herein for reference. In the aforementioned patent, a system for reducing power consumption of a receiver in a communication system having a transmitter and one or more receivers is described, in which regular messages from the transmitter to the receiver are scheduled in a "time slot". Each receiver is assigned a time slot when monitoring transmissions. The sender can only send messages to the receiver in the specified time slot. The receiver is "active" at its designated time slot. If the message requires the receiver to perform additional actions, the receiver can remain active after its designated time slot. This activation state is often referred to as the "wake-up" state. During the "passivation state", which is the time period between consecutively specified time slots, the receiver may perform any action that does not require coordination with the transmitter. During this period, power is removed by one or more components, such as monitoring transmitted components

第5頁 527840 五、發明說明（2) 去除功率可節省電力。此種鈍化態常稱作「休眠」態。於指定時槽之前不久於鈍化態期間，接收機外加功率至此等組件並執行初始化動作。若於先前鈍化態期間，接收機的時序信號已經偏離非與發送機同步，則初始化可能包括重新獲得一試驗頻道信號，接收機使本身與該信號同步。當行動站處於待機模時，換言之未完全活性接合一呼叫時，待機時間以及電池壽命係由行動站處於休眠模消耗電流量多達主控。於典型行動站，當行動站處於休眠模時，· >肖耗功毕約為於待機模期間平均電流 >肖耗ϊ之半。雖然行動站處於休眠模，但須至少維持一計數器來測量休眠時間，因此當於次一被指定的時槽時可「醒來」。於大半行動站，使用極為準確的時間參考值例如溫度補償晶體振盪器（TCX0)來測量休眠時間。1：外其它時脈信號產生電路例如時脈緩衝器、時脈劃分器及其它相關時脈產生元件典型須用以由TCX0參考值產生一有用且可靠的時脈信號。雖然如此獲得高度準確的時脈計畫，但全部組件仍消耗相當ΐ電流’約為3宅老j。為了降低休眠期的電流消耗，藉此延長待機時間，提議於脉眠模期間須關閉TCX0以及相關時脈信號產生電路，且使用低功率較低準確度的晶體振盪器替代。由於TCX0許可的準確度及TCX0產生的高頻於行動站醒來時最要緊，故提議使用低功率振盪器來計量休眠間，此時準確度較為不具關鍵重要性，且高時脈頻率解析度也較不重要。此外，低功率低頻晶體振盪器製造上相對廉價，普遍用Page 5 527840 V. Description of the invention (2) Removing power can save electricity. This passive state is often referred to as the "dormant" state. During the passive state shortly before the specified time slot, the receiver applies power to these components and performs initialization. If the timing signal of the receiver has deviated from being synchronized with the transmitter during the previous passivation state, initialization may include reacquiring a test channel signal and the receiver synchronizing itself with the signal. When the mobile station is in the standby mode, in other words, a call is not fully active, the standby time and battery life are consumed by the mobile station in the sleep mode as much as the main flow. In a typical mobile station, when the mobile station is in the sleep mode, > Xiao's power consumption is about half the average current during the standby mode > Although the mobile station is in sleep mode, it must maintain at least a counter to measure the sleep time, so it can "wake up" when the next time slot is specified. At most mobile stations, sleep time is measured using extremely accurate time references such as a temperature compensated crystal oscillator (TCX0). 1: External clock signal generation circuits such as clock buffers, clock dividers, and other related clock generation components are typically used to generate a useful and reliable clock signal from the TCX0 reference value. Although a highly accurate clock plan is obtained in this way, all the components still consume a considerable amount of current, which is about 3 years old. In order to reduce the current consumption during the sleep period and thereby extend the standby time, it is proposed that the TCX0 and related clock signal generating circuits must be turned off during the pulse sleep mode, and a low-power, low-accuracy crystal oscillator should be used instead. Because the accuracy of the TCX0 license and the high frequency generated by the TCX0 are most important when the mobile station wakes up, it is proposed to use a low-power oscillator to measure the sleep interval. At this time, accuracy is less critical and high clock frequency resolution. Less important. In addition, low-power low-frequency crystal oscillators are relatively inexpensive to manufacture and are commonly used

第6頁 527840 五、發明說明（3) 於手錶等用途。因此供應來源易得。其比較較為準確的晶體振盪器消耗電流也極小，約為0. 0 1 5毫安。所有此等電流節省及成本使其用於行動站計量休眠期具有吸引力。但此等低功率低頻晶體振盪器之缺點在於於預期的作業溫度範圍對溫度變化敏感，變化約為60 PPM。其無法校正且無法補償。此外時間解析度粗糙。所有此等誤差皆減低其適當監控行動站休眠期的能力。一種補償此等低功率晶體振盪器特有誤差之方式提示於· 美國專利第5，4 2 8，8 2 0號，名稱「適應性無線接收機控制器方法及裝置」，1 9 9 5年6月2 7日獲頒且讓與摩托羅拉公司。本專利案中，行動站利用低成本、低功率、低頻振盪器來計量休眠期。低功率振盪器之特有誤差藉由依據前一休眠期的時序準確度調適目前休眠期長度考慮在内。換言之，若前一休眠期由於低功率振盪器的誤差導致時間過長，則行動站於目前休眠期將提早醒來。為了決定休眠期是否過長或過短，行動站尋找一獨特字，例如來自發送器的訊息前言其表示被指定時槽的起點。若未接收到獨特字，則行動站太晚被叫醒故縮短休眠期。若接收到一有效獨特字，則行動站準時或過早叫醒，因此略微增長休眠時間。 5，4 2 8，8 2 0專利案之一大缺點為其仰賴偶爾不正確的接收到獨特字來找到正確的休眠期。又若獨特字未被正確接收以及解調，則休眠期基於預期修眠期長度為錯誤長度而’ 被改變。除了獨特字未被準確接收及解調之休眠期長度理Page 6 527840 V. Description of the invention (3) For watches and other purposes. Therefore, sources of supply are readily available. Its relatively accurate crystal oscillator consumes very little current, about 0. 1 5 mA. All these current savings and costs make it attractive for mobile stations to measure dormant periods. However, the disadvantage of these low-power low-frequency crystal oscillators is that they are sensitive to temperature changes over the expected operating temperature range, which is about 60 PPM. It cannot be corrected and cannot be compensated. In addition, the time resolution is rough. All these errors reduce their ability to properly monitor the dormant period of the mobile station. A way to compensate for the unique errors of these low-power crystal oscillators is suggested in US Patent No. 5, 4 2 8, 8 2 0, entitled "Adaptive Wireless Receiver Controller Method and Device", 195 5 Awarded and transferred to Motorola on March 27. In this patent, the mobile station uses a low-cost, low-power, low-frequency oscillator to measure the sleep period. The low-power oscillator-specific error is taken into account by adjusting the current sleep period length based on the timing accuracy of the previous sleep period. In other words, if the previous sleep period is too long due to the error of the low-power oscillator, the mobile station will wake up early in the current sleep period. In order to determine whether the sleep period is too long or too short, the mobile station looks for a unique word, such as a preamble of a message from a transmitter, which indicates the beginning of a designated time slot. If no unique word is received, the mobile station wakes up too late and shortens the dormant period. If a valid unique word is received, the mobile station wakes up on time or prematurely, thus increasing the sleep time slightly. One of the major shortcomings of the 5,4,8,20 patents is that they rely on the occasional incorrect reception of unique words to find the correct dormant period. If the unique word is not correctly received and demodulated, the dormant period is changed based on the expected length of the dormant period. Except for the length of the dormant period in which the unique words are not accurately received and demodulated

第7頁 527840 五、發明說明（4) 由外也有若干其它理由包括通訊頻道品質條件。需要有一種方法及電路考慮低功率振盪器的誤差來避免先前技術的限制，同時可靠地計量行動站的休眠期。發明概述「本發明為一種新穎及改良之控制於分時呼叫環境下作業的行動站之方法及電5^。本發明利用之事實為行動站於整個叫醒時間接收到來自發送機的穩定時間參考，並監控其被指定的呼叫時槽。於此叫醒期間，低頻時脈信號再度與高頻時脈信號同步化，藉此避免先前技術的限制，先前技術需要接收及解調一獨特字俾便決定適當休眠間期。該電路包含一低功率時脈用於產生一低頻時脈信號；一時脈信號產生器用以產生一高頻時脈信號；一同步化邏輯電路用以使低頻時脈信號與高頻時脈信號同步化；一頻率誤差估計器用以測量低頻時脈信號估值；及一休眠控制器用以由時脈信號產生器去除功率用以產生校正後之休期眠數值。較佳具體例中，電路進一步包含一可程式規劃計數器用以計量校正後之休眠時間值，及休眠控制器使用校正後之休眠時間值程式規劃該可程式規劃的計數器。一具體例中，同步化邏輯電路包含至少一數位閂鎖用以對正低頻時脈信號之上升緣至高頻時脈信號之上升緣。頻率誤差估計器也包含一計數器用以計數每個低頻時脈信號間期之高頻時脈信號間期數目：及一累加器，用以累加介於每個低頻時脈信號間期之預期高頻時脈信號間期數目、與每個低頻時脈信號間期之實際高頻時脈信號間期數目間Page 7 527840 V. Description of the invention (4) There are several other reasons including the quality conditions of communication channels. There is a need for a method and circuit that takes into account the errors of the low power oscillator to avoid the limitations of the prior art while reliably measuring the sleep period of the mobile station. SUMMARY OF THE INVENTION "The present invention is a novel and improved method and power for controlling a mobile station operating in a time-sharing call environment. The invention utilizes the fact that the mobile station receives a stable time from the sender throughout the wake-up time. Reference and monitor its designated calling time slot. During this wake-up period, the low frequency clock signal is synchronized with the high frequency clock signal again, thereby avoiding the limitations of the prior art, which requires receiving and demodulating a unique word Then the appropriate sleep interval is determined. The circuit includes a low-power clock for generating a low-frequency clock signal; a clock signal generator for generating a high-frequency clock signal; and a synchronization logic circuit for enabling the low-frequency clock. The signal is synchronized with the high-frequency clock signal; a frequency error estimator is used to measure the low-frequency clock signal estimate; and a sleep controller is used to remove power from the clock signal generator to generate a corrected resting sleep value. In a specific example, the circuit further includes a programmable counter to measure the sleep time value after correction, and the sleep controller uses the sleep time after correction. The sleep time value is programmed by the programmable counter. In a specific example, the synchronization logic circuit includes at least one digital latch for the rising edge of the positive low frequency clock signal to the rising edge of the high frequency clock signal. Frequency error The estimator also includes a counter to count the number of high-frequency clock signal intervals per low-frequency clock signal interval: and an accumulator to accumulate the expected high-frequency time between each low-frequency clock signal interval. Number of pulse signal intervals, and actual number of high frequency clock signal intervals of each low frequency clock signal interval

第8頁 527840 五 '發明說明（5) 之差值3 圖式之簡單說明本發明之特點、目的及優點由後文詳細說明參照附圖將顯然易明，附圖中類似參考符號表示各圖中之相同對應元件，附圖中：圖1為本發明之電路之功能方塊圖，以及圖2為本發明方法之流程圖。較佳具體例之詳細說明本發明特別可用於無線通訊裝置或行動站例如可攜式無線電話其係於分時呼叫環境作業。分時呼叫作業中，行動站於其未被指定的呼叫時槽保持休眠，而在其被指定的呼叫時槽之前即刻醒來，如前文參照併述於此之美國專利第 5，3 9 2，2 8 7 號所述。圖1顯示本發明電路之功能方塊圖。時脈信號產生器2 0 2 產生高頻高準綠度時脈信號。較佳時脈信號產生器2 0 2包括一參考振盪器2 0 4及一時脈合成器2 0 6 (如圖所示）。但時脈信號產生器2 0 2可為業界已知之任一種時脈信號產生電路。本發明未限於時脈信號產生器2 0 2的實際構造。較佳具體例中，如業界已知，參考振盪器2 0 4可為經補償且可校正的晶體振盪器例如TCX0或電壓控制TCX0 (VCTCX0)。參考振盪器2 0 4較佳產生高頻信號而由接收機 2 0 0用於獲得及解調R F信號。如此參考振盪器2 0 4對準確高頻信號產生為最適化。較佳具體例中，參考振盪器2 0 4產生1 9 . 6 8 Μ z信號或其它適當R F參考頻率1 9 . 2，1 9 . 8Page 8 527840 Differences of the 5 'invention description (5) 3 Simple illustration of the features, objects and advantages of the present invention will be apparent from the following detailed description with reference to the drawings, and similar reference symbols in the drawings represent the drawings The same corresponding elements in the drawings, in the drawings: FIG. 1 is a functional block diagram of a circuit of the present invention, and FIG. 2 is a flowchart of a method of the present invention. DETAILED DESCRIPTION OF PREFERRED SPECIFIC EXAMPLES The present invention is particularly applicable to wireless communication devices or mobile stations such as portable wireless telephones which operate in a time-sharing call environment. In the time-sharing call operation, the mobile station stays asleep during its unassigned call slot, and immediately wakes up before it is assigned to the call slot, as described in the above-mentioned US Patent No. 5, 3 9 2 , As described in No. 2 8 7. FIG. 1 shows a functional block diagram of the circuit of the present invention. The clock signal generator 2 0 2 generates a high-frequency high-quasi-greenness clock signal. The preferred clock signal generator 20 includes a reference oscillator 204 and a clock synthesizer 2 06 (as shown in the figure). However, the clock signal generator 202 can generate any clock signal circuit known in the industry. The present invention is not limited to the actual configuration of the clock signal generator 202. In a preferred embodiment, as known in the industry, the reference oscillator 204 may be a compensated and correctable crystal oscillator such as TCX0 or voltage controlled TCX0 (VCTCX0). The reference oscillator 2 0 4 preferably generates a high frequency signal and is used by the receiver 2 0 0 to obtain and demodulate the RF signal. In this way, the reference oscillator 204 is optimized for accurate high-frequency signal generation. In a preferred embodiment, the reference oscillator 204 generates a 19.68 MHz signal or other appropriate R F reference frequency 19.2, 19.8

第9頁 527840 五、發明說明（6) (Μ Η z )等。時脈合成器2 0 6較佳包含數位時脈產生邏輯，包括頻率劃分器、時脈緩衝器、及其它業界習知用於時脈的組件。較佳具體例中，由時脈合成器2 0 6產生的時脈信號具有頻率9 . 8 3 0 4 Μ Η ζ。當使用本發明之行動站被叫醒時，其監視其被指定的呼叫頻道。由此被指定的呼叫頻道，行動站獲得一準確時序參考值。接收機2 0 0如業界已知，使用參考振盪器2 0 4提供的參考頻率，接收及解調由發送器2 0 1發送的呼叫頻道。接收機2 0 0之一具體例之構造進一步敘述於美國專利申請案第0 8 / 7 7 9，6 0 1號，名稱「雙模數位F Μ通訊系統」，申請曰1 9 9 7年1月7日，讓與本發明之受讓人且併述於此以供參考。如前述專利案說明的接收機2 0 0包括一頻率追蹤回路，俗稱AFC (自動頻率控制）（圖中未顯示），其響應接收自發送器2 0 1之RF信號相位產生一頻率誤差信號由參考振盪器使用。因發送器2 0 1發送的R F信號相位經同步化至穩定系統時間，故接收機2 0 0可由接收得之R F信號相位導出穩定時間參考值。外加於參考振盪器2 0 4的頻率誤差信號有助於封閉回路追蹤接收得的RF載波頻率，結果獲得極為強勁有力的高度準確高頻參考信號，其由參考振盪器2 0 4輸出至時脈合成器2 0 6。相位及追蹤頻率回路為業界眾所周知，多種不同回路可視需要用以校正參考振盪器2 0 4的頻毕 ° 此外須注意，本發明非僅適用於有外部時間參考值可資Page 9 527840 V. Description of the Invention (6) (Μ Η z), etc. The clock synthesizer 206 preferably includes digital clock generation logic, including a frequency divider, a clock buffer, and other components commonly used in the industry for clocks. In a preferred embodiment, the clock signal generated by the clock synthesizer 206 has a frequency of 9.8 3 0 4 M Η ζ. When a mobile station using the present invention is woken up, it monitors its assigned calling channel. From the designated calling channel, the mobile station obtains an accurate timing reference value. The receiver 200, as known in the industry, uses the reference frequency provided by the reference oscillator 204 to receive and demodulate the calling channel transmitted by the transmitter 201. The structure of a specific example of the receiver 2000 is further described in U.S. Patent Application No. 0/8 / 7,9,601, with the name "Dual-modular Digital FM Communication System", and the application date is 197 1 On 7th, the assignee of the present invention was assigned and is hereby incorporated by reference. The receiver 2 0 0 described in the aforementioned patent case includes a frequency tracking loop, commonly known as AFC (Automatic Frequency Control) (not shown in the figure), which generates a frequency error signal in response to the phase of the RF signal received from the transmitter 2 0 1 Reference oscillator used. Because the phase of the R F signal sent by the transmitter 201 is synchronized to the stable system time, the receiver 200 can derive the stable time reference value from the phase of the received R F signal. The frequency error signal added to the reference oscillator 2 0 4 helps the closed loop track the received RF carrier frequency, resulting in a very powerful and highly accurate high-frequency reference signal, which is output to the clock by the reference oscillator 2 0 4 Synthesizer 2 0 6. The phase and tracking frequency loops are well known in the industry. A variety of different loops can be used to correct the frequency of the reference oscillator 2 0 as needed. In addition, it should be noted that the present invention is not only applicable to external time reference values.

第10頁 527840 五、發明說明（7) 利用的用途。換言之，時脈信號產生器2 0 2可為孤立參考值，位在行動站内部或外部。以孤立參考值為例，假設時脈信號產生器2 0 2未經任何外部校正而充分正確。卩寺脈信號產生器202也包括一致能輸入，於圖1標示為 F 0N/0FF」，此處致能信號可外加而開關時脈信號產生器 2 0 2。當時脈信號產生器2 0 2為開時，其產生前述時脈信號。但當一去能信號外加至時脈信號產生器2 0 2之致能輸入時，其停止產生前述時脈信號。電壓調節器也被去能。此外，當時脈信號產生器2 0 2被去能時，大致全部構成時脈信號產生器2 0 2的組件皆被關電。如此當去能信號外加至時脈信號產生器2 0 2的致能輸入時，其大致消耗零電流川。它方面，低功率時脈2 2 4較佳為3 2. 7 6 8 kHz晶體振盪器以及常見且如前述的關聯電路。但須注意於其它具體例中，須使用其它振盪器設計而未改變本發明之性質。較佳具體例中，低功率時脈2 2 4於行動站電源開啟時保持開電。此乃與時脈信號產生器2 0 2相反，其於行動站於休眠模式被關電。當行動站於休眠模式，低功率時脈2 2 4保持電源開且產生一低頻時脈信號。休眠控制器2 2 2程式規劃一休眠時間值至可程式規劃計數器2 2 6。休眠間隔時間隨連續指定時槽間之時間長短以及隨低功率時脈2 2 4之頻率誤差估值而異，容後詳述。如業界已知，休眠控制器2 2 2可為習知微處理器，使用軟體指令程式規劃，其連同關聯電路及記憶體一起控制休眠期Page 10 527840 V. Description of the invention (7) Uses of utilization. In other words, the clock signal generator 202 can be an isolated reference value, located inside or outside the mobile station. Taking the isolated reference value as an example, it is assumed that the clock signal generator 2 0 2 is sufficiently correct without any external correction. The Daisi pulse signal generator 202 also includes a consistent energy input, which is labeled F 0N / 0FF in FIG. 1. Here, the enable signal can be applied and the clock signal generator 202 is switched on and off. When the clock signal generator 202 is on, it generates the aforementioned clock signal. However, when a disabling signal is applied to the enable input of the clock signal generator 202, it stops generating the aforementioned clock signal. The voltage regulator is also disabled. In addition, when the clock signal generator 202 is disabled, almost all components constituting the clock signal generator 202 are turned off. In this way, when the disable signal is applied to the enable input of the clock signal generator 202, it consumes approximately zero current. In terms of it, the low-power clock 2 2 4 is preferably 3 2. 7 6 8 kHz crystal oscillator and the related circuit as usual and as mentioned above. Note, however, that in other specific examples, other oscillator designs must be used without changing the nature of the invention. In a preferred embodiment, the low power clock 2 2 4 remains powered on when the mobile station power is on. This is in contrast to the clock signal generator 2 02, which is powered off when the mobile station is in sleep mode. When the mobile station is in the sleep mode, the low power clock 2 2 4 keeps the power on and generates a low frequency clock signal. The sleep controller 2 2 2 programs a sleep time value to the programmable counter 2 2 6. The sleep interval time varies with the length of time between consecutive designated time slots and with the frequency error estimate of the low power clock 2 2 4, which will be described in detail later. As known in the industry, the sleep controller 2 2 2 can be a conventional microprocessor and is programmed using software instructions, which together with the associated circuit and memory control the sleep period

第11頁 527840 五、發明說明（8) 的進出。須注意，雖然休眠控制器係以單一功能方塊舉例說明，但實體上可以若干組件及關聯的軟體執行。可程式規劃計數器2 2 6如業界已知可為任一種適當計數器或計時 σσ 由低功率時脈2 2 4產生的低頻時脈信號被接收作為可程式規劃計數器2 2 6之一輸入。藉低頻時脈信號計時，可程式規劃計數器2 2 6根據由休眠控制器2 2 2先前程式規劃的休眠時間長度值，倒數計數至到期為止。當可程式規劃計數器2 2 6到期時，致能信號由休眠控制器2 2 2輸出而致能時脈信號產生器2 0 2的輸入。藉此方式當行動站由休眠模退出且準備監視器被指定的呼叫頻道時槽時，時脈信號產生器 2 0 2之電源開啟。相反地，於監視器被指定的呼叫頻道時槽後，若不再有供給行動站的訊息，則休眠控制器2 2 2發送一去能信號至時脈信號產生器2 0 2的致能輸入，藉此關閉構成時脈信號產生器2 0 2之大致全部時脈信號產生組件，包括參考振盪器2 0 4及時脈合成器2 0 6，而僅留下低功率時脈2 2 4被激勵而計時由休眠控制器2 2 2載入可程式規劃計數器2 2 6的次一休眠期數值。如至目前為止所述，顯然本發明藉由於休眠模期間切斷時脈信號產生器2 0 2的電源來節省休眠模期間的電流，同時留下低功率時脈2 2 4被激勵而計時休眠期長短。但如前述，低功率時脈2 2 4由於其構造本質以及溫度及製造品質有某些預期的頻率誤差。本發明藉由再度同步化低頻時脈Page 11 527840 Fifth, the description of the invention (8). It should be noted that although the hibernation controller is described by taking a single function block as an example, it can be physically implemented by several components and associated software. The programmable planning counter 2 2 6 may be any suitable counter or timing as known in the industry. Σσ The low frequency clock signal generated by the low power clock 2 2 4 is received as one of the inputs of the programmable planning counter 2 2 6. By counting the low-frequency clock signal, the programmable counter 2 2 6 counts down to the expiration time according to the sleep time length value programmed by the sleep controller 2 2 2 in the previous program. When the programmable counter 2 2 6 expires, the enable signal is output by the sleep controller 2 2 2 and the clock signal generator 2 0 2 is enabled. In this way, when the mobile station exits from the sleep mode and prepares the monitor to be assigned the calling channel time slot, the power of the clock signal generator 202 is turned on. Conversely, after the monitor is assigned the calling channel time slot, if there is no longer a message for the mobile station, the sleep controller 2 2 2 sends a disable signal to the enable input of the clock signal generator 2 02 Therefore, almost all of the clock signal generating components constituting the clock signal generator 2 02 are closed, including the reference oscillator 2 0 4 and the clock synthesizer 2 0 6, and only the low power clock 2 2 4 is excited. The timing is loaded by the sleep controller 2 2 2 into the next sleep period value of the programmable counter 2 2 6. As described so far, it is clear that the present invention saves the current during the sleep mode by cutting off the power of the clock signal generator 2 02 during the sleep mode, while leaving the low-power clock 2 2 4 to be excited to time the sleep Duration. However, as mentioned above, the low-power clock 2 2 4 has some expected frequency errors due to its structural nature, temperature, and manufacturing quality. The invention re-synchronizes the low-frequency clock

第12頁 527840 五、發明說明（9) 2 2 4與較為準確且穩定的時脈信號產生器2 0 2，而將低功率時脈2 2 4的誤差考慮在内。低功率時脈2 2 4產生低頻時脈信號被接收作為同步化邏輯2 0 8的第一輸入。時脈信號產生器2 0 2產生的高頻時脈信號被接收作為同步化邏輯2 0 8的第二輸入。同步化邏輯2 0 8之較佳具體例舉例說明於圖1為三個串聯聯結的反相閂鎖，接著為一 A N D閘其有一反相輸入。但須注意其它數位邏輯也可未悖離本發明用以達成相同功能。較佳具體例中，時脈信號產生器2 0 2產生的高頻時脈信號被接收作為第一閂鎖2 1 0的時脈輸入。低功率時脈2 2 4產生的低頻時脈信號被接收作為第一閂鎖2 1 0之資料輸入。如業界已知，典型數位閂鎖有一架設與維持時間，且於輸出產生如同閂鎖被計時時存在於輸入的相同邏輯值（或其反相值）。如此第一閂鎖2 1 0的輸出為波形，其具有極為類似低功率時脈2 2 4產生的低頻時脈信號之形狀及間期，但若第一閂鎖2 1 0為反相閂鎖則可被反相。顯著差異在於來自第一閂鎖2 1 0之輸出之上升或下降緣將與計時第一閂鎖 2 1 0之高頻時脈信號之上升或下降緣同步。第一閂鎖2 1 0之輸出被接收作為第二閂鎖2 1 2的資料輸入。同理，第二閂鎖2 1 2的輸出被接收作為第三閂鎖2 1 4的資料輸入。全部閂鎖2 1 0 - 2 1 4皆由時脈信號產生器2 0 2產生的高頻時脈信號計時。第二閂鎖2 1 2及第三閂鎖2 1 4執行前文參照第一閂鎖2 1 0所述的相同同步化功能。最後，第三閂鎖2 1 4的輸出被接收作為A N D閘2 1 6的反相Page 12 527840 V. Description of the invention (9) 2 2 4 and the relatively accurate and stable clock signal generator 2 02, and the error of the low power clock 2 2 4 is taken into account. The low-power clock 2 2 4 generates a low-frequency clock signal and is received as a first input to the synchronization logic 208. The high-frequency clock signal generated by the clock signal generator 202 is received as a second input of the synchronization logic 208. A preferred specific example of the synchronization logic 208 is illustrated in Figure 1 for three inverting latches connected in series, followed by an A N D gate which has an inverting input. However, it should be noted that other digital logics may also be used to achieve the same function without departing from the present invention. In a preferred embodiment, the high-frequency clock signal generated by the clock signal generator 202 is received as the clock input of the first latch 210. The low-frequency clock signal generated by the low-power clock 2 2 4 is received as the data input of the first latch 2 1 0. As known in the industry, a typical digital latch has an erection and hold time, and when the output produces the same logic value (or its inverse value) that is present at the input when the latch is timed. In this way, the output of the first latch 2 10 is a waveform, which has a shape and interval similar to the low-frequency clock signal generated by the low-power clock 2 2 4. However, if the first latch 2 1 0 is an inverted latch Can be inverted. The significant difference is that the rising or falling edge of the output from the first latch 2 10 will be synchronized with the rising or falling edge of the high frequency clock signal timing the first latch 2 10. The output of the first latch 2 10 is received as a data input for the second latch 2 1 2. Similarly, the output of the second latch 2 1 2 is received as the data input of the third latch 2 1 4. All latches 2 1 0-2 1 4 are timed by the high frequency clock signal generated by the clock signal generator 2 02. The second latch 2 1 2 and the third latch 2 1 4 perform the same synchronization function described earlier with reference to the first latch 2 10. Finally, the output of the third latch 2 1 4 is received as the inversion of the A N D gate 2 1 6

第13頁 527840 五、發明說明（1 〇) 輸入，第二閂鎖2 1 2的輸出被外加作為A N D問2丨6的非反相 ^入]如^界人士顯然易知，閃鎖210 一214及AND閘2丨6用以將低功率時脈2 2 4產生的低頻時脈信號與時脈信號產生哭？ 0 ?產生的高頻時脈信號同步化且其用以進行緣偵測。 °°須注~意可使用更多或更少問鎖以及其它數位邏輯來替代圖1說明者。同步化邏輯2 0 8之其它實施例對業界人士顯然易知。但於較佳具體例中，為了防止與閃鎖關聯的任何介稃問題，且如業界已知多個問鎖用來減少閃鎖的介穩之統計學可能率以及結果導致低頻時脈信號波形完整性喪失。同步化邏輯2 0 8輸出同步化低頻時脈信號至頻率誤差估器2 1 7。較佳具體例中，頻率估計器2 1 7包含9位元向上計數器2 1 8及1 6位元累加器2 2 0。同步化低頻時脈信號外加至 9位元向上計數器2 1 8之復置輸入。由時脈信號產生器2 0 2 產生的高頻時脈信號外加至9位元向上計數器2 1 8的時脈輸入。較佳具體例中，9位元向上計數器2 1 8由同步化低頻時脈信號復置至-3 0 0 ( - 1 6 0十六進位數字）。如此對各同步化低頻時脈信號間期而言，9位元向上計數器被復置且由 - 3 0 0重新開始向上計數。因較佳具體例中由時脈信號產生器2 0 2產生的高頻時脈信號頻率為9 · 8 3 0 4 Μ Η z，及由同步化邏輯2 0 8產生的同步化低頻時脈信號頻率為3 2 . 7 6 8 k Η ζ，故名目上對各個同步化低頻率時脈信號間期恰有3 〇〇個高頻時脈信號間期。如此對每次9位元向上計數器2 1 8由同步化低頻時脈信號被復置至-3 0 0時，名目上應藉由高頻時脈信號的計時一路向上倒數至零。Page 13 527840 V. Description of the invention (1) Input, the output of the second latch 2 1 2 is added as a non-inverting input of AND Q 2 6] As it is obvious to people in the industry, flash lock 210 1 214 and AND gate 2 丨 6 are used to generate low frequency clock signal and clock signal generated by low power clock 2 2 4? The 0? Generated high-frequency clock signal is synchronized and used for edge detection. °° Please note ~ It can be replaced by more or less interlocks and other digital logic. Other embodiments of the synchronization logic 208 will be apparent to those skilled in the art. However, in a better specific example, in order to prevent any intervening problems associated with the flash lock, and as known in the industry, multiple interlocks are used to reduce the statistical probability of the flash lock's dielectric stability and the resulting low-frequency clock signal waveform is complete. Sexual loss. The synchronization logic 2 0 8 outputs a synchronized low frequency clock signal to the frequency error estimator 2 1 7. In a preferred embodiment, the frequency estimator 2 1 7 includes a 9-bit up counter 2 18 and a 16-bit accumulator 2 2 0. Synchronized low-frequency clock signal is added to the reset input of the 9-bit up counter 2 1 8. The high-frequency clock signal generated by the clock signal generator 2 02 is applied to the clock input of the 9-bit up counter 2 1 8. In a preferred embodiment, the 9-bit up-counter 2 1 8 is reset to -3 0 0 (-1 6 0 hexadecimal digits) by a synchronized low frequency clock signal. In this way, for each synchronized low-frequency clock signal interval, the 9-bit up-counter is reset and restarts counting up from -300. Because in the preferred embodiment, the frequency of the high-frequency clock signal generated by the clock signal generator 202 is 9 · 8 3 0 4 Μ Η z, and the synchronized low-frequency clock signal generated by the synchronization logic 208 The frequency is 3 2. 7 6 8 k Η ζ, so there are exactly 300 high-frequency clock signal intervals for each synchronized low-frequency clock signal interval. In this way, when the 9-bit up counter 2 1 8 is reset from the synchronized low-frequency clock signal to -300, the name of the high-frequency clock signal should count down all the way to zero.

第14頁 527840 五、發明說明（11) 因9位元向上計數器2 1 8於復置前必須已經名目上倒數計時為零，故任何仍然保留的計數或任何超過零的計數皆代表低功率時脈2 2 4對一低頻時脈信號間期產生的頻率誤差估值。個別誤差計數值外加至1 6位元累加器2 2 0的輸入，於該處被累加經過同步化低頻時脈信號之2 5 6間期。1 6位元累加器2 2 0隨後供給頻率誤差估值至休眠控制器2 2 2。須注意9位元向上計數器2 1 8及1 6位元累加器2 2 0之確切位元大小及構造對本發明而言並無特殊限制。其它具有較’ 大或較小尺寸的計數器，例如8位元計數器或1 0位元計數器可未悖離本發明供使用。又業界人士顯然易知可以類似大小的向下計數器置換9位元向上計數器2 1 8，且被復置至 + 3 0 0。此外同理，9位元向上計數器2 1 8使用的-3 0 0復置值僅為高頻時脈信號頻率除以同步化低頻時脈信號頻率之值，任何其它復置值也可依據相關實際頻率使用。又另一具體例中，計數器2 1 8本身未被復置，但可由其輸出扣除一個常數俾便規度化頻率誤差。此外，業界人士顯然易知1 6位元累加器2 2 0可由具有不同大小或不同構造的裝置替代例如整合與傾銷元件。累加頻率誤差估值經歷2 5 6週期被選用作為統計學上有意義且方便的平均數。如此本發明非僅限於求取頻率誤差估值之週期數。最後，須注意頻率誤差估計器2 1 7方便設計為使用其它數位邏輯電路，其執行產生同步化低頻時脈信號之頻率誤差估值的相同功能而未悖離本發明之範圍。如前述，同步化低頻信號之頻率誤差估值係由1 6位元累Page 14 527840 V. Description of the invention (11) Since the 9-bit up counter 2 1 8 must have a countdown countdown to zero before resetting, any remaining count or any count exceeding zero represents low power. Pulse 2 2 4 estimates the frequency error produced by a low-frequency clock signal interval. The individual error count value is added to the input of the 16-bit accumulator 2 2 0, where it is accumulated and passed through the 256 interval of the synchronized low-frequency clock signal. The 16-bit accumulator 2 2 0 then supplies the frequency error estimate to the sleep controller 2 2 2. It should be noted that the exact bit size and structure of the 9-bit up counters 2 1 8 and 16-bit accumulator 2 2 0 are not particularly limited for the present invention. Other counters having a larger or smaller size, such as 8-bit counters or 10-bit counters, may be used without departing from the invention. It is also obvious to those in the industry that a 9-bit down counter 2 1 8 can be replaced with a down counter of a similar size and reset to + 3 0 0. In the same way, the reset value of -3 0 0 used by the 9-bit up counter 2 1 8 is only the value of the frequency of the high frequency clock signal divided by the frequency of the synchronized low frequency clock signal. Any other reset value can also be based on the correlation. Actual frequency used. In yet another specific example, the counter 2 1 8 itself is not reset, but a constant can be subtracted from its output to normalize the frequency error. In addition, it is obvious to those in the industry that the 16-bit accumulator 220 can be replaced by devices having different sizes or different configurations such as integration and dumping components. Accumulated frequency error estimates over a period of 256 cycles were chosen as the statistically meaningful and convenient average. As such, the present invention is not limited to the number of cycles to obtain a frequency error estimate. Finally, it should be noted that the frequency error estimator 2 1 7 is conveniently designed to use other digital logic circuits that perform the same function of generating a frequency error estimate of a synchronized low frequency clock signal without departing from the scope of the present invention. As mentioned above, the frequency error estimate of the synchronized low-frequency signal is accumulated by 16 bits.

第15頁 527840 五、發明說明（12) 加器2 2 0供給休眠控制器2 2 2。多重累加器輸出可共同於微處理器軟體求平均或濾波俾便產生休眠之準確頻率誤差。又如前述，休眠控制器2 2 2響應連續指定呼叫時槽間的間期而產生一休眠時間值。休眠控制器2 2 2以算術方式將此頻率誤差估值加至休眠時間值而產生一校正後的休眠時間值。然後校正後的休眠時間值用來程式規劃可程式規劃的計數器2 2 6，藉此考慮低功率時脈2 2 4的頻率誤差。換言之，若低功率時脈2 2 4比較較為準確的時脈信號產生器2 0 2為損失時間，則1 6位元累加器2 2 0產生的頻率誤差估值為負值。結果休眠控制器2 2 2將由休眠時間值扣除頻率誤差估值。因此用於程式規劃可程式規劃計數器2 2 6的所得校正後的休眠時間值將比否則單純基於時槽間休眠期需要的名目休眠時間更短。如此造成可程式規劃計數器 2 2 6較早逾期，如此對次一指定時槽「準時」叫醒行動站。若低功率時脈2 2 4比較時脈信號產生器2 0 2獲得時間增加，則反向操作亦為真。現在轉而餐考圖2 ’顯不如圖1電路貫施之本發明方法之流程圖。須瞭解若干步驟可並行執行。該方法始於方塊 3 0 0，此處本發明駐在的行動站被「叫醒」，表示其已經外加功率至全部接收與解調來自發送機2 0 1之信號所需的全部組件。包括供電給時脈信號產生器2 0 2，故其產生高頻時脈信號用以由接收機2 0 0及同步化邏輯2 0 8使用。於方塊3 0 2，如業界已知，行動站再度獲得呼叫頻道且開始監控其被指定的呼叫頻道時槽。當行動站醒來且監控Page 15 527840 V. Description of the invention (12) The adder 2 2 0 supplies the sleep controller 2 2 2. Multiple accumulator outputs can be averaged or filtered together with the microprocessor software to produce an accurate frequency error during sleep. As before, the sleep controller 2 2 2 generates a sleep time value in response to continuously specifying the interval between the time slots of the call. The sleep controller 2 2 2 arithmetically adds this frequency error estimate to the sleep time value to generate a corrected sleep time value. The corrected sleep time value is then used to program the programmable counter 2 2 6 to take into account the frequency error of the low power clock 2 2 4. In other words, if the low-power clock 2 2 4 is a relatively accurate clock signal generator 2 02 as the loss time, then the frequency error estimate generated by the 16-bit accumulator 2 2 0 is a negative value. As a result, the sleep controller 2 2 2 will subtract the frequency error estimate from the sleep time value. Therefore, the obtained corrected sleep time value for the program-programmable programmable counter 2 2 6 will be shorter than the nominal sleep time required otherwise based solely on the sleep period between slots. This caused the programmable counter 2 2 6 to expire earlier, so that the mobile station was “on time” for the next designated time slot. If the low-power clock 2 2 4 compares the time gain of the clock signal generator 2 0 2, the reverse operation is also true. Turning now to Fig. 2 ', the flowchart of the method of the present invention implemented by the circuit of Fig. 1 is shown. It is important to understand that several steps can be performed in parallel. The method starts at block 300, where the mobile station where the present invention resides is "woken up", indicating that it has applied power to all components required to receive and demodulate signals from the transmitter 201. It includes power supply to the clock signal generator 202, so it generates high-frequency clock signals for use by the receiver 200 and the synchronization logic 208. At block 302, as known in the industry, the mobile station obtains the calling channel again and starts monitoring its assigned calling channel slot. When the mobile station wakes up and monitors

ΙΊΤ 1—lyrlf MIIJ·-1 in II ϋ 527840 五、發明說明（13) 其被指定的時槽時，方法前進至方塊3 0 4，於此處低頻時脈信號藉前述同步化邏輯2 0 8同步化至高頻時脈信號。因行動站於監視被指定的時槽期間可能已經醒來2 0或4 0毫秒，故同步化邏輯2 0 8於行動站醒來時有充分時間來執行再度同步化工作。於方塊3 0 6，測量低頻時脈誤差估值。圖1之較佳具體例中，此步驟係就9位元向上計數器218及16位元累加器220 說明。於方塊3 0 8，休眠控制器2 2 2響應被指定的呼叫時槽· 產生一校正後的休眠時間值（亦即介於連續被指定的呼叫時槽間的時間間隔），及低頻時脈之頻率誤差估值。執行此步驟後，低頻時脈2 2 4之頻率誤差被校正，行動站再度進入休眠模經歷如前文參照圖1所述，被載入可程式規劃計數器2 2 6的校正後的休眠時間值。前文較佳具體例之說明係使業界人士可利用本發明。此等具體例之多種修改對業界人士顯然易知，此處定義的一般原則可應用至未使用本發明設施的其它具體例。如此本發明絕非意圖囿限於此處所示具體例，反而係涵蓋符合此處揭示之原理及新穎結構特徵之最寬廣範圍。ΙΊΤ 1—lyrlf MIIJ · -1 in II ϋ 527840 V. Description of the invention (13) When the time slot is designated, the method proceeds to block 3 0 4 where the low-frequency clock signal is borrowed from the aforementioned synchronization logic 2 0 8 Synchronized to high frequency clock signals. Because the mobile station may have woken up for 20 or 40 milliseconds during the designated time slot, the synchronization logic 208 has sufficient time to perform resynchronization when the mobile station wakes up. At block 3 0 6, measure the low frequency clock error estimate. In the preferred embodiment of FIG. 1, this step is described with respect to a 9-bit up counter 218 and a 16-bit accumulator 220. At block 3 0 8, the sleep controller 2 2 2 responds to the designated call time slot · Generates a corrected sleep time value (that is, the time interval between consecutive designated call time slots), and the low frequency clock Frequency error estimate. After performing this step, the frequency error of the low frequency clock 2 2 4 is corrected, and the mobile station enters the sleep mode again. As described above with reference to FIG. 1, the corrected sleep time value is loaded into the programmable counter 2 2 6. The foregoing description of the preferred specific examples enables the person skilled in the art to utilize the invention. Many modifications to these specific examples will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific examples that do not use the facilities of the present invention. As such, the present invention is by no means intended to be limited to the specific examples shown herein, but to encompass the broadest scope consistent with the principles and novel structural features disclosed herein.

第17頁Page 17

Claims

527840 六、申請專利範圍 1. 一種控制於分時呼叫環境作業之一行動站之電路，該電路包含：一低功率時脈用以產生一低頻時脈信號；一時脈信號產生器用以產生一高頻時脈信號；一同步化邏輯電路用以同步化低頻時脈信號與高頻時脈信號；一頻率誤差估計器用以測量低頻時脈誤差估值；以及一休眠控制器用以由時脈信號產生器對校正後的休眠時_ 間值去除功率。 2. 如申請專利範圍第1項之電路，其進一步包含一可程式規劃計數器用以計量校正後之修眠時間值，及其中該休眠控制器可以校正後之休眠時間值程式規劃該可程式規劃的計數器。 3. 如申請專利範圍第1項之電路，其中該同步化邏輯電路包括至少一數位閂鎖用以對正低頻時脈信號之一緣至高頻時脈信號之一上升緣。 4. 如申請專利範圍第1項之電路，其中該’頻率誤差估計器包含：一計數器用以計數每個低頻時脈信號間期之高頻時脈信號間期數目；以及一累加器用以累加介於每個低頻時脈信號間期之高頻時脈信號間期預期數目與每個低頻時脈信號間期之高頻時脈信號間期實際數目間之差值。 5 . —種控制於分時呼叫環境作業之一行動站之方法，包527840 VI. Application for patent scope 1. A circuit for controlling a mobile station operating in a time-sharing environment, the circuit includes: a low-power clock for generating a low-frequency clock signal; a clock signal generator for generating a high-frequency clock signal; Frequency clock signal; a synchronization logic circuit to synchronize the low frequency clock signal and the high frequency clock signal; a frequency error estimator to measure the low frequency clock error estimate; and a sleep controller to generate from the clock signal The device removes power from the corrected sleep time_time value. 2. If the circuit of the first patent application scope, further includes a programmable planning counter to measure the corrected sleep time value, and the sleep controller can program the programmed sleep time value after the correction. Counter. 3. The circuit of item 1 in the patent application scope, wherein the synchronization logic circuit includes at least one digital latch for aligning one edge of the positive low-frequency clock signal to one rising edge of the high-frequency clock signal. 4. The circuit of item 1 of the patent application scope, wherein the 'frequency error estimator includes: a counter for counting the number of high frequency clock signal intervals for each low frequency clock signal interval; and an accumulator for accumulating The difference between the expected number of high-frequency clock signal intervals between each low-frequency clock signal interval and the actual number of high-frequency clock signal intervals between each low-frequency clock signal interval. 5. — A method for controlling a mobile station in a time-sharing environmental operation, including

第18頁 527840 六、申請專利範圍含下列步驟：產生一低頻時脈信號；產生一高頻時脈信號；同步化該低頻時脈信號至該高頻時脈信號；測量低頻時脈信號誤差之估值；響應該低頻時脈誤差估值產生一校正後之休眠時間值；以及進入一休眠模經歷校正後之休眠時間值。 6. 如申請專利範圍第5項之方法，其進一步包含下列步驟：一校正後之休眠時間值程式規劃一可程式規劃計數器；以及計量該經校正後之休眠時間值。 7. 如申請專利範圍第5項之方法，其中該同步化低頻時脈信號至高頻時脈信號之步驟包含對正低頻時脈信號之一緣至該高頻時脈信號之一上升緣。 8. 如申請專利範圍第5項之方法，其中該測量低頻時脈信號誤差估值之步驟包含下列步驟：計數每個低頻時脈信號間期之高頻時脈信號間期數目；以及累加介於每個低頻時脈信號間期之高頻時脈信號間期預期數目與每個低頻時脈信號間期之高頻時脈信號間期實際數目間之差值。Page 527840 6. The scope of patent application includes the following steps: generating a low frequency clock signal; generating a high frequency clock signal; synchronizing the low frequency clock signal to the high frequency clock signal; measuring the error of the low frequency clock signal Estimate; generate a corrected sleep time value in response to the low frequency clock error estimate; and enter a sleep mode to undergo a corrected sleep time value. 6. The method according to item 5 of the patent application scope, further comprising the following steps: a corrected sleep time value programming and a programmable counter; and measuring the corrected sleep time value. 7. The method according to item 5 of the patent application, wherein the step of synchronizing the low frequency clock signal to the high frequency clock signal includes aligning one edge of the positive low frequency clock signal to one rising edge of the high frequency clock signal. 8. The method according to item 5 of the patent application, wherein the step of measuring the error estimation of the low frequency clock signal includes the following steps: counting the number of high frequency clock signal intervals for each low frequency clock signal interval; and an accumulation medium The difference between the expected number of high-frequency clock signal intervals in each low-frequency clock signal interval and the actual number of high-frequency clock signal intervals in each low-frequency clock signal interval.

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