TW527721B

TW527721B - Method of fabricating a stringerless flash memory

Info

Publication number: TW527721B
Application number: TW91104834A
Authority: TW
Inventors: Ching-Yu Chang
Original assignee: Macronix Int Co Ltd
Priority date: 2002-03-14
Filing date: 2002-03-14
Publication date: 2003-04-11

Abstract

A stringer block is formed on the interface between a HDP silicon oxide layer and a silicon substrate. During an etching process for defining the profile of a floating gate, the stringer block functions to expose a bottom corner stringer. Following that, a polysilicon etching process effectively removes the bottom corner stringer. As a result, a stringerless flash memory cell is formed to prevent leakage currents, resulting from the bottom corner stringer, and improve both the reliability and data retention ability of the device.

Description

527721527721

五、發明說明（1) 發明之領域本發明係關於一種快閃記憶體的製作方法，尤指_種無殘緣物（stringer less)快閃記憶體的製作方法，能夠有效解決快閃記憶體的漏電問題’同時提高快閃記憶體的數據維持能力（data retention ability)。背景說明V. Description of the invention (1) Field of the invention The present invention relates to a method for making flash memory, especially to a method for making stringer less flash memory, which can effectively solve the problem of flash memory. Leakage problem 'while improving flash memory's data retention ability. Background note

可電抹除且可程式唯讀記憶體（electrical ly erasable programmable read only memory, EEPROM)乓有可重複寫入、可被電抹除以及其所儲存之資料可保存十年以上的優點，因此已成為目前最常被使用也是發展最迅速的記憶體產品之一，然而EEPR0M卻具有存取速^較慢的缺點。為了解決這個缺點，一種稱作快閃·記憶體（f 1 & s h、 memory)的產品被英代爾（Intel)公司發展出來。快閃記情體的結構與E E P R 0 Μ相同，只不過快閃記憶體的資料抹除^ 作是以區域方式（block by block)進行，取代傳統EEpR〇MElectrically ly erasable programmable read only memory (EEPROM) has the advantages of being rewritable, electrically erasable, and its stored data can be stored for more than ten years. It has become one of the most commonly used and rapidly developing memory products. However, EEPROM has the disadvantage of slower access speed ^. To address this shortcoming, a product called flash memory (f 1 & sh, memory) was developed by Intel Corporation. The structure of the flash memory is the same as E E P R 0 Μ, but the data erasure of the flash memory is performed in a block by block mode, replacing the traditional EEPR〇M

以位元為單位（byte by byte)方式進行，因此能明顯地節省資料抹除的時間。 * 立請參考圖一，圖一為習知一快閃記憶體單元3〇的剖面示意圖。如圖一所示，快閃記憶體單元3 〇包含有一基^ 10、一浮動閘極（floating gate)17、一 0N0介電層J 8以及It is performed in byte by byte mode, so it can significantly save data erasure time. * Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional flash memory unit 30. As shown in FIG. 1, the flash memory cell 30 includes a base 10, a floating gate 17, a 0N0 dielectric layer J 8 and

527721 五、發明說明（2) 一多晶矽字元線2 〇。浮動閘極1 7係由第一多晶矽層1 4以及第二多晶石夕層1 6所構成，並且橫跨於介電層1 2 a以及1 2 b之間。在介電層1 2a以及1 2b之下方分別為一摻雜區n a以及 11 b ’用來作為快閃記憶體單元3 〇之位元線，有時又稱為埋藏沒極（buried drain)。此外，浮動閘極17與基底1〇之間尚包含有一浮動閘極氧化層1 3。熱電子即經由浮動閘極氧化層13遂穿（tunneling)進出浮動閘極17，而達到快閃記憶體單元3 0資料存取的功能。然而，習知製作快閃記憶體單元3 0的過程中常會產生多晶矽殘留（residue) 22，造成漏電現象，降低了記憶體的數據維持能力（data retention ability)。這是由於介電層12a以及12b的剖面輪廓未與基底呈垂直所致。當介電層12a以及12b與基底之間的角度0 (如圖一所示）超過90度時，在蝕刻字元線2 0、第一多晶矽層1 4以.及第二多晶矽層 1 6之後，結果會在介電層之側壁上形成未被蝕刻掉之多晶矽殘留2 2，此多晶矽殘留2 2又被習知該項技藝者通稱為殘緣物（stringer)0 因此，本發明之目的在於提供一種快閃記憶體製作方法，以解決上述問題。本發明之另一目的在於提供一種無殘緣物 (s t r i n g e r 1 e s s )快閃記憶體的製作方法，可獲得佳的可靠527721 V. Description of the invention (2) A polycrystalline silicon character line 2 0. The floating gate 17 is composed of a first polycrystalline silicon layer 14 and a second polycrystalline silicon layer 16, and spans between the dielectric layers 12 a and 12 b. Below the dielectric layers 12a and 12b are doped regions na and 11b ', respectively, which are used as bit lines of the flash memory cell 30, and are sometimes referred to as buried drains. In addition, a floating gate oxide layer 13 is further included between the floating gate 17 and the substrate 10. The hot electrons tunnel into and out of the floating gate 17 through the floating gate oxide layer 13 to achieve the flash memory unit 30 data access function. However, it is known that polycrystalline silicon residue 22 is often generated during the process of making the flash memory unit 30, which causes a leakage phenomenon and reduces the data retention ability of the memory. This is because the cross-sectional profile of the dielectric layers 12a and 12b is not perpendicular to the substrate. When the angle 0 (as shown in Fig. 1) between the dielectric layers 12a and 12b and the substrate exceeds 90 degrees, the word line 20, the first polycrystalline silicon layer 14 and the second polycrystalline silicon are etched. After layer 16 is formed, a polysilicon residue 2 2 that is not etched away is formed on the sidewall of the dielectric layer. This polycrystalline silicon residue 2 2 is also known as a stringer 0 by those skilled in the art. Therefore, this The purpose of the invention is to provide a flash memory manufacturing method to solve the above problems. Another object of the present invention is to provide a method for manufacturing a flash memory without stray matter (s t r i n g e r 1 e s s), which can obtain good reliability.

527721 五、發明說明（3) 度。本發明之另一目的在於提供一種無殘緣物快閃記憶體的製作方法，可以獲得較高的製程彈性（process window)。發明之詳細說明請參閱圖二至圖十一，圖二至圖十二為本發明較佳實施例於一矽基底5 0上製作一快閃記憶體單元的方法示意圖。其中圖七B為圖七A之側視圖，圖八B為圖八A之側視圖’而圖八B為圖八A之侧視圖。矽基底5 0表面一般可被區隔為一記憶區（memory area)以及一週邊區（peripheral area)，而為方便說明本發明之技術，圖二至圖十二只顯不與本發明相關之部份記憶區放大剖面 '矽基底5 〇上之其匕區域，例如週邊區，則未顯示在圖二至圖十二中。首先，如圖二所示，本發明方法先於一矽基底5 0表面，成一氧化層5 1。氧化層51可在後續作為浮動閘極之遂穿氧化層，其厚度係介於30至15〇埃之間。氧化層51的製法可為濕式氧化法或乾式氧化法。在本發明之較佳實施例中碎基底5 〇係為一具有<100 >晶格排列方向之輕捧雜 (1 ightly doped)P型單晶矽基底。然而本發明並不限定於此’其它基底，例如利用一般S I Μ 0 X法所形成之商業化石夕527721 V. Description of invention (3) Degree. Another object of the present invention is to provide a method for manufacturing a non-residue flash memory, which can obtain a high process window. Detailed description of the invention Please refer to FIG. 2 to FIG. 11. FIG. 2 to FIG. 12 are schematic diagrams of a method for fabricating a flash memory cell on a silicon substrate 50 according to a preferred embodiment of the present invention. Among them, Fig. 7B is a side view of Fig. 7A, Fig. 8B is a side view of Fig. 8A ', and Fig. 8B is a side view of Fig. 8A. The surface of the silicon substrate 50 can be generally divided into a memory area and a peripheral area. To facilitate the description of the technology of the present invention, FIG. 2 to FIG. 12 are only relevant to the present invention. Enlarged sections of the memory area, such as the peripheral area on the silicon substrate 50, are not shown in Figures 2 to 12. First, as shown in FIG. 2, the method of the present invention forms an oxide layer 51 before a silicon substrate 50 surface. The oxide layer 51 can be subsequently used as a floating gate oxide layer, and its thickness is between 30 and 150 angstroms. The method for producing the oxide layer 51 may be a wet oxidation method or a dry oxidation method. In a preferred embodiment of the present invention, the broken substrate 50 is a 1-doped P-type single crystal silicon substrate having a < 100 > lattice arrangement direction. However, the present invention is not limited to this ’other substrates, such as commercial fossils formed by the general S I M 0 X method.

527721 五、發明說明（4) 覆絕緣（silicon-on-insulator, SOI)基底，亦適用於本發明。、接著，於氧化層51表面上沈積一厚度約為8〇〇至16〇〇埃之多晶矽層52。沈積多晶矽層52的方法可以利用低壓化學氣相沈積（LPCVD)法，其製程的條件是：以石夕甲燒 (silane，SiD為反應氣體’溫度設定在攝氏57 〇度至6 5 〇度之間，壓力約為0 · 3至0 · 6托耳（t 〇 r r )。隨後再於多晶石夕層5 2表面上沈積一厚度約為4 0 0至1 5 0 0埃之氮化石夕層5 4。氮化矽層54可利用一般之CVD法所沈積，由於為習知該項技藝者所熟知，因此不再贅述。氮化矽層5 4係用來作為犧牲層，其在後續製程中將會被清除。接著，如圖三所示，進行一黃光（lithography)製程以於氮化碎層5 4的表面形成一光阻層（未顯示）。光阻層形成一圖案，用來定義浮動閘極的位置以及浮動閘極通道長度（channel length)。接著，進行一反應性離子蝕刻 (reactiveion etching, RIE)製程，以蝕刻未被光阻層覆蓋之氮化石夕層5 4以及多晶石夕層5 2。結果在記憶區之石夕基底5 0表面上形成複數條呈現條狀排列之立體結構5 8 a以及 58b。立體結構58a以及立體結構58b之間形成一寬度約為 0.1 5至0.2微米（micrometer)之淺溝59。在本發明之較佳實施例中，淺溝59底部與立體結構58a以及58b各邊側壁所構成之兩邊角0係略大於9 0度，即容易形成殘緣物527721 V. Description of the invention (4) Silicon-on-insulator (SOI) substrate is also applicable to the present invention. Next, a polycrystalline silicon layer 52 is deposited on the surface of the oxide layer 51 to a thickness of about 800 to 1600 Angstroms. The method for depositing the polycrystalline silicon layer 52 can be a low pressure chemical vapor deposition (LPCVD) method. The process conditions are: silane (SiD) is used as the reaction gas, and the temperature is set at 5700 to 6500 ° C. In the meantime, the pressure is about 0.3 to 0.6 Torr (t0rr). Subsequently, a nitride stone having a thickness of about 400 to 150 angstroms is deposited on the surface of the polycrystalline layer 52. Layer 5 4. The silicon nitride layer 54 can be deposited by a general CVD method. Since it is well known to those skilled in the art, it will not be repeated. The silicon nitride layer 54 is used as a sacrificial layer. It will be removed during the process. Next, as shown in FIG. 3, a yellow light (lithography) process is performed to form a photoresist layer (not shown) on the surface of the nitrided layer 54. The photoresist layer forms a pattern, It is used to define the position of the floating gate and the channel length of the floating gate. Next, a reactive ion etching (RIE) process is performed to etch the nitride nitride layer not covered by the photoresist layer 5 4 And polycrystalline stone Xi layer 5 2. The result is on the surface of Shi Xi substrate 50 in the memory area. A plurality of three-dimensional structures 5 8 a and 58 b are arranged in a stripe shape. A shallow trench 59 having a width of about 0.1 5 to 0.2 micrometers is formed between the three-dimensional structures 58 a and the three-dimensional structures 58 b. In a preferred embodiment of the present invention In the example, the angle 0 between the two sides of the bottom of the shallow groove 59 and the side walls of the three-dimensional structures 58a and 58b is slightly greater than 90 degrees, that is, it is easy to form a residue.

527721527721

(stringer)之角度製程，於立體結構積一氮化石夕層5 6。佳為1 0 0埃。。隨後去除光阻層。 58a以及58b表面以及氮化石夕層5 6的厚度約然後進行另一 CVD 淺溝5 9底部均勻沈為5 0至2 0 0埃，較圖四所不，接著進行一回蝕刻製程，回蝕刻氮化石夕層56’以於立體結構58a以及58b之各邊側壁上形成一氮化矽側壁子60。氮化矽側壁子6〇的底部厚度約為7〇至12〇埃左右。再進行一離子佈植製程，於矽基底50中植入一預定濃度之導電摻:質，#成摻雜區62，用來作為位元線，或稱為埋藏汲極（buried drain)。離子佈植製程係利用能量約為50至150KeV以及劑量1E14至1E17離子每平方公分 (ions/cm2)之砷離子，在室溫下以一垂直角度進行一次或多次的摻雜。其它N型離子，例如磷離子，亦適用於本發明0 接著，如圖五所不，進行一高密度電漿化學氣相沈積 (high-density plasma chemical vapor deposition HDPCVD)製程，沈積一 HDP石夕氧層64，並且填滿淺溝5卜隨後，如圖六所示，進行一化學機械研磨（chemical 思 mechanical polishing，CMP)製程，利用氮化矽層“為磨停止層，研磨HDP石夕氧層64直至暴露出氮化矽層54。製程可視製程需要額外再增加一過研磨時間 (over-pol ishing time)，用以消除晶圓間差異 527721(stringer) angle process, a nitride layer 5 6 is built on the three-dimensional structure. It is preferably 100 Angstroms. . The photoresist layer is subsequently removed. The thicknesses of the surfaces of 58a and 58b and the nitrided layer 55 are about 5 Å. Then another CVD shallow trench 5 9 is uniformly settled to 50 to 200 angstroms, which is different from that shown in FIG. The nitride nitride layer 56 'forms a silicon nitride sidewall 60 on each side wall of the three-dimensional structures 58a and 58b. The bottom thickness of the silicon nitride sidewall 60 is about 70 to 120 angstroms. Then, an ion implantation process is performed, and a conductive dopant of a predetermined concentration is implanted into the silicon substrate 50 to form a doped region 62, which is used as a bit line or a buried drain. The ion implantation process uses arsenic ions with an energy of about 50 to 150 KeV and doses of 1E14 to 1E17 ions per square centimeter (ions / cm2), and is doped one or more times at a vertical angle at room temperature. Other N-type ions, such as phosphorus ions, are also applicable to the present invention. Next, as shown in Figure 5, a high-density plasma chemical vapor deposition (HDPCVD) process is performed to deposit a HDP stone oxide. Layer 64, and fill the shallow trench 5b. Then, as shown in FIG. 6, a chemical mechanical polishing (CMP) process is performed. The silicon nitride layer is used as a grinding stop layer to grind the HDP stone oxide layer. 64 until the silicon nitride layer is exposed 54. The process can be visually processed and an additional over-pol ishing time is required to eliminate wafer-to-wafer differences 527721

(wafer-toiafer variation)或晶方間差異（die_t〇_die variat1〇n)。一般，過研磨時間約為5至25秒之間。經 CMP研磨之殘留HDP石夕氧層64表面可能會有輕微的淺碟 (dishing)現象，然而此現象並不影響本發明。、接著，如圖七A以及圖七B所示（圖七b為圖七A之側視圖），進行一濕餘刻（wet etch)製程，利用經加熱至15〇至 180°C的磷酸（phosphoric acid，Η 3P〇4)溶液作為蝕刻溶液，將氮化石夕層54完全剝除（strip)。濕蝕刻製程係在一姓刻槽（未顯示）中進行，浸泡時間約為數十分鐘，端視氮化石夕層54的厚度而定。此外，其它可以有效去除氮化矽層 54之濕蝕刻法亦適用於本發明。一部份之氮化矽側壁子6〇需在此濕餘刻製程中同時去除，使殘留氮化石夕側壁子6 〇高度剩下約2 0 0至8 0 0埃左右。殘留氮化矽倒壁子6 〇可作為後續製程中的殘緣物阻擋區塊（stringer block)。如圖八A以及圖八B所示（圖八B為圖八A之側視圖），接著於各多晶矽層5 2上形成一多晶矽層6 6。多晶矽層6 6的厚度約為5 0 0至1 2 0 0埃之間。多晶矽層5 2以及多晶矽層6 6故共同構成一快閃記憶體的浮動閘極6 8。形成多晶矽層6 6可以利用一般常用的CVD法，例如LPCVD法，黃光製程以及蝕刻製程。接著，如圖九A以及圖九B所示（圖九B為圖九A之側視(wafer-toiafer variation) or inter-cubic difference (die_to_die variat10n). Generally, the overgrinding time is between about 5 and 25 seconds. The surface of the residual HDP silicon oxide layer 64 polished by CMP may have a slight dishing phenomenon, but this phenomenon does not affect the present invention. Next, as shown in Figure 7A and Figure 7B (Figure 7b is a side view of Figure 7A), a wet etch process is performed, using phosphoric acid heated to 150-180 ° C ( phosphoric acid (3P04) solution as an etching solution, stripping the nitrided layer 54 completely. The wet etching process is performed in a groove (not shown), and the soaking time is about several tens of minutes, depending on the thickness of the nitrided layer 54. In addition, other wet etching methods that can effectively remove the silicon nitride layer 54 are also applicable to the present invention. A part of the silicon nitride sidewall 60 needs to be removed at the same time during this wet-etching process, so that the residual nitride nitride sidewall 60 remains at about 200 to 800 angstroms. The residual silicon nitride inverted wall 60 can be used as a stringer block in the subsequent process. As shown in FIGS. 8A and 8B (FIG. 8B is a side view of FIG. 8A), a polycrystalline silicon layer 66 is formed on each of the polycrystalline silicon layers 52. The thickness of the polycrystalline silicon layer 66 is about 500-1200 Angstroms. The polycrystalline silicon layer 5 2 and the polycrystalline silicon layer 6 6 together constitute a floating gate 68 of the flash memory. The polycrystalline silicon layer 66 can be formed by using a commonly used CVD method, such as the LPCVD method, a yellow light process, and an etching process. Next, as shown in Figure 9A and Figure 9B (Figure 9B is a side view of Figure 9A

第10頁 527721 五、發明說明（7) 圖）’依序於多晶碎層66表面形刪層72 【曰…4。再於摻雜多晶石夕層成一摻= |”2形成-字元線圖案’用來定義字元線的位置。2摻=且曰曰矽層74係用來作為字元線或快閃記憶體單元制閘 (⑽tr〇l gate)，可利用一般的⑽法配合現場摻工雜制閉極 (ln-S1tli d〇plng)或另外的離子佈植製程，使摻 I層74達到所要的摻質濃度。 > 7 ΟΝΟ層72係利用一氧化—氮化矽—含氧矽化物 (oxidized-silicon nitride— silicon oxide，0Ν0)製程 J形成。首先於多晶矽層6 6表面形成一厚度約丨0至5 〇埃的氧 |化層，然後利用電漿加強化學氣相沈積（plasma-enhanced CVD，PECVD)法或LPCVD法，以二氣矽甲烧 (dichlorosilane, SiH2Cl 2)以及氨氣（ammonia，NH3)為反 |應氣體，於氧化層的表面沈積一厚度約為45埃之氮化矽層 (未顯示）。最後於攝氏約8 0 0度的高溫含氧環境中進行約 3 0分鐘的高溫癒合（heal ing)製程，以於氮化矽層表面形 |成一厚度約40至80埃之含氧矽化物（Si 1 icori oxy-ni tride)層。含氧矽化物層主要是用來填補自然氧化 |層表面之氮化石夕層的缺陷（d e f e c t)，·以降低漏電流 (leakage current)。此外，其它形成ΟΝΟ層72的方法亦適用於本發明。隨後，如圖九Β以及圖十所示，利用光阻層8 2為一蝕 527721Page 10 527721 V. Description of the invention (7) Figure) ′ In order from the polycrystalline broken layer 66 surface shape Delete layer 72 [say ... 4. Then, a doped polycrystalline stone layer is formed into a doped = | "2 formation-word line pattern 'is used to define the position of the word line. 2 doped = and said that the silicon layer 74 is used as a word line or flash The memory cell gate (⑽tr〇l gate) can be combined with the on-site doped mixed electrode (ln-S1tli dopplng) or another ion implantation process to make the I-doped layer 74 reach the desired level. Dopant concentration. &Gt; The 7 ΟΝΟ layer 72 is formed by using an oxidation-silicon nitride-silicon oxide (ON0) process J. First, a thickness of about 6 is formed on the surface of the polycrystalline silicon layer 66. Oxygenation layer of 0 to 50 Angstroms, and then plasma-enhanced CVD (PECVD) or LPCVD, using dichlorosilane (SiH2Cl 2) and ammonia (ammonia) , NH3) is a reaction gas, and a silicon nitride layer (not shown) with a thickness of about 45 angstroms is deposited on the surface of the oxide layer. Finally, it is carried out in a high-temperature oxygen-containing environment at about 800 ° C for about 30 minutes. High temperature healing (heal ing) process to shape the surface of the silicon nitride layer | forming an oxygen-containing silicon with a thickness of about 40 to 80 angstroms (Si 1 icori oxy-ni tride) layer. The oxygen-containing silicide layer is mainly used to fill the defects of the nitrided layer on the surface of the natural oxidation layer, in order to reduce the leakage current. In addition, Other methods for forming the ONO layer 72 are also applicable to the present invention. Subsequently, as shown in FIG. 9B and FIG. 10, the photoresist layer 82 is used to form an etch 527721.

刻遮罩（etch mask)進行钻釗土、士上，a 4反應性離子餘刻（RIE)製程，, 蝕刻未被光阻層82覆蓋之摻雜多往, 浮動閉極咐包括多晶_層，72以性離子姓刻⑴E)製程中，氧化；^ 下及應最大。 j手比上對多日日矽的蝕刻率）建議調整至刻之邊角The etch mask is used to perform drilling, polishing, and a 4 reactive ion etching (RIE) processes. The etching is not performed on the doped photoresist layer 82, and the floating gate electrode includes polycrystalline silicon. In layer 72, engraved with the sex ion surname (E), oxidation; ^ and should be the largest. j hand to compare the etching rate of silicon for many days) It is recommended to adjust to the corner of the engraving

接I 4乃然如圖十所示，在完成浮動閉極6 8的兹後’由於角度的關係’仍然會在殘緣物阻擋區塊_ 落處形成多晶矽殘緣物9 2。接著，如圖十一所示，殘緣物阻擋區塊6〇可以繼續利用乾蝕刻或濕蝕刻方法去除。濕蝕刻方法一般是利用經加熱至1 5 0至1 8 0 C的磷酸溶液作為蝕刻溶液，將氮化矽殘緣物阻擋區塊60完全剝除。在去除殘緣物阻擋區塊6〇之後，形成於殘緣物阻擋區塊6 0側邊角落處之多晶矽殘緣物9 2可被暴露出來。Connected to I 4 as shown in Fig. 10, after the completion of the floating closed pole 68, the polycrystalline silicon residue 9 2 will still be formed at the residue blocking block _ due to the angle. Next, as shown in FIG. 11, the stumbling block 60 can be removed by dry etching or wet etching. The wet etching method generally uses a phosphoric acid solution heated to 150 to 180 C as an etching solution to completely strip the silicon nitride residue blocking block 60. After the residue blocking block 60 is removed, the polycrystalline silicon residue 92 formed at the side corners of the residue blocking block 60 may be exposed.

如圖十二所示，最後可以接著利用多晶矽乾蝕刻方法完全去除多晶矽殘緣物9 2，然後去除光阻層8 2，完成本發明無殘緣物快閃記憶體的製作。後續製程步驟，例如層間介電層沈積、金屬導線製程以及保護層（passi vat i〇n)的形成等等，由於與本發明無直接關係，因此不再贅述。As shown in FIG. 12, finally, the polycrystalline silicon dry etching method can be used to completely remove the polycrystalline silicon residue 92, and then the photoresist layer 82 is removed to complete the fabrication of the non-residue flash memory of the present invention. Subsequent process steps, such as interlayer dielectric layer deposition, metal wire process, and formation of a passivation layer, etc., are not directly related to the present invention, so they will not be described again.

第12頁 527721 五、發明說明（9) 相較於習知之快閃記憶體製作方法，本發明具有殘緣物阻擋區塊60’形成於HD P石夕氧層6 4側壁與石夕基底5 〇之間的底部邊角區域，因此在钱刻浮動閘極68時，底部邊角殘緣物（bottom corner stringer)可藉由後續的殘緣物阻擋區塊60去除動作而被暴露出來，方便利用多晶矽乾蝕刻方 ίίΠί:ί殘緣物快閃記憶體。本發明之快閃記憶底部邊角殘緣物所造成的漏電問題，可徒同產品的可罪度並且維姓維持§己憶體的數據維持能力。以上所述僅為本發明專利範圍所做之均等變較佳實施例，凡依本發明申請蓋範圍。變化與修飾，皆應屬本發明專利之涵Page 12 527721 V. Description of the invention (9) Compared with the conventional flash memory manufacturing method, the present invention has a stumbling block 60 'formed on the HD P stone oxidized layer 6 4 side walls and the stone xi substrate 5 The bottom corner area between 〇, so when the floating gate 68 is carved, the bottom corner stringer can be exposed through the subsequent removal action of the block 60 blocking the residue, which is convenient Dry etching of polycrystalline silicon using polycrystalline silicon: FL flash memory. The current leakage problem caused by the left-over corners of the flash memory of the present invention is similar to the guilty degree of the product and maintains the data retention ability of § self-memory. The above description is only an equivalent and preferred embodiment made by the patent scope of the present invention. Changes and modifications should be covered by the patent of the present invention

第13頁 527721 圖式簡單說明圖示之簡單說明圖一為習知製作一快閃記憶體單元的剖面示意圖。圖二至圖六，圖七A與圖七B，圖八A與圖八B，圖九A 與圖九B，以及圖十與圖十二為本發明製作一快閃記憶體單元的方法示意圖。圖示之符號說明 10 $夕基底 11a、b 摻雜區 12a、b 介電層 13 浮動閘極氧化層 14 第一多晶矽層 16 第二多晶矽層 17 浮動閘極 18 ΟΝΟ介電層 20 多晶碎子兀線 22 多晶矽殘留 30 快閃記憶體單元 50 矽基底 51 氧化層 52 多晶矽層 54 氮化矽層 56 氮化矽層 58a、b 立體結構 59 淺溝 60 氮化矽側壁子 62 摻雜區 64 HDP矽氧層 66 多晶矽層 68 浮動閘極 72 0Ν0層 74 字元線 82 光阻層 92 多晶矽殘緣物Page 13 527721 Brief description of the diagrams Brief description of the diagrams Figure 1 is a schematic cross-sectional view of a conventional flash memory unit. FIG. 2 to FIG. 6, FIG. 7A and FIG. 7B, FIG. 8A and FIG. 8B, FIG. 9A and FIG. 9B, and FIG. 10 and FIG. . Explanation of Symbols in the Figure 10: Substrate 11a, b doped regions 12a, b dielectric layer 13 floating gate oxide layer 14 first polycrystalline silicon layer 16 second polycrystalline silicon layer 17 floating gate 18 ONO dielectric layer 20 Polycrystalline chip line 22 Polycrystalline silicon residue 30 Flash memory cell 50 Silicon substrate 51 Oxidation layer 52 Polycrystalline silicon layer 54 Silicon nitride layer 56 Silicon nitride layer 58a, b Three-dimensional structure 59 Shallow trench 60 Silicon nitride sidewall 62 Doped region 64 HDP silicon oxide layer 66 polycrystalline silicon layer 68 floating gate 72 0N0 layer 74 word line 82 photoresist layer 92 polycrystalline silicon residue

第14頁Page 14

Claims

527721527721

1. 一種於半導體基底上製作一無殘緣物 (stringerless)結構的方法，該方法包含有下列步於該半導體基底形成一圖案化薄膜層（patterned film)；於該圖案化薄膜層側壁上形成一具有一預定厚度之側壁子；於該圖案化薄膜層以及該側壁子表面形成一覆蓋層，且該覆蓋層之厚度大於該圖案化薄膜層之厚度；於該覆蓋層表面形成一圖案化光阻層（pafterned photoresist layer)；利用該圖案化光阻層作為遮罩，進行一非等向性乾蝕刻，以去除該覆蓋層以及該圖案化薄膜層，其中當蝕刻該圖案化薄膜層後，會在該側壁子下產生一底部邊角殘緣物 (bottom corner stringer) » 去除該側壁子，以暴露出該底部邊角·殘緣物；以及去除該底部邊角殘緣物。 2·如申請專利範圍第1項之方法，其中該圖案化薄膜層係為一閘極層。 3 ·如申請專利範圍第1項之方法，其中該側壁子係為一氮化矽層。 4 ·如申請專利範圍第1項之方法，其中該覆蓋層係為一 5277211. A method for fabricating a stringerless structure on a semiconductor substrate, the method comprising the following steps: forming a patterned film layer on the semiconductor substrate; and forming a patterned film layer on a sidewall of the patterned film layer A sidewall having a predetermined thickness; forming a cover layer on the patterned film layer and the surface of the sidewall; and the thickness of the cover layer is greater than the thickness of the patterned film layer; forming a patterned light on the surface of the cover layer Pafterned photoresist layer; using the patterned photoresist layer as a mask, performing an anisotropic dry etching to remove the cover layer and the patterned film layer, wherein after the patterned film layer is etched, A bottom corner stringer will be created under the side wall »Remove the side wall to expose the bottom corner and residue; and remove the bottom corner residue. 2. The method according to item 1 of the patent application, wherein the patterned thin film layer is a gate layer. 3. The method according to item 1 of the patent application, wherein the sidewall subsystem is a silicon nitride layer. 4 · The method according to item 1 of the patent application scope, wherein the covering layer is a 527721

六、申請專利範圍氧化石夕層或一含有硼/填原子之氧化矽層。 5·如申請專利範圍第1項之方法，其中該側壁子的係介於7 0至1 2 〇埃左右。 ^ 6· 一種製作一無殘緣物（stringerless)快閃記憶體的方法，該方法包含有下列步驟：提供一半導體基底，其上形成有一矽氧層；Sixth, the scope of patent application: Stone oxide layer or a silicon oxide layer containing boron / filled atoms. 5. The method according to item 1 of the scope of patent application, wherein the side wall is between 70 and 120 angstroms. ^ 6. A method for making a stringerless flash memory, the method includes the following steps: providing a semiconductor substrate with a silicon oxide layer formed thereon;

於該石夕氧層上形成複數列堆疊層（layer stack)，使相鄰兩堆疊層夂間形成一淺溝，其中各該堆疊層皆由一第一多晶矽層以及一犧牲層上下堆疊而成，且各該堆疊層皆具有兩側壁；於各該堆疊層之側壁上形成一預定厚度之側壁子；沈積一 HDP；e夕氧層，覆蓋該複數列堆疊層並填滿該複數列堆疊層之間的淺溝； _ 平坦化該HDP石夕氧層，直至暴露出該犧牲層；去除該犧牲層以及部份該側壁子，使殘留的側壁子形成一殘緣物阻播區塊（stringer block);A plurality of layer stacks are formed on the stone oxide layer, so that a shallow trench is formed between two adjacent stacking layers. Each of the stacking layers is stacked by a first polycrystalline silicon layer and a sacrificial layer. And each of the stacked layers has two side walls; a side wall of a predetermined thickness is formed on the side walls of each of the stacked layers; an HDP is deposited; and an oxygen layer covers the plurality of stacked layers and fills the plurality of columns Shallow trenches between stacked layers; _ flatten the HDP stone oxide layer until the sacrificial layer is exposed; remove the sacrificial layer and part of the sidewalls, so that the remaining sidewalls form a residue blocking block (Stringer block);

於該第一多晶矽層上形成一第二多晶矽層，且該第一多晶石夕層以及第二多晶矽層共同構成一浮動閘極層；於該浮動閘極層上依序形成一絕緣層以及一控制閘極層；非等向性乾蝕刻該控制閘極層、該絕緣層以及該浮動閘極層’其中當蝕刻該浮動閘極層時，會在該殘緣物阻擋A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer, and the first polycrystalline silicon layer and the second polycrystalline silicon layer together form a floating gate layer; An insulating layer and a control gate layer are sequentially formed; the isotropic dry etching of the control gate layer, the insulating layer and the floating gate layer is performed, wherein when the floating gate layer is etched, it will be on the residue Block

527721 六、申請專利範圍區塊之一側產生一底部邊角殘緣物（bottom corner stringer); 去除該殘緣物阻擋區塊，以暴露出該底部邊角殘緣物；以及去除該底部邊角殘緣物。 7. 如申請專利範圍第6項之方法，另包含有一離子佈植製程，經由該淺溝於該半導體基底中形成一埋藏位元線 (buried bit line)0 8. 如申請專利範圍第7項之方法，其中該離子佈植製程係在形成該側壁子之後進行。 9 · 如申請專利範圍第6項之方法，其中該側壁子的厚度係介於7 0至1 2 0埃左右。 1 0 ·如申請專利範圍第6項之方法，其中該殘緣物阻擋區塊之厚度大於5 0埃。 1 1 ·如申請專利範圍第6項之方法，其中該殘緣物阻擋區塊之高度約為2 〇〇至1 0 0 0埃左右。 ϋ t T清專利範圍第6項之方法，其中該殘緣物阻擒區塊係由氮化矽所構成。527721 VI. A bottom corner stringer is generated on one side of the block in the scope of patent application; removing the block block of the residue to expose the bottom corner residue; and removing the bottom edge Horn residue. 7. If the method of applying for item 6 of the patent, further includes an ion implantation process, forming a buried bit line in the semiconductor substrate through the shallow trench. 8. If applying for item 7 of the patent, The method, wherein the ion implantation process is performed after forming the sidewall. 9. The method according to item 6 of the patent application, wherein the thickness of the side wall is between 70 and 120 angstroms. 1 0. The method according to item 6 of the patent application, wherein the thickness of the stumbling block is greater than 50 angstroms. 1 1 · The method according to item 6 of the scope of patent application, wherein the height of the stump blocking area is about 2000 to 100 angstroms. The method of item 6 of the patent scope, wherein the stumbling block is composed of silicon nitride.

第17頁 527721 六、申請專利範圍 1 3.如申請專利範圍第6項之方法，其中該犧牲層係由氮化矽所構成。第18頁Page 17 527721 6. Scope of Patent Application 1 3. The method according to item 6 of the patent application scope, wherein the sacrificial layer is composed of silicon nitride. Page 18