玖、發明說明 本發明是有關於一種晶片級封裝，且特別是有關於___ 種晶片之接點採用釦子型式之晶片級封裝。 近年來，隨著半導體業的進展以及電子產品的麋泛應 用，許多相關技術也日新月異地不斷演進中。就半導體成 品製造而言，一般可分爲三個階段，一爲半導體基底的形 成，即矽單晶成長及磊晶技術部份；再則半導體元件製造， 諸如MOS製程、多重金屬內連線等；最後則是封裝製程 (Package)。然而現今所有電子產品之開發莫不朝向輕、薄、 短、小的目標發展，對於半導體製程來說即是提高其積集 度（Integration)，至於封裝技術方面，則有晶片尺寸封裝 (Chip Scale Package，CSP)、多晶片型封裝（Multi-Chir)说明 Description of the invention The present invention relates to a wafer-level package, and more particularly to a wafer-level package in which the contacts of ___ types of wafers are buckled. In recent years, with the progress of the semiconductor industry and the widespread application of electronic products, many related technologies have also evolved with each passing day. In terms of semiconductor finished product manufacturing, it can generally be divided into three stages. One is the formation of a semiconductor substrate, that is, the silicon single crystal growth and the epitaxial technology part; and the semiconductor element manufacturing, such as the MOS process, multiple metal interconnects, etc. ; Finally, the package process (Package). However, the development of all electronic products today is directed towards the goals of lightness, thinness, shortness, and smallness. For semiconductor manufacturing, it is to increase its integration. As for packaging technology, there is Chip Scale Package. , CSP), Multi-Chir
Module，MCM)，晶片級封裝（Wafer Level Package)等封裝 技術的提出。由於半導體製程技術已發展至線寬〇.18]Um 的元件生產，在積集度提高上有許多突破，因此如何開發 出相對應之小體積封裝，以達到產品縮小化的目的，便成 爲現今重要課題。此外，爲了縮小組裝後之體積，因此有 將積體電路三次元堆疊（Three-Dimension Stack-Up)的丰冓 想’利用封裝中的晶片堆疊或封裝後的積體電路堆疊，以 達到縮小體積之目的。 請參照第1圖，其所繪示爲習知堆疊式的封裝架構示 爲 0。晶片 1 1 Oa、11 〇b、11 〇c 係經由導線 1 1 2(bonding wire) 與導線架1 1 4a、1 1 4b、114c(Lead Frame)連接，在包覆以 封裝材料116(molding material)，比如環氧樹脂（Epoxy)， 4327tvvfl .doc/008 5 527709 以形成獨立之晶片封裝 1 1 8a、11 8b、11 8c。利用導線架 ll4a、114b、114c之外導腳（outer lead)的折彎不同，使得 晶片封裝1 1 Sa、11 Sb、n 8c彼此以三次元方式疊合，如 第1圖所示。而最下方之晶片封裝118c的外導腳，則連 接至電路板12〇上之接點，最常利用此技術的封裝是軟片 自動接合封裝（Tape Automatic Bonding Package，TAB)。 習1知堆疊式封裝架構雖然可以減少晶片封裝所佔之面 積’但是由於仍需要封裝製程以適當承載器（導線架）對晶 片作封裝，一方面使得晶片封裝本身厚度增加，同時也讓 堆疊後整體封裝架構厚度遽增，並不符合實際輕薄短小之 需求。此外由於習知之堆疊架構訊號必須透過較長之路 徑’包括導腳及導線，才能傳遞至晶片，因此不但可能使 得線路阻抗（Impedance)增加，造成訊號衰減（Signal Decay) ’更可能造成訊號傳遞之延遲（signal Delay)。 此外，一般積體電路在半導體製程完成後，需經過許 多測試步驟，比如探針測試(Probing Test)、最終測試（Final Testing)、老化測試（Burning Test)等。以及許多封裝製程， 比如，打導線（Wire Bonding)、灌膠封裝（Molding)、接腳 成型（Lead Forming)及封裝測試（Assembly Test)等。徒增許 多製程及設備成本，並使得製造過程十分繁瑣。 因此本發明的目的之一就是在提供一種晶片級封裝， 在晶片周圍配置鈿子型式（Button Type)接點，可直接與承 載器或電路板接合，而無需透過任何介質或封裝製程，因 此縮短訊號傳輸距離，縮小訊號傳輸路徑之阻抗，避免訊 6 4327twfl.doc/008 527709 號延遲及衰減。 本發明的目的之二就是在提供一種晶片級封裝，其封 裝後大小幾乎與晶片相同，因此能達到縮小化的目的。 本發明的目的之三就是在提供一種晶片級封裝結構， 適於晶片的三次元疊合。 本發明的目的之四就是在提供一種晶片級封裝之晶圓 結構，將測試電路配置於晶圓切割道上，並與接點連接， 医•此無需探針測試，而最終測試與老化測試亦可在晶圓上 直接進行，簡化產品測試步驟，降低測試成本。 爲達成本發明之上述和其他目的，提出一種晶片級封 裝結構，在具有積體電路元件的晶片上，其上覆蓋有絕緣 層’而將多個銲墊，配置於晶片周緣之絕緣層上，銲墊分 別與積體電路元件電性連接。還有一保護層，配置於絕緣 層上及銲墊的部分表面上，保護層具有多個開口，使得每 一銲墊表面上分別具有一開口。在開口內壁及暴露出的銲 墊表面具有一金屬層，且金屬層延伸至開口附近的保護層 表面以及晶片邊緣。在未覆蓋金屬層之保護層表面則配置 有一封裝材料層，並且於每一開口之金屬層上分別具有一 金屬塊。 就依照本發明晶片級封裝的晶圓結構來說，除了晶圓 上的每一個晶片均具有上述之結構外，在晶片之間的切割 道上配置多條電路以及接點，以作爲晶圓測試之用。其可 以直接透過銲墊上的金屬層連接晶片與切割道之測試電 路，或者利用晶片中的多重金屬內連線連接晶片與切割道 4327twf 1 .doc/008 7 527709 之測試電路。 依照本發明的一較佳實施例，由於銲墊上之金屬塊_ 構成釣子型接點’其材質比如是錫鉛合金，可以直接與； 載器或電路板接合，因此縮短訊號傳輸的路徑，同時亦降 低訊號傳輸路徑之阻抗。然而封裝材料直接覆蓋於晶片 上，其大小幾與晶片相同，因此最後之封裝尺寸幾與晶片 尺寸相當，達到縮小封裝體積之目的。 此外’由於本發明中所採用之釦子型接點結構，金屬 塊可利用與封裝材料同側之表面或者與晶片側面同側之表 面對外連fee此種心構極有利於晶片之二次元疊合。只_ 配合適當之承載器，即可將多個本發明之晶片彼此疊合， 並由於本發明之晶片級封裝具有較薄之厚度，因此疊合後 不論在厚度或體積上，均可達到縮小的目的，同時亦可趣 供較短之訊號傳輸路徑。 再者，由於切割道之測試電路設計，以及在完成釣予 型接點後，晶圓只需切割而不必進行其他封裝製程，因止匕 可在晶圓未切割前進行最終測試與老化測試，而無需進行 探針測試’可以簡化產品測試步驟，降低測試成本。 爲讓本發明之上述和其他目的、特徵、和優點能更曰月 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作言_ 細說明如下： 圖式之簡單說明： 第1圖所繪示爲習知堆疊式的封裝架構示意圖。 第2A圖所繪示爲本發明晶片級封裝之剖面示意圖。 4327twfl .doc/008 8 527709 第2B圖所繪示爲相對於第2A圖之俯視圖。 第2C圖則是相對於第2A圖中10區域的局部剖面放 大不意圖。 第3圖所繪示爲具有本發明之晶片級封裝結構之晶圓 部分剖面示意圖。 第4圖所繪示爲本發明之晶片級封裝透過承載器連接 至電路板之剖面示意圖。 第5圖所繪示爲本發明之晶片級封裝直接連接至電路 板之剖面示意圖。 第6A圖所繪不爲適於本發明晶片級封裝疊合之承載 器剖面示意圖。 第6B圖所繪示爲相對於第6A圖之承載器的俯視圖。 第7圖所繪示爲本發明之晶片級封裝之疊合結構剖面 示意圖。 圖式之標示說明： 110a、110b、110c :晶片 112 :導線 114a、114b、114c :導線架116 :封裝材料 118a、118b、118c :晶片封裝 120 :電路板 11 :半導體晶片 14 :積體電路元件 18a、18b、18c :絕緣層 •22a、22b :金屬層 26 :絕緣層 10 :晶片級封裝部分區域 12 :基底 I6 :隔離結構 20a、20b、2〇c :金屬插塞 24 :銲墊 2 8 :有機絕緣層 4327twfl.doc/008 9 527709 30 :保護層 34 :金屬層 3 6 :封裝材料層 40a、40b :表面 44a、44b :晶片 48 :測試電路 60 、 60a 、 60b 、 60c : 52 :金屬層 64、72 :承載器 6 8 :電路板 74 :底板 82 :導線 32 :開口 35 :晶片邊緣 38 :金屬塊 42 :晶圓 46 :切割道 50 :測試接點 晶片級封裝 66 、 78 、 80 : 70 ··線路 76 :垂直側板 接點 實施例 請同時參照第2A、2B、2C圖，其繪示依照本發明一 較佳實施例的一種晶片級封裝的示意圖。其中第2A圖所 繪示爲本發明晶片級封裝之剖面示意圖；第2B圖所繪示 爲相對於第2A圖之俯視圖；而第2C圖則是相對於第2A 圖中10區域的局部剖面放大示意圖。本發明之晶片級封 裝係建構在一半導體晶片11上，半導體晶片11則包括基 底12(比如矽基底），基底12上具有一些積體電路元件14， 比如圖中之金氧半元件（MOS)，或者電阻、電容、電感、 雙載子電晶體（Bipolar Junction Transistor)等。而元件14 之間還包括一些隔離結構16,比如圖中之淺溝渠結構 4327twfl .doc/008 10 527709 (Shallow Trench Isolation)等。元件14上會覆蓋至少一層 之絕緣層18a、18b、18c，而元件14透過金屬內連線 (Interconnect)連接成複雜之電路，金屬內連線則由絕緣層 18a、18b、18c 中的金屬插塞 20a、20b、20c(Plug)，及絕 緣層18a、18b、18c間的金屬層22a、22b彼此相連而構 成。在最上層絕緣層18c上具有銲墊24，其透過金屬內連 線與元件14連接，使得外來訊號得以傳遞至元件14。銲 墊24上覆蓋有一絕緣層26，其材質比如是氧化矽、氮化 矽’或其組合等，而絕緣層26上通常還包括一有機絕緣 層28 ’比如聚乙醯胺，絕緣層26及有機絕緣層28共同形 成一保護層30，用以保護下方之元件及金屬連線。而保護 層30具有開口 32，以暴露出部分銲墊24表面，其開口 32 形成方法，可以利用微影蝕刻定義而成。金屬層34配置 於開口 32之內表面、暴露出之銲墊24表面，以及開口附 近之有機絕緣層2 8表面，並延伸至晶片11之邊緣3 5。此 金屬層34之主要功用在於提供後續之接點材料與銲墊24 間具有較佳之接合性，因此金屬層34之材質則包括銅、 鎳、銀、鈀、鈀鎳合金、金、鈦、氮化鈦及上述材料之組 合。而在未覆蓋金屬層34的保護層30表面則覆蓋有一封 裝材料層36，比如是環氧樹脂。在金屬層34上則配置金 屬塊38作爲封裝接點，金屬塊38之材質比如是錫鉛合金， 金屬塊38可以直接與承載器(Carrier)或電路板上的接點接 合’而無需透過其他介質。金屬塊3 8形成的方法則包括 類似凸塊(Bump)形成方式、電鍍等。 4327twfl .doc/008 11 527709 値得一提的是’一般銲墊24之佈置均是在晶片11的 周緣，因此金屬塊38亦是座落在晶片u的周緣，因此金 屬塊38可利用與封裝材料層36同側之表面40a或者與晶 片11側面35同側之表面4〇b對外連接，此種結構極有利 於晶片之三次元疊合。 接著請參照第3圖，其所繪示爲具有本發明之晶片級 封裝結構之晶圓部分剖面示意圖。在晶圓42未經過切割 成多個獨立之晶片4½、4仆前，晶片4如、4朴間是以切 割道46(Scdbe Line)彼此相連。本發明之晶片級封裝的另 〜特徵在於，本發明之晶片級封裝在晶圓42未切割階段， 即可以進行多種測試。吾人利用在切割道46上形成測試 電路48及多個測試接點50，比如可以藉由晶片44a、44b 中金屬內連線之金屬層52形成時，同時定義出切割道46 中的測試電路48。同樣地，熟習該技術者應知，測試電路 48或測試接點50可因應需要，藉由金屬內連線與欲測試 之元件或電路連接，亦可以透過金屬層34與銲墊24連接 至欲測試之元件或電路。 就習知技術來說，在完成半導體製程及銲墊形成後， 晶圓必須先進行探針測試(Probing Test)，判斷晶圓上之晶 片可用與否。接著’進行切割，將晶圓上之晶片分離，並 且將通過測試之晶片進行包裝(Packaging)，然後封裝後之 積體電路必須進行最終測試（Final Test)確定封裝後之積體 電路是否正常。接著進行老化測試（Burn-In Test);在老化 測試後還需再進行一次最終測試，測試十分繁瑣。然而， 4327twf! .doc/008 本發明之晶片級封裝結構，在晶圓階段即完成封裝之結 構，在晶圓切割後，並無需再進行任何封裝製程。因此’Γ ，晶圓f成封裝後即可直接進行產品測試，由於本發明之 晶片級封裝結構，對晶圓上的每一晶片都需進行封裝，因 此無需進行習知包裝前之探針測試，區別晶片之可用與 否。也由於本發明之晶片級封裝是針對晶圓上每一晶片Ϊ 因此在元成封裝後可省略第一次的最終測試，直接進行老 化測試及最後之最終測試。此外，由於本發明之晶圓在切 割道之測試電路與測試接點的設計，使得老化測試及最終 測試均可在晶圓階段，對晶圓上所有晶片同時進行測試， 顯著簡化產品測試程序，以及降低測試成本。 請參照第4圖，其所繪示爲本發明之晶片級封裝透過 承載器連接至電路板之剖面示意圖。適用於本發明之晶片 級60的承載器64，比如是插座型（Socket)承載器，其 主體呈一凹型承座，在其內部底面或是靠近底部之側壁， 具有多個接點66，對應於晶片級封裝60之金屬塊62。組 裝時，只需將本發明之晶片級封裝60壓入承載器64中， 透過適當的尺寸配合設計，即可達成晶片之金屬塊62與 承載器64接點66的接合，宛如釦子扣合般，十分簡便。 且金屬塊62與接點66之接合面可利用金屬塊62朝向承 載器64底部之表面，或者是金屬塊62朝向承載器64內 部側壁的表面。由於接觸面積的增加，可加強金屬塊62 與接點66的接合效果，再透過適當的熱製程’可確保金 屬塊62與接點66的接合品質。承載器64之接點66會透 4327twfl.doc/008 527709 過主體中的內部線路延伸至承載器64之外側底部，而與 電路板68上的線路70連接，連接方法比如是常用之表面 焊接技術（Surface Mount Technology)。 請參照第5圖，其所繪示爲本發明之晶片級封裝直|妾 連接至電路板之剖面示意圖。本發明之晶片級封裝60，亦 可以直接以金屬塊62，與電路板68上之線路70連接，無 需透過任何承載器。 本發明之晶片級封裝結構亦十分有利於晶片的三次元; 疊合’只要配合適當之承載器即可將本發明之晶片疊合。 請同時參照第6A圖及第6B圖，其中第6A圖所繪示爲適 於本發明晶片級封裝疊合之承載器剖面示意圖；第6B圖 所繪示爲相對於第6A圖之承載器的俯視圖。適於本發明 晶片級封裝疊合之承載器72至少由底板74即與其約略垂 直之垂直側板76所構成，底板74與垂直側板76組合成 一凹型承座。底板74在靠近垂直側板76接合部位之表面 具有多個接點78 ;而相對地，底板74的底面則配置有多 個接點80，接點78與接點80則透過底板74內部的線路 形成連接。其中底板74內部線路結構，可如一般多層印 刷電路板之結構，在此不再贅述。而在垂直側板76上對 應於接點78分別具有多條導線82配置於其內側表面，且 這些導線82分別與接點78連接。 請參照第7圖，其繪示本發明之晶片級封裝之疊合結 構剖面示意圖。利用第6A、6B圖中之承載器72，將本發 明之晶片級封裝60a、60b、60c逐一押入承載器72所形 4327twfl .doc/008 14 527709 成之凹型承座中，使其彼此疊合。其中晶片級封裝60a可 以具有金屬塊62之表面朝向底板74壓入，因此晶片級封 裝60a之金屬塊62可同時與承載器72之接點78與導線82 接合。當然晶片級封裝亦可以反向壓入承載器72中，如 第7圖中之60b所示。這些晶片級封裝60a、60b、60C透 過導線82與接點78，而彼此電性連接。並透過承載器72 之接點80，與電路板68之線路70連接。上述之疊合結構 由於晶片間的間距很小，且晶片級封裝本身之厚度就較 薄，因此與習知技術相較，顯著縮小疊合整體厚度。 綜上所述，本發明至少具有下列優點： 1·本發明之晶片級封裝結構，由於在晶片周圍配置釦 子型式接點，可直接與承載器或電路板接合，而無需透過 任何介質或封裝製程，因此縮短訊號傳輸距離，縮小訊號 傳輸路徑之阻抗，包括電阻、電容、電感，更可以避免訊 號延遲及衰減。 2·本發明之晶片級封裝結構，其封裝後大小幾乎與晶 片相同，因此能達到縮小化的目的，符合現今晶片尺寸封 裝（Chip Scale Package)的趨勢。 3 ·本發明之晶片級封裝結構，適於晶片的三次元疊合， 並且可縮小疊合後整體體積及厚度，達到積集化功效，並 且晶片間訊號傳輸路徑亦較短，可避免訊號延遲或衰減。 4.本發明之具有晶片級封裝之晶圓結構，將測試電路 配置於晶圓切割道上，並與接點連接，且在晶圓階段即完 成封裝，因此無需探針測試，而最終測試與老化測試亦可 15 4327twf 1 .doc/008 527709 在晶圓上直接進行，簡化產品測試步驟，降低測試成本。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 4327twfl .doc/008 16Proposals for packaging technologies such as Module (MCM) and Wafer Level Package. Since the semiconductor process technology has developed to the line width of 0.18] Um, there have been many breakthroughs in increasing the degree of accumulation. Therefore, how to develop a corresponding small volume package to achieve the purpose of product reduction has become the present day important topic. In addition, in order to reduce the volume after assembly, there is a great idea of three-dimensional stack-up of integrated circuits. The chip stack in the package or the integrated circuit package after packaging is used to reduce the volume. Purpose. Please refer to FIG. 1, which shows a conventional stacked package architecture as 0. The chips 1 1 Oa, 11 〇b, and 11 〇c are connected to the lead frame 1 1 4a, 1 1 4b, and 114c (Lead Frame) via wires 1 12 (bonding wire), and are covered with a molding material 116 (molding material). ), Such as Epoxy, 4327tvvfl.doc / 008 5 527709 to form independent chip packages 1 1 8a, 11 8b, 11 8c. The bending of the outer leads of the lead frames ll4a, 114b, and 114c is different, so that the chip packages 1 Sa, 11 Sb, and n 8c are stacked in a three-dimensional manner as shown in FIG. 1. The outer leads of the lowermost chip package 118c are connected to the contacts on the circuit board 120. The most commonly used package for this technology is the Tape Automatic Bonding Package (TAB). Xi 1 knows that the stacked package architecture can reduce the area occupied by the chip package, but because the packaging process is still required to package the chip with a suitable carrier (lead frame), on the one hand, the thickness of the chip package itself is increased, and after stacking, The thickness of the overall package structure is increasing, which does not meet the requirements of actual thinness and shortness. In addition, the conventional stacked structure signal must be transmitted to the chip through a longer path, including guide pins and wires, so it may not only increase the impedance of the circuit, but also cause signal decay. It is more likely to cause signal transmission. Delay (signal Delay). In addition, after a semiconductor process is completed, a general integrated circuit needs to go through many test steps, such as a probe test, a final test, and a burn-in test. And many packaging processes, such as wire bonding, mold packaging (Lead Forming) and packaging test (Assembly Test). It adds a lot of process and equipment costs, and makes the manufacturing process cumbersome. Therefore, one of the objectives of the present invention is to provide a wafer-level package. Button type contacts are arranged around the wafer, which can be directly connected to a carrier or a circuit board without passing through any medium or packaging process, thus shortening Signal transmission distance, reduce the impedance of the signal transmission path, and avoid signal 6 4327twfl.doc / 008 527709 delay and attenuation. Another object of the present invention is to provide a wafer-level package, the size of which is almost the same as that of a wafer after packaging, so that the purpose of reduction can be achieved. A third object of the present invention is to provide a wafer-level package structure suitable for three-dimensional stacking of wafers. The fourth object of the present invention is to provide a wafer structure of a wafer-level package. The test circuit is arranged on a wafer dicing track and connected to a contact. This does not require a probe test, and the final test and the aging test can also be performed. Directly on the wafer, simplifying product testing steps and reducing test costs. In order to achieve the above and other objects of the present invention, a wafer-level package structure is proposed. A wafer having integrated circuit elements is covered with an insulating layer, and a plurality of pads are arranged on the insulating layer on the periphery of the wafer. The solder pads are electrically connected to the integrated circuit components, respectively. There is also a protective layer disposed on the insulating layer and a part of the surface of the pad, and the protective layer has a plurality of openings, so that each surface of the pad has an opening. A metal layer is provided on the inner wall of the opening and the surface of the exposed pad, and the metal layer extends to the surface of the protective layer near the opening and the edge of the wafer. An encapsulating material layer is arranged on the surface of the protective layer not covered with the metal layer, and a metal block is respectively provided on the metal layer of each opening. As for the wafer structure of the wafer-level package according to the present invention, in addition to each of the wafers on the wafer having the above-mentioned structure, a plurality of circuits and contacts are arranged on the dicing lanes between the wafers for wafer testing. use. It can directly connect the test circuit of the wafer and the scribe line through the metal layer on the bonding pad, or use multiple metal interconnects in the wafer to connect the test circuit of the wafer and the scribe line 4327twf 1 .doc / 008 7 527709. According to a preferred embodiment of the present invention, since the metal block on the solder pad constitutes a fishing tackle-type contact, the material of which is, for example, a tin-lead alloy, can be directly connected to a carrier or a circuit board, thereby shortening a signal transmission path, It also reduces the impedance of the signal transmission path. However, the packaging material is directly covered on the wafer, and its size is almost the same as that of the wafer. Therefore, the final package size is equivalent to the size of the wafer, so as to reduce the packaging volume. In addition, because of the button-type contact structure used in the present invention, the metal block can use the surface on the same side as the packaging material or the surface on the same side as the chip to connect to the outside. This heart structure is very conducive to the two-dimensional superposition of the chip . Only with the appropriate carrier, multiple wafers of the present invention can be stacked on each other, and because the wafer-level package of the present invention has a thin thickness, it can be reduced in thickness or volume after being stacked The purpose is also to provide a shorter signal transmission path. In addition, due to the design of the test circuit of the dicing track and the completion of the pre-contact, the wafer only needs to be cut without other packaging processes. Because the dagger can be used for final testing and aging test before the wafer is not cut, Without the need for probe testing, it can simplify product testing steps and reduce testing costs. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings : Figure 1 shows a schematic diagram of a conventional stacked package architecture. FIG. 2A is a schematic cross-sectional view of a wafer-level package of the present invention. 4327twfl .doc / 008 8 527709 Figure 2B is a plan view relative to Figure 2A. Figure 2C is intended to be enlarged relative to the partial cross section of area 10 in Figure 2A. FIG. 3 is a schematic partial cross-sectional view of a wafer having a wafer-level package structure of the present invention. Figure 4 is a schematic cross-sectional view of a wafer-level package of the present invention connected to a circuit board through a carrier. Figure 5 is a schematic cross-sectional view of a wafer-level package of the present invention directly connected to a circuit board. Figure 6A is not a schematic cross-sectional view of a carrier suitable for lamination of a wafer-level package of the present invention. Figure 6B is a top view of the carrier relative to Figure 6A. FIG. 7 is a schematic cross-sectional view of a stacked structure of a wafer-level package of the present invention. Description of the drawings: 110a, 110b, 110c: Chip 112: Wires 114a, 114b, 114c: Lead frame 116: Packaging materials 118a, 118b, 118c: Chip package 120: Circuit board 11: Semiconductor wafer 14: Integrated circuit components 18a, 18b, 18c: Insulating layers 22a, 22b: Metal layers 26: Insulating layers 10: Wafer-level package partial area 12: Substrate I6: Isolation structures 20a, 20b, 20c: Metal plugs 24: Solder pads 2 8 : Organic insulating layer 4327twfl.doc / 008 9 527709 30: Protective layer 34: Metal layer 3 6: Packaging material layers 40a, 40b: Surfaces 44a, 44b: Chips 48: Test circuits 60, 60a, 60b, 60c: 52: Metal Layers 64, 72: Carrier 6 8: Circuit board 74: Backplane 82: Conductor 32: Opening 35: Wafer edge 38: Metal block 42: Wafer 46: Cutting track 50: Test contact wafer-level package 66, 78, 80 : 70 ·· Line 76: Example of vertical side plate contact Please refer to Figures 2A, 2B, and 2C at the same time, which shows a schematic diagram of a wafer-level package according to a preferred embodiment of the present invention. Figure 2A is a schematic cross-sectional view of a wafer-level package of the present invention; Figure 2B is a plan view relative to Figure 2A; and Figure 2C is a partial cross-sectional view enlarged from the area 10 in Figure 2A schematic diagram. The wafer-level package of the present invention is constructed on a semiconductor wafer 11. The semiconductor wafer 11 includes a substrate 12 (such as a silicon substrate). The substrate 12 has some integrated circuit elements 14, such as a metal-oxide-semiconductor (MOS) device. , Or resistance, capacitance, inductance, bipolar junction transistor (Bipolar Junction Transistor), etc. The elements 14 also include some isolation structures 16, such as the shallow trench structure in the figure 4327twfl.doc / 008 10 527709 (Shallow Trench Isolation). The element 14 will be covered with at least one layer of insulation layers 18a, 18b, 18c, and the element 14 is connected to a complex circuit through a metal interconnect (Interconnect), and the metal interconnect is inserted by the metal in the insulation layers 18a, 18b, 18c The plugs 20a, 20b, and 20c (Plug) and the metal layers 22a and 22b between the insulating layers 18a, 18b, and 18c are connected to each other. There is a pad 24 on the uppermost insulating layer 18c, which is connected to the component 14 through a metal interconnect, so that an external signal can be transmitted to the component 14. The pad 24 is covered with an insulating layer 26, which is made of silicon oxide, silicon nitride, or a combination thereof, and the insulating layer 26 usually further includes an organic insulating layer 28 'such as polyethyleneimide, the insulating layer 26 and The organic insulating layer 28 collectively forms a protective layer 30 for protecting the components below and the metal wiring. The protective layer 30 has an opening 32 to expose a part of the surface of the pad 24. The method for forming the opening 32 can be defined by lithographic etching. The metal layer 34 is disposed on the inner surface of the opening 32, the surface of the exposed pad 24, and the surface of the organic insulating layer 28 near the opening, and extends to the edge 35 of the wafer 11. The main function of the metal layer 34 is to provide better bonding between subsequent contact materials and the pads 24. Therefore, the material of the metal layer 34 includes copper, nickel, silver, palladium, palladium-nickel alloy, gold, titanium, nitrogen Titanium and a combination of the above materials. The surface of the protective layer 30 which is not covered with the metal layer 34 is covered with a packaging material layer 36, such as epoxy resin. A metal block 38 is arranged on the metal layer 34 as a package contact. The material of the metal block 38 is, for example, a tin-lead alloy. The metal block 38 can be directly bonded to the carrier (Carrier) or the contact on the circuit board without passing through other medium. The method of forming the metal block 38 includes a bump-like formation method, electroplating, and the like. 4327twfl .doc / 008 11 527709 It is worth mentioning that 'General pads 24 are arranged on the periphery of the wafer 11, so the metal block 38 is also located on the periphery of the chip u, so the metal block 38 can be used and packaged. The surface 40a on the same side of the material layer 36 or the surface 40b on the same side as the side 35 of the wafer 11 is connected to the outside. This structure is very conducive to the three-dimensional stacking of the wafer. Next, please refer to FIG. 3, which is a schematic cross-sectional view of a wafer having a wafer-level package structure of the present invention. Before the wafer 42 is cut into a plurality of independent wafers 4½ and 4, the wafers 4 and 4 are connected to each other by a cutting line 46 (Scdbe Line). Another feature of the wafer-level package of the present invention is that the wafer-level package of the present invention can perform various tests at the uncut stage of the wafer 42. I use the test circuit 48 and a plurality of test contacts 50 formed on the scribe line 46. For example, when the metal layer 52 of the metal interconnects in the wafers 44a and 44b is formed, the test circuit 48 in the scribe line 46 is also defined. . Similarly, those skilled in the art should know that the test circuit 48 or the test contact 50 can be connected to the component or circuit to be tested through a metal interconnect, or can be connected to the The component or circuit under test. As far as the conventional technology is concerned, after the semiconductor process is completed and the pads are formed, the wafer must first undergo a probing test to determine whether the wafer on the wafer is available or not. Then, dicing is performed to separate the wafers on the wafer, and the wafers that pass the test are packaged. Then, the packaged integrated circuit must be subjected to a final test to determine whether the packaged integrated circuit is normal. The burn-in test is then performed; after the burn-in test, a final test is required again, and the test is very tedious. However, the 4327twf! .Doc / 008 wafer-level packaging structure of the present invention completes the packaging structure at the wafer stage, and does not require any packaging process after wafer dicing. Therefore, 'Γ, product testing can be performed directly after the wafer f is packaged. Due to the wafer-level packaging structure of the present invention, each wafer on the wafer needs to be packaged, so there is no need to perform probe testing before packaging. To distinguish the availability of the chip. Also, since the wafer-level package of the present invention is directed to each wafer on the wafer, the first final test can be omitted after the Yuancheng package, and the aging test and the final final test can be directly performed. In addition, due to the design of the test circuit and test contact of the wafer in the dicing path of the present invention, the aging test and the final test can be performed at the wafer stage at the same time on all wafers on the wafer, which significantly simplifies the product test process. And reduce test costs. Please refer to FIG. 4, which is a schematic cross-sectional view of a wafer-level package of the present invention connected to a circuit board through a carrier. The carrier 64 suitable for the wafer-level 60 of the present invention is, for example, a socket-type carrier. The main body of the carrier 64 is a concave socket. The inner bottom surface or the side wall near the bottom has multiple contacts 66, corresponding to Metal block 62 in wafer level package 60. When assembling, the wafer-level package 60 of the present invention only needs to be pressed into the carrier 64, and the metal block 62 of the wafer and the contact point 66 of the carrier 64 can be achieved through proper size matching design, just like a button fastening Very simple. And the joint surface of the metal block 62 and the contact 66 can be the surface of the metal block 62 facing the bottom of the carrier 64, or the surface of the metal block 62 facing the inner side wall of the carrier 64. As the contact area increases, the joining effect between the metal block 62 and the contact 66 can be enhanced, and the quality of the joining between the metal block 62 and the contact 66 can be ensured through an appropriate thermal process'. The contact 66 of the carrier 64 will pass through 4327twfl.doc / 008 527709 through the internal circuit in the main body to the bottom of the outer side of the carrier 64, and connect to the circuit 70 on the circuit board 68. The connection method is, for example, the commonly used surface welding technology (Surface Mount Technology). Please refer to FIG. 5, which is a schematic cross-sectional view of a wafer-level package connected to a circuit board in the present invention. The wafer-level package 60 of the present invention can also be directly connected to the circuit 70 on the circuit board 68 by a metal block 62 without going through any carrier. The wafer-level packaging structure of the present invention is also very beneficial to the three-dimensional of the wafer; as long as it is matched with an appropriate carrier, the wafer of the present invention can be laminated. Please refer to FIG. 6A and FIG. 6B at the same time, in which FIG. 6A is a schematic cross-sectional view of a carrier suitable for stacking of wafer-level packages of the present invention; FIG. 6B is a drawing relative to the carrier of FIG. 6A Top view. The carrier 72 suitable for the superposition of the wafer-level package of the present invention is composed of at least a bottom plate 74, that is, a vertical side plate 76 which is approximately perpendicular to the bottom plate 74. The bottom plate 74 and the vertical side plate 76 are combined into a concave socket. The bottom plate 74 has a plurality of contacts 78 on the surface close to the joint portion of the vertical side plate 76. In contrast, the bottom surface of the bottom plate 74 is provided with a plurality of contacts 80, and the contacts 78 and the contact 80 are formed through the lines inside the bottom plate 74. connection. The internal circuit structure of the base plate 74 can be the same as that of a general multilayer printed circuit board, and will not be repeated here. On the vertical side plate 76, a plurality of wires 82 corresponding to the contacts 78 are respectively disposed on the inner surface thereof, and these wires 82 are connected to the contacts 78, respectively. Please refer to FIG. 7, which is a schematic cross-sectional view of a stacked structure of a wafer-level package of the present invention. Using the carrier 72 in Figs. 6A and 6B, the wafer-level packages 60a, 60b, and 60c of the present invention are each pressed into the recessed seats formed by the carrier 72 4327twfl.doc / 008 14 527709, so that they overlap each other. . The wafer-level package 60a can be pressed in with the surface of the metal block 62 facing the base plate 74, so that the metal block 62 of the wafer-level package 60a can be simultaneously joined with the contact 78 of the carrier 72 and the wire 82. Of course, the wafer-level package can also be pressed into the carrier 72 in the opposite direction, as shown by 60b in FIG. These wafer-level packages 60a, 60b, and 60C are electrically connected to each other through the wires 82 and the contacts 78. It is connected to the circuit 70 of the circuit board 68 through the contact 80 of the carrier 72. Since the above-mentioned stacked structure has a small pitch between the wafers and the thickness of the wafer-level package itself is thin, the overall thickness of the stacked structure is significantly reduced compared with the conventional technology. In summary, the present invention has at least the following advantages: 1. The wafer-level packaging structure of the present invention, because buckle-type contacts are arranged around the wafer, can be directly bonded to a carrier or a circuit board without passing through any medium or packaging process Therefore, shortening the signal transmission distance and reducing the impedance of the signal transmission path, including resistance, capacitance, and inductance, can avoid signal delay and attenuation. 2. The wafer-level package structure of the present invention has almost the same size as the wafer after packaging, so it can achieve the purpose of downsizing, which is in line with the current trend of chip scale packaging. 3 · The wafer-level package structure of the present invention is suitable for three-dimensional stacking of wafers, and can reduce the overall volume and thickness after stacking to achieve the integration effect, and the signal transmission path between the chips is also short, which can avoid signal delay Or decay. 4. In the wafer structure with wafer-level packaging of the present invention, the test circuit is arranged on the wafer dicing path and connected to the contacts, and the package is completed at the wafer stage, so no probe test is required, and the final test and aging The test can also be performed directly on the wafer at 15 4327twf 1 .doc / 008 527709, which simplifies product testing steps and reduces test costs. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 4327twfl .doc / 008 16