527544 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（（） 發明領域 本發明係關於一電腦系統中繪圖處理的裝置與方法， 尤指支援嵌入式與外加式繪圖加速器合作的裝置與其方 法。 發明背景 電腦因電腦繪圖顯示的出現而在很多活動中變的更加 有用，電腦繪圖顯示使表現不再只是數字與文字資料，而 是代表那些數字含意與增加文字資料意義的圖片與圖像。 如第一圖所示，以往在一電腦系統中，繪圖工作習慣上會 從一中央處理器（CPU) 14透過一晶片組12與加速圖形 介面（Accelerated Graphics Port 簡稱 AGP)或周邊零件 連接介面（Peripheral Component Interconnect 簡稱 PCI) 匯流排13被送到一繪圖加速器11。此圖像架構減少了中 央處理器14中處理依賴（processing recourse)的超載， 中央處理器可以更專注於繪製圖片外的其他事物。在繪圖 加速器11處理完圖像的基元（primitives，包含變換 《transformation》、計算不同的基原屬性《attributes》、 亮度計算《lighting calculation》、截割計算《clipping calculation》與平面方程式計算《plane equation calculation》）後，一區域記憶體（local memory)的會協 助基元的紋理映射（texture mapping)。最後，繪圖加速 4SIS/199906TW 1 表紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ----------------h—^tr-—、-------線-φ- (請先閱讀背面之注意事項再填寫本頁) 527544 A7 __B7 五、發明說明（» 器11藉由爲每一像素計算出適當値而發揮一點陣化功能 (rasterization function)，其中每一像素代表基元。接著 (請先閱讀背面之注咅心事項再填寫本頁) 每一像素被擷取出來並一個〜個顯示在顯示器螢幕上。 不過因爲半導體製造科技的進展，繪圖加速器u嵌 入晶片組12內到一積體晶片21中、以及區域記憶體15 結合在傳統系統記憶體22已蔚爲趨勢。這種積體記憶體 結構通吊被稱爲統口日5憶體構造（Unifie(J mem〇ry architecture簡稱UMA)。因此，繪圖工作會被直接送到 積體晶片21，如第二圖所示，而積體晶片21會跟前述繪 圖加速器11 一樣處理繪圖的基元並映射基元的紋理。這 種整合大大地減低了一電腦系統的成本，同時也滿足了一 般使用者的需求，因爲一般使用者不必花多餘的錢去購置 包含一外加式繪圖加速器的一繪圖卡。 經濟部智慧財產局員工消費合作社印製 然而，積體晶片21中的嵌入式繪圖加速器211，其效 率不如現在可買到之通常承載與封裝在一繪圖卡上的繪圖 加速器。況且迨種整合封想要目則最進步（the state of the art )之繪圖加速器者而言並不合理也無法接受。目前最 進步的繪圖加速器可以輕易處理三維（3D)圖片且可以 玩三維遊戲。因此，急切的使用者常會購買另一繪圖卡30 加到其電腦中，繪圖卡30上有外加式目前最進步的一繪 圖加速器31，以使繪圖加速功能更加強大。在這樣狀況 下之電腦結構如第三圖所示。這種狀況下，一定要使位於 積體晶片21上的嵌入式繪圖加速器211失能（disabled)， 以避免其與封裝在繪圖卡30上之外加式繪圖加速器31產 4SIS/199906TW 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 527544 A7 B7 五、發明說明（3) 生干擾。這麼一來嵌入式繪圖加速器211就被浪費掉了。 因此，有外加式繪圖加速器31與積體晶片21中之嵌入式 繪圖加速器211合作的需要。藉支援這合作可引致更佳之 效能。 發明槪述 本發明的目的是提供一種支援嵌入式與外加式繪圖加 速器合作的裝置，藉由此裝置所繪之圖框與圖片，依比例 被分割並根據主與僕繪圖加速器的效能被送到此兩繪圖加 速器中。 本發明的另一目的是嵌入式繪圖加速器所繪的圖框將 會被送到外加式繪圖加速器。外加式繪圖加速器輸出嵌入 式繪圖加速器與外加式繪圖加速器所繪的圖框到顯示器螢 幕0 在本發明中，在一電腦系統中，一種支援一僕繪圖加 速器與一主繪圖加速器合作的裝置，以進行繪圖工作，此 裝置包含： 分配裝置，該分配裝置根據此兩繪圖加速器的效能依比例 分配一第一部份圖框到僕繪圖加速器並分配一第二部分圖 框到主繪圖加速器； 互動工具，該互動工具連結於僕繪圖加速器與主繪圖加速 器，使兩加速器握手以讓僕繪圖加速器完成的圖框的第一 部分，移到主繪圖加速器； 4SIS/199906TW 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------9----!:訂ί-------線蜂 (請先閱讀背面之注音？事項再填寫本頁) 527544 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（斗0 藉此，主繪圖加速器將主繪圖加速器繪製的第二部分圖框 與僕繪圖加速器繪製的第一部分圖框予以互換。僕繪圖加 速器可能是嵌入式繪圖加速器而主繪圖加速器可以是外加 式繪圖加速器，反之亦可。 本發明也包含在一電腦系統中支援一嵌入式繪圖加速 器與一外加式繪圖加速器合作的一方法，以進行繪圖工 作。此方法可以根據嵌入式與外加式繪圖加速器之效能， 依比例分配圖框到此兩繪圖加速器。如此一來整體繪製圖 框的繪圖效率可藉此兩繪圖加速器同時運作之助而提升。 此方法給予各加速器不同組指令。提出兩加速器之間的握 手協定（handshaking protocol)。此握手提供資訊以移動 一嵌入式加速器所繪的一圖框到外加式加速器控制的圖框 緩衝區（frame buffer)。在此方法中，外加式與嵌入式加速 器只需要一點額外的線路。 本發明附加的目的與優點會在後面的敘述中提出，而 這些附加的目的與優點在某種程度上會在敘述中顯而易 見，或可在實施本發明時學到。本發明的目的與優點可藉 由所附申請專利範圍中特別指明的手段與組合而理解與獲 得。 圖式簡單說明 第一圖揭示一有晶片組與一 AGP或PCI繪圖加速器 之傳統繪圖系統的方塊圖； 4SIS/199906TW , 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------:訂 ί--------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 527544 A7 B7 五、發明說明（£ ) 第二圖揭示一繪圖系統的一方塊圖，此繪圖系統有一 積體晶片而積體晶片包含一嵌入式繪圖加速器； 第三圖揭示一繪圖系統的一方塊圖，此繪圖系統有一 積體晶片，積體晶片包含一嵌入式繪圖加速器與一外加式 AGP或PCI繪圖加速器； 第四圖揭示一裝置之方塊圖，此裝置在本發明中繪製 圖框的一電腦系統內支援一僕繪圖加速器與一主繪圖加速 器之合作； 第五圖揭示在傳統繪圖加速器之指令區隔匡（command parser)的方塊圖； 第六圖揭示本發明中提供之裝置與兩繪圖加速器合作 的方塊圖。 發明之詳細說明 請參照第四圖，第四圖揭示一裝置.40之一方塊圖， 在本發明中裝置40於一電腦系統內，支援一僕繪圖加速 器41與一主繪圖加速器42之合作，以進行繪圖工作。該 繪圖工作包含一連續圖框（a sequence of frames )。裝置40 包含一分配裝置401與一互動裝置402。分配裝置401根 據此兩繪圖加速器之效能，依比例分配一第一部份繪圖工 作到僕繪圖加速器41，並分配一第二部分繪圖工作到主 繪圖加速器42。第一部分與第二部分繪圖工作可從連續 圖框，依圖框或部分圖框（例如四分之一圖框）加以分開。 4SIS/199906TW 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------^----* 訂1·-------線 (請先閱讀背面之注意事項再填寫本頁) 527544 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（（9 ) 另一方面，分別連接到僕繪圖加速器41與主繪圖加速器 42的互動裝置402議此兩繪圖加速器握手，以使繪圖加 速器繪製的第一部份繪圖工作移到主繪圖加速器。主繪圖 加速器將主繪圖加速器繪製的第二部分繪圖工作與僕繪圖 加速器繪製的第一部分繪圖工作予以互換。每一個第一部 分與第二部分繪圖工作的像素都會顯示在顯示器螢幕上。 在本發明中，因爲僕與主繪圖加速器一同運作以繪製並處 理繪圖工作，繪圖的整體效率得到提升。 爲了偵測僕與主繪圖加速器的效能，裝置進一步包含 一測量裝置403。測量裝置403能偵測僕繪圖加速器41 與主繪圖加速器42之效能，並傳送此兩繪圖加速器之效 能到分配裝置401，以使分配裝置401能根據此兩繪圖加 速器之效能，依比例分配一第一部份繪圖工作到僕繪圖加 速器41，並分配一第二部分繪圖工作到主繪圖加速器42。 僕繪圖加速器41可以是位於積體晶片內的嵌入式繪 圖加速器，而主繪圖加速器會是在繪圖卡中外加式繪圖加 速器，反之亦可。 吾人皆熟知可以藉由繪圖加速器處理圖框的速度而測 量每一個繪圖加速器的效能。因此，測量裝置4〇3能在線 上（on-line)偵測僕繪圖加速器與主繪圖加速器的效能。 另一方面，如果我們可以得到每個繪圖加速器的規格’此 測量裝置也可以藉由參考此兩繪圖加速器的規格來偵測僕 繪圖加速器與主繪圖加速器的效能。527544 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (() Field of the Invention The present invention relates to a device and method for graphics processing in a computer system, especially a device that supports the cooperation of embedded and external graphics accelerators. Background of the Invention Computers have become more useful in many activities due to the emergence of computer graphics. Computer graphics display makes the performance no longer just numbers and text, but pictures and images that represent the meaning of numbers and increase the meaning of text. As shown in the first figure, in a computer system, drawing work used to be connected from a central processing unit (CPU) 14 to an Accelerated Graphics Interface (AGP) or peripheral parts through a chipset 12 in the past. Interface (Peripheral Component Interconnect, referred to as PCI) bus 13 is sent to a graphics accelerator 11. This image architecture reduces the overload of processing recourse in the central processing unit 14, and the central processing unit can focus more on drawing outside the picture Other things. After processing the image in the graphics accelerator 11 (Primitives, including transformation "transformation", calculation of different primitive attributes "attributes", brightness calculation "lighting calculation", cutting calculation "clipping calculation" and plane equation calculation "plane equation calculation", a region of memory (Local memory) will assist the texture mapping of the primitives. Finally, drawing acceleration 4SIS / 199906TW 1 The paper size of the table applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ ---------- h— ^ tr -— 、 ------- line-φ- (Please read the notes on the back before filling this page) 527544 A7 __B7 V. Description of the invention (» The device 11 performs a bit of rasterization function by calculating the appropriate frame for each pixel, where each pixel represents a primitive. Then (please read the note on the back before filling this page) each pixel Are extracted and displayed on the display screen one by one. However, due to the advancement of semiconductor manufacturing technology, the graphics accelerator u is embedded in the chipset 12 into an integrated chip 21, and the area memory 15 is integrated in the traditional system. The unified memory 22 has become a trend. This type of integrated memory structure is called the Unifie (Jmemory architecture referred to as UMA). Therefore, the drawing work will be directly sent to the integrated chip 21, as shown in the second figure, and the integrated chip 21 will process the drawing primitives and map the texture of the primitives in the same way as the aforementioned drawing accelerator 11. This integration greatly reduces the cost of a computer system, and also meets the needs of ordinary users, because ordinary users do not have to spend extra money to purchase a graphics card that includes an external graphics accelerator. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs However, the embedded graphics accelerator 211 in the integrated chip 21 is not as efficient as the graphics accelerator that is currently available and usually carries and packages on a graphics card. Moreover, it is unreasonable and unacceptable for any kind of integrated graphics accelerator to aim for the state of the art. The most advanced graphics accelerators available today can easily process three-dimensional (3D) pictures and play three-dimensional games. Therefore, eager users often purchase another graphics card 30 to add to their computer. The graphics card 30 has an add-on graphics accelerator 31, which is the most advanced, to make the graphics acceleration function more powerful. The computer structure in this situation is shown in Figure 3. In this case, the embedded graphics accelerator 211 on the integrated chip 21 must be disabled to avoid it and the add-in graphics accelerator 31 packaged on the graphics card 30. 4SIS / 199906TW 2 Paper size Applicable to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 527544 A7 B7 V. Description of the invention (3) Interference. In this way, the embedded graphics accelerator 211 is wasted. Therefore, there is a need for the external graphics accelerator 31 to cooperate with the embedded graphics accelerator 211 in the integrated chip 21. Supporting this cooperation can lead to better performance. Description of the invention The object of the present invention is to provide a device that supports the cooperation of embedded and external graphics accelerators. The frames and pictures drawn by the device are divided into proportions and sent to the performance of the master and slave graphics accelerators. This two drawing accelerators. Another object of the present invention is that the frame drawn by the embedded graphics accelerator will be sent to the external graphics accelerator. The external graphics accelerator outputs an embedded graphics accelerator and a frame drawn by the external graphics accelerator to a display screen. In the present invention, in a computer system, a device that supports the cooperation of a slave graphics accelerator and a master graphics accelerator, To perform drawing work, this device includes: a distribution device that allocates a first part frame to a slave drawing accelerator and allocates a second part frame to a main drawing accelerator in proportion to the performance of the two drawing accelerators; an interactive tool The interactive tool is connected to the slave graphics accelerator and the master graphics accelerator, so that the two accelerators shake hands to allow the slave graphics accelerator to complete the first part of the frame, and move to the master graphics accelerator; 4SIS / 199906TW 2 This paper standard applies to the Chinese national standard (CNS ) A4 size (210 X 297 mm) ------------ 9 ---- !: order ί ------- line bee (please read the phonetic on the back? Matters before (Fill in this page) 527544 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (Dou 0 By this, the main graphics accelerator will draw the second part of the main graphics accelerator frame It is interchangeable with the first part of the frame drawn by the server graphics accelerator. The server graphics accelerator may be an embedded graphics accelerator and the main graphics accelerator may be an external graphics accelerator, and vice versa. The present invention also includes a computer system that supports an embedded graphics accelerator. A method in which the graphics accelerator cooperates with an external graphics accelerator to perform drawing work. This method can allocate the graphics frame to the two graphics accelerators in proportion according to the performance of the embedded and external graphics accelerator. In this way, the overall drawing frame is drawn. The drawing efficiency can be improved by the simultaneous operation of two graphics accelerators. This method gives different sets of instructions to each accelerator. A handshake protocol between the two accelerators is proposed. This handshake provides information to move the image drawn by an embedded accelerator. A frame to a frame buffer controlled by an external accelerator. In this method, the external and embedded accelerators require only a little extra wiring. Additional objects and advantages of the present invention will be presented in the following description. And these additional purposes and advantages are somehow The degree will be obvious in the description, or can be learned in the practice of the present invention. The purpose and advantages of the present invention can be understood and obtained by means and combinations specifically specified in the scope of the attached patent application. The figure reveals a block diagram of a traditional graphics system with a chipset and an AGP or PCI graphics accelerator; 4SIS / 199906TW, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ --------------: Order ί -------- line (please read the precautions on the back before filling this page) Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 527544 A7 B7 V. Description of the Invention (£) The second figure shows a block diagram of a drawing system. The drawing system has an integrated chip and the integrated chip contains an embedded graphics accelerator. The third figure shows a block diagram of a drawing system. This drawing system has an integrated chip. The integrated chip includes an embedded graphics accelerator and an external AGP or PCI graphics accelerator. The fourth figure shows a block diagram of a device, which is a computer that draws a frame in the present invention. Support one servant in the system The cooperation between a graphics accelerator and a main graphics accelerator; the fifth figure shows a block diagram of a command parser in a conventional graphics accelerator; the sixth figure shows a block diagram of a device provided by the present invention in cooperation with two graphics accelerators. For a detailed description of the invention, please refer to the fourth figure. The fourth figure discloses a block diagram of a device. 40. In the present invention, the device 40 supports the cooperation of a slave graphics accelerator 41 and a master graphics accelerator 42 in a computer system. For drawing work. The drawing work includes a sequence of frames. The device 40 includes a distribution device 401 and an interactive device 402. Based on the performance of the two graphics accelerators, the distribution device 401 allocates a first part of the graphics work to the slave graphics accelerator 41 and a second part of the graphics work to the main graphics accelerator 42 in proportion. The first part and the second part of the drawing work can be separated from the continuous frame, by the frame or part of the frame (such as a quarter frame). 4SIS / 199906TW 5 This paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) ---------------- ^ ---- * Order 1 ·- ----- line (Please read the precautions on the back before filling this page) 527544 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ((9) On the other hand, it is connected to the slave graphics accelerator The interactive device 41 and the main graphics accelerator 402 negotiate the two graphics accelerators to shake hands to move the first part of the drawing work drawn by the drawing accelerator to the main drawing accelerator. The main drawing accelerator transfers the second part of the drawing work drawn by the main drawing accelerator to The first part of the drawing task drawn by the servant drawing accelerator is interchanged. Each pixel of the first part and the second part of the drawing job is displayed on the display screen. In the present invention, because the servant works with the main drawing accelerator to draw and process the drawing job The overall efficiency of drawing has been improved. In order to detect the performance of the master drawing accelerator, the device further includes a measuring device 403. The measuring device 403 can detect the slave drawing accelerator 41 and the main drawing The performance of the accelerator 42 and the performance of the two graphics accelerators are transmitted to the distribution device 401, so that the distribution device 401 can allocate a first part of the graphics work to the slave graphics accelerator 41 in proportion to the performance of the two graphics accelerators, and allocate A second part of the drawing work goes to the main graphics accelerator 42. The slave graphics accelerator 41 can be an embedded graphics accelerator located in the integrated chip, and the main graphics accelerator will be an external graphics accelerator in the graphics card, and vice versa. It is well known that the performance of each graphics accelerator can be measured by the speed at which the graphics accelerator processes the frame. Therefore, the measuring device 403 can detect the performance of the slave graphics accelerator and the main graphics accelerator on-line. If we can get the specifications of each graphics accelerator, 'This measuring device can also detect the performance of the slave graphics accelerator and the master graphics accelerator by referring to the specifications of the two graphics accelerators.
4SIS/199906TW 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------------1* 訂 -------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 527544 A7 B7 五、發明說明（ο ) 實施例 當一外加式繪圖加速器（主）加到一有一嵌入式繪圖 加速器（僕）的一電腦系統中，我們可以定義如下的三種 模式： 1. 雙監視器模式（Dual Monitor Mode):有兩個監 視器，一個加速器對一個監視器。 2. 加入模式（Add-in Mode):使僕繪圖加速器失能 (disabled) 〇 3. 引擎加速模式（Engine Acceleration Mode ):主 與僕繪圖加速器合作以在監視器中繪製圖框。 在雙監視器模式中，主與僕繪圖加速器的行爲除了僕繪圖 加速器在加入模式中是失能的外，都跟一獨立（stand-alone)繪圖加速器一樣。在此，一獨立繪圖加速器是指 一被設計成可獨立運作的一繪圖加速器。一獨立繪圖加速 器50的一指令區隔匡501如第五圖所示，指令區隔匡501 通常包含一佇列控制器（queue controller) 51、一硬體佇 歹ij ( hardware queue )52、一 指令解碼器（command recorder ) 53、爲獨立加速器中一二維引擎（2D engine) 502所設之 一二維先進先出緩衝區（2D FIFO buffer) 54、爲獨立加 速器中一三維引擎（3D engine) 503所設之一三維先進先 4SIS/199906TW 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------^ 訂 i--------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 527544 A7 B7 五、發明說明（δ) 出緩衝區（3D FIFO buffer) 55，爲獨立加速器中一陰極 射線管控制器（CRT controller) 504所設之一互換先進現 出緩衝區（flip FIFO buffer ) 56、以及連接在互換先進 先出緩衝區56的一互換控制器57。 在引擎加速器模式中，如果指定在繪圖卡中之外加式 繪圖加速器爲主繪圖加速器，則儲存圖框資料的緩衝區 506位於一區域記憶體505中，如第五圖所示。它們儲存4SIS / 199906TW This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------------- 1 * Order ------ -Line (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 527544 A7 B7 V. Description of Invention (ο) Example When an external graphics accelerator (main) is added to a In a computer system with embedded graphics accelerator (server), we can define the following three modes: 1. Dual Monitor Mode: There are two monitors, one accelerator to one monitor. 2. Add-in Mode: Disables the drawing accelerator. 3. Engine Acceleration Mode: The master cooperates with the drawing accelerator to draw a frame on the monitor. In dual monitor mode, the master and slave graphics accelerators behave the same as a stand-alone graphics accelerator except that the slave graphics accelerator is disabled in the join mode. Here, an independent graphics accelerator refers to a graphics accelerator designed to operate independently. An instruction segment 501 of an independent graphics accelerator 50 is shown in the fifth figure. The instruction segment 501 generally includes a queue controller 51, a hardware queue 52, a Command decoder (command recorder) 53, a two-dimensional first-in-first-out buffer (2D FIFO buffer) set up in a two-dimensional engine (502) in an independent accelerator 54, a three-dimensional engine (3D engine) in an independent accelerator ) One of the three-dimensional advanced 4SIS / 199906TW set by 503 7 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------------ -^ Order i -------- line (please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 527544 A7 B7 V. Description of the invention (δ) Out of the buffer zone (3D FIFO buffer) 55, which is an interchangeable advanced FIFO buffer 56 that is set in a cathode ray tube controller (CRT controller) 504 in the independent accelerator, and is connected to the interchangeable first-in-first-out buffer 56. One interchange controller 57. In the engine accelerator mode, if an external graphics accelerator is specified as the main graphics accelerator in the graphics card, the buffer 506 for storing frame data is located in a region memory 505, as shown in the fifth figure. They store
I 一電腦螢幕的顯示資料。主繪圖加速器可以控制它們。如 果圖框緩衝區的資料已經顯示在螢幕上了，圖框緩衝區 506就可重複使用且可存取（accessible)。互動裝置402 用AGP與PCI匯流排的兩腳，使主繪圖加速器與繪圖加 速器握手，如第六圖所示。在此，三個互換指令（fliPPing command)與兩個轉移位元塊（bit block transfer簡稱 BitBlt)指令定義如下： ♦ N_Flipping (normal flipping):本指令是一主繪圖加 速器所繪一畫面的互換指令，只下到主繪圖加速器。 籲S_Flipping (slave flipping) ··本指令是一僕繪圖加速 器所繪一畫面的互換指令，只下到僕繪圖加速器。 籲 M—Flipping (master flippping):本指令是一僕繪圖 加速器所繪一圖框的互換指令。它保持與M_BitBlt 一致並且只下到主繪圖加速器。 ♦ N_BitBlt (normal BitBlt) ♦ M_BitBlt (master BitBlt):本指令是用來移動僕繪圖 加速器繪製的一圖框到主繪圖加速器之面緩衝區， 4SIS/199906TW 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------^訂 ί，-------線 (請先閱讀背面之注咅9事項再填寫本頁) 527544 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（q) 只下到主繪圖加速器。 分配裝置401根據僕繪圖加速器41與主繪圖加速器42 的效能，分配依圖框或部分圖框分割繪圖。舉例來說，如 果僕繪圖加速器41的效能與主繪圖加速器42的效能一 樣，包含圖框A、圖框B、圖框C與圖框D的一連續圖 框會被分割成兩部分。包含圖框A與圖框C的一第一部 份圖框會被送到主繪圖加速器去做繪圖，而包含圖框B 與圖框D的一第二部分圖框會被送到僕繪圖加速器去做 繪圖。接著主繪圖加速器（42)中的指令佇列會是： {Draw_A，N_Flipping，M_BitBlt，M Flipping，Draw_C， N—Flipping，M—BitBlt，M_Flipping} 而在僕繪圖加速器41中的指令佇列會是z {Draw_B，S—Fliping，Draw C，S_Flipping} ，其中 Draw_A、Draw B、Draw—C、以及 Draw_D 示 一般常見之使主與僕繪圖加速器繪製圖框A、圖框B、圖 框 C與圖框 D 的指令。指令{Draw_A，N_Flipping，M—BitBlt， M_Fliping}在主繪圖加速器42中執行如下。依據指令 Draw_A，主繪圖加速器開始在區域記憶體505中的可存 取圖框緩衝區506中繪製圖框A。當主繪圖加速器畫完圖 框A，依據N_Flipping，一互換指令被送到互換先進先出 4SIS/199906TW 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ^1 ^1 ϋ 1_| ·ϋ 1^» 一θ、1 I I ϋ ϋ ϋ I ϋ i^i a^i I ϋ ϋ a^i ϋ I ϋ H ϋ ϋ i^i n I ^1 ^1 ϋ ι 經濟部智慧財產局員工消費合作社印製 527544 A7 _______ B7 五、發明說明（（0 ) 緩衝區56。陰極射線管控制器504可讀取互換先進先出 緩衝區56以決定下一個要顯示哪一個圖框緩衝區506。 如果圖框緩衝區之一仍可存取，主繪圖加速器42會接著 處理下一個指令。否則主繪圖加速器42會停止直到主繪 圖加速器的圖框緩衝區506之一可被存取。此外，在被陰 極射線管控制器504互換後，圖框緩衝區506是可存取的。 指令M_BitBlt在主繪圖加速器器42的二維引擎502 中執行。爲了使僕與主繪圖加速器握手，互動裝置402能 使用API或PCI匯流排的兩腳，一個是一 Frame_Ready 訊號61而另一個是一 BitBlt_end訊號62。如果 Frame^Ready訊號61等於1，主繪圖加速器42中的二維 引擎502會將一僕繪圖加速器41所繪製的一圖框移到主 繪圖加速器42中的可存取的圖框緩衝區506中。接著在 一個時鐘週期（clock cycle)中，BitBlt—end的訊號62被 設爲1以告知僕繪圖加速器41。依據M_FHpping，主繪 圖加速器42送一互換指令到互換先進先出緩衝區56,然 後繼續執行下一指令。否則，主繪圖加速器會停下來直到 圖框緩衝區506可被存取。因爲M_BitBlt是一二維訊號， 它可以獨立於三維引擎外執行。指令{ Draw_C，N_Flipping， M__BitBlt，M_Flipping}在主繪圖加速器42中如指令 { Draw—A，N_Flipping，M—BitBlt，M—Flipping}— 般執行。 指令{Draw_B，S_Flipping}執行如下。依據指令 Draw_B，僕繪圖加速器41開始在系統記憶體63內一可 存取的圖框緩衝區631中繪圖。完成繪圖工作後，一互換 4SIS/199906TW 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) W I** ϋ ϋ ϋ n 1 n i^i · 一 0,鼸 ΜΜ IBM· an· W · ϋ· ϋ 1 ·ϋ n ϋ ϋ- ϋ ^1- —ϋ βϋ ϋ ϋ ^1 經濟部智慧財產局員工消費合作社印製 527544 A7 B7 五、發明說明（1 p 指令被送到僕繪圖加速器41中的互換先進先出緩衝區56 而Frame_Ready訊號61會依據指令S_Flipping被設爲1。 系統記憶體63中的圖框緩衝區631會變成唯讀的（read only)。在BitBlt_end訊號62被主繪圖加速器42設爲1 後，Frame_Ready訊號61被僕繪圖加速器41淸除爲0而 圖框緩衝區631會再次變爲可存取。指令{Draw_D， S_FliPPing}在僕繪圖加速器41中如指令{ Draw_B， S_Flipping}— 般執行。 本發明也揭露了一種在一電腦系統中支援一僕繪圖加 速器與一主繪圖加速器合作的方法，以進行繪圖工作。此 繪圖包括一連續圖框，此方法包含下列步驟： (A) 決定僕繪圖加速器與主繪圖加速器的效能； (B) 根據此兩繪圖加速器的效能，分配一第一部分繪 圖工作到僕繪圖加速器，並分配一第二部分繪圖工 作到主繪圖加速器； (C) 此兩繪圖加速器握手以將僕繪圖加速器所繪之繪 圖的第一部份移到主繪圖加速器； (D) 在主繪圖加速器中，依連續圖框的順序，將主繪 圖加速器繪製的第二部分繪圖工作，以及由僕繪圖 加速器繪製的第一部分繪圖工作予以互換。 在前述的方法中，第一與第二繪圖可從連續圖框依圖 框或部分圖框（例如四分之一圖框）分割。在步驟（A) 中此兩加速器的效能可由線上偵測或參考此兩加速器的規 4SIS/199906TW 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------—.—1"訂---------線 (請先閲讀背面之注音心事項再填寫本頁) 527544 經濟部智慧財產局員工消費合作社印製 A7 B7__ 五、發明說明（\〇L) &定。此外，步驟（B)的兩繪圖加速器的握手可以 使用API與pci匯流排的兩腳，一個是Frame__Ready訊 號而另一個是BitBlt_end訊號。其中API與PCI匯流排 分接到僕繪圖加速器與主繪圖加速器。如果僕繪圖加 速器41已完成圖框繪製，Frame_Ready訊號被設爲工。 一旦Frame_Ready等於！，主繪圖加速器42會將一僕繪 圖加速器中所繪的一圖框移到主繪圖加速器42中的可存 取圖框緩衝區。然後BitBlt_end訊號在一時鐘週期中被 設爲1以告知僕繪圖加速器41。在BitBlt_eiid訊號被主 繪圖加速器42設爲1後，Frame_Ready訊號1被僕繪圖 加速器41淸除爲〇。因此，此兩繪圖加速器的握手能成 功運作。 綜觀以上，本發明提供了一種裝置與一種方法，此種 方法與裝置支援僕與主繪圖加速器之合作，藉此繪圖工作 可根據此兩繪圖加速器的效能，依比例分割並被送到僕與 主繪圖加速器。僕繪圖加速器所繪部分的繪圖工作會再被 送到主繪圖加速器。主繪圖加速器輸出分別由僕與主繪圖 加速器所繪的繪圖部分到顯示器螢幕上。因此，支援此合 作能引致較好的效能且圖框繪製的效率藉由此兩繪圖加速 器同時運作之助而提升。 儘管本發明是以現在被認爲最實在與較好的實施例來 加以敘述，本發明將不會被已發現的實施例所限制。本發 明希望能涵蓋了在所附專利申請範圍之精神與範圍內各種 修改與同等配置。 4SIS/199906TW 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------1——：訂ί-------線 (請先閱讀背面之注意事項再填寫本頁)I Display data of a computer screen. The master graphics accelerator can control them. If the frame buffer data is already displayed on the screen, the frame buffer 506 is reusable and accessible. The interactive device 402 uses the two feet of the AGP and the PCI bus to make the main graphics accelerator shake hands with the graphics accelerator, as shown in the sixth figure. Here, the three swap instructions (fliPPing command) and two bit block transfer (BitBlt) instructions are defined as follows: ♦ N_Flipping (normal flipping): This instruction is a swap instruction for a picture drawn by a main graphics accelerator. , Just down to the main graphics accelerator. S_Flipping (slave flipping) ·· This instruction is a swap instruction for a picture drawn by a slave drawing accelerator, only down to the slave drawing accelerator. Call M—Flipping (master flippping): This instruction is a swap instruction for a frame drawn by a slave drawing accelerator. It remains consistent with M_BitBlt and only goes down to the main graphics accelerator. ♦ N_BitBlt (normal BitBlt) ♦ M_BitBlt (master BitBlt): This instruction is used to move a picture frame drawn by the slave graphics accelerator to the surface buffer of the master graphics accelerator. 4SIS / 199906TW 8 This paper standard applies to China National Standard (CNS) A4 specifications (210 X 297 mm) -------------------- ^ Order ί, ------- line (Please read Note 9 on the back first Please fill in this page again for matters) 527544 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (q) Only down to the main graphics accelerator. The allocation device 401 allocates the drawing according to the frame or a part of the frame according to the performance of the slave drawing accelerator 41 and the main drawing accelerator 42. For example, if the performance of the slave graphics accelerator 41 is the same as that of the main graphics accelerator 42, a continuous frame including frame A, frame B, frame C, and frame D will be divided into two parts. A first part of the frame containing frame A and frame C will be sent to the main graphics accelerator for drawing, and a second part of the frame containing frame B and frame D will be sent to the slave graphics accelerator Go for drawing. Then the command queue in the main drawing accelerator (42) will be: {Draw_A, N_Flipping, M_BitBlt, M Flipping, Draw_C, N_Flipping, M_BitBlt, M_Flipping} and the command queue in the slave drawing accelerator 41 will be z {Draw_B, S—Fliping, Draw C, S_Flipping}, where Draw_A, Draw B, Draw—C, and Draw_D show that the master and slave drawing accelerators are commonly used to draw frame A, frame B, frame C, and graph Box D instructions. The instructions {Draw_A, N_Flipping, M_BitBlt, M_Fliping} are executed in the main drawing accelerator 42 as follows. According to the instruction Draw_A, the main drawing accelerator starts drawing frame A in the accessible frame buffer 506 in the area memory 505. When the main graphics accelerator finishes drawing frame A, according to N_Flipping, a swap instruction is sent to the swap FIFO 4SIS / 199906TW 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read first Note on the back, please fill out this page again) ^ 1 ^ 1 ϋ 1_ | · ϋ 1 ^ »-θ, 1 II ϋ ϋ ϋ I ϋ i ^ ia ^ i I ϋ ϋ a ^ i ϋ I ϋ H ϋ ϋ i ^ printed in I ^ 1 ^ 1 To determine which frame buffer 506 to display next. If one of the frame buffers is still accessible, the main graphics accelerator 42 will then process the next instruction. Otherwise the main graphics accelerator 42 will stop until the main graphics accelerator's image One of the frame buffers 506 can be accessed. In addition, the frame buffer 506 is accessible after being interchanged by the cathode-ray tube controller 504. The instruction M_BitBlt is executed in the two-dimensional engine 502 of the main graphics accelerator 42 In order for the servant to shake hands and interact with the master graphics accelerator Set 402 can use the two pins of the API or PCI bus, one is a Frame_Ready signal 61 and the other is a BitBlt_end signal 62. If the Frame ^ Ready signal 61 is equal to 1, the 2D engine 502 in the main graphics accelerator 42 will A frame drawn by the slave graphics accelerator 41 is moved to an accessible frame buffer 506 in the main graphics accelerator 42. Then in a clock cycle, the signal 62 of BitBlt_end is set to 1 In order to inform the slave graphics accelerator 41. According to M_FHpping, the master graphics accelerator 42 sends an interchange instruction to the swap FIFO buffer 56 and then continues to execute the next instruction. Otherwise, the master graphics accelerator will stop until the frame buffer 506 can be accessed. Access. Because M_BitBlt is a two-dimensional signal, it can be executed independently of the three-dimensional engine. The instruction {Draw_C, N_Flipping, M__BitBlt, M_Flipping} is in the main graphics accelerator 42 as the instruction {Draw_A, N_Flipping, M_BitBlt, M —Flipping} — The instruction {Draw_B, S_Flipping} is executed as follows. According to the instruction Draw_B, the slave drawing accelerator 41 starts to be accessible in the system memory 63. The drawing is in the frame buffer 631. After completing the drawing work, it is interchangeable with 4SIS / 199906TW 10 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page ) WI ** ϋ ϋ ϋ n 1 ni ^ i · -0, 鼸 MM IBM · an · W · ϋ · ϋ 1 · ϋ n ϋ ϋ- ϋ ^ 1- —ϋ βϋ ϋ ϋ ^ 1 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 527544 A7 B7 V. Description of the invention (1 p instruction is sent to the swap FIFO buffer 56 in the slave graphics accelerator 41 and the Frame_Ready signal 61 is set to 1 according to the instruction S_Flipping. The frame buffer 631 in the system memory 63 becomes read only. After the BitBlt_end signal 62 is set to 1 by the main graphics accelerator 42, the Frame_Ready signal 61 is divided by the slave graphics accelerator 41 to 0 and the frame buffer 631 becomes accessible again. The instruction {Draw_D, S_FliPPing} is executed in the slave drawing accelerator 41 as the instruction {Draw_B, S_Flipping} —. The invention also discloses a method for supporting a slave graphics accelerator to cooperate with a master graphics accelerator in a computer system to perform drawing work. The drawing includes a continuous frame, and the method includes the following steps: (A) determining the performance of the slave graphics accelerator and the main graphics accelerator; (B) allocating a first part of the graphics work to the slave graphics accelerator based on the performance of the two graphics accelerators, And assign a second part of the drawing work to the main drawing accelerator; (C) the two drawing accelerators shake hands to move the first part of the drawing drawn by the slave drawing accelerator to the main drawing accelerator; (D) in the main drawing accelerator, In the order of successive frames, the second part of the drawing work drawn by the main drawing accelerator and the first part of the drawing work drawn by the slave drawing accelerator are interchanged. In the foregoing method, the first and second drawings may be divided from a continuous frame by a frame or a portion of a frame (for example, a quarter frame). In step (A), the performance of the two accelerators can be detected online or refer to the specifications of the two accelerators. 4SIS / 199906TW 11 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----- -------—.— 1 " Order --------- line (please read the phonetic notes on the back before filling out this page) 527544 Printed by A7 B7__, Employee Cooperative of Intellectual Property Bureau 5. Description of the invention (\ 〇L) & In addition, the handshake of the two graphics accelerators in step (B) can use the two pins of the API and PCI bus, one is the Frame__Ready signal and the other is the BitBlt_end signal. The API and PCI buses are connected to the slave graphics accelerator and the master graphics accelerator. If the slave drawing accelerator 41 has finished drawing the frame, the Frame_Ready signal is set to ON. Once Frame_Ready is equal! The main graphics accelerator 42 moves a frame drawn in a slave graphics accelerator to an accessible frame buffer in the main graphics accelerator 42. The BitBlt_end signal is then set to 1 in one clock cycle to inform the slave graphics accelerator 41. After the BitBlt_eiid signal is set to 1 by the master graphics accelerator 42, the Frame_Ready signal 1 is divided by the slave graphics accelerator 41 to zero. Therefore, the handshake of the two graphics accelerators can successfully operate. To sum up, the present invention provides a device and a method that support the cooperation between the server and the master graphics accelerator, so that the drawing work can be divided into proportions and sent to the server and the master according to the performance of the two graphics accelerators. Drawing accelerator. The drawing work of the slave drawing accelerator will be sent to the main drawing accelerator. The main graphics accelerator outputs the drawing parts drawn by the slave and main graphics accelerators to the monitor screen, respectively. Therefore, supporting this cooperation can lead to better performance and the efficiency of frame drawing is improved by the help of two graphics accelerators operating simultaneously. Although the invention has been described in terms of what is now considered to be the most practical and preferred embodiment, the invention will not be limited by the embodiments found. The invention is intended to cover various modifications and equivalent arrangements that are within the spirit and scope of the scope of the appended patent application. 4SIS / 199906TW 12 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------------- 1——: Order ί ----- --Line (Please read the notes on the back before filling this page)