TW525257B

TW525257B - Improvement method of forming integrated circuit shallow trench isolation region

Info

Publication number: TW525257B
Application number: TW88100509A
Authority: TW
Inventors: Chen-Hua Yu; Syun-Ming Jang
Original assignee: Taiwan Semiconductor Mfg
Priority date: 1999-01-14
Filing date: 1999-01-14
Publication date: 2003-03-21

Abstract

A method of planarization treatment a surface of a semiconductor substrate during formation of shallow trench isolation (STI) region is provided, which can prevent dishing occurred in wide STI region and prevent erosion occurred in the smaller silicon nitride region on the surface of the semiconductor substrate. First, in a platform, a chemical mechanical polishing (CMP) process is performed with a high (product of rotary platen pressure and rotary platen speed) to planarize the semiconductor substrate with a higher material removal rate and a lower selectivity and thus the production capacity is increased. Subsequently, when the end point is detected, the substrate is moved to a second platform for a second CMP process using a low (product of rotary platen pressure and rotary platen speed) to continue planarizing the semiconductor substrate, in which the low polishing rate can control the thickness of the trench oxide of the STI region and thus reduce dishing and erosion phenomena.

Description

525257 —----案號 88100509__年月曰_修正__ 五、發明說明（1) 【發明的領域】本發明係有關用於半導體基底之化學/機械平坦化處理（CMP )的方法和裝置。更明確地說，本發明係有關於一種平坦化處理半導體基底的方法及其裝置，其可減少寬的 ‘溝槽隔離區發生淺碟凹陷（^丨s h i n g )，並可使半導體基底表面上氮化矽的侵蝕（erosi〇n)減至最小。【習知技藝的說明】半導體基底的化學/機械平坦化處理（CMP)已廣為此技藝^ 士所熟知。有關CMP技術的說明可見於張俊彥和施敏所著由 McGraw-Hill Co· Inc·，New York, 1 996 年出版的 ULSI Technology —書的第434 — 439頁，以及說明書後的第 1圖中。研磨介電層的要求為，在保持整個基底表面平坦度的同時能有效去除不需要的材質。CMp程序包括了化學性與機械性的研磨以去除材質。請參見第1圖，CMP機器的研磨台1〇〇設有一旋轉盤5。一研磨墊10依附在轉盤5上。一半導體基底2〇則固定=一晶圓載台15上。將晶圓載台15下降而使半導體基底2〇與研磨塾1 0相接觸。以無關於轉盤5的速度旋轉晶圓載台丨5，並調整晶圓載台1 5而對轉盤5施加壓力。從研磨漿液供應器3 0提供研磨漿液2 5以確保均勻地弄溼研磨墊1〇，並適當地供給與回收研磨漿液25。而研磨漿液25主要係包括懸浮於氫氧化鉀（K〇H)溶液中的膠狀矽土（colloidal si 1ica) 〇一台CMP機器可具有數個研磨台1〇〇，其以自動匣對匣525257 —---- Case No. 88100509__Year Month _Revision__ V. Description of the Invention (1) [Field of the Invention] The present invention relates to a method for chemical / mechanical planarization (CMP) of a semiconductor substrate and Device. More specifically, the present invention relates to a method and a device for planarizing a semiconductor substrate, which can reduce the occurrence of shallow dishing in a wide 'trench isolation region, and enable nitrogen on the surface of the semiconductor substrate. Erosion of siliconized compounds is minimized. [Explanation of Known Techniques] Chemical / mechanical planarization (CMP) of semiconductor substrates has been widely known by those skilled in the art. A description of CMP technology can be found in Zhang Junyan and Shi Min, ULSI Technology, published by McGraw-Hill Co. Inc., New York, 1996 — pages 434 — 439, and in the first figure after the description. The requirement for polishing the dielectric layer is to effectively remove unwanted materials while maintaining the flatness of the entire substrate surface. The CMp procedure involves chemical and mechanical grinding to remove material. Referring to FIG. 1, the grinding table 100 of the CMP machine is provided with a rotating disc 5. A polishing pad 10 is attached to the turntable 5. A semiconductor substrate 20 is fixed = on a wafer stage 15. The wafer stage 15 is lowered and the semiconductor substrate 20 is brought into contact with the polishing pad 10. The wafer stage 5 is rotated at a speed irrespective of the turntable 5, and the wafer stage 15 is adjusted to apply pressure to the turntable 5. The polishing slurry 25 is supplied from the polishing slurry supplier 30 to ensure that the polishing pad 10 is evenly wetted, and the polishing slurry 25 is appropriately supplied and recovered. The grinding slurry 25 mainly includes colloidal silica (colloidal si 1ica) suspended in a potassium hydroxide (KOH) solution. A CMP machine can have several grinding tables 100.

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)相連接壤研磨者之：) Connected to the soil grinder:

搬運手臂（cassette-to-cassette handlers 以及自動晶圓裝填器。 & 、研磨二氧化矽的基本研磨機制係類似於破 ~械f生的去除率可以pres^〇n’s eqUati〇n表示 R = Kppv 其中，R是材質的去除率， Ρ是半導體基底20與旋轉盤5之間的壓力， ν是半導體基底20與旋轉盤5之間的相對速率，以 Κρ是一比例常數。Carrying arms (cassette-to-cassette handlers and automatic wafer loaders.) The basic polishing mechanism for grinding silicon dioxide is similar to the removal rate of mechanical and mechanical removal. The removal rate can be pres ^ 〇n's eqUati〇n means R = Kppv Among them, R is the removal rate of the material, P is the pressure between the semiconductor substrate 20 and the rotating disk 5, ν is the relative rate between the semiconductor substrate 20 and the rotating disk 5, and Kρ is a proportional constant.

Preston’ s常數κρ係二氧化矽介電層之機械性質的函 =，例如硬度和楊氏參數、研磨漿液、以及研磨墊的構造面的方程式係平坦化處理時材質去除速率就機械研-…與面的描述。然而，就研磨處理微觀現象而言，係包括' =學與機械兩部份。雖然確切的研磨處理機制尚未完全知· ^，但目前為止的理解係將化學程序部分區分成四個階 · 段。在第一階段時，氫元素與半導體基底20的氧化物表面產，鍵結。在第二階段時，讓研磨漿液25和半導體基底2〇的氫鍵結合在一起。在第三階段時，研磨漿液2 5和半導體赢基！ 2 0的矽元素鍵結到一共用白勺氧原子上以形《分子冑。· 在第四階段時’移開載有分子矽的研磨漿液25，藉此去除半導體基底20表面上的材質。窃上面欽述的階段具有三個重要的暗示：研磨處理並不只是研磨聚液25之矽土對半導體基底2〇的磨耗。水的存在.Preston's constant κρ is a function of the mechanical properties of the silicon dioxide dielectric layer, such as the equations of hardness and Young's parameters, polishing slurry, and the structural surface of the polishing pad. The material removal rate during flattening is mechanically studied ... With face description. However, as far as the microscopic phenomenon of grinding process is concerned, the system includes two parts: science and mechanics. Although the exact grinding process mechanism is not yet fully understood, the understanding so far has divided the chemical program part into four stages. In the first stage, the hydrogen element is bonded to the oxide surface of the semiconductor substrate 20. In the second stage, the hydrogen bond between the polishing slurry 25 and the semiconductor substrate 20 is bonded together. In the third stage, grinding slurry 25 and semiconductor win base! The silicon element of 20 is bonded to a common oxygen atom in the form of "molecular tritium." In the fourth stage, the polishing slurry 25 carrying the molecular silicon is removed, thereby removing the material on the surface of the semiconductor substrate 20. The above-mentioned stages have three important implications: the grinding process is not just abrasion of the semiconductor substrate 20 by the grinding of the silica of the polymer 25. The presence of water.

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和溶液的pH值影響著氫鍵的形粒大小和組成決定其效能，最係尺寸介於10nm至90nm的石夕土成。再者，研磨漿液25之顆常使用於研磨漿液25之顆粒由Preston’ s equation很明顯可知去除率r係直接關於所施加的壓力p和轉盤的速率v。第4圖所示之材質去除率’以及弟5圖所示化學/機械平坦化研磨處理的選擇率，即是相對於轉盤壓力與轉盤速度之乘積值所緣的。現在請參見第2A和2B圖，以討論現有CMp實務上使用習知研磨技術處理具有淺溝槽隔離區（ST丨）之半導體芙底時所遭遇的問題。在半導體基底20 0的上表面形成一 If 化矽（SiOd層210。在二氧化矽層210上，沈積一層氮化石夕 (S ix Ny)以形成一平坦化處理終止層2 1 5。在平坦化處理終止層2 1 5上形成一光學微影罩幕（未顯示）。對上述光學微影罩幕進行曝光程序以形成定義淺溝槽205a、205b、205c、和205d的圖案，然後對光學微影罩幕施行顯影程序以露出半導體基底20 0將形成淺溝槽2〇5a 、20 5b、205c、和205d的區域。將半導體基底200的表面暴露於一蝕刻劑中，依序去除平坦化處理終止層2 1 5、 S i 〇2層2 1 0、和部分的半導體基底2 〇〇，藉以形成淺溝槽 205a、205b、205c、和20 5d。沈積一 3丨02填充物於半導體基底200的表面上。此一沈積§丨〇2填充物的步驟通常可由此技藝人士熟知的OrTE0S化學氣相沈積（CVD)，或是旋覆玻璃（S0G)程序來達成。接著，即以上面所述的CMP程序去除Si 02填充物22 0。The pH value of the solution affects the size and composition of the hydrogen bonds to determine its effectiveness. The most important factor is the formation of stone soil with a size between 10nm and 90nm. Furthermore, the particles of the grinding slurry 25 are often used in the grinding slurry 25. It is clear from the Preston's equation that the removal rate r is directly related to the applied pressure p and the speed v of the turntable. The material removal rate shown in Fig. 4 'and the selection rate of the chemical / mechanical flattening polishing process shown in Fig. 5 are related to the product of the pressure of the turntable and the speed of the turntable. Please refer to Figs. 2A and 2B to discuss the problems encountered when the conventional CMP is used to process a semiconductor substrate with a shallow trench isolation region (ST 丨) using conventional polishing techniques. An If silicon (SiOd layer 210) is formed on the upper surface of the semiconductor substrate 200. On the silicon dioxide layer 210, a layer of silicon nitride (Six Ny) is deposited to form a planarization termination layer 2 1 5. An optical lithography mask (not shown) is formed on the chemical treatment termination layer 2 1 5. The above-mentioned optical lithography mask is subjected to an exposure procedure to form a pattern defining shallow grooves 205a, 205b, 205c, and 205d, and then the optical The lithographic mask performs a development process to expose areas where the semiconductor substrate 200 will form shallow trenches 205a, 205b, 205c, and 205d. The surface of the semiconductor substrate 200 is exposed to an etchant, and the planarization is sequentially removed. Process the termination layers 2 1 5, the Si 2 layer 2 1 0, and a portion of the semiconductor substrate 2 00 to form shallow trenches 205a, 205b, 205c, and 20 5d. A 3 丨 02 filler is deposited on the semiconductor substrate On the surface of 200. This step of depositing the filling material can usually be achieved by OrTEOS chemical vapor deposition (CVD) or spin-on-glass (S0G) procedures, which are well known to those skilled in the art. Then, using the above The described CMP procedure removes Si 02 filler 22 0.

525257 五、發明說明（4) 研磨去除Si 02填充物220的步驟係進行到其表面與平坦化處理終止層2 1 5等高時為止。然而，習知的C Μ P程序會在半導體基底2 0 0的表面上造成三種形式的問題。第一個問題顯示於第2Β圖的區段I中。半導體基底2 0 0的表面被過度研磨，導致SixNy材質之平坦化處理終止層215遭受侵餘而薄化。第二個問題顯示於第2B圖的區段Π中。半導體基底 2 0 0的表面再度被過度研磨，然而在這個例子中係因轉盤不平整而導致過度研磨並造成淺碟凹陷（dishing)。此一淺碟凹陷現象係發生於大的淺溝槽2〇5c和2〇5d分布的區域中，其將平坦化處理終止層2 0 7完全地去除了。第三個問題則顯示於第2 B圖的區段皿中。半導體基底 200的表面區域研磨不足，因此在半導體基底2〇〇的表面上遺留有S i 02填充物2 2 0。本公一種用以置與製程場來控制研磨塾之率，將可若在半導向電場， Tsai 場於半導司Tsai等人的美國專利第5 , 5 75, 7〇6號，揭示了化，/機械平坦化處理半導體晶圓表面的改良裝在半導體晶圓載台與研磨墊之間施加一電門、登—沾r a 者精由在半導體晶圓載台與個“影響研磨去除速體晶圓載台與研磨墊ί t材質去除的均-性。可進-步控制材質去區域上施加-雙等人所提出之研磨裝置體晶圓載台與研磨墊之n新穎處在於，施加一電 3 ’當作控制要被研磨之525257 V. Description of the invention (4) The step of grinding and removing the Si 02 filler 220 is performed until the surface thereof is equal to the leveling treatment termination layer 2 1 5. However, the conventional CMP procedure causes three forms of problems on the surface of the semiconductor substrate 2000. The first problem is shown in section I of Fig. 2B. The surface of the semiconductor substrate 2000 is excessively polished, causing the planarization termination layer 215 of the SixNy material to suffer from erosion and thinning. The second question is shown in section Π of Figure 2B. The surface of the semiconductor substrate 2000 was over-polished again. However, in this example, the polishing of the turntable caused over-grinding and shallow dishing. This shallow dishing phenomenon occurs in the area where large shallow trenches 205c and 205d are distributed, which completely removes the planarization termination layer 207. The third question is shown in the section dish in Figure 2B. The surface area of the semiconductor substrate 200 is insufficiently polished, so that the Si 02 filler 2 2 0 remains on the surface of the semiconductor substrate 200. The present invention is used to control the rate of the grinding mill by placing a process field. The Tsai field can be used in a semi-directed electric field. The Tsai field is in US Pat. No. 5,575,706 of Tsai et al. Improved mechanical planarization of the surface of semiconductor wafers. A switch is applied between the semiconductor wafer stage and the polishing pad. The semiconductor wafer stage and the "influence polishing removal speed wafer wafer stage" Uniformity with the material removal of the polishing pad. You can further control the application of the material to the area.-The polishing device body wafer stage and polishing pad proposed by Shuang et al. Are novel. Control to be ground

525257 五、發明說明（5) 半導體基底表面上研磨漿液濃度的裝置。控制研磨漿液的濃度暨研磨去除速率，將可增進半導體晶圓表面研磨去除率的均一性。525257 V. Description of the invention (5) Device for grinding slurry concentration on the surface of a semiconductor substrate. Controlling the concentration of the polishing slurry and the polishing removal rate will improve the uniformity of the polishing removal rate on the surface of the semiconductor wafer.

Beyer等人的美國專利第4, 671，851號，揭示了一種用以去除的1製程後在矽基底表面所留下凸起（^1)11^1^3)的方法，通常係脊狀Si〇2突起，稱之為「鳥頭」（bird, s heads)。該發明係藉由對矽基底的表面施MCMp處理而達成。3石夕基底已先覆蓋一研磨終止阻障層，通常是CyD程序形，的SisN4層。由於承受了比覆蓋在基底表面平坦部分者更高的CMP研磨速率，因而可去除位在鳥頭弧線頂部上的SisN4層以及下層的Si〇2突起。如此，CVD 層便出乎意料之外地僅在基底表面的平坦部分當作一研^或蝕刻終止阻障層。藉由調節性地施加不同壓力至研磨墊上，即可改變這些研磨速率的差異值。CMP程序能否成功地平坦化處理這些突起物，取決於研磨溶液的化學性質。在這方面，以S 1 〇2水溶液為主的研磨漿液已證明了其有效性。U.S. Patent No. 4,671,851 to Beyer et al. Discloses a method for removing protrusions (^ 1) 11 ^ 1 ^ 3) on the surface of a silicon substrate after a 1-step removal process, usually a ridge shape Si〇2 prominence, called "bird, s heads". This invention is achieved by applying MCMp treatment to the surface of a silicon substrate. 3 The Shi Xi substrate has been covered with a polishing stop barrier layer, usually a CyD-programmed SisN4 layer. Because it withstands a higher CMP polishing rate than that covered on a flat portion of the substrate surface, the SisN4 layer on the top of the bird's head arc and the underlying Si02 protrusion can be removed. In this way, the CVD layer is unexpectedly only used as a research or etching stop barrier layer on a flat portion of the substrate surface. The difference in these polishing rates can be changed by applying different pressures to the polishing pads. The success of the CMP process in flattening these protrusions depends on the chemistry of the polishing solution. In this respect, the grinding slurry, which is dominated by the S 100 solution, has proven its effectiveness.

Si〇2和S“N4之間的研磨速率比必須介於4比1的下限和4〇比 1的上限。The polishing rate ratio between SiO2 and S "N4 must be between the lower limit of 4 to 1 and the upper limit of 40 to 1.

Sub^amanian等人的美國專利教導了一種用以研磨平坦化覆蓋在半導體基底上之填充物質的製程。在一個實施例中’沈積一第二平坦化層於填充物質上，並且去除一部份填充物質而留下其他部分。調整CMp裝置的研磨墊壓力，以在研磨程序期間產生第一壓力。然後，去除其他部分的填充物質，並以第二壓力操作CMp裝置。研磨程序的 525257 、發明說明（6) ，擇率可藉由降低第二階段研磨處理的研磨墊壓力而保持著。在第二個實施例中，當施行第一階段研磨程序之後，係以一蝕刻程序去除填充物質的其餘部分。有鑑於此，本發明之一個目的，在提供一種平坦化處理具有淺溝槽隔離區之半導體基底表面的方法。本發明另一個目的，在提供一種平坦化處理具有淺溝槽隔離區之半導體基底表面的方》，以避免氮化♦材質之平坦化處理終止層受到侵餘。本發明又：個目的，在提供一種平坦化處理具有淺溝槽隔離區之半導體基底表面的方〉去’以避免淺溝槽隔離區較大的區域發生淺碟凹陷（dishing)。本發明再一個目的，在槽隔離區之半導體基底表面半導體基底時，將部分二氧坦化處理終止層上方。提供一種平坦化處理具有淺溝的方法’以避免在平坦化處理化石夕層遺留在氮化矽材質之平為了達成上述及八他目的，本發明提出理具有淺溝槽隔離區之半導體基底表面的方法。= 高的「轉盤壓力與轉盤速度之乘積值」條件下施行一化: /機械平坦化研磨私序以平坦化該半導體基「轉盤壓力與轉盤速度之乘積值」條件下，可^ 材質去除速率和較低的選擇率來提井1 馒致权同白、 throughput)。然後檢視氮化矽終止芦\ 研磨終點。 θ疋路出以檢測出當檢測到用來標示該氮切區域已露出的研磨終點The U.S. Patent to Subamanian et al. Teaches a process for grinding and flattening a filling material overlying a semiconductor substrate. In one embodiment, 'a second planarization layer is deposited on the filling material, and a portion of the filling material is removed while leaving other portions. The pressure of the polishing pad of the CMP device is adjusted to generate a first pressure during the polishing procedure. Then, the other parts of the filling material were removed, and the CMP device was operated at a second pressure. According to 525257 and (6) of the polishing program, the selectivity can be maintained by reducing the pressure of the polishing pad in the second-stage polishing process. In the second embodiment, after the first-stage grinding process is performed, the remaining part of the filling material is removed by an etching process. In view of this, it is an object of the present invention to provide a method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region. Another object of the present invention is to provide a method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region, so as to prevent the planarization treatment termination layer of the nitride material from being invaded. The present invention also has the object of providing a method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region, so as to avoid shallow dishing in a larger area of the shallow trench isolation region. Yet another object of the present invention is to partially dioxygenate the termination layer above the semiconductor substrate on the surface of the semiconductor substrate in the trench isolation region. A method for planarizing a shallow trench is provided to avoid the planarization of the fossil layer left on the silicon nitride material. In order to achieve the above and other objectives, the present invention proposes to rationalize the surface of a semiconductor substrate with a shallow trench isolation Methods. = High-speed "product of the pressure of the turntable and the speed of the turntable" under the conditions of implementation: / mechanical flattening grinding order to flatten the semiconductor-based "product of the pressure of the turntable and the speed of the turntable" conditions, ^ material removal rate And lower selection rate to improve well 1 (Zhongzhiquan Tongbai, throughput). Then check the silicon nitride termination refining end point. θ 疋 Road out to detect when the end point of the grind used to indicate that the nitrogen-cut region has been exposed is detected

525257 、發明說明（7) $與改用低的「轉盤壓力與轉盤速度之乘積值」來施行一化予/機械平坦化研磨程序，以繼續平坦化該半導體基 & 藉由減慢研磨速率以控制該淺溝槽隔離區之溝槽氧化物的厚度而減少淺碟凹陷和侵蝕現象。 "亥方法更包括一拋光（buffing)該半導體基底表面的 ^驟，以去除上述化學/機械平坦化研磨程序的殘留物，並'肖除該半導體基底表面的微刮痕（microscratches)。、上述平坦化處理具有淺溝槽隔離區之半導體基底表面的方法，係於一化學/機械平坦化（CMP)研磨機器上完成的。其中，在高的轉盤壓力與轉盤速度之乘積值時所施行的研磨程序，係於CMP研磨機器的第一平台（pUten)進行的，而在低的轉盤壓力與轉盤速度之乘積值時所施行的研磨程序，係於CMP研磨機器的第二平台進行的；至於拋光步驟則係於CMP研磨機器的第三平台進行的。有關南的轉盤壓力與轉盤速度之乘積值係介於約5〇〇 Psi-rpm 至約 700 psi-rpm，最好是約為6〇〇 psi—rpm。而在高的轉盤壓力與轉盤速度之乘積值時，最佳的轉盤壓力係介於約7 p s i至8 p s i。有關低的轉盤壓力與轉盤速度之乘積值係介於約2〇〇 psi-rpm 至約 40 0 psi-rpm，最好是約為3〇〇 psi 一 rpm。而在低的轉盤壓力與轉盤速度之乘積值時，最佳的轉盤壓力係介於約3 p s i至4 p s i。【圖式之簡單說明】為了讓本發明上述之目的、特徵、和優點能更明顯易525257, invention description (7) $ and use a low "product of turntable pressure and turntable speed" to implement a flattening / mechanical planarization polishing process to continue flattening the semiconductor substrate by slowing the polishing rate In order to control the thickness of the trench oxide in the shallow trench isolation region, the shallow dish depression and erosion phenomenon are reduced. The "Hai method further includes a step of buffing the surface of the semiconductor substrate to remove the residue of the above-mentioned chemical / mechanical planarization polishing process, and to remove microscratches on the surface of the semiconductor substrate. The method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region is completed on a chemical / mechanical planarization (CMP) polishing machine. Among them, the grinding process performed at the product of the high turntable pressure and the speed of the turntable is performed on the first platform (pUten) of the CMP polishing machine, and it is performed at the product of the low turntable pressure and the speed of the turntable. The polishing procedure is performed on the second platform of the CMP polishing machine; the polishing step is performed on the third platform of the CMP polishing machine. The value of the product of the turntable pressure and the turntable speed for the south ranges from about 500 Psi-rpm to about 700 psi-rpm, preferably about 600 psi-rpm. At the product of high turntable pressure and turntable speed, the optimal turntable pressure is between about 7 p s i to 8 p s i. The value of the product of low turntable pressure and turntable speed is between about 2000 psi-rpm and about 400 psi-rpm, preferably about 300 psi-rpm. In the case of the product of the low turntable pressure and the turntable speed, the optimal turntable pressure is between about 3 p s i to 4 p s i. [Brief description of the drawings] In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easier

525257525257

懂’以下特舉出一較佳實施例，並配合所附圖式，作詳細第1圖係一化學/機械平坦化（CMP)研磨機器之研磨么 (polishing station)的示意圖；口第2 A和2 B圖均為一半導體基底的剖面圖，顯示形養溝槽隔離區，以及習知平坦化處理半導體基底之方 = 成的問題；所过第3圖係本發明平坦化處理具有淺溝槽隔離區之半體基底方法的流程圖；Understand that the following is a detailed description of a preferred embodiment and the accompanying drawings. Figure 1 is a schematic diagram of the polishing station of a chemical / mechanical planarization (CMP) polishing machine; port 2A Figures 2 and 2B are cross-sectional views of a semiconductor substrate, showing the formation of trench isolation regions, and the conventional planarization process of the semiconductor substrate = the problem; the third figure is that the planarization process of the present invention has shallow trenches. Flowchart of half-body base method for trench isolation area;

第4圖係兩種二氧化隙填充物（〇3_TE〇s和§〇(；)和氮化矽層之研磨速率，相對於轉盤壓力與轉盤速度乘積值係圖；以及 _ 第5圖係Os-TEOS分別相對於S〇G和氮化矽層之研磨擇率’與轉盤壓力與轉盤速度乘積值之關係圖。、【發明的詳細說明】現在請參見第4圖，就〇3-TEOS CVD程序所形成的二' 化矽（SiOJ填充物4〇〇、氮化矽（SixNy)42〇、及旋覆玻璃羊 (S0G)所形成的si 〇2填充物41〇其研磨速率或材質去除速率作一討論。如所見者，氮化矽（SixNy)42〇是這些材質中磨速率（去除速率）最低者。在一給定的轉盤壓力盎轉般度乘積值下，OfTEOS CVD·序所形成的二氧化矽（si〇p)填充物40 0具有最快的研磨速率，而旋覆玻璃（s〇G)所形^的Figure 4 is a graph of the grinding rate of two kinds of dioxide gap fillers (〇3_TE〇s and §〇 (;) and the silicon nitride layer relative to the product of the pressure of the turntable and the speed of the turntable; and _ Figure 5 is Os -The graph of the relationship between the grinding selectivity of TEOS relative to SOG and silicon nitride layer, and the product of the rotary table pressure and rotary table speed. [Detailed description of the invention] Now refer to FIG. 4, for 〇3-TEOS CVD The silicon dioxide (SiOJ filling material 400, silicon nitride (SixNy) 42) formed by the procedure, and the SiO 2 filling material 41 formed by spin-on glass sheep (SOG) have a grinding rate or material removal rate. Let's discuss. As you can see, silicon nitride (SixNy) 42 is the one with the lowest abrasion rate (removal rate) among these materials. Of a given turntable pressure and rotation degree product, OfTEOS CVD sequence is formed SiO 2 (SiO 2) filler 40 0 has the fastest grinding rate, while spin-on glass (S 0 G)

Si〇2填充物410則具有與氮化矽（SixNy)42〇相似的研磨速率〇Si02 filler 410 has a polishing rate similar to that of silicon nitride (SixNy) 42.

第11頁 525257Page 11 525257

五、發明說明（9) 因此，耩由選取第2B圖的训層220可以相對較快的速率度值出， SixNy材質之平坦化處理終止層時，即表示檢二:二的轉盤壓力與轉盤速度乘積值處理的終點悉此技藝人士常用的方法來達成，像是目視檢到材質去除速率發生變化等。】$疋偵知第5圖顯示在化學/機械平坦化研磨處理期間，去除各，材質的選擇率。所謂的選擇率係比較 = 率：〇3 —薦CVD程序所形成的二氧化石夕⑻〇2)填1 = 於鼠化石夕（SlxNy)的選擇率顯示於曲線5〇〇。考艮明顯地，〇 -TEOS CVD程序所形成的二氧化矽（Si〇2)填充物，係以比3 氮化矽（SixNy)者快約3·〇至3·5倍的速率去除的。並且，在低的轉盤壓力與轉盤速度乘積值條件下，其選擇率仍約為 3.5。因此，當露出氮化矽以^)平坦化處理終止層時，降低轉盤壓力與轉盤速度的乘積值將更有利於控制第以圖中Si〇2層2 20的厚度。此外，較低的轉盤壓力與轉盤速度乘積值，也有助於減小第2 B圖所示的淺碟凹陷和侵蝕問題，並且可完全去除第2B圖區段瓜中的“〇2層22()。現在請參見第1圖和第3圖，歸結此一平坦化處理具有淺溝槽隔離區之半導體基底的方法。當第2A圖的Si〇2層 220沈積在第2A圖的半導體基底2〇〇表面上之後，將第1圖所示的半導體基底20固著於晶圓載台15上。旋轉轉盤5和晶圓載台1 5，然後將轉盤5與晶圓載台丨5相接觸以開始研磨半導體基底2 〇。注入研磨漿液2 5以淹沒轉盤5上的研磨V. Description of the invention (9) Therefore, the training layer 220 in Figure 2B can be selected at a relatively fast rate. When the flattening process of the SixNy material terminates the layer, it means that the pressure of the turntable and the turntable are two. The end of the processing of the velocity product value is achieved by the methods commonly used by this artist, such as visual inspection to the change in the material removal rate. 】 $ 疋探知 Figure 5 shows the selection rate of materials during the chemical / mechanical planarization polishing process. The so-called selectivity is compared = rate: 03-the recommended dioxide formation by CVD process 2) fill 1 = the selectivity of the rat fossil evening (SlxNy) is shown in the curve 500. Cogan clearly observed that the silicon dioxide (SiO2) filler formed by the 0-TEOS CVD process was removed at a rate of about 3.0 to 3.5 times faster than that of a 3N nitride (SixNy). And, under the condition that the product of the pressure of the turntable and the speed of the turntable is low, the selection rate is still about 3.5. Therefore, when the silicon nitride is exposed to planarize the termination layer, reducing the product of the pressure of the turntable and the speed of the turntable will be more conducive to controlling the thickness of the Si02 layer 220 in the figure. In addition, the lower product of the pressure of the turntable and the speed of the turntable also helps to reduce the problem of dish sags and erosion shown in Figure 2B, and can completely remove the "〇2 层 22 ( ). Now referring to FIGS. 1 and 3, a method for planarizing a semiconductor substrate having a shallow trench isolation region is summarized. When the Si02 layer 220 of FIG. 2A is deposited on the semiconductor substrate 2 of FIG. 2A 〇〇 After the surface, the semiconductor substrate 20 shown in FIG. 1 is fixed on the wafer stage 15. The turntable 5 and the wafer stage 15 are rotated, and then the turntable 5 is brought into contact with the wafer stage 5 to start polishing. Semiconductor substrate 2 0. Grinding slurry 25 is injected to drown the grinding on the turntable 5

第12頁 525257 五、發明說明（10) 塾1 〇 ’然後在高的轉盤壓力與轉盤速度乘積值條件下研磨該半導體基底20。依據發明人實驗的結果，此處所謂高的轉盤壓力與轉盤速度之乘積值，係介於約5〇〇 psi_rpm至，700 pSi—rpm ’最好是約為6〇〇 pS卜rpm。而在高的轉盤壓力與轉盤速度之乘積值時，最佳的轉盤壓力係介於約7Page 12 525257 V. Description of the invention (10) 塾 1 〇 'The semiconductor substrate 20 is then ground under the condition of a high product of the turntable pressure and the speed of the turntable. According to the results of the inventor's experiments, the product of the so-called high turntable pressure and the speed of the turntable is between about 500 psi_rpm and 700 pSi-rpm ', preferably about 600 pS / rpm. At the product of high turntable pressure and turntable speed, the optimal turntable pressure is about 7

Psi至8 psi。藉此，可獲得較高的材質去除速率而在相同的時間内平坦化處理更多的半導體基底，達到提升產能的效果。、，檢視半導體基底20以檢測第2A圖中所示氮化石夕材質之平坦化終止層215是否露出。在第3圖的步驟31〇中，若第 2A圖中所示氮化矽材質之平坦化終止層215尚未露出來，則依，號312之指示繼續進行步驟3〇〇之程序，亦即在高的轉盤壓力與轉盤速度乘積值情況下繼續研磨半導體基底 2 0 ° 一 s達到第2 A圖之s i Ο?層2 2 0的研磨終點時，亦即第2 A 圖中所不匕氮化石夕材質之平坦化終止層215露出來時，依箭號315之指示而進行步驟320的程序，其改用低的「轉盤壓 2與轉盤速度之乘積值」來施行一化學/機械平坦化研磨 ^ ^續平坦化該半導體基底。此處所謂低的轉盤壓力與轉盤速度之乘積值，係介於約2 00 psi-rpm至約4〇〇 psirpm，最好是約為3〇〇 psi_rpm。而在低的轉盤壓力與轉盤速度》之乘積值時，最佳的轉盤壓力係介於約3 psi至4 P、si。如第5圖所示者，低的轉盤壓力與轉盤速度乘積值可增加研磨選擇率，因此步驟320所施行在低的轉盤壓力與Psi to 8 psi. Thereby, a higher material removal rate can be obtained and more semiconductor substrates can be planarized in the same time, thereby achieving the effect of improving productivity. 2. Check the semiconductor substrate 20 to check whether the planarization stop layer 215 of the nitride nitride material shown in FIG. 2A is exposed. In step 31 of FIG. 3, if the planarization stop layer 215 of the silicon nitride material shown in FIG. 2A has not been exposed, then the process of step 300 is continued according to the instruction of No. 312, that is, in When the product of the high turntable pressure and the speed of the turntable continues to grind the semiconductor substrate 20 ° for one second to reach the end point of the si of Figure 2A, the grinding end of layer 2 2 0, that is, the nitride is not shown in Figure 2A When the flattening stop layer 215 of the evening material is exposed, the process of step 320 is performed according to the instruction of the arrow 315, which uses a low "product value of turntable pressure 2 and turntable speed" to perform a chemical / mechanical flattening polishing ^ Continue to planarize the semiconductor substrate. The product of the low turntable pressure and the speed of the turntable here ranges from about 200 psi-rpm to about 400 psirpm, preferably about 300 psi_rpm. At the product of low turntable pressure and turntable speed, the optimal turntable pressure is between about 3 psi to 4 P, si. As shown in FIG. 5, the product of the low turntable pressure and the turntable speed can increase the grinding selection rate, so the step 320 is performed at the low turntable pressure and

第13頁 525257Page 13 525257

轉1速度乘積值條件下的研磨程序，可藉由減慢研磨速率以控，第2B圖中Si〇2層22 0的厚度，並減少第2B圖區段j 中的氮化矽（SixNy)平坦化處理終止層215發生侵蝕 (er〇slon)現象，以及第“圖區段n中的淺溝淺碟凹陷（dishing)。 ^ 當完成步驟32 0所施行在低的轉盤壓力與轉盤速度乘積值條件下的研磨程序之後，即進行步驟33〇的修整程序，將去離子水加在研磨墊1〇上，溫和地拋光（buff)半導體基底20的表面，以去除上述化學/機械平坦化研磨程中研磨漿液的殘留#。並且，此—拋光程序也可去除該半導體基底20表面的微刮痕（micr〇scratches)。上述的方法可以有效地應用在多重研磨台（mul tipie P^hsUng station)的CMp研磨機器上。其中，cMp研磨機器的第一平台（platen)可進行步驟3 〇()所述在高的轉盤壓 $ /、轉派速度乘積值條件下的研磨程序；CMp研磨機器的第一平台則可進行步驟32〇所述在低的轉盤壓力與轉盤速度乘積值條件下的研磨程序。而步驟33〇的拋光修整程序則可在CMP研磨機器的第三平台中進行。有許多方法可用於檢測第2A圖之Si 〇2層22 0的研磨終點，例如可用橢圓儀技術來量測Si〇2層或氮化矽層的厚度。此外，如前所述者氮化矽的研磨速率較低，其摩擦力相對而言也就較大，為維持「定的轉盤速度，勢必提高施加到轉盤的電流量，因此透過凰控施加到轉盤的電流量變化，也可以量測出的終點。 μThe lapping procedure under the condition of 1 speed multiplication value can be controlled by slowing down the lapping rate. The thickness of the Si0 2 layer in Fig. 2B is 22 0, and the silicon nitride (SixNy) in section j of Fig. 2B is reduced. The flattening treatment termination layer 215 has an erroson phenomenon and a shallow trench and dish dishing in the ninth figure. ^ When step 32 0 is completed, the product of the low disk pressure and the disk speed is applied. After the polishing procedure under the optimal conditions, the dressing procedure of step 33 is performed. Deionized water is added to the polishing pad 10, and the surface of the semiconductor substrate 20 is gently buffed to remove the chemical / mechanical planarization polishing. Residues of the grinding slurry during the process. And, the polishing process can also remove micro scratches on the surface of the semiconductor substrate 20. The above method can be effectively applied to multiple grinding tables (mul tipie P ^ hsUng station). ) On the CMP grinding machine. Among them, the first platen of the cMp grinding machine can perform the grinding procedure under the condition of the high rotary table pressure $ /, and the speed of the multiplication value as described in step 30; First platform The polishing procedure under the condition of the product of the low rotary table pressure and the rotary table speed described in step 32 can be performed. The polishing and dressing procedure of step 33 can be performed in the third platform of the CMP polishing machine. There are many methods for testing The polishing end point of the Si 0 2 layer in FIG. 2A is, for example, the thickness of the Si 0 2 layer or the silicon nitride layer can be measured by using an ellipsometry technique. In addition, as described above, the polishing rate of silicon nitride is low. The friction is relatively large. In order to maintain a "stable turntable speed, the amount of current applied to the turntable is bound to increase. Therefore, the change in the amount of current applied to the turntable through the Phoenix Control can also measure the end point. Μ

第14頁 525257 修正曰號 881(105^ 五、發明說明（12) 根據本發明技術的較佳實施例，可如上所述者藉由自動 E對匣之搬運手臂（cassette_t〇_cassette handlers) 及自動晶圓裝填器（automatic wafer loader)，而將半導體基底20從第一研磨台移往第二研磨台，再移往第三研磨台。本發明雖以一較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 [元件符號說明] 5〜旋轉盤； 1 5〜晶圓載台； 2 5〜研磨漿液； 1 0 0〜研磨台； 205a 、 205b 、 205 1 0〜研磨墊； 20〜半導體基底； 3 0〜研磨漿液供應器； 205d〜淺溝槽圖案 2 1 0〜二氧化矽層； 2 1 5〜平坦化處理終止層（例如是氮化矽声 220〜Si02填充物；日’ 400〜研磨OrTEOS之Si〇2填充物的速率曲線； 4 10〜研磨SOG之Si 〇2填充物的速率曲線； 4 2 0〜研磨氮化矽層的速率曲線； 50 0〜OfTEOS相對於氮化矽層的研磨選擇率曲線； 510〜〇3-丁£03相對於8〇(；的研磨選擇率曲線。第15頁 0503-3475-EF1 ； TSMC-1-97-509 » Jacky.ptcPage 14 525257 Correction No. 881 (105 ^ V. Description of the invention (12) According to the preferred embodiment of the technology of the present invention, it is possible to use the automatic E-to-box handling arms (cassette_t〇_cassette handlers) and An automatic wafer loader moves the semiconductor substrate 20 from the first grinding table to the second grinding table, and then to the third grinding table. Although the present invention is disclosed above in a preferred embodiment, it is It is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the attached patent application. [Element symbol description] 5 ~ rotating disk; 15 ~ wafer stage; 25 ~ polishing slurry; 100 ~ polishing table; 205a, 205b, 20510 ~ polishing pad; 20 ~ semiconductor substrate; 3 0 ~ grinding slurry supplier; 205d ~ shallow groove pattern 2 1 0 ~ silicon dioxide layer; 2 1 5 ~ flattening treatment termination layer (for example, silicon nitride sound 220 ~ Si02 filler; day '400 ~ grinding OrTEOS Si02 Filler Rate curve; 4 10 ~ rate curve of Si SiO 2 filler for grinding SOG; 4 2 0 ~ rate curve for grinding silicon nitride layer; 50 0 ~ OfTEOS grinding selectivity curve for silicon nitride layer; 510 ~ 〇3- 丁 £ 03 grind selectivity curve with 80%; page 15503-3475-EF1; TSMC-1-97-509 »Jacky.ptc

Claims

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在南的「轉盤壓力與轉盤速度之乘積值」條件下施行 ::學/機械平坦化研磨程序，#此可以較高的材質去除 =和較低的選擇率來平坦化該半導體基底，從而提升其產旎（production throughput); 1.種在形成淺溝槽隔離區時用以平坦化一半導礞』 ^表面的方法’以防止寬的、淺溝槽隔離區發生淺陷 (d1Shlng)，並避免在該半導體基底表面上區域造成侵餘（erosion)，包括下列步驟：j的孔檢測用來標示該氮化矽區域已露出的研磨終點；以及當到達研磨終點時，改用低的r轉盤壓力與轉盤速度 =乘積值」來施行一化學/機械平坦化研磨程序'，以繼續平坦化該半導體基底，其減慢研磨速率以控制該淺溝槽隔離區之溝槽乳化物的厚度而減少淺碟凹陷和侵餘現象。 2 ·如申請專利範圍第1項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，更包括一拋光 (buffing)該半導體基底表面的步驟，以去除上述化學/機械平坦化研磨程序的殘留物，並消除該半導體基底表面的微刮痕（microscratches)。 3 ·如申請專利範圍第1項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，其中在高的轉盤壓力與轉盤速度之乘積值時所施行的研磨程序，係於一化學/機械平坦化裝置的第一平台（platen)進行的。 4 ·如申請專利範圍第1項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，其中在低的轉盤壓力與轉盤速度之乘積值時所施行的研磨程序，係於一化Under the condition of "product of turntable pressure and turntable speed" in the south :: learning / mechanical flattening and grinding process, #this can remove higher material = and lower selectivity to flatten the semiconductor substrate, thereby improving Its production throughput; 1. A method for flattening half of the surface when forming a shallow trench isolation region "^ surface" to prevent shallow depression (d1Shlng) from occurring in a wide, shallow trench isolation region, and Avoiding erosion on the surface of the semiconductor substrate surface, including the following steps: the hole detection of j is used to mark the exposed end point of the silicon nitride region; and when the end point of the end point is reached, a low r dial is used. "Pressure and turntable speed = product value" to perform a chemical / mechanical planarization polishing process' to continue to planarize the semiconductor substrate, which slows down the polishing rate to control the thickness of the trench emulsion in the shallow trench isolation region and reduces Shallow dish depression and invasion. 2 · The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of patent application, further comprising a step of buffing the surface of the semiconductor substrate to remove the above chemical / Residues of the grinding process are mechanically planarized and microscratches on the surface of the semiconductor substrate are eliminated. 3. The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of the patent application, wherein the grinding process is performed at a high value of the product of the turntable pressure and the turntable speed, It is performed on a first platen of a chemical / mechanical planarization device. 4 · The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of the patent application, wherein the grinding process is performed at a low multiplication value of the disk pressure and the disk speed, Tied to one

0503-3475-EF1 ； TSMC-1-97-509 ； Jacky.pt 第16頁 525257 _塞號 88100509 _年月日_條正 _ — 六、申請專利範圍學/機械平坦化裝置的第二平台進行的。 5 ·如申請專利範圍第2項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，其中拋光該半導體基底表面的步驟，係於一化學/機械平坦化裝置的第三平台進行的。 6 ·如申請專利範圍第1項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，其中高的轉盤壓力與轉盤速度之乘積值係介於約5〇〇 psi_rpm至約7〇〇 ps i-rpm 〇 7 ·如申請專利範圍第i項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，其中低的轉盤壓力與轉盤速度之乘積值係介於約2〇〇 psi_rpm至約4〇〇 psi-rpm ° 8.如申請專利範圍第丨項所述之在形成淺溝槽隔離區時用以平坦化一半導體基底表面的方法，其中在高的轉盤壓力與轉盤速度之乘積值時’其轉盤壓力係介於約7 psi 至8 ps i 。 ± 9、.如申請專利範圍第1項所述之在形成淺溝槽隔離區二化一半導體基底表面的方法，#中在低的轉盤壓力與轉盤速度之乘積值時，其轉盤壓力係介於約31)“ 至4 ps i 〇 10. —種在半導體基底上形成一大致平坦化之淺溝積體電路構造的方法，包括下列步驟：主墓3广t ί體基底’其具有—氮化矽阻障層沈積於該半導體基底的表面上；0503-3475-EF1; TSMC-1-97-509; Jacky.pt page 16 525257 _ plug No. 88100509 _ year month day _ article Zheng _ — six, the scope of the patent application / mechanical flattening device on the second platform of. 5. The method for planarizing the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 2 of the scope of patent application, wherein the step of polishing the surface of the semiconductor substrate is performed by a chemical / mechanical planarization device. The third platform. 6. The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of patent application, wherein the product of the high turntable pressure and the turntable speed is between about 500 psi_rpm Up to about 700ps i-rpm 〇7. A method for planarizing the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item i of the patent application scope, wherein a low turntable pressure and a turntable speed The product value ranges from about 2000 psi_rpm to about 400 psi-rpm ° 8. The method for planarizing the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 丨 of the patent application range, Among them, at the product of high turntable pressure and turntable speed, its turntable pressure is between about 7 psi and 8 ps i. ± 9. As described in item 1 of the scope of the patent application, the method of forming a semiconductor substrate surface in a shallow trench isolation region is described below. When the product of the low disk pressure and the disk speed is a medium value, the disk pressure is referred to (Approximately 31) "to 4 ps i 〇10.-A method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate, including the following steps: The main tomb of the main tomb has a nitrogen substrate A siliconized barrier layer is deposited on the surface of the semiconductor substrate;

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修正、、鲞播在邊半導體基底的表面餘刻出淺溝槽’以形成製作淺溝僧隔離區的區域；形，一二氧化矽層覆於該半導體基底的表面上；一化t高的「轉盤壓力與轉盤速度之乘積值」條件下施行 &予/機械平坦化研磨程序，用以平坦化並且以高速且梦，:+的方式去除該半導體基底表面上多餘的二氧化從而 k 升其產能（produc t i on throughput ); 檢測用來標示該氮化矽阻障/層已露出的研磨終點；以 ^田到達研磨終點時，改用低的「轉盤壓力與轉盤速度 ^ =積值」來施行一化學/機械平坦化研磨程序，以繼續平化忒半導體基底，其減慢研磨速率以控制該淺溝槽隔離區之溝槽氧化物的厚度而減少淺碟凹陷和侵蝕現象。、一 1 1 ·如申請專利範圍第丨0項所述之在半導體基底上形成/大致平坦化之淺溝槽積體電路構造的方法，更包括一 2光（buffing)該半導體基底表面的步驟，以去除上述化學/機械平坦化研磨程序的殘留物，並消除該半導體基底表面的微刮痕（microscratches)。、1 2 ·如申請專利範圍第1 〇項所述之在半導體基底上形成:大致平坦化之淺溝槽積體電路構造的方法，其中在轉盤壓力與轉盤速度之乘積為高值時所施行的研磨程序，係於一化學/機械平坦化裝置的第一平台（platen)進行的。 1 3 ·如申請專利範圍第丨〇項所述之在半導體基底上形成一大致平坦化之淺溝槽積體電路構造的方法，其中在低的轉盤壓力與轉盤速度之乘積值時所施行的磨Correcting and broadcasting the shallow trenches inscribed on the surface of the edge semiconductor substrate to form a region for making the shallow trench isolation region; shape, a silicon dioxide layer covers the surface of the semiconductor substrate; Perform the & pre / mechanical planarization polishing procedure under the condition of "product value of turntable pressure and turntable speed" to flatten and remove high-speed and high-speed, dream-like, + on the surface of the semiconductor substrate to thereby increase k liters. Its production capacity (produc ti on throughput); detection is used to indicate the polishing end point of the silicon nitride barrier / layer has been exposed; when ^ field reaches the polishing end point, use a lower "turntable pressure and turntable speed ^ = product value" A chemical / mechanical planarization polishing process is performed to continue to planarize the holmium semiconductor substrate, which slows down the polishing rate to control the thickness of the trench oxide in the shallow trench isolation region and reduces shallow dishing and erosion. 1, 1 1 · The method for forming / substantially planarizing a shallow trench integrated circuit structure on a semiconductor substrate as described in item 1 of the scope of patent application, further including a step of buffing the surface of the semiconductor substrate To remove residues from the above-mentioned chemical / mechanical planarization polishing process and eliminate microscratches on the surface of the semiconductor substrate. 1 2 · A method for forming a shallow trench integrated circuit structure on a semiconductor substrate as described in item 10 of the scope of patent application: a substantially planar shallow trench integrated circuit structure, which is performed when the product of the pressure of the turntable and the speed of the turntable is high The grinding process is performed on the first platen of a chemical / mechanical planarization device. 1 3 · The method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate as described in item No. of the patent application scope, wherein the method is performed at the time of the product of the low turntable pressure and the turntable speed. mill

525257 __案號 88100509___年月曰_仏正六、申請專利範圍 ^ 於一化學/機械平坦化裝置的第二平台進行的。 1 4 ·如申請專利範圍第11項所述之在半導體基底上形成一大致平坦化之淺溝槽積體電路構造的方法，其中拋光該半導體基底表面的步驟，係於一化學/機械平坦化裝置的第三平台進行的。 1 5 ·如申請專利範圍第1 〇項所述之在半導體基底上形成一大致平坦化之淺溝槽積體電路構造的方法，其中高的轉盤壓力與轉盤速度之乘積值係介於約5 0 0 pSi-rpm至約 7 0 0 ps i -rpm 〇 1 6·如申請專利範圍第1 〇項所述之在半導體基底上形成一大致平坦化之淺溝槽積體電路構造的方法，其中低的轉盤壓力與轉盤速度之乘積值係介於約2 0 0 psi-rpm至約 40 0 ps i -rpm 〇 1 7 ·如申請專利範圍第1 〇項所述之在半導體基底上形成一大致平坦化之淺溝槽積體電路構造的方法，其中在高的轉盤壓力與轉盤速度之乘積值時’其轉盤壓力係介於約 7 ps i 至8 ps i 〇 1 8 ·如申請專利範圍第i 〇項所述之在半導體基底上形成一大致平坦化之淺溝槽積體電路構造的方法’其中在低的轉盤壓力與轉盤速度之乘積值時’其轉盤壓力係介於約 3 ps i 至4 ps i 〇525257 __ Case No. 88100509 ___ Month _ _ Zheng Zheng 6. Scope of patent application ^ It is carried out on the second platform of a chemical / mechanical planarization device. 1 4 · The method for forming a substantially planar shallow trench integrated circuit structure on a semiconductor substrate as described in item 11 of the scope of the patent application, wherein the step of polishing the surface of the semiconductor substrate is a chemical / mechanical planarization The third platform of the device was carried out. 1 5 · The method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate as described in item 10 of the scope of the patent application, wherein the product value of the high turntable pressure and the turntable speed is between about 5 0 0 pSi-rpm to about 7 0 0 ps i-rpm 〇1 6. A method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate as described in item 10 of the patent application scope, wherein The product of the low turntable pressure and the turntable speed is between about 2000 psi-rpm and about 400 ps i-rpm. 〇1 7 · As described in item 10 of the scope of patent application, a rough A method of flattening a shallow trench integrated circuit structure, wherein at a product value of a high turntable pressure and a turntable speed, its turntable pressure is between about 7 ps i to 8 ps i 〇1 8 The method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate described in item i ′, where the product of the low turntable pressure and the speed of the turntable has a turntable pressure of about 3 ps i To 4 ps i 〇

0503-3475-EFl ； TSMC-1-97-509 ； Jacky.ptc 第 19 買0503-3475-EFl; TSMC-1-97-509; Jacky.ptc buy 19