TW525184B - Stackable modules with clustered connections - Google Patents

Abstract

The present invention provides a method for improving the performance of high speed, impedance-controlled bussed data subsystems through the reduction of the data path lengths between high speed semiconductor devices such as high speed control elements (e.g., memory controllers, small computer system interface (SCSI) drivers, peripheral component interconnect (PCI) chipsets and bridges and their intended target devices on the channel (e.g., SDRAM, DDR SDRAM, RAMBUS, FLASH, static RAM, SCSI drives, PCI devices, I/O cards and mezzanines), and an optimized electronic package for interconnecting the devices. The clustered shape and relatively centered placement of the interconnection pads on the circuit members in the electronic package, as well as the potential stacking of multiple circuit members, further enhance the performance and reduce costs.

Description

525184 五、發明說明（1) 【相關專利應用】 本項專利申請案係有關美國第6, 1 72, 895號專利案， 由Brown等人所提出之「具有内建高速匯流排終端之高速 記憶體模組」’於1 999年12月9日申請之美國專利申請案 號0 9/457, 776，及2000年8月24日中請之美國專利中請案 號09/645,860，〇9/645,859，09/6 45,858。200 1 年1月31 曰申請之美國專利申請案號09/774, 857 ; 200 1年2月5日申 請之美國專利中請案號09/775, 99 1 ; 200 1年2月26日申請 之美國專利申請案號09/835, 1 23，200 1年4月13日申請之 美國專利申請案號09/835，123及20 0 1年5月29日申請^美 國專利申請案號09/866, 434，以上各專利中請案在此指定 為本專利案之參考文獻。 【發明範疇】 本發明係有關於一種具有高速、匯流排資料路徑之半 導體裝置電氣連接，尤指一種例如是雙倍資料速率 (double data rate，DDR)同步動態隨機存取記憶體 (SDRAM)及RAMBUS ®裝置等高速匯流排資料之記憶體裝 置。 心 【發明背景】 現今，多樣化之軟體在高速數位計算裝置上執行1 二匕：前更多之動態隨機存取記憶體或是更先 ： 存取記憶體例如是_ SDMM。但是當系統中資機 之速度增加時，互相連接之各種零件之實 命 配置變得很重要’現今之個人電腦即是二個範：：對525184 V. Description of the invention (1) [Related patent applications] This patent application is related to US Patent No. 6, 1 72, 895 and was proposed by Brown et al. As "High-speed memory with built-in high-speed bus terminal" "Module" "U.S. Patent Application No. 0 9/457, 776, filed on December 9, 1999, and U.S. Patent Application No. 09 / 645,860, 009 /, filed on August 24, 2000 645,859,09 / 6,45,858. 200 US Patent Application No. 09/774, 857 filed January 31, 2001; 200 US Patent Application No. 09/775, 99 1; 200 filed on February 5, 2001 U.S. Patent Application No. 09/835, 1 23,200 filed on February 26, 2001 U.S. Patent Application Nos. 09/835, 123, and April 20, 2001 filed on May 29, 2001 ^ U.S. Patent Application No. 09/866, 434, among the above patents, is hereby designated as a reference for this patent. [Invention category] The present invention relates to an electrical connection of a semiconductor device with a high-speed, bus data path, and more particularly, a double data rate (DDR) synchronous dynamic random access memory (SDRAM) and Memory devices such as RAMBUS ® devices for high-speed bus data. [Background of the Invention] Nowadays, diversified software executes one or two daggers on high-speed digital computing devices: more dynamic random access memory before or earlier: access memory such as _SDMM. But as the speed of capital equipment in the system increases, the real-life configuration of various interconnected parts becomes very important. Today's personal computers are two models:

525184 五、發明說明（2) 微處理器及記憶體控制器等許多裝置間之互連組 5 2破执區5中陣列互連的。在某些情形中該互連是經由 二（例如^距列（baU KM ，BGA)技術永久性的連 amy，PGA)連接卷、分開WV立格距陣列（Pin grid ^ ^ 〇 ^1 ,；nV ；" 'Vh V|£ ^ ^ ^ 組是一外觀為長方形】：：=描個人電腦中之記憶體模 之兩邊線性陣列接點互：：η组底部邊緣(e d g e)長度 依記情# a ΰ + ” 相連接。雖然該記憶體模組大小係525184 V. Description of the invention (2) Interconnection group among many devices such as microprocessor and memory controller 5 2 The array in the breaking zone 5 is interconnected. In some cases, the interconnection is connected via two (for example, permanent grid amy (PGA) technology of baU KM (BGA) technology), and the WV grid array (Pin grid ^ ^ ^^) is separated; nV ； " 'Vh V | £ ^ ^ ^ The group is a rectangle with a rectangular shape] :: == describes the linear array contacts on both sides of the memory module in a personal computer: η The length of the bottom edge of the group depends on the situation # a ΰ + ”to connect. Although the size of the memory module is

觀依:為：方r小’接點數量，及晶片技術而改變，該外I 觀約s i f二，。一個目前適用之DDR SDRAM模組測量外 J約為長5.25英时寬或高15英时係依據系統令之方向而 時序憶體匯流排週期之 遠(例如記憶體控制器次V;; J (之如最記姜，體裝置)與離它最 延遲影響而改變。如此將、有 （worst case)傳輸 是SDRAM，EDO RAM及FUSiH二土之0己憶體次系統（例如 M &FLASH)中，該記憶體週期及銓屮為蛀 料間之路徑長度影響非常重大。Πΐί;: ‘ 位長度減去時脈源之最短路徑長度將影塑匯比排 七岐）將受資料之最短路_長产=本f ^枓持有時間（hold 度之最大變化所影響…減去時脈源之最長路徑長 在任何特疋圮憶體為基礎之記憶體週期中，該設定時Guanyi: It is: the number of contact points of square r is small, and the chip technology changes. The external view is about s i f. A current applicable DDR SDRAM module measures J approximately 5.25 inches long or 15 inches high according to the direction of the system order and the timing memory bus cycle is far away (for example, the memory controller times V ;; J ( Such as the most memorable ginger, body device) and the most delayed impact from it. So the worst case transmission is SDRAM, EDO RAM, and FUSiH, the second memory system (such as M & FLASH) In this case, the memory cycle and the path length between the data are very important. Πΐί ;: 'Bit length minus the shortest path length of the clock source will affect the plastic-to-sin ratio, and will be affected by the shortest of the data _Long production = this f ^ 枓 holding time (affected by the largest change in hold degree ... minus the longest path length of the clock source in any special memory-based memory cycle, the setting time

第7頁 525184 五、發明說明（3) J 2 :,間將有—定之基本值’以便將來計算時脈及資 4之間電氣路徑長度變化之延長，此即為所謂之二㊁： 板（PCB)歪斜（skew)。兮μ 车門及括 以偵累畔趑办l 士垓5又疋時間及持有時間必須被延伸 乂便累计將來如時脈抖動（jitter)及製 引起之變化等因素所⑴如* a、尿”广 服度及電源所 之最快匯产挑调如β ^起 遲。匯流排為基礎之系統 N 〜月及輸出主要係由支持裝置操作在所有條 料路徑長度變化下之該設定時間及持有= 長之ί姐 所3定。因此，針對SDRAM，資料長度中較 可处：：t徑及貧料長度變化在設計中對所需要之時序及 了此之輸出可以提供重大貢獻。 《 資斜咖記憶體次系統之設計者曾經嘗試藉由沿著 蜮轸2之炫閃控（strobe)信號至每一目標記憶體裝置以測 ;“德ϊ。對每一記憶體裝置至時脈之資料中該閃控 本地時脈般被使用。當該閃控信號之長度與資 盥資配Ϊ將送出時脈’且既然該閃控信號也需遭遇 二=之！程及溫度條件…以像是-個非常有效 因素已鐵ΐ擬地消除t述之印刷電路板歪斜因素，該 '、^成共用時脈基礎系統架構之輸出瓶頸。 此牟Γίί該資料路徑可以有無限大之輸出。設計者採用< 排考來源同步設計。在最近幾年以高速匯流 之架構中該設計策略已經變得非常普遍。無論如 大夕ίΐ際上有許多理由為何來源同步設計並不展現無限 輸出且在高速、高效率之匯流排設計上也已經變 有問題之架構。甚至，該架構對於具有較長之匯流排路徑Page 7 525184 V. Description of the invention (3) J 2: There will be a fixed basic value in order to calculate the extension of the length of the electrical path between the clock and the data in the future. This is the so-called two. PCB) skew. The door and brackets of the vehicle are covered. The time and holding time must be extended to accumulate future factors such as jitter and changes caused by the system, such as * a, Urine "breadth and the fastest exchange rate of the power supply are selected as β ^. The bus-based system N ~ month and output are mainly set by the support device at the set time under the change of the length of all the strip paths And holding = Changzhi's sister 3. Therefore, for SDRAM, the data length is more useful: the t path and the length of the lean material can provide a significant contribution to the required timing and output in this design. "The designers of the Zixie Coffee Memory Subsystem have tried to measure each strobe memory device by strobe signals along 蜮 轸 2; For data from each memory device to the clock, the flash control is used like the local clock. When the length of the flash control signal and the configuration of the bathroom control device will send out a clock ’, and since the flash control signal also needs to encounter two = of it! Process and temperature conditions ... This is a very effective factor that has been used to eliminate the printed circuit board skew factor described in this article. This is the output bottleneck of the shared clock infrastructure system. This data can have infinite output. Designers adopt the < Examination Source Synchronous Design. This design strategy has become very common in high-speed convergence architectures in recent years. No matter there are many reasons in the world, the source synchronization design does not show infinite output and it has become a problematic architecture in high-speed and high-efficiency bus design. Even more, the architecture has a longer bus path

第8頁 525184 ⑷ 時變得更難加以實現。 在來源同步設計中，資料線及閃控信號間之長度匹配 需要通常對資料線而言是一重要的長度。因為該資料不再 可以直接路由到達其目的端，取而代之的是必須迁迴更遠 地且碗蜒形式之路由以使長度匹配其他匯流排上之資料線 及閃控信號。此最終長度匹配路徑需要板子大部分實際之 空間。在習知之雙排記憶體模組（D IMM)設計上特別地明 顯。 此外’目前需要去降低路徑間（inter-trace)串音 (crosstalk)且在高速設計中使阻抗變化效應最小化，此_ 代表這些路徑需要一較大之路徑間隔以滿足信號整體之需 要以對抗縮小之雜訊邊界。以蜿蜒之方式配置以使長度匹 配外部之路徑之該内部路徑，在沒有更多印刷電路板空間 以供佈置該等路徑下將更難以完成。並且，調整任意特定 内部惋蜒部分中之路徑需要一定之空間以使自感串音最小 化且藉以維護所有信號路徑之完整性。 這兩個效應在長度匹配相位設計中彼此互相增強，在 習知技術以DIMM為基礎之記憶體系統中有一長度匹配匯流 排之範例’該距離三英吋之兩點間最長路徑長度需要五到鲁 六英忖之電路。該距離一英吋之兩點間最短路徑長度也需 要五到六英吋之電路。 當然，只要長度匹配所需要之實際空間是足夠的，將 可降低印刷電路板歪斜以大幅提昇匯流排設定及持有時 間，如此將使以較高速匯流排為基礎之設計變成可能。Page 8 525184 ⑷ becomes more difficult to achieve. In source synchronization design, the length matching between the data line and the flash control signal needs to be an important length for the data line. Because the data can no longer be routed directly to its destination, it must be moved back to a more remote and bowl-shaped route to match the length of the data lines and flash control signals on other buses. This final length matching path requires most of the actual space on the board. It is particularly obvious in the design of the conventional dual-row memory module (D IMM). In addition, at present, it is necessary to reduce inter-trace crosstalk and minimize the effect of impedance change in high-speed designs. This means that these paths need a larger path interval to meet the overall signal needs to counteract Reduced noise boundary. The internal path configured in a meandering manner to match the length of the external path will be more difficult to complete without more printed circuit board space for arranging those paths. Also, adjusting the paths in any particular internal serpentine section requires a certain amount of space to minimize self-inductive crosstalk and thereby maintain the integrity of all signal paths. These two effects reinforce each other in the length matching phase design. There is an example of a length matching bus in the conventional DIMM-based memory system. 'The longest path length between two points of three inches needs five to five Lu Liuying's circuit. The shortest path length between the two points of one inch also requires five to six inches of circuitry. Of course, as long as the actual space required for the length matching is sufficient, the skew of the printed circuit board can be reduced to greatly improve the bus setting and holding time, which will make it possible to design based on higher speed buses.

$ 9頁 525184 五、發明說明（5) 此外’第二階及第三階之效應如阻抗、製程及溫度變 化、反射、振龄（ringing)、振鈐回授（ringback)、集膚 效應（ski n effect )、非線性相位變化、符號間互相干擾 (inter—symbol lnterference，ISI)、錯誤的觸發、接地 彈跳、非理想回返路徑及串音等不能再被忽略。 因為這些第二階及第三階之效應，來源同步架構（例 如DDR SDRAM)將报快進入許多設計上效能之限制或甚至效 能瓶頸。任何可以降低信號路徑長度及致力以設計容納這 些效應之架構在較高速之工作中擁有一較佳之機會。因 =任；可以降低此最差情形，及降低資料線及資料問控< U之電氣路徑長度之平均值將可大幅提昇系統之效^控 種改良上述問題之方向是提供一具有一區域陣列互 了 k致此改良之優點，該記憶體模組 的放置。如此允許以BGA方式連接之記憶1 體與二 更接近記憶體模組之處且最差情形 D 在 低。 〜吟仫長度將可大幅降 為了更進一步提昇記憶體次系統之效能， 及最小化記憶體模組上之資料線及資匕 組之中央位置，各種不同記憶裝置與區; 度。-：解決方法係將記憶體模組區域二 不同於習知技術之記憶體模組具有長像正方形， W焚万形之外翻。 另一種使記憶體次系統之效能更為 曰延〈万法，特别$ 9Page 525184 V. Description of the invention (5) In addition, the effects of the second and third orders such as impedance, process and temperature change, reflection, ringing, ringback, skin effect ( ski n effect), non-linear phase changes, inter-symbol interference (ISI), false triggering, ground bounce, non-ideal return paths, and crosstalk can no longer be ignored. Because of these second- and third-order effects, source-synchronous architectures (such as DDR SDRAM) will quickly enter many design limitations or even performance bottlenecks. Any architecture that can reduce the length of the signal path and strive to design to accommodate these effects has a better opportunity at higher speeds. Because = any; can reduce this worst case, and reduce the average of the electrical path length of the data line and data control U will greatly improve the effectiveness of the system ^ control the improvement of the above problem is to provide a region The arrays have the advantages of this improvement, the placement of the memory modules. This allows the BGA-connected memory 1 and 2 to be closer to the memory module and the worst case D is low. ~ The length of the chanting can be greatly reduced. In order to further improve the performance of the memory subsystem, and to minimize the data line on the memory module and the central position of the data set, various memory devices and areas; -: The solution is to change the memory module area 2 to a memory module that is different from the conventional technology. The memory module has a long square shape and is turned outward. The other is to make the performance of the memory subsystem more prolonged.

第10頁 525184 五、發明說明（6) 疋兄憶體次系統具有大量之記憶體裝置，係被堆疊在第一 記憶體模組之上以增加記憶體模組之數量，且以區域陣列 互連將它們連接起來。與現今個人電腦所採用之配置方法 相比較，例如，四個記憶體模組，每個約長5· 25英吋和高 1 · 5英忖且彼此在主機板上具有〇 · 5英吋之距離，堆疊記憶 體模組提供重大之效能增進及其他優點。這些優點包括： 因為只有堆疊中之第一個記憶體模組需要佈線，可以簡化 主機板之佈線；降低因主機板及記憶體模組間信號旅行所 引起之反射以致於信號整體衰減；及對於主機板之眾多零 件及信號路徑幾乎沒有高頻耦合雜訊。 < 因為本發明之模組經由堆疊配置可以使模組間更為接 近（例如’在一種情況中只有3 fflnl距離），與單一記憶體模 組之情況相比較只會增加非常小之傳輸延遲。 名改良過之兄憶體模組次系統亦提供大幅降低使用系 統板實際)空間之優點。在使用四個記憶體模組之習知技術 中使用空間為20平方英吋，使用本發明之組態後將降低至 4平方英吋。因此，9個較新之記憶體模組將被包裝成與習 知技術一個記憶體模組之相同高度。Page 10 525184 V. Description of the invention (6) The Brother Brothers system has a large number of memory devices, which are stacked on top of the first memory module to increase the number of memory modules. Connect them together. Compared with the configuration methods used in today's personal computers, for example, four memory modules, each approximately 5.25 inches long and 1.5 inches high and each having 0.5 inch inches on the motherboard Distance, stacked memory modules provide significant performance improvements and other advantages. These advantages include: because only the first memory module in the stack needs to be routed, the wiring of the motherboard can be simplified; reducing the overall signal attenuation caused by reflections caused by signal travel between the motherboard and the memory modules; and Many parts of the motherboard and signal path have almost no high frequency coupling noise. < Because the module of the present invention can make the modules closer to each other by stacking configuration (for example, 'only 3 fflnl distance in one case), compared with the case of a single memory module, it will only increase a very small transmission delay . The improved brother memory module system also provides the advantage of significantly reducing the actual space used by the system board. In the conventional technology using four memory modules, the space used is 20 square inches, which will be reduced to 4 square inches after using the configuration of the present invention. Therefore, the 9 newer memory modules will be packaged to the same height as a memory module of the conventional technology.

上述之改良不僅節省使用空間且因佈線長度之減少4 降低系統板及記憶體模組間之複雜性，還因減少最差情子 之傳輸延遲而導致記憶體次系統中許多可能之改良。許 不同之改良與架構是相依的。例如，在許多以匯流排為j 礎之次系統中，路徑阻抗及系統特徵阻抗 ’ (characteristic impedance)間之變化 ^數將決定每一：The above-mentioned improvements not only save space and reduce the complexity between the system board and the memory module due to the reduction of the wiring length4, but also reduce many worst-case transfer delays, resulting in many possible improvements in the memory subsystem. Many different improvements and structures are interdependent. For example, in many secondary systems based on bus j, the change between path impedance and system characteristic impedance ′ (characteristic impedance) will determine each:

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匹配區段之反射大b # μ 長度其必須花費較長J2電壓之準位。對於較長之路徑 非常有可能在記情ί匯::旎到達穩態。對於高速匯流排 沒到達穩態電壓;體===格中設定_ 料資訊被栓鎖或閃控。隐體中不正確位址/控制或資 叢集（clustered)區域陣列互連概念亦允許包含不同 /ί，：同記憶體裝置的記憶體模組共享堆疊中模組與模 、，且s目5之區域陣列互連。相似地，在系統板中相同之區 域陣列互連亦可共享。這與現今之個人電腦在記憶體昇級 時之情形相類似。本概念之優點包含簡化系統板及記憶體 模組之設計，且降低研發測試之需求及新產品之限制。此 代表在新設計之記憶體模組被實現時可靠度及效能限制不 需要再被重複。 對於其他記憶體技術，互連之放置及記憶體裝置與 DDR記憶體有一位元之差別可能是較佳的。例如，對於以 RAMBUS為基礎之記憶體模組，將互連切分成兩個或更多較 小部分可能是較佳的，中央地配置區域陣列（但並不需要 中心點）然後最佳化地放置記憶體裝置。 對於DDR記憶體次系統，甚至DDR記憶體規格需要在兩鲁 端附加終端（termination) ’如果一電氣路徑長度相對於 經過路徑所需之傳輸延遲之上升時間是足夠短，則沿著較 短路徑反射之振鈴週期可能夠低，以致於可節省第二個終 端，因此可簡化及降低記憶體次系統之成本。需不需要第 二個終端係由所使用之次系統可以被電氣模組化成一集成The reflection of the matching section has a large b # μ length, which must take a longer J2 voltage level. For longer paths, it is very likely to remember huihui :: 旎 to reach steady state. For high-speed busbars, the steady-state voltage has not been reached; the setting in the body === grid is locked or flashed. The concept of incorrect address / control or clustered area array interconnection in the hidden body also allows for the inclusion of different / lower: modules and modules in the stack are shared with the memory modules of the memory device, and item 5 The area arrays are interconnected. Similarly, the same area array interconnects on the system board can also be shared. This is similar to the situation in today's personal computers when the memory is upgraded. The advantages of this concept include simplifying the design of system boards and memory modules, and reducing the need for R & D testing and the limitations of new products. This means that when the newly designed memory module is implemented, the reliability and performance limitations need not be repeated. For other memory technologies, it may be better to place the interconnect and the memory device with a one-bit difference from the DDR memory. For example, for RAMBUS-based memory modules, it may be better to divide the interconnect into two or more smaller parts. Centrally configure the area array (but does not need a center point) and then optimize the Place the memory device. For DDR memory sub-systems, even DDR memory specifications need additional terminations at both ends. 'If the rise time of an electrical path length relative to the required transmission delay through the path is short enough, follow the shorter path The reflected ringing period can be low, so that the second terminal can be saved, thus simplifying and reducing the cost of the memory subsystem. No need for a second terminal. The secondary system used can be electrically modularized into an integrated

第12頁 525184 發明說明（8) 化（lumped)或分散化（distributed)之級數（degree)所決 疋。實際上，這疋由電氣路徑長度及信號經由該路徑時之 邊緣率（edge rate)所控制的。較短的路徑長度及較低的 邊緣率使所使用之次系統更集成化且較少分散化。一分散 化系統已定義的線通常被當成較六分之一邊緣率大之電氣 ，度。因此僅僅因為一系統以此準則被分散化，如果該電 氣路徑長度足夠短可能只要一個終端以取代兩個終端即可 保留信號之完整性。其他使用節省傳輸延遲之方式去增進 及/或降低成本之記憶體技術，及其他記憶體技術，在本 技術中將是顯而易見的。 籲 在增加路徑長度時，傳輸線效應變得更具決定性，一 系統板及記憶體模組間之特徵阻抗只要有百分之十之不匹 配，對於相較於一所有路徑長度為1英吋之長度為3或4英 对的所有路徑將有一重大振鈴（過振（〇versh〇〇t)及乏振 Undershoot))週期。該振鈴週期及該設定時間皆可被路 徑長度刻度化（scaled)。即使可預期將來操作在更高頻 率’在時脈週期允許之時間内使信號安定（sett le)在最終 值之百分之一將變得更加困難。在一個範例中，一記憶體 晶片被放置在距離控制器4英吋遠之處將在約72〇 pS後接_ 收到該信號（在FR4中每英吋180 pS)。將在約2160 pS、 3600 pS，及5040 pS時從來源端依序接收到前三個反射信 號。 〇 、變得更緊急的是反射信號來回時間（ronundtrip)與時 脈週期相較將變得可比較的，因此驅動器在一時脈週期内Page 12 525184 Description of the invention (8) The degree of lumped or distributed depends on the degree. In practice, this is controlled by the length of the electrical path and the edge rate of the signal as it passes through the path. Shorter path lengths and lower edge rates make the secondary systems used more integrated and less decentralized. The defined lines of a decentralized system are usually regarded as electrical degrees greater than one-sixth the edge rate. So just because a system is decentralized by this criterion, if the electrical path length is short enough, only one terminal can replace two terminals to preserve the integrity of the signal. Other memory technologies that use transmission-saving ways to increase and / or reduce costs, and other memory technologies, will be apparent in this technology. When increasing the path length, the transmission line effect becomes more decisive. As long as the characteristic impedance between a system board and a memory module is 10% mismatch, it is 1 inch compared to all path lengths. All paths with a length of 3 or 4 pairs will have a significant ringing period (overshoot and undershoot) period. The ringing period and the set time can be scaled by the path length. Even in the future, it can be expected that it will become more difficult to settle the signal at one hundredth of the final value at a higher frequency 'within the time allowed by the clock cycle. In one example, a memory chip placed 4 inches away from the controller will receive this signal after about 72 pS (180 pS per inch in FR4). The first three reflected signals will be received sequentially from the source at approximately 2160 pS, 3600 pS, and 5040 pS. 〇 It becomes more urgent that the reflected signal round-trip time (ronundtrip) and the clock cycle will become comparable, so the driver will be within one clock cycle

525184 五、發明說明（9) 在資料路徑上送出邏輯“1”可以決定在下一個時脈週期 内送出邏輯“0” ，但是從原來“1”所反射之信號將依缺 在線上存在，可能擾亂驅動器正欲傳送“〇 ”之雜訊邊 、 界。此外，如果驅動器在下一個時脈週期再次嘗試傳送 “1 ’’ ’如此將增強前一週前之反射或甚至被以後回來\ 週期所反射。 第一個反射可在驅動器正在切換之瞬間回來。一驅動 器在切換狀態時經過其最大之功率使用。如果從所有長产 匹配線所反射之信號在驅動器切換狀態時回來，且其電^ 準位經過驅動器增強，此種情況將可輕易增加功率消耗且( 降低記憶體控制器之壽命。甚至更差的是，如果經過驅動 器增強之電壓準位輸出導致在所供應之電壓上彈跳 (bounce)足夠長之時間，一典型之CM〇s基礎之裝置驅動 器，如果其輸入/輸出驅動器在一大於供應電源或在地電 位之下接觸足夠長時間週期可能對鎖住（丨 為敏感。 P文付平乂525184 V. Description of the invention (9) Sending logic "1" on the data path can decide to send logic "0" in the next clock cycle, but the signal reflected from the original "1" will exist on the line depending on the lack, which may disturb The driver is trying to transmit the noise edge and boundary of “〇”. In addition, if the drive tries to transmit "1" again in the next clock cycle, this will enhance the reflection from the previous week or even be reflected later. The first reflection can come back as soon as the drive is switching. A drive When switching states, it passes its maximum power usage. If the signal reflected from all long-production matching lines returns when the driver switches states, and its electrical level is enhanced by the driver, this situation will easily increase power consumption and ( Reduce the life of the memory controller. Even worse, if the boosted voltage level output of the driver results in a bounce on the supplied voltage for a long enough time, a typical CMOS-based device driver, If its input / output driver is in contact with the power supply or ground for a long enough period of time, it may be sensitive to lockout. P Wen Fuping 乂

對於未=之記憶體裝置當其供應電壓進 所f訊邊界也將被降低且控制信號線振鈴之過振L 生錯誤，或避免錯誤或位址/控制/資料信號線發彳 更緊急(critiCa"。腳位之第二時脈將變得 時將變得更顯著，在系：之t向率(siew rate)增加 源平面出現像-個由變動之^壓徑網路中使地電位及電 勒之電壓準位、反應不同之線-驅 525184 五、發明說明（ίο) 1~~- 動條件之形狀動態變化之三維拓樸地圖。如此，降低信號 線電氣路徑長度可能也可增加信號之電氣整合度。 當時脈頻率持續的增加，不只長度匹配變得更緊魚， 且電氣損失及由集膚效應所導致之電阻損失，將使目前吃 憶體模組設計在路徑長度上更難以容忍，因為信號之衰減 損失因子（factor)沿著信號路徑隨著雜訊邊界之降低^降 低。此種結果在較長之匯流排例如高密度RAMBUS形式之設 计中將特別明顯，RAMBUS形式之匯流排必須操作在沿著長 ，氣路徑及在較高時脈率之電容性信號負載路徑中信號路 徑具有百分之三至七典型值之衰減損失因子條件下。_ —在較高頻率時（例如大於GHz)印刷電路板不再被當成 固疋阻抗傳輸線而展現線性相位變化，因此其他效應將變 知更顯著’將取代頻率相依之電阻並將展現一與頻率相依 之非線性相位變化。此係較高頻零件之通道電導值 (conductance)增加所致。 ，對高頻信號有兩項效應值得注意。第一，不再，可能將 路=阻抗當成頻率相依電阻，而使用單一電阻去通當匹配 較间頻零件之路徑阻抗。由複數個電阻及電容所組成之匹 配網路去趨近較高頻率頻道之路徑阻抗是值得關心的。這籲 ，相似於設計具高解析度、低頻匹配網路之MX系統之線 ^面，語音郵件系統，及地震學等將與本案含之技術 相類似。 、 第厂，因為頻率依相位而變化，數位信號傳輸共通之 波脈衝（pulse)藉由通道變成脈衝形狀，改變它們的外For non- = memory devices, when their supply voltage enters the boundary of the signal, the control signal line will ring too much, causing errors, or avoiding errors or address / control / data signal line is more urgent (critiCa " The second clock of the foot position will become more and more significant. In the system: the t-direction rate (siew rate) increases. The plane of the source appears like a ground pressure and The voltage level and response of different electric lines-drive 525184 V. Description of the invention 1 ~~-A three-dimensional topographic map of the dynamic changes of the shape of the dynamic conditions. In this way, reducing the electrical path length of the signal line may also increase the signal The degree of electrical integration. The clock frequency continues to increase, not only the length matching becomes tighter, but also the electrical loss and the resistance loss caused by the skin effect will make the current memory module design more difficult in the path length. Tolerance, because the signal's attenuation loss factor (factor) along the signal path decreases as the noise boundary decreases ^ This result will be particularly obvious in the design of longer buses such as high-density RAMBUS form, The streamer must be operated along a long, air path and a capacitive signal load path with a higher clock rate with a signal path with an attenuation loss factor of three to seven percent typical. _ — At higher frequencies (For example, greater than GHz) Printed circuit boards are no longer treated as fixed impedance transmission lines and exhibit linear phase changes, so other effects will become more significant. 'It will replace frequency-dependent resistance and will exhibit a frequency-dependent nonlinear phase change. This is due to the increase in channel conductance of higher frequency parts. There are two effects on high frequency signals worth noting. First, no longer, it may be possible to treat circuit = impedance as a frequency-dependent resistor and use a single resistor to It should be used to match the path impedance of the parts with relatively high frequency. The matching network composed of a plurality of resistors and capacitors is approaching to the path impedance of the higher frequency channel. This appeal is similar to the design of high resolution, low frequency The MX plane, voice mail system, and seismology of the matching network will be similar to the technology included in this case. The first plant, because the frequency varies depending on the phase Digital transmission signal in common wave pulse (Pulse) by a pulse-shaped channel, changing their outer

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因為這些高頻的效應，對 長度變得更有益處。在本發明 的結合，以改進許多緊急設計 更佳空間解決方法。 高頻數位信號傳輸降低通道 之技術中將會出現巧妙不同 參數及執行效率，以建立一 本發明圮憶體系統中之叢集區域陣列互連亦提供機 上重大之改良。所有印刷電路板在兩個平面上有一固定 之經線（warp)。印刷電路板每一英吋之長或寬會有數千馨 經線之變化是一典型特徵，經線使任何區域陣列連接器^ 低量或接觸力量去可靠地使用所有接點變得更困難。藉由 在許多較小區域中之保持互連，經線效應可被最小化。曰對 於陸地格距陣列（land grid array，LGA)連接器及夾箝 (clamp)此將可簡易設計需求，及降低大小及/或成本。 為了焊接例如球格距陣列（ball grid array，BGA)及 列格距陣列（column grid array，CGA)及表面黏著pGA等 連接器之互連’叢集亦提供機構穩定性之改善。此乃導因 於與接地點（neutral point，DNP)距離之減少，其可使熱魯 擴展係數（coefficient of thermal expansion，CTE)不 匹配所引起之機構不穩定性最小化。此外，因為在一較小 區域中非平面性較少於轉角，因此生產力亦可提升。 以上所揭露之創見可使用在非常多之應用及需求中， 因此’可以實現在更多樣化之電子封裝中。一些影響實現Because of these high-frequency effects, length becomes more beneficial. The present invention combines better spatial solutions to improve many emergency designs. High-frequency digital signal transmission technology that will reduce the channel will appear cleverly different parameters and execution efficiency, to establish a cluster area array interconnect in the memory system of the present invention also provides a significant improvement on board. All printed circuit boards have a fixed warp on two planes. A printed circuit board has a typical characteristic of thousands of warp changes per inch or width. Warp warps make it more difficult to use all contacts reliably with low volume or contact force in any area array connector. . By maintaining interconnections in many smaller areas, the warp effect can be minimized. For land grid array (LGA) connectors and clamps, this will simplify design requirements and reduce size and / or cost. Interconnecting 'clusters for soldering connectors such as ball grid array (BGA) and column grid array (CGA) and surface-adhered pGA connectors also provide improved stability of the mechanism. This is due to the reduced distance from the neutral point (DNP), which can minimize the instability of the mechanism caused by the mismatch of the coefficient of thermal expansion (CTE). In addition, productivity is increased because non-planarity is less than corners in a smaller area. The above-discussed ideas can be used in many applications and requirements, so 'can be implemented in more diverse electronic packages. Some influences achieved

525184 五、發明說明（12) 決策之參數是穩定性需要之級數、需要之場地分離，封裝 之大小、特定晶片技術或包含技術、匯流排速度、及所要 互連之裝置數目、量產因素及成本等。這些參數影響許多 項目包含從封裝至系統板之互連方法，封裝内部之互連方 法，材料之使用，所需電路元件之數目及複雜度，夾箝及 冷卻的方法等。例如，從封裝至系統板及封裝内部之互連 方法是特定之應用可能可以與焊接、PGA、LGA組合在一 起。LGA連接器及夾箝之一較佳範例可參考一些前述申請 中之美國專利案。 因此，本發明之一目的係增強高速、匯流排資料次系 統之技術。 本發明之另一目的係提供一高速模組，其具有一互連 至一系統板之叢集陣列接點’且允許外加模組在信號適當 佈置時與原來相同接點堆疊之匯流排資料裝置。 本發明之再一目的係上述模組與一系統板至少是分開 的。 本發明之另一目的係上述模組提供一低的外型。 本發明之再一目的係上述模組之裝置在溫度增加時， 亦可穩定操作。 本發明之另一目的係上述模組提供機構效能之改良。 【發明概述】525184 V. Description of the invention (12) The parameters for the decision are the number of stages required for stability, the separation of the required site, the size of the package, the specific chip technology or technology, the speed of the bus, the number of devices to be interconnected, and mass production factors. And costs. These parameters affect many items including the interconnection method from the package to the system board, the interconnection method inside the package, the use of materials, the number and complexity of circuit components required, the method of clamping and cooling, and so on. For example, the interconnection method from the package to the system board and inside the package is application specific. It may be combined with soldering, PGA, LGA. For a preferred example of an LGA connector and clamp, refer to some of the aforementioned U.S. patent applications. Therefore, one object of the present invention is to enhance the technology of the high-speed, bus data subsystem. Another object of the present invention is to provide a high-speed module, which has a bus array device that is interconnected to a cluster array contact of a system board and allows additional modules to be stacked with the same contacts as the original when the signals are properly arranged. It is still another object of the present invention that the above-mentioned module and a system board are at least separated. Another object of the present invention is to provide the module with a low profile. Another object of the present invention is that the device of the above-mentioned module can also operate stably when the temperature increases. Another object of the present invention is to improve the performance of the mechanism provided by the module. [Overview of Invention]

一、^I明係提供一種改良高速度效能之方法，藉由降低 同速"導體裝置例如記憶體控制器及DDr SDRAM及RAMBUS 裝置之貧料路徑長度以控制阻抗匯流排資料次系統，及一 525184 五、發明說明（13) 圮憶體裝置互連之最佳化電子。 裝中之電路元件互連接點相關集中放置以 行效率及降低成本。 且子之位置，更增強執 改良後之記憶體次4 i ^ ^ 空間。此外，叢隼F敁陆、了大幅降低系統板之真實使用 化’以簡化設計需求及降低任 之夾線效應最小 積大小及/或u。 連接器之夾*使用面 一些封裝之零件根據特定用途可能會有所化，兮 方法，所使用之材料，所需電路叙封裝内部之互連 敕伽认真； 叮而電路兀件之數目及複雜性，在 冷卻的方法。例如，從1陣列式樣，以及夾箝及 二，列如，從糸統板至封裝及封裝 法可以是BGA，PGA及LGA之組合。 【圖式簡單說明】 為使t審查委員㉟進一步瞭解本發明之結構、特徵 后了目的，茲附以圖式及較佳具體實施例之詳細說明如 憶=是二習知技藝中記憶體控制器裝置及-複數個記· "模、、且在兄憶體次系統安排之匯流排互連之示意圖； 圖2是記憶體控制器裝置與目標裝置之區域陣列接點 之匯流排互連之底視圖； · 圖3a是本發明一較佳實施例之一DDR SDRAM基礎之記 思體次系統其電路元件區域陣列接點互連之集中化配置之 第18頁 525184 五' ^ 香明說明（14) 頂 視 圖 礎 圖 3b 是 圖: 3a 中 本發 明 一 較 佳 實 施 例 之 DDR ； SDRAM 基 之 記 憶 體 次 系 統 其 電 路 元 件 區 域 陣 列 接 點 互 連 之 另 一 組 態 之 頂 視 圖 9 個 圖 3c 是 斷 面 圖 5 係 擴 大 圖 3a 之 較 佳 實 施 例 中 該 複 數 電 路 元 件 之 側 視 圖 藉 圖 3d 是 斷 面 圖 係 擴 大 圖 3c 之 較 佳 實 施 例 之 側 視 圖 由 包 含 其 他 裝 置 以 提 供 額 外 功 能 次 圖 4a 是 本發 明 一 較 佳 實 施 例 之 RAMBUS 基礎 之 記 憶 體赢 系 統 其 電 路 元 件 區 域 陣 列 接 點 互 連 之 集 中 化 配 置 修 正 後· 之 頂 視 圖 9 圖 4b 是 圖 4a 之 較 佳 實 施 例 中 該 複 數 個 電 路 元 件 更 緊 密 結 合 之 頂 視 圖 > 體 圖 4c 是 根據 圖 4a 之 較 佳 實 施 例 之 一 RAMBUS 基礎 之 記 憶 次 系 統 其 電 路 元 件 區 域 陣 列 接 點 互 連 之 集 中 化 配 置 修 正 後 之 頂 視 丨圖 圖 4d 是 一一 斷 面 圖 係 擴 大 圖 4a 之 較佳 實 施 例 中 該 複 數 個 電 路 元 件 之 側 視 圖 > 圖 4e 是 顯 示 圖 4d 之 較 佳 實 施 例 中RAMBUS 通 道 之 路 徑 示_ 意 圖 1 圖 4f 顯 示 圖 4a 至 圖 4c 之 較佳 實 施 例 中RAMBUS 基礎 記 憶 體 次 系 統 之 另 —丨__ 種 組 態 之 頂 視 圖 ； 以 及 圖 4g 顯 示 圖 4f 之 較 佳 實 施 例 中RAMBUS 基礎 記 憶 體 次 系 統 之 另 種 組 態 之 頂 視 圖 〇1. ^ I provides a method for improving high-speed performance by controlling the impedance bus data subsystem by reducing the lean path length of the same-speed conductor devices such as memory controllers and DDR SDRAM and RAMBUS devices, and A 525184 V. Description of the invention (13) Optimized electrons for the interconnection of memory devices. The interconnection points of the circuit components in the assembly are placed in a centralized manner for efficiency and cost reduction. And the position of the son is even more enhanced. The improved memory space is 4 i ^ ^ space. In addition, Fong Lu has greatly reduced the real use of system boards ’to simplify the design requirements and reduce the minimum product size and / or u of any pinch effect. Connector clips * Some packaged parts on the use side may be changed according to the specific purpose. The methods, materials used, and the interconnections required in the package are carefully considered. The number and complexity of circuit components The method of cooling. For example, from 1 array pattern, and clamps and two, for example, from the system board to the packaging and packaging method can be a combination of BGA, PGA and LGA. [Brief description of the drawings] In order to make the reviewing committee better understand the structure and characteristics of the present invention, the drawings and detailed descriptions of the preferred embodiments are attached. Schematic diagram of a bus device and a plurality of memory modules interconnected in a memory system arrangement; Figure 2 is a bus interconnection between a memory controller device and an area array contact of a target device. Bottom view; Figure 3a is a centralized configuration of circuit element area array contact interconnections of a memory system based on a DDR SDRAM, one of the preferred embodiments of the present invention. (14) Top view. Figure 3b is a top view of another configuration of the DDR in a preferred embodiment of the present invention in 3a; SDRAM-based memory sub-system, another configuration of the circuit element area array contacts interconnection 9 views 3c is a sectional view. FIG. 5 is an enlarged side view of the complex circuit element in the preferred embodiment of FIG. 3a. Figure 3d is a cross-sectional view which is a side view of the preferred embodiment of Figure 3c. Other devices are provided to provide additional functions. Figure 4a is a circuit element area of a RAMBUS-based memory win system according to a preferred embodiment of the present invention. Top view of the centralized configuration of the array contact interconnection after modification. Figure 9b is a top view of the plurality of circuit elements in the preferred embodiment of Figure 4a being more closely combined. Figure 4c is a better view according to Figure 4a. One embodiment of the RAMBUS-based memory sub-system. The top view of the centralized arrangement of the circuit element area array contact interconnections after correction is modified. Figure 4d is a cross-sectional view that expands the complex number in the preferred embodiment of Figure 4a. Side view of each circuit element> Fig. 4e shows the way of the RAMBUS channel in the preferred embodiment of Fig. 4d Figure _ Intention 1 Figure 4f shows another top view of the RAMBUS basic memory sub-system in the preferred embodiment of Figures 4a to 4c; and Figure 4g shows the preferred embodiment of Figure 4f Top view of another configuration of the RAMBUS base memory sub-system.

第19頁 525184 發明說明（15) 【較佳實施例之詳細說明】 :般來說’本發明係提供一種改良高速度效能之方 法’藉由降低南速半導體裝置例如高速控制元件（例如記 憶體控制器’小型電腦系統介面（s cs丨）驅動器，週邊裝置 (PCI)互連晶片組及橋接器及其通道上之目標裝置（例如 SDRAM，DDR SDRAM，RAMBUS，FLASH，SRAM，SCSI 驅動 器’PC I裝置’I/o卡等等），及一裝置互連之最佳化電子 封裝。该叢集外型及電子封裝中之電路元件互連接點相關 集中放置’以及當裝置數目獲得保證時複數個電路元件互 相堆疊時之位置，俾增強執行效率及降低成本。該複數個· 電路元件可使用具成本效益之印刷電路板之線寬及空間， 以形成一俗稱印刷電路卡，該印刷電路板上具有封裝或解 除封裝之裝置直接附著在複數個電路元件上，且更可能包 =選擇性之匯流排終端。該封裝亦可能包含夾箝裝置，熱 官理結構及需要時之排直線之裝置。 一明參照圖1 ’其繪示出習知技藝中記憶體次系統丨〇在 :統板1 2上，包含一記憶體控制器1 4及一複數個記憶體 f安排之匯流排互連之示意圖。在該範例中，雖然有 二二?他技術可以應用，記憶體次系統10係以DDR SDRAM · 術為基礎。圮憶體控制器丨4經由複數個匯流排互連 性連接至記憶體模組16a —16d，其中每個記憶 、==複數個記憶體裝置28所組成。為了提供更高密 ^雨Ϊ ί憶體裝置28可以被放置在記憶體模組1 6a] 6d 且至在一邊或兩邊彼此堆疊。此種堆疊型態是具Page 19 525184 Description of the invention (15) [Detailed description of the preferred embodiment]: Generally, the present invention provides a method for improving high-speed performance by reducing the speed of a semiconductor device such as a high-speed control device such as a memory Controller 'Small Computer System Interface (SCS 丨) Driver, Peripheral Device (PCI) Interconnect Chipset and Bridge and Target Device on its Channel (eg SDRAM, DDR SDRAM, RAMBUS, FLASH, SRAM, SCSI Driver' PC I device 'I / o card, etc.), and an optimized electronic package for device interconnection. The cluster shape and the interconnection of circuit component interconnection points in the electronic package are placed in a centralized manner' and multiple when the number of devices is guaranteed The position of circuit components when stacked on each other, enhances execution efficiency and reduces costs. The plurality of circuit components can make the cost-effective printed circuit board line width and space to form a commonly known printed circuit card. The printed circuit board A device with a package or unpackage is directly attached to a plurality of circuit elements, and is more likely to include a = selective bus terminal. The package can also be Contains clamp device, thermal management structure, and device for aligning lines when needed. Refer to Figure 1 'It shows the memory sub-system in the conventional technique. 丨 On the system board 12, it contains a memory. Schematic diagram of the bus interconnects between the controller 14 and a plurality of memories f. In this example, although there are two or two other technologies that can be applied, the memory subsystem 10 is based on DDR SDRAM technology. 圮The memory controller 4 is connected to the memory modules 16a-16d via a plurality of bus interconnects, where each memory is composed of a plurality of memory devices 28. In order to provide higher density ^ 雨 Ϊ ίMemory The device 28 can be placed on the memory module 16a] 6d and stacked on one or both sides. This type of stacking is

第20頁 525184 五、發明說明（16) 有成本的，但是，並不可靠，及難以重複執行。此外，如 此堆疊之裝置散熱是非常困難的。 記憶體控制器1 4經由其底部22之BGA焊點2 0 (圖2所示） 陣列連接至系統板1 2。記憶體控制器1 4之長度“M，，為約1 英吋’使該裝置之大小約為1平方英吋。記憶體模組 16a-16d之長約5·25英吋及1.5英吋高，模組16a-16d間具 有0 · 5夬忖之 P 距離。沿著模組1 6 a -1 6 d之較低邊緣皆 具有接點2 4。經由一邊緣連接器接點2 4提供與系統板1 2之 電性連接’未予圖不因此並不加以詳細說明。 記憶體模組1 6 a -1 6 d典型的係印刷電路構造，係由環_ 氧基-玻璃-基（epoxy-glass-based)材料所組成（例如， FR4)且包含一或多個導電層（例如，信號，電源及/或接 地）在其中。因為嚴格之電氣規格，信號路徑之阻抗必須 與系統板1 2上相對應路徑之阻抗匹配，且誤差只能在百分 之十内。 各己憶體控制器1 4及第一個記憶體模組1 6 a間之距離 “W ’’係提供複數個匯流排互連i8a —18(1與它們連接之區 域。因為記憶體技術之需求，大部分複數個匯流排互連 18a-18d之長度必須在0. 1英吋之内。如此將會導致大量沒 有效率之佈線。因此雖然看似互連18a將被從記憶體控制" 器14直接連接至記憶體模組16a之中央接點24，但必須加 上額外之長度以匹配互連18b較長之路徑，特別是18c及 18d。此額外之佈線將導致距離“w，，增加，從一最佳 ^英叶增加至更實際之3英时，3戈在FR4上額外之36 /Page 20 525184 V. Description of the invention (16) There are costs, but they are not reliable and difficult to repeat. In addition, it is very difficult for such stacked devices to dissipate heat. The memory controller 14 is connected to the system board 12 via a BGA solder joint 20 (shown in FIG. 2) at the bottom 22 thereof. The length “M” of the memory controller 14 is about 1 inch, which makes the size of the device about 1 square inch. The memory modules 16a-16d are about 5.25 inches long and 1.5 inches high Modules 16a-16d have a P distance of 0 · 5 夬 忖. Contacts 2 4 are provided along the lower edges of the modules 16a to 16d. The contacts 24 are provided via an edge connector The electrical connection of the system board 12 is not shown in the figure and will not be described in detail. Memory modules 1 6 a -1 6 d are typically printed circuit structures made of epoxy_glass-based (epoxy) -glass-based) material (for example, FR4) and contains one or more conductive layers (for example, signal, power, and / or ground). Because of strict electrical specifications, the impedance of the signal path must be the same as that of the system board 1 The impedance of the corresponding path on 2 is matched, and the error can only be within 10%. The distance "W" between each memory controller 14 and the first memory module 16a is provided in plural. Bus interconnects i8a-18 (1 The area connected to them. Due to the memory technology requirements, most of the multiple bus interconnects 18a-18d Must be within 0.1 inch. This will result in a lot of inefficient wiring. So although it seems that the interconnect 18a will be directly connected from the memory controller " memory 14 " to the central contact 24 of the memory module 16a , But additional length must be added to match the longer path of interconnect 18b, especially 18c and 18d. This additional wiring will cause the distance "w ,," to increase, from an optimal ^ English leaf to a more practical 3 In the case of British time, 3 Ge has 36 /

525184 五、發明說明（π) 傳輸延遲。系統板1 2上提供給記憶體控制器1 4及記憶體模 組1 6 a間互連1 8 a - 1 8 d所需之總區域大約2 〇平方英对。記憶 體模組1 6 a -1 6 d間之互連長度匹配也必然會發生，如此將 會增加傳輸延遲及佈線衝突。 必須瞭解的是當頻率不斷的增加，互連18a —18d之長 度匹配並不保證匯流排次系統之正常功能。此乃導因於較 長路徑長度沿著上述許多其他之電氣效應。 請參照圖2 ’其繪示依據本發明之記憶體次系統3 〇中 介於記憶體控制器14及針對目標記憶體裝置28(圖3a)之區( 域陣列互連接點3 2間部分匯流排互連之底視圖。圖中所提 及之概念不只可以應用在DDR SDRAM，亦可應用在所有形 式之匯流排互連。該記憶體控制器丨4藉由複數個匯流排互 連34a - 34c連接至記憶體裝置28(圖3a)。 記憶體控制器14經由其底部22之BGA焊點20陣列連接 至系統板1 2。記憶體控制器丨4之長度“μ ”為約1英吋，使 該裝置之大小約為1平方英吋。在此情況中區域陣列互連 接點3 2之長度“c ”係與記憶體控制器丨4之長度相同。區 域陣列互連接點32從系統板12至複數個電路元件36、38、 ^ (圖3c)間允許許多連接方法。包含BGA焊點附著，pGa附鲁 著及LGA附著，所有可能之選擇視特定設計需求而定。 “ 記憶體控制器14及區域陣列互連接點32間之距離 X 係提供複數個匯流排互連34a-34c與它們連接之區 域| °因為匯流排互連34a-34c嚴格之長度匹配要求，距離 X 降低至約〇 · 5英吋。與圖1習知技術之範例比較，對 第22頁 525184 五、發明說明（18) 於單一記憶體模組之情況，路徑長度之最差情形從2· 91英 吋降低至1·34英吋，如此可降低在FR4介電質中283 pS之 路徑飛行時間（t i m e -1 〇 - f 1 y )，且在四個記憶體模組之情 況，路徑長度之最差情形甚至從3· 78英吋降低至1. 94英 时，如此可降低在FR4介電質中349 pS之路徑飛行時間。 降低匯流排路徑長度可降低信號傳輸延遲，因此可増 加資料輸出率（throughput)。其亦可降低線上反射之週期 時間及相鄰信號線間之遠端串音數量，如此在高頻工作時 以保護信號之完整性。此外，其亦可簡化終端之需求。此 終端需求及用於佈線之實際空間之降低，亦可降低所有系 統之成本。以下所述將描述此概念亦可降低複數個電路元 件36、38、40 (圖3c)間之互連長度。 明參照圖3 a，係繪示依據本發明之一較佳實施例之記 憶體次系統30，其包含一記憶體控制器14及一電路元件° 36，及針對DDR SDRAM基礎之記憶體次系統3〇中電路元件 36之區域陣列互連接點32之集中化配置之頂視圖。 Π至少在-表面中包含複數個記憶體裝㈣，可以看到 j數個記憶體裝置28與區域陣列互連接點32接近相等距 離，因此可大幅降低記憶體裝置28與區 間最差情形之佈線距離。依據李m 9益:J互連接點32< 連之特定實現及電路元件與電路元件36間互 可以被放置在比圖3&所示更接、^ =疋’記憶體控制器14 連接點32處。 更接近電路元件36之區域陣列互 兄憶體控制器1 4及區域陣列互連接點3 2其他合適組態525184 V. Description of the invention (π) Transmission delay. The total area required on the system board 12 for the memory controller 14 and the memory module group 16 a interconnect 1 8 a-18 d is about 20 square inches. The matching of the interconnection length between the memory modules 16a to 16d will also occur, which will increase the transmission delay and wiring conflicts. It must be understood that when the frequency is constantly increasing, the length matching of interconnects 18a-18d does not guarantee the normal function of the bus system. This is due to the longer path length along many of the other electrical effects described above. Please refer to FIG. 2 ′, which shows the memory sub-system 3 according to the present invention. The areas between the memory controller 14 and the target memory device 28 (FIG. 3 a) (area array interconnection points 3 and 2 partial buses) Bottom view of the interconnect. The concepts mentioned in the figure can be applied not only to DDR SDRAM, but also to all forms of bus interconnects. The memory controller 4 is interconnected by a plurality of buses 34a-34c Connected to the memory device 28 (Fig. 3a). The memory controller 14 is connected to the system board 12 via an array of BGA solder joints 20 on its bottom 22. The length "μ" of the memory controller 4 is about 1 inch, The size of the device is about 1 square inch. In this case, the length "c" of the area array interconnection point 32 is the same as the length of the memory controller 4. The area array interconnection point 32 is from the system board 12 Many connection methods are allowed to a plurality of circuit elements 36, 38, ^ (Fig. 3c). Including BGA solder joint attachment, pGa attachment and LGA attachment, all possible choices depend on specific design requirements. "Memory Controller The distance between 14 and the area array interconnection point 32 is provided by X Multiple bus interconnects 34a-34c and the area they connect to On page 22, 525184 V. Description of the invention (18) In the case of a single memory module, the worst case of path length is reduced from 2.91 inches to 1.34 inches, which can reduce the dielectric properties in FR4. The path flight time of 283 pS (time -1 0-f 1 y), and in the case of four memory modules, the worst case of path length is even reduced from 3.78 inches to 1.94 inches, This can reduce the path flight time of 349 pS in the FR4 dielectric. Reducing the bus path length can reduce the signal transmission delay, so the data output rate can be increased. It can also reduce the cycle time of the line reflection and adjacent signals The number of far-end crosstalk between the lines, so as to protect the integrity of the signal when working at high frequencies. In addition, it can also simplify the requirements of the terminal. The reduction of the terminal requirements and the actual space used for wiring can also reduce all systems Cost. Following The description will describe that this concept can also reduce the interconnection length between a plurality of circuit elements 36, 38, 40 (FIG. 3c). Referring to FIG. 3a, a memory subsystem according to a preferred embodiment of the present invention is shown. 30, which includes a top view of a memory controller 14 and a circuit element ° 36, and a centralized configuration of the area array interconnection points 32 of the circuit element 36 in the memory sub-system 30 based on DDR SDRAM. Π At least A plurality of memory devices are included in the-surface, and it can be seen that the j memory devices 28 and the area array interconnection point 32 are close to the same distance, so the wiring distance between the memory device 28 and the worst case interval can be greatly reduced. According to Li M 9 Yi: J interconnection point 32 < specific implementation of the connection and the circuit element and circuit element 36 can be placed in more connections than shown in Figure 3, ^ = 疋 'memory controller 14 connection point 32 Office. Area array mutual closer to circuit element 36. Memory controller 14 and area array interconnection point 3 2 Other suitable configurations

525184525184

系統板1 2典型是一種印刷電路板構造，係由環氧基一 玻璃-基（eP〇xy-glass —based)材料所組成（例如，FR4)且 之接點亦可被使用。例如’只要記憶體裝置28與電路元件 36之區域陣列互連接點32間有大的空間，記憶體裝置28亦 可以其他組態方式配置，包括圓形’對稱多邊型，或JL他 較佳之幾何圖形（圖未示）。 /、 如圖3a所示範例中，區域陣列互連接點32之外型非常 類似於&己憶體控制器1 4。如此允許兩個陣列間信號路徑之 最短匹配長度，因為其他設計之考量，外型上不太可能如 此匹配。圖3b繪示另外一種組態，在此範例中，記憶體次 系統30中電路元件36之區域陣列互連接點32，之外型更接 近長方形。雖然區域陣列互連接點32，並非如圖3a之區域 陣列互連接點32具有最佳化外型，但仍然可提供比習知技 術（圖1 )大幅之改良。 現在請參照圖3c，其繪示一斷面圖，係擴大圖3a之較 佳實施例中該複數個電路元件之側視圖。本範例示範可能 技術中許多可能之選擇。記憶體控制器丨4經由系統板丨2之 印刷電路路徑（圖未示）與記憶體裝置28通訊。 包含一或多個導電層（例如，信號，電源及/或接地）在其 中。其他材料可能因為不同理由而被使用，包含電氣效 應，佈線性，及熱效能，但環氧基—玻璃—基材料具有價格 效應（cost-effect ive)且具有熱擴展係數（CTE)以匹配週 遭構造。因為嚴格之電氣規格，信號路徑之阻抗必須與系 統板1 2上相對應路徑之阻抗匹配且誤差只能在百分之十The system board 12 is typically a printed circuit board structure composed of an epoxy-glass-based (ePoxy-glass-based) material (for example, FR4) and its contacts can also be used. For example, 'As long as there is a large space between the area array interconnection points 32 of the memory device 28 and the circuit element 36, the memory device 28 can also be configured in other configurations, including circular' symmetrical polygons, or JL's preferred geometry Graphic (not shown). /. In the example shown in FIG. 3a, the area array interconnection point 32 has an appearance very similar to & This allows the shortest matching length of the signal path between the two arrays, because of other design considerations, it is unlikely to match in this way. Fig. 3b shows another configuration. In this example, the area array interconnection points 32 of the circuit elements 36 in the memory subsystem 30 are closer to a rectangular shape. Although the area array interconnection point 32 is not the optimized shape of the area array interconnection point 32 as shown in Fig. 3a, it can still provide a significant improvement over the conventional technology (Fig. 1). Referring now to FIG. 3c, a cross-sectional view is shown, which is an enlarged side view of the plurality of circuit components in the preferred embodiment of FIG. 3a. This example demonstrates many possible options among possible technologies. The memory controller 4 communicates with the memory device 28 via a printed circuit path (not shown) of the system board 2. Contains one or more conductive layers (eg, signal, power, and / or ground) in it. Other materials may be used for different reasons, including electrical effects, wiring properties, and thermal performance, but epoxy-glass-based materials have a cost-effect ive and a coefficient of thermal expansion (CTE) to match the surroundings structure. Because of strict electrical specifications, the impedance of the signal path must match the impedance of the corresponding path on the system board 12 with an error of only 10%

第24頁 525184 五、發明說明（20) 内。 本實施例包含3個電路元件36、38、40每一個由複數 個記憶體裝置28分別圍繞在中央區域36c、38c、40c所組 成’在較低及較高表面上其包含複數個接點4 2以允許其他 電路元件之互連以及系統板12之連接Q複數個接點42被安 排及互相連接以允許電路元件36、38、40堆疊且不管電路 元件3 6、3 8、4 0在堆疊中之那一位置記憶體裝置2 8皆可正 常工作。 適合互連電路元件之範例包含印刷電路板、電路模組 等。該項“印刷電路板π包含但不侷限是一多層電路板結· 構，其包含一或多個導電層（例如，信號，電源及/或接 地）在其中。此印刷電路板，通常亦稱為印刷佈線板，在 業界是習知以下將不再詳細說明。該“電路模組"表示包 含一基板或類似具有不同電子零件之元件（例如，半導體 晶片，導電電路’導電接腳等等），其可由其中零件所組 成。此模組亦為業界所習知以下將不再詳細說明。 對應於電路元件36、38、40之基板36s、38s、40s可 由非常多種介電材料所組成。在一範例中基板36s、38s、 40 s係由係由典型使用於印刷電路板生產之環氧基-玻璃-籲 基材料所製造，且亦包含一或多個導電層在其中。因為嚴 格之電氣規格，信號路徑阻抗必須與系統阻抗匹配且誤差 只能在百分之十内。這些材料因為其CTE嚴格地匹配週遭 結構（特別是LGA連接器50 )之CTE，並因為它們相對的便宜 因此較為適合。必須瞭解的是本發明中所揭露之技術中不Page 24 525184 V. Description of Invention (20). This embodiment includes 3 circuit elements 36, 38, 40, each of which is composed of a plurality of memory devices 28 surrounding the central areas 36c, 38c, 40c, respectively. 'It contains a plurality of contacts on the lower and higher surfaces 4 2 to allow interconnection of other circuit elements and connection of the system board 12 Q multiple contacts 42 are arranged and interconnected to allow circuit elements 36, 38, 40 to be stacked regardless of circuit elements 3 6, 3 8, 4 0 being stacked Any one of the position memory devices 28 can work normally. Examples of suitable circuit components include printed circuit boards, circuit modules, and the like. The term "printed circuit board π includes, but is not limited to, a multilayer circuit board structure that includes one or more conductive layers (eg, signal, power, and / or ground). This printed circuit board, usually also It is called a printed wiring board, and it is known in the industry. It will not be described in detail below. The "circuit module" means that it contains a substrate or similar components with different electronic parts (for example, semiconductor wafers, conductive circuits, conductive pins, etc. Etc.), which can be composed of parts. This module is also known to the industry and will not be described in detail below. The substrates 36s, 38s, and 40s corresponding to the circuit elements 36, 38, and 40 may be composed of a wide variety of dielectric materials. In one example, the substrates 36s, 38s, and 40s are made of epoxy-glass-based materials typically used in printed circuit board production, and also include one or more conductive layers therein. Because of strict electrical specifications, the signal path impedance must match the system impedance with an error of only ten percent. These materials are suitable because their CTE strictly matches the CTE of the surrounding structure (especially the LGA connector 50), and because they are relatively inexpensive. It must be understood that the technology disclosed in the present invention is not

525184 五、發明說明（21) " " -- 同零件亦可採用不同材料，俾取代前述發明實施例中所揭 露之特定材料，亦不脫離本發明之精神。 f數個記憶體裝置28可以是具有許多附著選擇之已封 裝或是未封裝裝置包含但不侷限於表面黏著（surf ace mounted) ’BGA及佈線結合（wire bond)。必須瞭解的是其 他電子零件’包含但不侷限於電阻器及電容器，將典型的 互連至複數個記憶體裝置28。只是為了說明目的在此它們 並未顯示。 第一個電路元件36具有複數個接腳44連接至其底部表 面之接點42，接腳44是用以***位於外殼（housing) 47之攀 腳座46。在此種情況中腳座46係表面黏著在系統板12相對 應之接點42上。 一接腳44陣列對於需要場地隔離ield separability)，允許電氣不連續，連接之數量及密度是 受到限制的，及一分離的箝板是不允許或不提供之應用是 非常有用的。 第一個電路元件36在其底表面36b包含一選擇性的凸 出中央區域36c，以允許記憶體裝置28及其他元件例如冷 卻結構（圖未示）在不干擾底表面36b互連下具有更多的空_ 間0 第一個電路元件36之上表面36t之接點42經由BGA焊點 48連接至第二個電路元件38底表面38b之接點42。焊點48 是不可重新使用的，但當適當使用時可提供兩平面之表面 間高可靠度互連的方法。第二個電路元件38在其上表面525184 V. Description of the invention (21) " "-Different materials can be used for the same parts, instead of the specific materials disclosed in the aforementioned embodiments of the invention, without departing from the spirit of the invention. The f memory devices 28 may be packaged or unpackaged devices with many attachment options including, but not limited to, surf ace mounted 'BGA and wire bonds. It must be understood that other electronic components ', including but not limited to resistors and capacitors, typically interconnect to a plurality of memory devices 28. They are not shown here for illustrative purposes only. The first circuit element 36 has a plurality of pins 44 connected to the contacts 42 on the bottom surface thereof. The pins 44 are used to be inserted into the climbing base 46 located in a housing 47. In this case, the feet 46 are adhered to the corresponding contacts 42 of the system board 12 on the surface. A pin 44 array is useful for applications that require site isolation (ield separability), allow electrical discontinuities, limit the number and density of connections, and that a separate clamp is not allowed or not provided. The first circuit element 36 includes a selectively protruding central region 36c on its bottom surface 36b to allow the memory device 28 and other components such as a cooling structure (not shown) to have a greater degree without disturbing the interconnection of the bottom surface 36b. A lot of space_ The contact 42 on the upper surface 36t of the first circuit element 36 is connected to the contact 42 on the bottom surface 38b of the second circuit element 38 via the BGA solder joint 48. Solder joints 48 are not reusable, but when used appropriately, they provide a highly reliable method of interconnecting the surfaces of two planes. Second circuit element 38 on its upper surface

第26頁 525184 五、發明說明（22) 38t包含一選擇性的凸出中央區域3 8c以允許記憶體裝置28 及其他元件例如冷卻結構（圖未示）在不干擾上表面38t互 連下有更多之空間。 上表面38t之接點42被除去以允許LGA連接器50經由第 三個電路元件40底表面40b之接點42提供電氣連接至第三 個電路元件40。與PGA連接器相比較，本發明之LGA連接器 50 (特別參考前述申請中之美國專利案）提供效能之改善， 增加密度，較低高度，及與週遭結構較佳匹配之CTE。 此外，因為連接器5 0每個接點所需之力量低，在一定 保留力量下允許接點數量大幅增加。因為保留力量在上述 之腳位及插座型（pin-and-socket)PGA互連中不是固有 的’一箝板機構（圖未示）可被用來創造所需力量以確保每 一接點元件52在使用時被壓縮一適當數量以形成電路元件 38、40上之接點42互連。該箝板可以許多方式被實現。根 據應用所需，電路元件40可以被箝制到電路元件38，至電 路元件36或甚至到系統板12。 在該穩定結構中箝板機構並不需要任何承載孔洞 (mounting holes)是較為適合的，以提供接點元件52之陣 列一控制及一致之代替力量，以避免與CTE不匹配相結合鲁 之問題，及隔離空間以方便使用者之維修及升級。必須注 意的是在一較小之空間中藉由保持互連叢集，該等電路元 件3 8、40之經線（warpage)效應將可最小化。如此將可簡 化設計需求並使箝板之大小及/或成本降低。 電路元件40在其兩上表面40t和底表面4〇b間亦包含一Page 26 525184 V. Description of the invention (22) 38t includes a selectively protruding central area 38c to allow the memory device 28 and other components such as cooling structures (not shown) to be present without interfering with the 38t interconnection on the upper surface. More space. The contact 42 on the upper surface 38t is removed to allow the LGA connector 50 to provide electrical connection to the third circuit element 40 via the contact 42 on the bottom surface 40b of the third circuit element 40. Compared with the PGA connector, the LGA connector 50 of the present invention (especially referring to the US patent in the aforementioned application) provides improved performance, increased density, lower height, and a CTE that better matches the surrounding structure. In addition, because the force required for each contact of the connector 50 is low, the number of contacts allowed to increase significantly with a certain reserve of force. Because the retention force is not inherent in the pin-and-socket PGA interconnection described above, a 'jaw mechanism (not shown) can be used to create the required force to ensure each contact element 52 is compressed in use by an appropriate number to form the interconnections of contacts 42 on the circuit elements 38,40. This jaw can be implemented in many ways. The circuit element 40 can be clamped to the circuit element 38, to the circuit element 36, or even to the system board 12 as required by the application. In this stable structure, the nipper mechanism does not require any mounting holes. It is more suitable to provide an array of control elements 52 and a consistent replacement force to avoid the problem of combining with the CTE mismatch. , And isolated space to facilitate user maintenance and upgrade. It must be noted that by maintaining interconnect clusters in a smaller space, the warpage effect of these circuit elements 38, 40 can be minimized. This will simplify design requirements and reduce the size and / or cost of the jaws. The circuit element 40 also includes a portion between its two upper surfaces 40t and the bottom surface 40b.

第27頁 525184Page 525184

凸Lt九區以允許記憶體裝置28及其他元件例如冷 U(圖未不）在不干擾互連下具有更多的空間。上表面 40t之接點42被壓迫以允許更多之連接。 雖然本實施例中並未特別顯示 40成一排直線（aligning)之裝置， 可以實現之方法。 一用以使電路元件38、 在本技術中已經有許多 電路元件36、38、40可6匕φ a a & ^ ^ 了此更包含熱及電氣導電層54以 改D記憶體次系統各方面之效能。例如，在中央區域 36c、38c、40c可以分別提供較長貫穿孔的保護。 雖然在同一時間所有不同之電路元件及互連選擇在一_ 封裝應用中同時出現並不常見，必須瞭解的是本描述只是 :以揭路之目6¾。该互連使用將視已知應用之特定需求而 ^。例如，如果一應用不需要場地隔離，BGA焊點互連將 ^供堆疊一種最具價格效應及可靠互連之選擇。但如果是 一高速，具有最高電氣整合性之場地隔離設計是需要的， 取代有腳位的，只有LGA連接器（最好是具有包覆）及BGA焊 點互連是可以考慮的。 現在請參照圖3d，其繪示一斷面圖，係擴大圖3c之較 實施例之側視圖，藉由包含其他裝置以提供額外功能。 f此一範例中，其中零件56當成類似電阻之終端零件之功 犯電路元件之複數個阻塞（blocking)電容及/或複數 個去耦合電容（取代前述之美國第6，172, 895號專利案中之 $統板12)，有許多被認知之好處，包括降低互連，節省 二間，及提昇系統之效能。在其他情況中零件5 6可由其他The nine Lt areas are convex to allow the memory device 28 and other components such as cold U (not shown in the figure) to have more space without disturbing the interconnection. The contacts 42 on the upper surface 40t are pressed to allow more connections. Although this embodiment does not specifically show a device aligned in a row of 40, a method that can be implemented. One is used to make the circuit element 38. There are already many circuit elements 36, 38, and 40 in the art. Aa & ^ ^ This also includes a thermal and electrical conductive layer 54 to modify all aspects of the D memory sub-system. Effectiveness. For example, the central regions 36c, 38c, 40c may provide protection for longer through holes, respectively. Although it is not common for all the different circuit components and interconnection options to appear simultaneously in a package application at the same time, it must be understood that this description is only for the purpose of opening the road 6¾. This interconnection use will depend on the specific needs of the known application. For example, if an application does not require site isolation, BGA solder joint interconnects will provide the most cost-effective and reliable interconnection option for stacking. However, if it is a high-speed, site isolation design with the highest electrical integration is required. Instead of pins, only LGA connectors (preferably with cladding) and BGA solder joint interconnections can be considered. Referring now to FIG. 3d, a cross-sectional view is shown, which is an enlarged side view of the comparative embodiment of FIG. 3c, by including other devices to provide additional functions. f In this example, part 56 is used as a plurality of blocking capacitors and / or decoupling capacitors of a power-off circuit component of a terminal component similar to a resistor (replacing the aforementioned US Patent No. 6,172,895 The US $ 12 board has many recognized benefits, including reduced interconnection, saving two rooms, and improving system performance. In other cases parts 5 6 can be made by other

525184 五、發明說明（24) 裝置組成例如一微處理器或一控制器，以便更增強次系統 之效能。 現在請參照圖4 a，其繪示本發明一較佳實施例之一記 憶體次系統6 0之部分頂視圖，其包含一記憶體控制器6 2及 一第一電路元件64，而RAMBUS基礎之記憶體次系統6〇之電 路元件6 4上設有叢集區域陣列接點互連7 〇。該電路元件6 4 在至少一表面上包含複數個記憶體装置58。如圖所示 RAMBUS通道76之路徑經過第一電路元件64之複數個記憶體 裝置58。因為RAMBUS技術與DDR SDRAM之不同，叢集區域· 陣列接點互連70之位置及複數個記憶體裝置58必須被調響 整。 叢集區域陣列接點互連70是由兩個較小之陣列組成： 輸入陣列70a及輸出陣列70b。這些陣列70a及70b被放置在 接近電路元件64的一個邊緣上，其係與圖3c中之DDr SDRAM裝置之情況相反，如此允許與記憶體控制器62之距 離可被最小化。電路元件6 4上每一記憶體裝置5 8及叢集區 域陣列接點互連70間之距離被等化並非關鍵性的。將從輸 入陣列70a及輸出陣列70b至第一及最後之記憶體裝置58間 之路徑長度最小化，無論如何，只要將與記憶體裝置5 8間_ 之路彳泛長度最小化，藉由降低所有之傳輸延遲對記憶體次 系統60之所有效能將提供大幅改善。 現在請參照圖4b，其繪示圖4a之較佳實施例中該複數 個電路元件更緊密結合之頂視圖。這兩個實施例功能上是 等效的。圖4b所示之實施例對空間之使用上更具效率。525184 V. Description of the Invention (24) The device is composed of, for example, a microprocessor or a controller, so as to further enhance the performance of the secondary system. Please refer to FIG. 4a, which shows a partial top view of a memory subsystem 60, which is a preferred embodiment of the present invention, which includes a memory controller 62 and a first circuit element 64. The circuit element 64 of the memory sub-system 60 is provided with a cluster area array contact interconnection 70. The circuit element 6 4 includes a plurality of memory devices 58 on at least one surface. As shown, the path of the RAMBUS channel 76 passes through the plurality of memory devices 58 of the first circuit element 64. Because of the difference between RAMBUS technology and DDR SDRAM, the location of the cluster area array contact 70 and the multiple memory devices 58 must be adjusted. The cluster area array contact interconnect 70 is composed of two smaller arrays: an input array 70a and an output array 70b. These arrays 70a and 70b are placed near one edge of the circuit element 64, which is the opposite of the case of the DDR SDRAM device in Fig. 3c, thus allowing the distance from the memory controller 62 to be minimized. It is not critical that the distance between each memory device 58 and the cluster area array contact interconnect 70 on the circuit element 64 be equalized. The path length from the input array 70a and the output array 70b to the first and last memory device 58 is minimized. In any case, as long as the path length from the memory device 58 to _ is minimized, by reducing All transmission delays will provide a significant improvement in all performance of the memory subsystem 60. Reference is now made to Fig. 4b, which illustrates a top view of the plurality of circuit elements being tightly coupled in the preferred embodiment of Fig. 4a. These two embodiments are functionally equivalent. The embodiment shown in Figure 4b is more efficient in the use of space.

第29頁 525184 五、發明說明（25) ' "" ^ 現在請參照圖4c，其繪示根據圖4a之較佳實施例之一 記憶體，系統60,之部份頂視圖，其包含一記憶體控制器 62及一第一電路元件64，。該RAMBUS基礎之記憶體次系統 6〇之電路元件64’的區域陣列接點互連70,被置於中央， 並視為圖4a所示實施例之延伸。該電路元件64，在一表面 上至少包含大量之記憶體裝置58。如圖所示RAMBUS通道76 之路控經過第一電路元件64，之複數個記憶體裝置58。因 為RAMBUS技術與DDR SDRAM之不同，叢集區域陣列接點互 連70之位置及複數個記憶體裝置58必須被調整。 叢集區域陣列接點互連7 〇 ’是由兩個較小之陣列組 成：輸入陣列70a’及輸出陣列7〇b，。這些陣列70a，及70b， 被放置但接近邊緣的一端，其係與圖3C中之ddr SDRAM裝 置之情況相反，如此允許與記憶體控制器6 2之距離可被最 小化。電路元件64’上每一記憶體裝置58及叢集區域陣列 接點互連7 0 ’間之距離被等化並非關鍵性的。將從輸入陣 列7 0a’及輸出陣列70b’至第一及最後之記憶體裝置58間之 路徑長度最小化，無論如何，只要將與記憶體裝置5 8間之 路徑長度最小化，藉由降低所有之傳輸延遲對記憶體次系 統6 0 ’之所有效能將提供大幅改善。 現在請參照圖4d，其繪示出一斷面圖，係擴大圖4a之 較佳實施例中該複數個電路元件之侧視圖；及圖4e繪示出 圖4d之RAMBUS通道76通過不同元件之路徑示意圖。RAMBUS 記憶體次系統60之記憶體控制器62是包含一直接RAMBUS時 脈產生器（1)1^0)電路6 23及一包含直接1^%61^細胞（1)1^(：)Page 29, 525184 V. Description of the invention (25) '" " ^ Please refer to FIG. 4c, which illustrates a top view of a part of the memory, system 60, according to one of the preferred embodiments of FIG. 4a, which includes A memory controller 62 and a first circuit element 64. The area array contact interconnects 70 of the circuit elements 64 'of the RAMBUS-based memory subsystem 60 are placed in the center and considered as an extension of the embodiment shown in Fig. 4a. The circuit element 64 includes at least a large number of memory devices 58 on one surface. As shown in the figure, the road control of the RAMBUS channel 76 passes through the first circuit element 64 and a plurality of memory devices 58. Because of the difference between RAMBUS technology and DDR SDRAM, the position of the cluster area array contact 70 and the plurality of memory devices 58 must be adjusted. The cluster area array contact interconnection 70 'is composed of two smaller arrays: an input array 70a' and an output array 70b. These arrays 70a, and 70b are placed at one end near the edge, which is the opposite of the case of the ddr SDRAM device in FIG. 3C, which allows the distance from the memory controller 62 to be minimized. It is not critical that the distance between each memory device 58 on the circuit element 64 'and the cluster area array contact interconnect 70' is equalized. The path length from the input array 70a 'and the output array 70b' to the first and last memory devices 58 is minimized. In any case, as long as the path length from the memory devices 58 to 8 is minimized, by reducing All transmission delays will provide a significant improvement in all performance of the memory subsystem 60 '. Please refer to FIG. 4d, which illustrates a cross-sectional view, which is an enlarged side view of the plurality of circuit components in the preferred embodiment of FIG. 4a; and FIG. 4e illustrates the RAMBUS channel 76 of FIG. 4d through different components. Schematic diagram of the path. The memory controller 62 of the RAMBUS memory subsystem 60 includes a direct RAMBUS clock generator (1) 1 ^ 0) circuit 6 23 and a direct 1 ^% 61 ^ cell (1) 1 ^ (:)

第30頁 525184 五、發明說明（26) 之一主裝置62b在系統板12上所實現。在RAMBUS記憶體次 系統60中資料路徑係由記憶體控制器62開始並經過次系統 60之每一個電路元件直到最後到達一匯流排終端74(請參 照圖4e) ’該匯流排終端74可以被放置在系統板12之後或 路徑上最後一個電路元件上。 藉由小心地配置RAMBUS不同之信號、電源、及接地連 接至特定接點42，在一已知之記憶體數量（例如是256MB) 中簡單地藉由將堆疊中每一不同電路元件垂直反向連接以 創造單一電路元件部件號碼是可能的。如此允許一電路元I 件中輸出陣列70b之接點42被垂直地放置在堆疊中下一個^ 電路元件之輸入陣列70a之下且反之亦然。只要區域陣列 接點互連70接點42之組態不變，此觀念亦允許其他具有不 同數量記憶體之電路元件在堆疊中被使用。 請再次參照圖4 d，本範例再次示範可能之技術選擇中 之一些可能的選擇並包含三個電路元件64、66、68。記憶 體控制器62藉由系統板1 2中之印刷電路板（圖未示）與記憶 體裝置58通訊。再者，因為高速匯流排系統嚴格之電氣規 格，信號路徑必須與系統之阻抗匹配且誤差只能在百分之 十内。 j 每一電路元件64、66及68包含複數個記憶體裝置58分 別圍繞在中央區域64c、66c及68c，在較低及較高表面上 其包含複數個接點42以允許與其他電路元件及系統板丨2之 互連。接點4 2被安排及互連以允許堆疊及在堆疊中無論電 路元件64、66及68中之位置為何記憶體裝置58皆可正常工Page 30 525184 V. Invention Description (26) One of the main devices 62b is implemented on the system board 12. In the RAMBUS memory subsystem 60, the data path starts from the memory controller 62 and passes through each circuit element of the subsystem 60 until it finally reaches a bus terminal 74 (please refer to FIG. 4e). Placed after the system board 12 or on the last circuit element on the path. By carefully configuring the different signals, power, and ground connections of the RAMBUS to specific contacts 42, in a known amount of memory (for example, 256MB), simply by vertically reversing each different circuit element in the stack It is possible to create a single circuit element part number. This allows the contacts 42 of the output array 70b in a circuit element I to be placed vertically below the input array 70a of the next circuit element in the stack and vice versa. This concept also allows other circuit elements with different amounts of memory to be used in the stack, as long as the configuration of the area array contact interconnection 70 contact 42 is unchanged. Please refer to FIG. 4d again, this example demonstrates again some of the possible technical options and includes three circuit elements 64, 66, 68. The memory controller 62 communicates with the memory device 58 through a printed circuit board (not shown) in the system board 12. Furthermore, because of the strict electrical specifications of the high-speed bus system, the signal path must match the impedance of the system and the error can only be within 10%. j Each circuit element 64, 66, and 68 includes a plurality of memory devices 58 surrounding the central regions 64c, 66c, and 68c, respectively. On the lower and upper surfaces, it includes a plurality of contacts 42 to allow communication with other circuit elements and Interconnection of the system board 丨 2. The contacts 4 2 are arranged and interconnected to allow the stack and the memory device 58 to work normally regardless of the position of the circuit elements 64, 66, and 68 in the stack.

第31頁Page 31

525184 五、發明說明（27) 作0 電路元件64、66及68相對應之基板64s、66s及68s可 由非常多種介電材料組成。在一範例中基板64s、66s及 68s係由典型使用於印刷電路板生產之環氧基—玻璃-基材 料所製造，且亦包含一或多個導電層在其中。因為嚴格之 電氣規格，信號路徑阻抗必須與系統阻抗匹配且誤差只能 在預先決定之範圍内。這些材料因為其CTE嚴格地匹配週 遭結構（特別是LGA連接器72)之CTE且因為它們相對的便宜 因此較適合。再者，其他可能之材料是聚亞胺 (po1y i m i de )。 · 吞己憶體裝置58可以是具有許多附著選擇之已封裝或是 未封裝裝置包含但不侷限於表面黏著。“。“ mounted)，BGA及佈線結合（wire b〇nd)。其他電子零件， 例如電阻及電容，將典型的互連至複數個記憶體裝置5 8。 如圖所示第一電路元件64在底表面64b之輸入陣列7〇a 具有複數個接點42，俾允許經由相對應之lga連接器72之 複數個接點52以電性連接至系統板12之接點42。對於這個 範例可以看到LGA連接器72之複數個接點52亦被分割以匹 配在輸入陣列70a及輸出陣列7〇1)中接點42之位置。第一電_ 路兀件64在其兩上表面64t和底表面64b間包含一凸出中央 區域64c以允許記憶體裝置58及其他元件例如冷卻結構（圖 未示）在不干擾互連下有更多的空間。 第一電路元件64在上表面64t之輸出陣列70b的接點42 被設置以允許其他LGA連接器72經由第二電路元件66在上525184 V. Description of the invention (27) The substrates 64s, 66s, and 68s corresponding to the circuit components 64, 66, and 68 can be composed of a variety of dielectric materials. In one example, the substrates 64s, 66s, and 68s are made of epoxy-glass-base materials typically used in printed circuit board production, and also include one or more conductive layers therein. Because of strict electrical specifications, the signal path impedance must match the system impedance and the error can only be within a predetermined range. These materials are suitable because their CTE strictly matches the CTE of the surrounding structure (especially the LGA connector 72) and because they are relatively inexpensive. Furthermore, other possible materials are polyimide (po1y i m i de). The memory device 58 can be a packaged or unpackaged device with many attachment options including but not limited to surface adhesion. "." Mounted), BGA and wire bonding. Other electronic components, such as resistors and capacitors, are typically interconnected to a plurality of memory devices 58. As shown in the figure, the input array 70a of the first circuit element 64 on the bottom surface 64b has a plurality of contacts 42, and allows electrical connection to the system board 12 through the plurality of contacts 52 of the corresponding lga connector 72.之 接点 42。 Contact 42. For this example, it can be seen that the plurality of contacts 52 of the LGA connector 72 are also divided to match the positions of the contacts 42 in the input array 70a and the output array 701). The first electrical circuit element 64 includes a protruding central area 64c between its two upper surfaces 64t and the bottom surface 64b to allow the memory device 58 and other components such as a cooling structure (not shown) to More space. The contacts 42 of the output array 70b of the first circuit element 64 on the upper surface 64t are provided to allow other LGA connectors 72 to pass above the second circuit element 66.

第32頁 525184 五、發明說明（28) 表面66ΐ之輸入陣列7〇a的接點42提供電氣連接。需注意的 是連接到電路元件66之上表面而非底表面，因此在具有單 一設計中電路元件6 6被垂直旋轉以取得適當信號路徑。 再者，因為保留力量在上述第一實施例中（請參照圖 3c)之腳位及插座型（pin — and-socket)型互連中不是固有 的’一箝板機構（圖未示）可被用來創造所需力量以確保每 一LGA連接器72之接點元件5 2在使用時被壓縮一適當數量 以形成電路元件6 4、6 6上之接點4 2互連。該箝板可以許多 方式被實現。第二電路元件66在其兩上表面66t和底表面 66b間包含一凸出中央區域66c，以允許記憶體裝置58及其鲁 他元件例如冷卻結構（圖未示）在不干擾互連下有更多的空 間。 第二電路元件66在上表面66b之輸出陣列7〇b的接點42 經由一BGA焊點48被連接至第三電路元件68之輸入陣列7〇a 的接點42。第三電路元件68在其上表面68t和底表面68b間 包含一凸出中央區域6 8c，以允許記憶體裝置58及其他元 件例如冷卻結構（圖未示）在不干擾互連下有更多的空間。 上表面68ΐ之輸出陣列70b的接點42被設置以允許更多連 接。 · 如上所述，一RAMBUS基礎次系統6〇需要一匯流排終端 7 4 (請參照圖4 e )跟在路徑中最後一個記憶體裝置5 8之後。 如果匯流排終端74被放置在電路元件68(請參照圖4e)或一 外加只有終端（only-termination)之模組（圖未示）時，則 只需要一半之互連。另一半之互連可以被省略，以支援一Page 32 525184 V. Description of the invention (28) The contact 42 of the input array 70a of the surface 66A provides electrical connection. It should be noted that the circuit element 66 is connected to the upper surface and not the bottom surface, so in a single design, the circuit element 66 is rotated vertically to obtain a proper signal path. In addition, because the reserve force is not inherent in the pin-and-socket type interconnection in the first embodiment (see FIG. 3c), a “nipper mechanism (not shown)” may be used. It is used to create the necessary force to ensure that the contact elements 52 of each LGA connector 72 are compressed to an appropriate number when in use to form the contact 4 2 interconnects on the circuit elements 64, 66. This jaw can be implemented in many ways. The second circuit element 66 includes a protruding central area 66c between its two upper surfaces 66t and the bottom surface 66b to allow the memory device 58 and other components such as a cooling structure (not shown) to More space. The contacts 42 of the output array 70b of the second circuit element 66 on the upper surface 66b are connected to the contacts 42 of the input array 70a of the third circuit element 68 via a BGA pad 48. The third circuit element 68 includes a protruding central region 68c between the upper surface 68t and the bottom surface 68b thereof to allow the memory device 58 and other components such as a cooling structure (not shown) to have more without interfering with the interconnection. Space. The contacts 42 of the output array 70b on the upper surface 68 'are provided to allow more connections. · As mentioned above, a RAMBUS basic subsystem 60 requires a bus terminal 74 (see FIG. 4e) to follow the last memory device 58 in the path. If the bus terminal 74 is placed on the circuit element 68 (refer to FIG. 4e) or an additional only-termination module (not shown), only half of the interconnection is required. The other half of the interconnect can be omitted to support one

第33頁 525184 五、發明說明（29) 第二記憶體通道，或提供系統板丨2之回返路徑以到達最後 之匯流排終端74。此外，在接近匯流排終端以處亦包含一 電壓調節模組及複數個去耦合電容（兩者皆圖未示）以改善 電氣效能。 如圖所示，雖然DRCG電路62a(請參照第4d及4e圖）為 了揭露的目的被放置在系統板1 2中，它可以被更最佳化地 被放置在其他位置，例如放在具有自我—終端之電路元件 68(明參照圖4e)或其他外加只有終端（oniy — terininati〇n) 之模組（圖未示）中。DRCG電路62a產生一差動時脈對 (differential clock pair)，其行進與次系統60中所有 其它信號係為相反方向。 信號衰減會沿著所有RAMBUS通道的路徑發生，尤其在 連接器上。可以看到的是，與一般RAMBUs基礎次系統相比 較’本發明之記憶體次系統6 〇之所有匯流排路徑長度及所 有之傳輸延遲將被大幅降低。一般而言，藉由改良RAMBUS 通道之品質（即降低長度、通道延遲、串音等等）可以得到 較高之記憶體存取速度。此降低之路徑長度，可以減少介 於複數個記憶體卡及模組上終端間之腳位及插座型連接器 數量，並大幅改善電氣整合性。 雖然本實施例中並未特別顯示一用以使系統板丨2中電 路元件64、66、68成一排直線（al i gning)之裝置，然而在 本技藝中已經有許多可以實現的方法。 電路元件64、66、68可以更包含熱及電氣導電層54以 改善記憶體次系統各方面之效能。例如，在中央區域Page 33 525184 V. Description of the invention (29) The second memory channel, or provides a return path for the system board 2 to reach the final bus terminal 74. In addition, a voltage regulation module and a plurality of decoupling capacitors (both are not shown) are included near the bus terminal to improve electrical performance. As shown in the figure, although the DRCG circuit 62a (refer to Figures 4d and 4e) is placed in the system board 12 for the purpose of disclosure, it can be more optimally placed in other locations, such as the —The circuit element 68 of the terminal (refer to FIG. 4e) or other modules (not shown) with only terminals (oniy — terinination). The DRCG circuit 62a generates a differential clock pair, which travels in the opposite direction to all other signals in the sub-system 60. Signal attenuation occurs along the path of all RAMBUS channels, especially on the connector. It can be seen that all bus path lengths and all transmission delays of the memory sub-system 600 of the present invention will be greatly reduced compared with the general RAMBUs base sub-system. Generally speaking, by improving the quality of the RAMBUS channel (ie reducing the length, channel delay, crosstalk, etc.), a higher memory access speed can be obtained. This reduced path length can reduce the number of pins and socket-type connectors between terminals on multiple memory cards and modules, and greatly improve electrical integration. Although this embodiment does not specifically show a device for making the circuit elements 64, 66, and 68 in the system board 2 a line, there are many methods that can be implemented in this technology. The circuit elements 64, 66, 68 may further include a thermal and electrical conductive layer 54 to improve the performance of various aspects of the memory subsystem. For example, in the central area

第34頁 525184Page 525184

64c、66c、68c可以分別提供較長貫孔之保護。64c, 66c, 68c can provide protection for longer through holes, respectively.

因為在記憶體裝置28、58之晶片或封裂至 :有效之熱轉移介質及在氣流之方向中(即與系：板;2缺平乏 仃）缺乏一紐空氣通道使記憶體次系統3〇、6〇之自然 (natural)冷卻係數是低的。今日相對大之記憶體g置 28、58及在此封裝中接近其他熱產生記憶體裝置28、58使 冷卻問題更被加重。熱管理結構59可能被包含在本發明之 系統中以使熱傳導及輻射最佳化，如此允許不需熱建立 (build-up)即有最大電路密度，該熱建立會降低=憶體裝 置28、58之效能及可靠度。熱管理結構59之—個; 在圖4d中。 熱管理結構59企圖從記憶體裝置28、58吸熱且可以呼 多方式被實現。它們可能是簡單的一層熱傳導^料，例^ 鋁，藉由熱增強混合或箝板附著至記憶體裝置28、58。兮 熱管理結構59可能更複雜且包含例如鰭狀物以增強散熱。 其他方式可能包含使用'一致的液癌熱轉移材料小袋體， 薄的散熱管，及熱電氣裝置。其他解決散熱問題之方法在 本技藝中將是顯而易見的。 現在請參照圖4 f ’其、纟會不第4 a - 4 c圖之實施例之另— 種組態。對於這些需要更高記憶體次系統輸出率之應用， 一位系統設計者可能包含複數個記憶體通道。在圖4 f中顯 示一RAMBUS基礎之電路元件80之頂視圖，其包括一第_ $ 憶體通道82，一第二記憶體通道82’ ，在至少一表面上乂 有複數個記憶體裝置58，及區域陣列接點互連84之集中/化Because the chips in the memory devices 28 and 58 are cracked to: an effective heat transfer medium and in the direction of the air flow (ie, the system: the board; 2 lack of flatness and lack of air) makes the memory subsystem 3 The natural cooling coefficients of 0 and 60 are low. Today's relatively large memory devices 28, 58 and close to other heat-generating memory devices 28, 58 in this package exacerbate the cooling problem. The thermal management structure 59 may be included in the system of the present invention to optimize heat conduction and radiation, thus allowing maximum circuit density without thermal build-up, which will be reduced = memory device 28, 58 performance and reliability. One of the thermal management structures 59; in Figure 4d. The thermal management structure 59 attempts to absorb heat from the memory devices 28, 58 and can be implemented in multiple ways. They may be a simple layer of thermally conductive material, such as aluminum, attached to the memory devices 28, 58 by thermally enhanced mixing or clamps. The thermal management structure 59 may be more complex and include, for example, fins to enhance heat dissipation. Other approaches may include the use of 'consistent liquid cancer heat transfer material pouches, thin heat pipes, and thermoelectric devices. Other solutions to heat dissipation problems will be apparent in the art. Please refer to FIG. 4 f ′, which is another configuration of the embodiment of FIGS. 4 a-4 c. For applications that require higher memory subsystem output rates, a system designer may include multiple memory channels. A top view of a RAMBUS-based circuit element 80 is shown in FIG. 4F, which includes a first memory channel 82, a second memory channel 82 ', and a plurality of memory devices 58 on at least one surface. And centralization / localization of area array contact interconnection 84

525184 五、發明說明（31) 配置。亦顯示出該RAM BUS通道8 6及8 6’之路徑經過第一電 路元件80之複數個記憶體裝置58。 區域陣列接點互連8 4係由四個較小之陣列所組成，輸 入陣列84a及84a’及輸出陣列84b及84b，，這些小陣列被放525184 V. Description of the invention (31) Configuration. It is also shown that the paths of the RAM BUS channels 86 and 86 'pass through the plurality of memory devices 58 of the first circuit element 80. The area array contact interconnection 8 4 is composed of four smaller arrays, the input arrays 84a and 84a 'and the output arrays 84b and 84b. These small arrays are placed

置在較接近電路元件80之中央部分。電路元件go上每一記 憶體裝置5 8及叢集區域陣列接點互連8 4間之距離被等化並 非疋關鍵性的。將從輸入陣列8 4 a及8 4 a ’及輪出陣列8 4 b及 84b’至第一及最後之記憶體裝置58間之路徑長度最小化， 無論如何，只要將與記憶體裝置58間之路徑長度最小化， 藉由降低所有之傳輸延遲對記憶體次系統（圖未示）之所有 效能將提供大幅改善。 之數量 圖。電 RAMBUS 道92， 數量之 配置。 元件90 每個係 及輸出 件90之It is located closer to the center of the circuit element 80. It is not critical that the distance between each memory device 58 on the circuit element go and the cluster area array contact interconnections 84 be equalized. The path lengths from the input arrays 8 4 a and 8 4 a ′ and the round-out arrays 8 4 b and 84 b ′ to the first and last memory devices 58 are minimized. The path length is minimized, and all performance of the memory subsystem (not shown) will be greatly improved by reducing all transmission delays. Number of figures. The number of RAMBUS channels 92 is configured. Element 90 and each output 90

在睛參照圖4 g，其繪示圖4 f所示之實施例中當裝 是少的（例如每個通道是兩個或四個）時之延伸示 路元件之所有尺寸也變得較小，在圖4g中顯示一 基礎電路元件90之頂視圖，其包括一第一記憶體: =第二記憶體通道92，，在至少一表面上具有^較少 記憶體裝置58，及區域陣列接點互連94及96之叢 亦顯示出RAMBUS通道98及98,之路徑經過第一雷於 之複數個記憶體裝置58。區㈣列接//連94電；； 由兩個較小之陣列所組成，如輸入陣列94a及943, 陣列96b及9 6b’ ，這些小陣列被放置在第一電天 相反邊緣部分。 本範例 彼此互鄰， 示範前述實施例之叢集。輸入陣列94a及94a, 輸出陣列96b及96b，亦彼此互鄰。但是因為電Referring to Fig. 4g, which shows the embodiment shown in Fig. 4f when the installation is small (for example, each channel is two or four), all the dimensions of the extended path element also become smaller. A top view of a basic circuit element 90 is shown in FIG. 4g, which includes a first memory: a second memory channel 92, which has at least one surface with fewer memory devices 58, and an area array interface. The clusters of the dot interconnects 94 and 96 also show the RAMBUS channels 98 and 98, the path of which passes through the first memory device 58. The zone array is connected // connected with 94 electrical power; It is composed of two smaller arrays, such as input arrays 94a and 943, arrays 96b and 96b '. These small arrays are placed on the opposite edge of the first electrical day. This example is adjacent to each other and demonstrates the clustering of the foregoing embodiments. The input arrays 94a and 94a and the output arrays 96b and 96b are also adjacent to each other. But because of electricity

525184 五、發明說明（32) 路元件90與先前描述由許多記憶體裝置58所組成之電路元 件相比是非常小，較大電路元件所需考慮之DNp及CTE將不 再疋一個議題’因此並不需要四個陣列。此分離之輸入及 輸出陣列9 4及9 6提供電路元件9 〇在不影響機構穩定度的情 況下改良之佈線能力。 雖然上述實施例之實施為了揭露的目的顯示記憶體裝 置具有三個電路元件，可以明顯得知的是複數個參數例如 數量’特定外型’尺寸大小，及卡的材料，複數個記憶體 裝置之佈局及封裝將視特定之需求而改變。這些形之 化亦在本發明保護之範疇内。 一 _ 此外 了揭露的 之準則不 用於多種 這些包含 礎之應用 在前 施例而說 行不同之 與附圖係 雖然 限定本發 神和範圍 護範圍當 ，當DDR SDRAM-及RAMBUS-基礎記憶體次系統為 目的而被選擇，可以明顯得知的是本發明所教導 只可，應用於其他高速記憶體次系統，亦可被應 其他高速，阻抗控制匯流排資料次系統及應用。 但不限於微處理器，數位信號處理器，及通訊基 及次系統，及其他以上所揭露之應用。 述說明書中，本發明參照了特定示範性之具體實 明，但明顯地在不背離本發明之 修正與變動，如申嗜衰剎銘m ^ 作為參考而非限Γ 所示。目此說明書( 二發:月已以較佳實施例揭露如上，然其並非用以 内’ 習此項技藝者，☆不脫離本發明之精 田可作少許之更動與潤飾，因此本發明之保 視後附之申請專利範圍所界定者為準。525184 V. Description of the invention (32) The circuit element 90 is very small compared with the circuit element composed of many memory devices 58 described previously. The DNp and CTE for larger circuit elements will no longer be an issue. There is no need for four arrays. The separate input and output arrays 94 and 96 provide circuit elements 9 0 with improved wiring capabilities without affecting the stability of the mechanism. Although the implementation of the above embodiment shows that the memory device has three circuit elements for the purpose of disclosure, it can be clearly known that a plurality of parameters such as the quantity 'specific appearance' size and the material of the card, the plurality of memory devices The layout and packaging will change according to specific needs. These modifications are also within the scope of the present invention. _ In addition, the disclosed principles are not used for a variety of these inclusive applications. They are different from the previous examples. Although the drawings are limited in scope and scope, when DDR SDRAM- and RAMBUS-based memory The secondary system was selected for the purpose. It is obvious that the teaching of the present invention can only be applied to other high-speed memory secondary systems, and can also be applied to other high-speed, impedance-controlled bus data secondary systems and applications. But it is not limited to microprocessors, digital signal processors, and communication based and sub-systems, and other applications disclosed above. In the description, the present invention refers to specific exemplified concrete explanations, but obviously does not deviate from the amendments and changes of the present invention, as shown in the application of the malignant decay m ^ m ^ as a reference rather than limitation Γ. This description (Second issue: The month has been disclosed as above with a preferred embodiment, but it is not intended to be used for this skill. ☆ Without leaving the fine field of the present invention, you can make a few changes and retouching, so Subject to the scope of the attached patent application.

525184 五、發明說明（33) --*- 【圖式簡單說明】 圖1是一習知技藝中記憶體控制器裝置及一複數個記 憶體模組在記憶體次系統安排之匯流排互連之示意圖。 圖2是記憶體控制器裝置與目標裝置之區域陣列接點 之匯流排互連之底視圖。 # 圖3a是本發明一較佳實施例之一DDR sdraM基礎之記 憶體次系統其電路元件區域陣列接點互連之集中化配置之 頂視圖。 圖3b是圖3a中本發明一較佳實施例之一 DDR SDRAM基 礎之a己憶體次系統其電路元件區域陣列接點互連之另一組_ 態之頂視圖。 ^ 圖3c是一斷面圖，係擴大圖3a之較佳實施例中該複數 個電路元件之側視圖。 圖3d是一斷面圖，係擴大圖3c之較佳實施例之側視圖 藉由包含其他裝置以提供額外功能。 圖4a是本發明一較佳實施例之一RAMBUS基礎之記憶體 次系統其電路元件區域陣列接點互連之集中化配置修正後 之頂視圖。 圖4b是圖4a之較佳實施例中該複數個電路元件更緊密鲁 結合之頂視圖。 圖4c是根據圖4a之較佳實施例之一RAMBUs基礎之記憶 體次系統其電路元件區域陣列接點互連之集中化配置修正 後之頂視圖。 圖4d是一斷面圖，係擴大圖4a之較佳實施例中該複數525184 V. Description of the invention (33)-*-[Brief description of the diagram] Figure 1 is a bus interconnecting arrangement of a memory controller device and a plurality of memory modules in a memory subsystem in a conventional technique The schematic. Figure 2 is a bottom view of the bus interconnects of the area array contacts of the memory controller device and the target device. # FIG. 3a is a top view of a centralized configuration of circuit element area array contact interconnections of a DDR sdraM-based memory system according to a preferred embodiment of the present invention. FIG. 3b is a top view of another set of states of the circuit element area array contacts of a memory system based on a DDR SDRAM based on a preferred embodiment of the present invention in FIG. 3a. ^ Fig. 3c is a sectional view showing an enlarged side view of the plurality of circuit elements in the preferred embodiment of Fig. 3a. Fig. 3d is a cross-sectional view, which is an enlarged side view of the preferred embodiment of Fig. 3c, by including other devices to provide additional functions. FIG. 4a is a top view of a RAMBUS-based memory sub-system according to a preferred embodiment of the present invention, in which the centralized configuration of the interconnection of the circuit element area array contacts is modified. Fig. 4b is a top view of the plurality of circuit elements in the preferred embodiment of Fig. 4a being more tightly coupled. Fig. 4c is a top view of a modified, centralized arrangement of circuit element area array contact interconnections of a RAMBUs-based memory sub-system according to one of the preferred embodiments of Fig. 4a, after modification. Fig. 4d is a cross-sectional view, which is an enlarged view of the complex number in the preferred embodiment of Fig. 4a

第38頁 525184 五、發明說明（34) 個電路元件之側視圖。 圖4e是顯示圖4d之較佳實施例中RAMBUS通道之路徑示 意圖。 圖4f顯示圖4a至圖4c之較佳實施例中RAMBUS基礎記憶 體次系統之另一種組態之頂視圖。 圖4g顯示圖4f之較佳實施例中RAMBUS基礎記憶體次系 統之另一種組態之頂視圖。 【圖式元件標號說明】 記憶體次系統 10 系統板 12 記憶體控制器 14 記憶體模組 16a-16d 匯流排互連 1 8 a -1 8 d BGA焊點 20 底部 22 接點 24 記憶體裝置 28 記憶體次系統 30 區域陣列互連接點 匯流排互連 電路元件 底表面 中央區域 基板 上表面 32、32， 34a-34c 36 H 40 36b、38b、40b 36c " 38c ^ 40c 36s '38s ^40s 36t ^ 38t - 40t 接點 42 接腳 44 腳座 46 外殼 4 7 BGA焊點 48 LGA連接器 50 接點元件 52 電氣導電層 54Page 38 525184 V. Description of the invention (34) Side view of circuit components. Fig. 4e is a schematic diagram showing the path of the RAMBUS channel in the preferred embodiment of Fig. 4d. Fig. 4f shows a top view of another configuration of the RAMBUS base memory subsystem in the preferred embodiment of Figs. 4a to 4c. Figure 4g shows a top view of another configuration of the RAMBUS base memory subsystem in the preferred embodiment of Figure 4f. [Illustration of component numbers of diagrams] Memory sub-system 10 System board 12 Memory controller 14 Memory modules 16a-16d Bus interconnect 1 8 a -1 8 d BGA solder joint 20 Bottom 22 Contact 24 Memory device 28 Memory Subsystem 30 Area Array Interconnection Point Bus Interconnect Circuit Components Bottom Surface Central Area Substrate Upper Surface 32, 32, 34a-34c 36 H 40 36b, 38b, 40b 36c " 38c ^ 40c 36s' 38s ^ 40s 36t ^ 38t-40t Contacts 42 Pins 44 Pins 46 Housings 4 7 BGA Solder Joints 48 LGA Connectors 50 Contact Elements 52 Electrically Conductive Layers 54

第39頁 525184 五、發明說明（35) 零件 56 記憶體裝置 58 熱管理結構 59 記憶體次系統 60 >60, 記憶體控制器 62 時脈產生器電路 62a 主裝置 62b 電路元件 64 、 64’ 、 66 、 68 底表面 64b 、 66b 、 68b 中央區域 64c ' 66c ^ 68c 基板 64s ^ 66s - 68s 上表面 641、66t、68t 叢集區域陣列接點互連 70 > 70’ 輸入陣列 70a 、 70a’ 輸出陣列 70b 、 70b’ LGA連接器 72 匯流排終端 74 RAMBUS通道 76 電路元件 80 第一記憶體通道 82 第二記憶體通道 82J 區域陣列接點互連 84 輸入陣列 84a 、 84a’ 輸出陣列 84b 、 84b’ RAMBUS通道 86 ^ 86? 電路元件 90 第一記憶體通道 92 第二記憶體通道 92J 區域陣列接點互連 94、96 輸入陣列 94a 、 94a’ 輸出陣列 96b 、 96b’Page 39 525184 V. Description of the invention (35) Parts 56 Memory device 58 Thermal management structure 59 Memory subsystem 60 > 60, Memory controller 62 Clock generator circuit 62a Main device 62b Circuit elements 64, 64 ' , 66, 68 bottom surface 64b, 66b, 68b central area 64c '66c ^ 68c substrate 64s ^ 66s-68s upper surface 641, 66t, 68t cluster area array contact interconnection 70 > 70' input array 70a, 70a 'output Array 70b, 70b 'LGA connector 72 Bus terminal 74 RAMBUS channel 76 Circuit element 80 First memory channel 82 Second memory channel 82J Area array contact interconnection 84 Input array 84a, 84a' Output array 84b, 84b ' RAMBUS channel 86 ^ 86? Circuit element 90 first memory channel 92 second memory channel 92J area array contact interconnection 94, 96 input array 94a, 94a 'output array 96b, 96b'

第40頁 525184Page 525184

第41頁Page 41

Claims (1)

525184 六、申請專利範圍 1· 一種可堆疊電子模組，其包括： a) —基板，具有一第一本 行之一第二表面； 表面及實質上與該第一表面平 b) 在一第一二維式樣中山 -式樣設置在該基板的第：：；數個電氣接點組成之-第 外接匯流排； |面上’並可合調地以連接一 c )複數個電氣連接裝晋 點組成之第-式樣，以形成，：有效地連接至該等電氣接 複數個裝置，係流排之擴充；以及 二表面之至少一表面上該第一表面及該第I 外接匯流排之擴充；違等裝置可選擇性地被連接至該 一式樣 2·如 中該外接 3. 如 更包含複 流排之擴 該特徵阻 4. 如 中該等匯 複數個電 5 ·如 中該等電 =中該等裝置被設置在緊鄰該等電氣接點組成之該第 申請專利範 匯流排包括 申請專利範 數個匯流排 充，該等匯 抗。 申睛專利範 流排終端裝 @ ’複數個 申請專利範 阻係由複數 圍第1項所述之可堆疊電子模組，其 一特徵阻抗。 圍第2項所述之可堆疊電子模組，其 終端裴置，俾有效地連接至該外接匯 流排終端裝置顯示一阻抗實質上匹配 圍第3項所述之可堆疊電子模組，其 置包含下列群組之至少一電氣零件·· 電容及複數個電感。 圍第4項所述之可堆疊電子模組，其 個分散式電阻所組成。 ’、525184 6. Scope of patent application 1. A stackable electronic module includes: a) a substrate having a first surface and a second surface; a surface and a surface substantially parallel to the first surface b) a first A two-dimensional style Zhongshan-the style is arranged on the base of the base plate ::; a number of electrical contacts-the first external bus; the surface can be adjusted to connect a c) a plurality of electrical connection points The first pattern of the composition is formed to: effectively connect to the plurality of electrical devices, expand the bus; and expand the first surface and the first external bus on at least one of the two surfaces; Illegal devices can be selectively connected to the pattern 2. If the external connection 3. If the expansion resistors are included, the characteristic resistance 4. If the middle and multiple electricity 5 • If the middle == middle These devices are arranged next to the first patent application bus composed of the electrical contacts, including a number of patent application patent buses, and these exchange reactances. Shenyan patent range 排 Terminal mounting @ 复 Multiple patent applications The resistance is a stackable electronic module as described in item 1 above, one of the characteristic impedances. The terminal of the stackable electronic module described in item 2 is installed, and the terminal is effectively connected to the external bus terminal device. An impedance that substantially matches the stackable electronic module described in item 3 is provided. Contains at least one electrical part of the following group ... capacitors and multiple inductors. The stackable electronic module described in item 4 is composed of a distributed resistor. ’, 525184 六、申請專利範圍 6#如申請專利範圍第5項所 中该等電阻係由一排阻所組成。 隹且電子模組 中該7等Ϊ I ί ί利範圍第6項所述之可堆疊電子模組 等電阻係由一固態電阻性裝置所組成。 ^如申請專利範圍第丨項所 中該等裝置至少包含一記憶體裝置。隹疊電子《組 中續9等ΐ Π:ΐ範圍第1項所述之可堆疊電子模組 電乳連接裝置包含複數個焊接接點。 中二°電如/二專/範圍第1項所述之可堆疊電子模組 中肩等電氧連接裝置包含一 PGA連接器。 11 ·如申請專利範圍第丨項所述之可 中該等電氣連接裝置包含一LGA連接器。茶子棋組 12.如申請專利範圍第u項所述之可堆疊電 其中該LGA連接器係由高度連接密度公司所提供之一'以 SuperbuttonTM為基礎之連接器。 1 3 ·如申請專利範圍第丨項所述之可堆疊電子模組 中該基板包含至少一種絕緣材料。 1 4 ·如申請專利範圍第丨3項所述之可堆疊電子模組 其中δ亥至少一種絕緣材料係為環氧基—玻璃—基 (epoxy-glass-based) ° 15·如申請專利範圍第14項所述之可堆疊電子模組 其中該至少一種絕緣材料包含FR4。 1 6.如申請專利範圍第1 3項所述之可堆疊電子模組 其中5¾至少一種絕緣材料包含一聚亞胺（p〇iyimide)。 第43頁 其 Ml 其 苴 525184 六、申請專利範固 其中該至如少申」二利:士圍第13項所述之可堆疊電子模組， ^ 一種絕緣材料包含陶瓷。 其中該至如少申」#種專絕^二第 分。 、、材料包含一聚合物（Polymeric)成 等電二·接νΛ專利範圍第1項之可堆疊電子模組，其中該 冤=接點組成之該第一式樣係叢集在一起。 其中該等如專利範圍第19項所述之可堆疊電子模組， 係為正方：點組成之該第-式樣所形成之外形實質上( 立中請專利範圍第19項所述之可堆疊電子模組， 係為：方ί耽接點組成之該第一式樣所形成之外形實質上 22.如申請專利範圍第19項所述之可堆疊 電氣接點組成之該第-式樣所形成之外形實質上 2 3 ·如申請專利範圍第1 g項所述之可堆疊電子模組， 其中該等電氣接點組成之該第一式樣所形成之外 係為多角形。 Λ M J1 2 4 ·如申請專利範圍第1 9項所述之可堆疊電子模組， 其中4專電氣接點組成之該第^ —式樣包含由叢隼在一起之 複數個電氣接點組成之至少兩個較小式樣。 2 5·如申請專利範圍第19項所述之可堆疊電子模組， 其更包含該基板之第二表面上在一第二二維式樣中由複數525184 VI. Application for patent scope 6 # As in Item 5 of the scope of patent application, these resistors are composed of an array of resistors. (7) In the electronic module, the resistors such as the stackable electronic module described in item 6 of the scope of the sixth item are composed of a solid-state resistive device. ^ As described in item 丨 of the patent application, these devices include at least one memory device. The stackable electronic module described in item 1 of the 隹 stack electronics group 组: 可: The stackable electronic module described in the first item of the range includes a plurality of solder joints. The second-degree electrical module is a stackable electronic module as described in the first item of the second item / the second item. The middle-shoulder electrical connection device includes a PGA connector. 11 · The electrical connection device described in item 丨 of the patent application scope includes an LGA connector. Tea chess set 12. The stackable electrical device as described in item u of the patent application range wherein the LGA connector is one of the 'SuperbuttonTM-based' connectors provided by High Connection Density Corporation. 1 3 · The substrate of the stackable electronic module according to item 丨 of the patent application scope includes at least one insulating material. 1 4 · The stackable electronic module as described in item 3 of the scope of patent application, wherein at least one kind of insulation material of δH is epoxy-glass-based ° 15 The stackable electronic module according to item 14, wherein the at least one insulating material comprises FR4. 1 6. The stackable electronic module according to item 13 of the scope of patent application, wherein at least one of the insulating materials comprises a polyimide. Page 43 Its Ml Its 苴 525184 VI. Application for patent Fangu which should be applied as little as possible "Second benefit: stackable electronic module described in Shiwei Item 13, ^ An insulating material contains ceramics. Which should be applied as little as possible "# 种 专 绝 ^ 二 分 分. The materials include a polymer (Polymeric) stackable electronic module connected to the first item of the νΛ patent scope, where the first type system consisting of contacts is clustered together. Among them, the stackable electronic module as described in item 19 of the patent scope is a square: the shape formed by the-pattern consisting of dots is essentially (stackable electronics as described in item 19 of the patent scope) The module is: the outer shape formed by the first pattern composed of squared contact points is substantially 22. the outer shape formed by the first pattern composed of stackable electrical contacts as described in item 19 of the scope of patent application Essentially 2 3 · The stackable electronic module as described in item 1g of the scope of the patent application, wherein the outer shape formed by the first pattern composed of the electrical contacts is polygonal. Λ M J1 2 4 · 如The stackable electronic module described in item 19 of the scope of the patent application, wherein the third pattern consisting of four specialized electrical contacts includes at least two smaller patterns composed of a plurality of electrical contacts clustered together. 25. The stackable electronic module according to item 19 of the scope of patent application, further comprising a plurality of numbers in a second two-dimensional pattern on the second surface of the substrate. 第44頁 525184 /、、申晴專利範圍 個電氣接點組成之一第二式樣， 等電氣接點組成之該第一式樣之至少一、、裝置連，該 點組成之該第二式樣之至少一接點。 .、至該等電氣接 26·如申請專利範圍第25項 其中該等電氣接點組成之該第：電子模組， 接點組成之該i式樣。 &樣實質上等於該等電氣 27. 如中請專利範圍第26項所述之可 其中該等連線裝置擴充該外接匯流排至電子模^ 子模組。 拱隱抓排至一第二可堆疊電痛 28. 如申請專利範圍第19項所述之可堆疊電子模組， 其更包含一外接印刷電路板構造’且其中該 與該外接印刷電路板構平行。 极竹貰買上 29·如申請專利範圍第28項所述之可堆疊電子模组， 其中該外接印刷電路板構造更包括在一第三二維式樣中由 複數個電氣接點組成設置在該外接印刷電路板構之一第一 表面上，並合適地以連接該外接匯流排。 3 0 ·如申請專利範圍第2 9項所述之可堆疊電子模組， 其中該等電氣接點組成之該第三式樣係叢集在一起’ 3 1 ·如申請專利範圍第3 〇項所述之可堆疊電子模組， 其中該等電氣接點組成之該第三式樣所形成之外形尺寸 質上等於該等電氣接點組成之該第一式樣所形成之外形。 32·如申請專利範圍第31項所述之可堆疊電子模組， 其中該等電氣接點組成之該第三式樣所形成之外形形狀實Page 44 525184 /, Shen Qing patent range one of the electrical contacts composed of a second style, at least one of the first style composed of electrical contacts, the device is connected, the point constitutes at least the second style of the second style One point. . To these electrical connections 26. If the scope of the patent application is No. 25, where the electrical contact is composed of the first: electronic module, the contact is composed of the i-style. & sample is substantially equal to the electrical 27. As described in item 26 of the patent application, where the connected devices expand the external bus to the electronic module ^ sub-module. The arch is hidden to a second stackable electric pain 28. The stackable electronic module described in item 19 of the scope of patent application, further includes an external printed circuit board structure ', and wherein the external printed circuit board structure and the external printed circuit board structure parallel. Buy the 29. The stackable electronic module as described in item 28 of the scope of patent application, wherein the external printed circuit board structure further includes a third two-dimensional pattern composed of a plurality of electrical contacts and arranged on the external One of the printed circuit board structures is on the first surface and is suitably connected to the external bus. 3 0 · The stackable electronic module described in item 29 of the scope of patent application, wherein the third pattern system composed of the electrical contacts is clustered together '3 1 · as described in item 30 of the scope of patent application The stackable electronic module, wherein the outer shape formed by the third pattern composed of the electrical contacts is qualitatively equal to the outer shape formed by the first pattern composed of the electrical contacts. 32. The stackable electronic module according to item 31 of the scope of patent application, wherein the external shape formed by the third pattern composed of the electrical contacts is solid 第45頁 525184 六、申請專利範圍 質上類似於該等電氣接點組成之該第一式樣所形成之外 形。 33·如申請專利範圍第1項之所述可堆疊電子模組，其 中該等裝置係環繞該等電氣接點組成之該第一式樣之至少 兩侧。 3 4 ·如申請專利範圍第1 3項所述之可堆疊電子模組， 其中該絕緣材料具有一熱擴展係數（CTE)以實質上匹配其 内部連接之該構造材料之該熱擴展係數（CTE)。 35· —具有多重通道之可堆疊電子模組，其包括： a) —基板，具有一第一表面及實質上與該第一表面平 4亍之 '一第^一表面； b) 在一第一二維式樣中由複數個電氣接點組成之一第 一式樣設置在該基板之第一表面上，並合適地以連 外接匯流排； ~ c )複數個電氣連接裝置，係有效地連接至該等電 點組成之第一式樣，以形成該二外接匯流 d):組複數個装置，係黏著在該基板之該第一表= ^苐一表面之至少一表面上，每一組被單獨 外接匯流排之一； 饮 Λ —組 其中該二組複數個裝置被設置在緊鄰該 J 成之該第一式樣。 伐點組Page 45 525184 VI. Scope of patent application The shape which is similar to the first pattern composed of these electrical contacts is qualitatively similar. 33. The stackable electronic module according to item 1 of the scope of patent application, wherein the devices surround at least two sides of the first pattern composed of the electrical contacts. 34. The stackable electronic module according to item 13 of the scope of patent application, wherein the insulating material has a coefficient of thermal expansion (CTE) to substantially match the coefficient of thermal expansion (CTE) of the structural material connected internally. ). 35 · — A stackable electronic module with multiple channels, including: a) — a substrate having a first surface and a first surface substantially parallel to the first surface; b) a first surface One of the two-dimensional patterns is composed of a plurality of electrical contacts. The first pattern is disposed on the first surface of the substrate and is suitably connected to an external bus; ~ c) A plurality of electrical connection devices are effectively connected to The first pattern composed of the electrical points to form the two external buses d): a group of a plurality of devices, which are adhered to at least one surface of the first table of the substrate = a surface, each group is individually One of the external buses; drink Λ — group in which the two groups of plural devices are arranged in the first pattern next to the J member. Cutting point group