TW523877B - Method for increase the contact between conducting wire and landing pad - Google Patents

Abstract

The present invention relate to a method for increase the contact between the conducting wire and the landing pad, and improve the problem of bitline capacitor contact resistance. The method of present invention utilizes hot H3PO4 to eliminate the cap layer of nitride layer to expose more contact area onto landing pad poly silicon, which is between gates. Therefore, the align accuracy of bitline can be improved due to increasing the contact in following process of depositing the bitline polysilicon, and can also decrease the capacitor contact resistance.

Description

523877523877

五、發明說明（1) 5 -1發明領域： 本發明疋有關於一種積體電路中線路的製程，特曰 一種動態隨機存取記憶體（DRAM)中增加導線與著路塾^ landing pad)接觸面’以提高位元線對準準確度的方法。 2發明背景 近來 i ntegrat 半導體技 增加的結 大。近來 縮小元件 ，DRAM 之 (p〇 1 y s i 過程，尤 準準確度 的問題。 ，由於超大 ion, ULSI) 術’使得晶 果’造成個 ’高解析度 尺寸為其主 位元線與節 1 i con p lug 其在毫微米 不正確的問 型積體 形成於 片上的 別元件 的微影 要'目的 點需縮 )上形 的尺寸 題可以 私路（ultra large scale 半導體基板上具有引人注目的 積體電路密度增加，此種密度 的尺寸縮小及元件群密度的^ 技術、蝕刻技術的進步，都以 。因此，為了縮小元件的尺寸 小，這種在DRAM多晶矽插塞 成位凡線需要非常準確的微影 ，非常不容易辦得到。由於對 引起線路短路及其他難以控制 傳統製作位元線方法，主暴古τ 提供-底#(未顯示），底材2下列幾個步驟。首先， 下：在第-A圖中第一層内- 一裝置’該裝置顯示如 θ内夕晶矽介電層（interpoly 523877 五、發明說明（2) ---— dielectric layer， IPD1) 105填充在兩閘極的上邊、a 與中間，閘極上面形成一多晶矽層（p〇lysiHc〇n ia = 101 ’接者在多晶石夕層101上面形成鐫金屬石夕化物芦（ tungsten silicide layer)102，接著在鎢金屬石/化物層 1 0 2上开> 成氮化石夕層（S is N4) 1 0 3 ’並在閘極兩邊形成氮化石夕 間隙壁（Silicon nitride spacer)l〇4 。接著，進行第— 層内多晶石夕介電層平坦化過程’以利於接下來的圖T案轉移 與姓刻的製程。經過光阻107圖案轉移與蝕刻過程將第一夕 層内多晶石夕介電層（IPD1) 105經過部分的蝕刻，剩下問極 上面的内多晶矽介電層（IPDl) 1 〇5Α與側邊内多晶矽介電層 (I P D 1 ) 1 0 5 Β及閘極上面的柱狀多晶矽層丨〇 1及鎢金屬石夕化 物層1 0 2、氮化矽層1 〇 3及氮化矽間隙壁1 〇 4，如第一 β圖 所示。接著，如第一C圖所示，將蝕刻的部分清除乾淨並 填充著路墊多晶矽（landing pad polys il icon) 106，以填 補飯刻過的空間，接著以回I虫過程去除部分的著路塾多晶 石夕（landing pad polysilicon)106，接著，以化學機械研 磨法（CMP )切齊内多晶矽介電層柱狀頂部1 〇 5 A與側邊内 多晶矽介電層（IPDl ) 1 05B頂部的部份，如第一d圖所示。 接著再沈積一弟二層内多晶石夕介電層（IPj)2)i〇g，並進行 平坦化過程。 接著’上光阻1 〇 9，如第一 E圖所示。接著，钱刻以去 除位於兩閘極中間的第二層内多晶矽介電層（丨pD2 )丨〇 8部 份’並形成位元線接觸面A A1，並進行位元線多晶矽（V. Description of the invention (1) 5 -1 Field of the invention: The present invention relates to a process of a circuit in an integrated circuit, and particularly to a type of dynamic random access memory (DRAM) with additional wires and routing (^ landing pad) Contact surface 'method to improve bit line alignment accuracy. 2 BACKGROUND OF THE INVENTION Recently, integrat semiconductor technology has increased its junctions. Recently, the size of components and DRAM (p0ysi process, especially the accuracy problem), due to the ultra-large ion (ULSI) technique 'makes the crystal fruit' caused a 'high resolution size for its main bit line and section 1 i con p lug The size problem on the large-scale semiconductor substrate with ultra large scale lithography on the lithography of other components formed on the chip with incorrect micrographs must be 'reduced'. The density of integrated circuits has increased, and the reduction in the size of this density and the advancement of ^ technology and etching technology for component group density have been achieved. Therefore, in order to reduce the size of components, this type of line in DRAM polysilicon plugs requires very much Accurate lithography is very difficult to achieve. Due to the short circuit and other traditional methods of making bit lines that are difficult to control, the main storm provides-bottom # (not shown), substrate 2 following steps. First, Bottom: In the first layer in Figure -A-a device 'This device shows a dielectric layer such as θ eve silicon crystal (interpoly 523877 V. Description of the invention (2) --- — dielectric layer (IPD1) 105) A polycrystalline silicon layer (p〇lysiHcón ia = 101) is formed on the upper, a, and middle sides of the two gate electrodes, and then a tungsten silicide layer 102 is formed on the polycrystalline layer 101. Then, on the tungsten metal stone / metal compound layer 102, a nitride nitride layer (S is N4) 103 is formed, and a silicon nitride spacer 104 is formed on both sides of the gate. Next, a planarization process of the polysilicon dielectric layer in the first layer is performed to facilitate the process of transferring and engraving in the next figure T. The polycrystalline silicon in the first layer is transferred through the photoresist 107 pattern transfer and etching process. The Shi Xi dielectric layer (IPD1) 105 is partially etched, and the inner polycrystalline silicon dielectric layer (IPDl) 1 〇5Α above the interrogator and the inner polycrystalline silicon dielectric layer (IPD 1) 1 0 5 Β on the gate and the gate are left. The surface of the columnar polycrystalline silicon layer 01 and the tungsten metal oxide layer 10 2, the silicon nitride layer 1 0 3, and the silicon nitride spacer 1 0 4 are shown in the first β diagram. As shown in Figure C, the etched portion is cleaned and filled with a land pad polys il icon 106, so that Fill up the engraved space, then remove part of the landing pad polysilicon 106 in the process of worming, and then cut the columnar top of the inner polycrystalline silicon dielectric layer by chemical mechanical polishing (CMP). 105 A and the top part of the polycrystalline silicon dielectric layer (IPDl) 1 05B on the side, as shown in the first figure d. Next, a second polycrystalline silicon dielectric layer (IPj) 2) i0g was deposited, and a planarization process was performed. Next, the photoresist is 109, as shown in the first E diagram. Next, Qian carved to remove the second polycrystalline silicon dielectric layer (丨 pD2) in the middle of the two gates, and formed a bit line contact surface A A1, and performed bit line polycrystalline silicon (

523877 五、發明說明（3) bitline polyS1lic〇n)沈積n〇，使得上下層之位 線路相通。上述傳統作法的缺點是位元線接觸面、 A:觸^ 米的尺度而t，位元線的對準在如此：的 接觸面進订接合的確有其困難。 因此’為增進位元線對準的準確度，利用加大 :接觸面積提升位元線接觸面的準確度，{可行的改良部 5-3發明目的及概述 情二目的是提供一方法以改善動態隨機擷取記 "" 中著路墊（1 anding pad)上位元線接觸的社構 ’以提高位元線接觸準確度的方法。 ^ 接觸個目的是提供-方法以減少位元線電容 著陸ί據：i: L，：發明方法主要是將閘極與閘極間的 1 a川）部份並ϋ /面齊L去除氮化石夕的帽層（cap polysi lic〇n f 曰 的耆陸墊多晶矽（landing _ τ * , _ 使彳于位元線接觸有更大的接觸面積，在接 下來的位凡線多晶石夕（bltllne㈣灿咖）沈積過在^523877 V. Description of the invention (3) bitline polyS1lic0n) deposit n0, so that the upper and lower bit lines communicate. The disadvantage of the above-mentioned traditional method is that the bit line contact surface, A: touch ^ meters and t, the bit line is aligned in this way: the contact surface ordering and joining does have its difficulties. Therefore, in order to improve the accuracy of bit line alignment, the use of increased: contact area to improve the accuracy of the bit line contact surface. {Practical Improvement Department 5-3 Invention Purpose and Overview The second purpose is to provide a method to improve Dynamic Random Capture " " A method to improve the bit line contact accuracy in a social organization with 1 anding pad on the road pad. ^ The purpose of the contact is to provide-a method to reduce the bit line capacitance landing. According to: i: L, the method of the invention is mainly to remove the nitride from the gate and the gate 1 part of the gate. Xi ’s cap layer (cap polysi lic〇nf called “land pad polycrystalline silicon” (landing _ τ *, _) makes the bit line contact have a larger contact area. In the following bit line polycrystalline stone (bltllne) Chanka) deposited in ^

第8頁 晶矽的 523877 五、發明說明（4) 中，由於接觸面積的加大，即可 accuracy )的準確度。實際步驟 沈積有一多晶矽層與矽化金屬層 接著在其周圍填滿第一層内多晶 polysilicon dielectric, IPD1 程，將蝕刻的部分去除，並回填 landing pad polysilicon)，以 以回蝕過程，去除部分的著路墊 的内多晶矽介電層柱狀頂部，再 silicon nitride layer)，接著 以Ρ Ο*去除，以增加位元線接觸 晶矽介電層（inter p〇iysUieQn ，並進行第二層内多晶矽的平坦 蝕刻兩閘極中間的第二層内多晶 ，間作為位元線多晶矽的沈積^ 多晶矽介電層被蝕刻的部份作為 然大許多，這種接觸面的加大， 度，接著，進行位元線多 線路的連接。 5 4發明詳細說明： 本發明的較佳實施例將詳 增加位元線對準（align 如了，首先，在一底材上 與氮化矽層以作為閘極。 石夕介電層（inter )經過圖案轉移與蝕刻過 一層著路墊多晶矽（ 填補蝕刻 多晶吩層 沈積一層 將兩閘極 面積，再 d i e 1 ect 化過程， 矽介電層 比傳統技 位元線接 可提高位 沈積，便 過的空間。接著 ’並露出#刻後 氮化矽層（ 中間的氮化石夕層 進行第二層内多 r ic， IPD2)沈積 接著圖案轉移及 這個倒T字型的 藝中以第二層内 觸面，其範圍顯 元線對準的準確 完成M0S著路墊 細討論如後。實施例乃是用Page 8 523877 of crystalline silicon 5. In the description of the invention (4), due to the increase of the contact area, the accuracy can be obtained. In the actual step, a polycrystalline silicon layer and a silicided metal layer are deposited, and then a polycrystalline polysilicon dielectric, IPD1 process is filled around the first layer to remove the etched part and backfill the land pad polysilicon), in order to remove part of the The columnar top of the inner polycrystalline silicon dielectric layer facing the road pad, and then a silicon nitride layer), and then removed by P 0 * to increase the bit line contact with the inter polysilicon dielectric layer (inter p0iysUieQn), and perform the second inner polycrystalline silicon layer. The second layer of polycrystalline silicon in the middle of the two gates is etched as a bit line. Polycrystalline silicon is deposited ^ The polysilicon dielectric layer is etched much larger. This contact surface is enlarged, and then, Perform bit line multi-line connection. 5 4 Detailed description of the invention: The preferred embodiment of the present invention will increase the bit line alignment (alignment). First, a silicon nitride layer is used as a gate on a substrate. The Shi Xi dielectric layer (inter) is pattern-transferred and etched with a layer of polycrystalline silicon (filling the etch polycrystalline layer to deposit a layer of two gate areas, and then die 1 ect process, silicon The dielectric layer can improve the bit deposition and pass the space than the conventional bit line connection. Then, the silicon nitride layer (the middle nitride stone layer is deposited in the second layer, IPD2) after the #etch is exposed. Next, the pattern transfer and this inverted T-shaped art use the second layer of internal contact surface, and the range of the pixel line alignment accurately completes the MOS landing pad. The details are discussed later. The example is to use

523877523877

並非用以限定本發明的 以描述使用本發明的一特定範例 範圍。 在本貫施例中，第二A圖至第二G圖為本發明的 每 施例。在第二A圖中，首先，提供一底材（未顯示又土只 材上有·一裝置，該裝置顯示如下：有一第一層内多）曰’氏入 電層（interpoly dielectric layer, IPDl)2〇5 埴=少；1 閘極的上面、旁邊與中間，並針對第一層内多晶矽二： 的上表面進行CMP平坦化過程，閘極上面形成一曰It is not intended to limit the invention to describe the scope of a particular example using the invention. In this embodiment, the second diagram A to the second G diagram are each embodiment of the present invention. In the second diagram A, first, a substrate is provided (a device is not shown on the substrate, and the device is shown as follows: there is a first layer inside) and an interpoly dielectric layer (IPDl) 2〇5 少 = 少; 1 The top, side and middle of the gate, and the CMP planarization process is performed on the upper surface of the polycrystalline silicon in the first layer.

(iirst layer polysilicon layer)201，接著在多晶石夕声 (p〇lysilicon layer)201上面形成鎢金屬矽化物層日（曰 tungsten si 1 icide layer ) 20 2。接著在鎢金屬矽化物層 202上面形成氮化矽層（Si3N4)2〇3，並在閘極側邊形成氮^匕 矽間隙壁（Si 1 icon nitride spacer ) 204。接著，進行第 一層内多晶矽介電層2 0 5平坦化過程，以利接下來的圖案 轉移與蝕刻製程。經過光阻2 〇 7圖案轉移與蝕刻過程將第 一層内多晶矽介電層（IPD 1 ) 2 0 5經過部分的蝕刻，剩下間(iirst layer polysilicon layer) 201, and then a tungsten metal silicide layer (tungsten si 1 pesticide layer) 20 2 is formed on the polysilicon layer 201. Next, a silicon nitride layer (Si3N4) 203 is formed on the tungsten metal silicide layer 202, and a silicon nitride spacer (Si1 icon nitride spacer) 204 is formed on the gate side. Next, a planarization process of the first polycrystalline silicon dielectric layer 205 is performed to facilitate subsequent pattern transfer and etching processes. After the photoresist 2.0 pattern transfer and etching process, the first inner polycrystalline silicon dielectric layer (IPD 1) 2 0 5 is partially etched, and the remaining

極上面的柱狀内多晶矽介電層（I P D 1 ) 2 0 5 A與側邊内多晶石夕 介電層（IPD1 ) 2 0 5B及閘極上面的多晶矽層201、鎢金屬石夕 化物層2 0 2、氮化矽層2 0 3，及閘極側邊的氮化矽間隙壁 204 ’如第二B圖所示。 接著，如第二C圖所示，將#刻的部分填充著路墊多 晶矽層（landing pad polysilicon) 20 6，以填補 I虫刻過The inner polycrystalline silicon dielectric layer (IPD 1) 2 0 5 A above the electrode and the polycrystalline silicon dielectric layer (IPD 1) 2 0 5B on the side and the polycrystalline silicon layer 201 on the gate and the tungsten metal silicon oxide layer 202, the silicon nitride layer 203, and the silicon nitride spacer 204 'on the gate side are shown in the second figure B. Next, as shown in FIG. 2C, the #scribed portion is filled with a landing pad polysilicon 20 6 to fill the I-etched portion.

523877523877

的空間，並針對著路墊多晶矽層的上表面進行CMp平坦化 過程’接著以回蝕、（etch back)過程去除部份的著路塾多 晶石夕（landing pad polysilicon cap)，我們將兩閘極 $ 間凹下陷的空間稱為著路墊多晶矽帽（landing pad polysilicon cap) 20 6A ’接著，再沈積一層氮化石夕層（ si 1 icon nitride layer)301如第二D圖所示。接著，曰並用 熱的ί^ΡΟ4溶劑，蝕刻兩閘極中間的氮化矽層，形成著路塾 301再沈積第二層内多晶石夕介電層（inte]f ⑶〇 cHelectnc， IPD2 ) 3 0 2，並在第二層内多晶矽介電層3〇2 上面上一層光阻3 0 3，如第二E圖所示。在這裡必須提曰醒的 是内介電層的移除，是以稀釋的氫氟酸（dUute hdrofluoric acid，DHF)作為濕式蝕刻鎔劑，進行濕式蝕 刻。接著，以微影過程將光阻下面第二層内多晶矽介^層 (inter poly dielectric layer)3〇2 去除，此一接觸窗 ^ 塞與著路墊空間301相通並形成位元線接觸（bitHne contact)面BB1，如第二F圖所示。這時候的位元線接觸面 積已加大，如BB1線所示，對於位元線結構而言，由於接 觸面的加大，能增加對準的準確率。接著，如第二〇圖所 示，將位元線多晶矽（1^1：1；[1161)〇;^以14〇1〇 3 04沈積，完 成位元線結構。 以上所述僅為本發明之較佳實施例而已，並非用以限 疋本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請Space, and the Cmp planarization process is performed on the upper surface of the polysilicon layer of the road pad. Then, a part of the landing pad polysilicon cap is removed by an etch back process. The space where the gate electrode is recessed is called a landing pad polysilicon cap. 20 6A 'Next, a layer of silicon nitride layer (Si 1 icon nitride layer) 301 is deposited as shown in the second D diagram. Next, the hot silicon oxide solution was used to etch the silicon nitride layer in the middle of the two gates to form the circuit 301 and then deposit the second polycrystalline silicon dielectric layer (inte) f (CDOcHelectnc, IPD2). 3 0 2, and a photoresist 3 3 on the polycrystalline silicon dielectric layer 30 2 in the second layer, as shown in the second E diagram. It must be mentioned here that the removal of the inner dielectric layer is performed by using wet dilute hydrofluoric acid (dUute hdrofluoric acid (DHF)) as a wet etchant. Next, the lithography process is used to remove the second inter poly dielectric layer 302 under the photoresist. This contact window plug communicates with the landing pad space 301 and forms a bit line contact (bitHne contact) plane BB1, as shown in the second F diagram. At this time, the bit line contact area has increased, as shown by the BB1 line. As for the bit line structure, the increase of the contact surface can increase the accuracy of the alignment. Next, as shown in FIG. 20, the bit line polycrystalline silicon (1 ^ 1: 1; [1161) 0; ^ was deposited at 1,040,044 to complete the bit line structure. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Application described

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第12頁 523877 圖式簡單說明 第一 A圖至第一 F圖，顯示傳統位元線結構的結構的截 面圖； 第二A圖至第二G圖，顯示根據本發明之實施例以製造 位元線結構流程的截面圖。 主要部分之代表符號： 101 多晶矽 1 02 鎢金屬矽化物層The 523877 diagram on page 12 briefly illustrates the first diagram A to the first diagram F, which are cross-sectional views showing the structure of a conventional bit line structure; the second diagram A to the second diagram G show the manufacturing steps according to an embodiment of the present invention. A cross-sectional view of the element line structure process. Representative symbols of main parts: 101 polycrystalline silicon 1 02 tungsten metal silicide layer

1 03 氮化矽層 104 氮化矽間隙壁 105 第一層内多晶矽介電層 105A 閘極上面的内多晶矽介電層 105B 側邊内多晶矽介電層 106 著路墊多晶矽 107 光阻 108 第二層内多晶矽介電層 1 0 Θ 光阻1 03 Silicon nitride layer 104 Silicon nitride spacer wall 105 First polycrystalline silicon dielectric layer 105A Polycrystalline silicon dielectric layer above the gate 105B Polycrystalline silicon dielectric layer on the side 106 Polysilicon pad 107 Photoresist 108 Second In-layer polycrystalline silicon dielectric layer 1 0 Θ photoresist

110 位元線多晶矽 201 多晶矽 2 0 2 鎢金屬矽化物層 2 0 3 氮化矽層 2 04 氮化矽間隙壁 2 0 5 第一層内多晶石夕介電層110 bit line polycrystalline silicon 201 polycrystalline silicon 2 0 2 tungsten metal silicide layer 2 0 3 silicon nitride layer 2 04 silicon nitride spacer 2 0 5 polycrystalline silicon dielectric layer in the first layer

第13頁 523877 圖式簡單說明 2 0 5A 閘極上面的内多晶矽介電層 2 0 5 B 側邊内多晶矽介電層 2 0 6 著路墊多晶矽 2 0 6A 著路墊多晶矽帽 2 0 7 光阻 301 氮化矽層 301A 著路墊 3 0 2 第二層内多晶矽介電層 3 0 3 光阻 3 04 位元線多晶矽 3 0 9 位元線接觸 AA1 傳統式位元線接觸面 BB1 本發明位元線接觸面Page 13 523877 Brief description of the diagram 2 0 5A Inner polycrystalline silicon dielectric layer on the gate 2 0 5 B Inner polycrystalline silicon dielectric layer on the side 2 0 6 Landing pad polycrystalline silicon 2 0 6A Landing pad polycrystalline silicon cap 2 0 7 Light 301 silicon nitride layer 301A landing pad 3 0 2 polycrystalline silicon dielectric layer in the second layer 3 0 3 photoresist 3 04 bit line polycrystalline silicon 3 0 9 bit line contact AA1 traditional bit line contact surface BB1 The present invention Bit line contact surface

第14頁Page 14

Claims (1)

加導線與著路墊接觸面的方 523877 六、申請專利範圍 1. 一種在積體電路裝置命 法，該方法至少包含： 提供一底材，其具有一第一閘極結構以及一第二閘極 結構位於該底材之上； 沈積一第一内介電層在該底材上； 除去部分的該第一内介電層； 形成一第一導體層於該第一閘極及該第二閘極之間； 回餘部份該第一導體層； 形成覆蓋層於第一導體層上； 沈積一第二内介電層於該覆蓋層及第一内介電層上； 除去部份位於該第一閘極及該第二閘極間上方的該第 二内介電層，及該覆蓋層；以及 形成一第二導體層於該第一閘極及該第二閘極之上的 第一導體層之上。Method for adding the contact surface of the conducting wire and the road pad 523877 6. Scope of patent application 1. A method of integrative circuit device at least comprising: providing a substrate having a first gate structure and a second gate A pole structure is located on the substrate; a first internal dielectric layer is deposited on the substrate; a portion of the first internal dielectric layer is removed; a first conductor layer is formed on the first gate and the second Between the gates; the remaining part of the first conductor layer is formed; a cover layer is formed on the first conductor layer; a second internal dielectric layer is deposited on the cover layer and the first internal dielectric layer; The second inner dielectric layer above the first gate and the second gate, and the cover layer; and a second conductor layer forming a second conductor layer on the first gate and the second gate On a conductor layer. 第15頁 内内 ㉟ 層 第第 亥亥 =口=口 積平 沈磨 該以 中， 其程 ，過 法化 方坦 之平 項 P 11 PIW 第以 圍含 《祀包 利，’ 專程 請過。 申層層 如電電 • 介人7Γ 6 y > 523877 六、申請專利範圍 上面的該第一内介電層。 5.如申請專利範圍第1項之方法，其中該回蝕該覆蓋層的 溶劑至少包含Η3Ρ04。 7. 如申請專利範圍第1項之方法，其中該沈積第二層内介 電層過程，包含以CMP平坦化過程，以磨平第二層内介電 層 〇 8. 如申請專利範圍第1項之方法，其中該兩閘極間覆蓋層 的回餘為去除氮化石夕帽層（Silicon nitride cap)。 9. 如申請專利範圍第1項之方法，其中該内介電層的移除 ，至少包含以稀釋的氫氟酸（dilute hdrofluoric acid， D H F )作為濕式#刻（w e t e t c h i n g )技術之溶劑。 10. —種在積體電路裝置中加導線與著路墊接觸面的 方法，該方法至少包含： 提供一底材，其具有一第一閘極結構以及一第二閘極 結構位於該底材之上；The inner inner layer on page 15th. Hai Hai = mouth = mouth product level, pondering the middle, the process, passing the French Fang Tan's flat item P 11 PIW, the enclosing "Sacrifice to Boli, 'Please pass by special trip . Application layers such as electricity • Intermediary 7Γ 6 y > 523877 6. Scope of patent application The first internal dielectric layer above. 5. The method according to item 1 of the scope of patent application, wherein the solvent of the etch-back coating layer contains at least 3P04. 7. The method according to the first item of the patent application, wherein the process of depositing the second inner dielectric layer includes a CMP planarization process to smooth the second inner dielectric layer. 0. The first application of the first patent application The method of claim 1, wherein the rest of the capping layer between the two gates is removing a silicon nitride cap. 9. The method according to item 1 of the patent application scope, wherein the removal of the inner dielectric layer comprises at least dilute hdrofluoric acid (D H F) as a solvent for wet #etch (wet e t c h i n g) technology. 10. A method for adding a contact surface of a conducting wire and a road pad in an integrated circuit device, the method at least comprising: providing a substrate having a first gate structure and a second gate structure located on the substrate Above 第16頁 523877 六、申請專利範圍 沈積一第一氧化矽層在該底材上； 除去部分的該第一氧化矽層層；以微影製程形成一第 一接觸窗開口，該接觸窗開口位於該第一閘極結構以及該 第二閘極結構之間； 沈積一第一多晶矽層在該接觸窗開口内以形成一接觸 窗插塞； 回蝕一部份該接觸窗插塞的頂部的一部份以形成一著 路墊； 填入一氮化矽層在該著路墊内；Page 16 523877 6. The scope of the patent application deposits a first silicon oxide layer on the substrate; removes part of the first silicon oxide layer; forms a first contact window opening by a lithography process, and the contact window opening is located at Between the first gate structure and the second gate structure; depositing a first polycrystalline silicon layer in the contact window opening to form a contact window plug; etch back a part of the top of the contact window plug Part to form a landing pad; fill a silicon nitride layer in the landing pad; 回蝕該兩閘極間的該氮化矽層； 沈積一第二多晶矽層在該氮化矽層與該第一氧化矽層 上面； 以微影製程形成一第二開口 ，該第二開口位於兩閘極 中間該第二氧化矽層上面；以及 沈積一位元線多晶矽以填充該著路墊、該第二開口及 該第二多晶石夕層上面。 11.如申請專利範圍第1 0項之方法，其中該閘極結構至少 包含一多晶石夕層、一氧化石夕層及底材。Etch back the silicon nitride layer between the two gates; deposit a second polycrystalline silicon layer on the silicon nitride layer and the first silicon oxide layer; form a second opening by a lithography process, and the second The opening is located above the second silicon oxide layer in the middle of the two gates; and a bit line polycrystalline silicon is deposited to fill the landing pad, the second opening, and the second polycrystalline silicon layer. 11. The method of claim 10, wherein the gate structure includes at least a polycrystalline layer, a monocrystalline layer, and a substrate. 1 2.如申請專利範圍第11項之方法，其中該多晶矽層為鎢 金屬石夕化物層。 1 3 ·如申請專利範圍第1 0項之方法，其中該第一次微影過1 2. The method according to item 11 of the application, wherein the polycrystalline silicon layer is a tungsten metal oxide layer. 1 3 · If the method in the scope of patent application No. 10, wherein the first lithography 第17頁 523877 六、申請專利範圍 程至少包含：圖案轉移與蝕刻該兩閘極旁邊與該閘極上面 -的該第一内介電層。 1 4.如申請專利範圍第1 0項之方法，其中該回餘該氮化石夕 層的溶劑至少包含H3 P 04。 1 5.如申請專利範圍第1 0項之方法，其中該沈積該第一層 内介電層過程，包含以CMP平坦化過程，以磨平該第一層 内介電層。 1 6.如申請專利範圍第1 0項之方法，其中該沈積第二層内 介電層過程，包含以C Μ P平坦化過程，以磨平該第二層内 介電層。 1 7.如申請專利範圍第1 0項之方法，其中該兩閘極間覆蓋 層的回餘為去除氮化石夕帽層（Silicon nitride cap)。 1 8.如申請專利範圍第1 0項之方法，其中該内介電層的移‘ 除，至少包含以稀釋的氫氟酸（dilute hdrofluoric a c i d，D H F )作為濕式餘刻（w e t e t c h i n g )技術之溶劑。 _Page 17 523877 6. The scope of patent application includes at least: pattern transfer and etching of the first inner dielectric layer next to the two gate electrodes and above the gate electrodes. 14. The method according to item 10 of the scope of patent application, wherein the solvent of the remaining nitride layer includes at least H3P04. 15. The method of claim 10, wherein the process of depositing the first inner dielectric layer comprises a CMP planarization process to smooth the first inner dielectric layer. 16. The method of claim 10, wherein the process of depositing the second inner dielectric layer comprises a planarizing process with CMP to smooth the second inner dielectric layer. 1 7. The method according to item 10 of the scope of patent application, wherein the rest of the covering layer between the two gates is the removal of a silicon nitride cap. 18. The method according to item 10 of the scope of patent application, wherein the removal of the inner dielectric layer includes at least dilute hdrofluoric acid (DHF) as a wet-etching technology. Solvent. _ 第18頁Page 18