TW520442B

TW520442B - Measurement circuit of capacitance

Info

Publication number: TW520442B
Application number: TW90130268A
Authority: TW
Inventors: Tsung-Hsuan Hsieh; Yao-Wen Chang; Tao-Cheng Lu
Original assignee: Macronix Int Co Ltd
Priority date: 2001-12-06
Filing date: 2001-12-06
Publication date: 2003-02-11

Abstract

The present invention provides a measurement circuit of capacitance, in which the measurement circuit includes a PMOS device, an NMOS device, the first terminal and the second terminal for measuring the capacitance value of a capacitor device. In the invention, the drain electrode of PMOS device is electrically connected with the drain electrode of NMOS device. One end of the first terminal is electrically connected between the drain electrode of PMOS device and the drain electrode of NMOS device, and the other end of the first terminal is electrically connected to one side of the capacitor device. One end of the second terminal is electrically connected to the other side of the capacitor device. The present invention also provides a kind of method for measuring capacitance through the use of aforementioned capacitance measurement circuit.

Description

520442 五、發明說明（1) 【發明領域】本發明係關於一種電容量測電路與方法，特別關於一種利用一CMOS元件來量測電容的電容量測電路與方法。【習知技術】隨著半導體元件之集積度（integrati〇n)的提高，對準確測量内連線延遲（interconnect delay)之特性的需求已經顯得日益重要，因為，事實證明，目前的半導體元件中每一金屬層的電路已經是非常的密集而且有許多的線路分佈。在習知的内連線電容技術領域中，通常是利用參考電容、複雜的測試結構設計、或是複雜的量測步驟來求得内連線電容，但是其只能夠測量出微微法拉（piC0 —farad， pF )的電容。為了測量更微小的電容，例如毫微微法拉 (f emto-f arad，f F )的電容，科學家提供了一種新的測量方法，稱為CBCM (Charge-Based Capacitance Measurement )，利用CBCM來測量寄生内連接電容值可以達到0 · 0 1 f F的解析度。請參照圖1所示，CBCM測試的結構包括二NM0S電晶體以及二PM0S電晶體，其中一NM0S電晶體與一PM0S電晶體電連接，另一NM0S電晶體與另一PM0S電晶體電連接，而待測電容C則電連接至其中一組NM0S電晶體與PM0S電晶體之間，然後量測出分別流過二組NM0S電晶體與PM0S電晶體之520442 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a capacitance measurement circuit and method, and particularly to a capacitance measurement circuit and method using a CMOS element to measure capacitance. [Known Technology] With the increase of the integration of semiconductor devices, the need for accurate measurement of the characteristics of the interconnect delay has become increasingly important because, as it turns out, current semiconductor devices The circuit of each metal layer is already very dense and has a lot of wiring distribution. In the conventional field of interconnected capacitor technology, reference capacitors, complex test structure designs, or complex measurement steps are commonly used to obtain interconnected capacitors, but they can only measure pico farads (piC0 — farad, pF). In order to measure even smaller capacitances, such as femto-f arad (f F) capacitance, scientists have provided a new measurement method, called CBCM (Charge-Based Capacitance Measurement), which uses CBCM to measure The connection capacitance value can reach a resolution of 0 · 0 1 f F. Please refer to FIG. 1. The structure of the CBCM test includes two NMOS transistors and two PM0S transistors. One NMOS transistor is electrically connected to one PM0S transistor, the other NMOS transistor is electrically connected to another PM0S transistor, and The capacitor C to be tested is electrically connected between one of the NM0S transistors and the PM0S transistor, and then measured through two sets of NM0S transistors and PM0S transistors.

520442 五、發明說明（2) 二電流，並利用二電流的差可以反推得到待測電容(；的電容值。有關於CBCM測試結構的詳細說明可以參考Pr〇c. IEEE 1997 Int. Conference on Microelectronic Test Structures期刊，於西元1 9 97年3月發行的第l〇期中所刊載的「An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad520442 V. Description of the invention (2) Two currents, and the difference between the two currents can be used to infer the capacitance value of the capacitance to be measured. For a detailed description of the CBCM test structure, refer to PrOc. IEEE 1997 Int. Conference on Microelectronic Test Structures, "An On-Chip, Interconnect Capacitance Characterization Method with Sub-Femto-Farad," published in Issue 10, March 1997

Resolution」一文，凡熟悉該項技藝者應該對CBCM的技術有相當的瞭解，故此不再闡述。凡熟悉該項技藝者都知道，CBCM是在假設二組pM〇s元組件與NM0S元件具有相同寄生電容值的情況了，利用一阳 PM0S元件與NM0S元件來量測待測電容[，但是，實際上一 ^PMOS元件與關⑽元件的寄生電容值可能有差異，因此一利 =BCM測试結構來量測電容的結果會有誤差。 i ^亡T ^如何提供一種能夠測量微小電容並減少誤差的電谷置測電路與方法，是目前一個重要的課題。【發明概要】針對上述問題，士 & n 測一微小電容之Θ S明之目的為提供一種能夠減少量太狀〇决差的電容量測電路盥方法。本發明之特徼盘口 U杰測微小電衮，* i马/、利用一PM0S元件與一NM0S元件來量為達上述之目2 *微微法拉（fF )的解析度。 PM0S元件、一NM〇s的’依本發明之電容量測電路包括一便用來量測一電办兀件、一第一端子以及一第二端子，以〜70件的電容值。在本發明中，PM0S元件"Resolution", anyone who is familiar with the art should have a good understanding of the CBCM technology, so it will not be described here. Anyone familiar with this art knows that CBCM assumes that the two sets of pM0s element components have the same parasitic capacitance value as the NM0S element, and uses a male PM0S element and NM0S element to measure the capacitance to be measured. In fact, the parasitic capacitance values of a PMOS element and a switching element may be different. Therefore, there is an error in the result of measuring the capacitance by the BCM test structure. It is an important issue how to provide an electrical valley measurement circuit and method capable of measuring small capacitance and reducing errors. [Summary of the Invention] In view of the above problems, the purpose of measuring Θ S of a small capacitor is to provide a method for measuring the capacitance of a capacitor, which can reduce the amount of the capacitor. According to the present invention, the special handicap U U is used to measure micro-electricity, and the power is measured by using a PMOS element and a NMOS element to achieve the above-mentioned purpose 2 * The resolution of the pico farad (fF). The PM0S element and a NMOS 'capacitance measuring circuit according to the present invention include a capacitor for measuring an electrical component, a first terminal, and a second terminal, with a capacitance value of ~ 70 pieces. In the present invention, the PMOS device

520442 五、發明說明（3) 閘極分別電連接至一第_電壓源與-第二電壓凡件之汲極則與NM0S元件之汲極電連接，NM0S元而第二f與源極分別電連接至一第三電壓源與一接地端，、、 &子之一端電連接至PM0S元件之汲極與nm〇S元件之 f，間其另一端電連接至電容元件之一側，第二端子之四接至電容元件之另一側’其另一端電連接至一第在本發明中，第一電壓源提供具有穩定電壓值之電堅β’第二電壓源與第三電壓源所提供的電壓具有相同之一，疋脈，，期；並且，當第四電壓源的電壓值維持與第一端子的電壓值相同時，進行PM0S元件之源極與接地端之間電流的量測，另外，當第四電壓源的電壓值恆為零時，進行PM0S元件之源極與接地端之間電流的測取得之二電流值求得電容元件的電容值/依據一-人里旦本發明亦提供一種電容量測方法，其利用上述的電容里測電路來測量電容元件的電容值，電容量測方法之流程包含輸入第一電壓源至PM0S元件之源極、輸入第1電^源至PM0S元件之閘極、輸入第三電壓源至NM〇s元件之閘極’、、輸入第四電壓源至第二端子以及量測PM0S元件之源極與接地端之間的電流值。 “ 在本發明中，當第四電壓源的電壓維持與第一端子的 =£ 2同k，$ _pM〇S兀件之源極與接地端之間的電流值為一第一電流值；當將第四電壓源的電壓設為零時，量測 PM0S元件之源極與接地端之間的電流值為一第^電流值。520442 V. Description of the invention (3) The gates are electrically connected to a first voltage source and a second voltage. The drain of each element is electrically connected to the drain of the NM0S element. The NM0S element and the second f are respectively electrically connected to the source. Connected to a third voltage source and a ground terminal, one terminal of the,, & sub-terminals is electrically connected to the drain of the PM0S element and f of the nmOS element, and the other end is electrically connected to one side of the capacitor element, and the second Four of the terminals are connected to the other side of the capacitor element, and the other end thereof is electrically connected to the first terminal. In the present invention, the first voltage source provides a voltage having a stable voltage value β 'provided by the second voltage source and the third voltage source. And the voltage has the same one, the pulse, and the period; and when the voltage value of the fourth voltage source remains the same as the voltage value of the first terminal, the current measurement between the source and the ground of the PM0S element is performed, In addition, when the voltage value of the fourth voltage source is constant to zero, the capacitance value of the capacitive element is obtained by measuring the current value of the current between the source and the ground terminal of the PM0S element. A capacitance measuring method is also provided, which utilizes the capacitance described above The test circuit measures the capacitance of the capacitive element. The flow of the capacitance measurement method includes inputting the first voltage source to the source of the PM0S element, inputting the first electrical source to the gate of the PM0S element, and inputting the third voltage source to the NM. 〇s the gate electrode of the element, input the fourth voltage source to the second terminal, and measure the current value between the source and the ground of the PM0S element. "In the present invention, when the voltage of the fourth voltage source remains the same as that of the first terminal = £ 2, the current value between the source and the ground of the $ _pMOS component is a first current value; when When the voltage of the fourth voltage source is set to zero, the current value between the source and the ground terminal of the PMOS device is measured as a third current value.

第6頁 520442Page 6 520442

五、發明說明（4) 依據在本發明的電容量測方法操作，則當PM〇s元件為導通時，NM0S元件為不導通，當NM0S元件為導通時，pM〇s元件為不導通。承上所述，依據第一電流值、第二電流值、電壓值以及電壓脈衝週期’可以利用式（丨）計算求得電容元件的電容值。式（1 )如下所述：值―ί第二電流值-第一電流值）χ電壓脈衝堳拟第—電、之電壓值~ — (工）由於本發明之電容量測電路與方法只利用-PM0S元件與一 NM0S元件來量測微小電容’所以沒有寄生電容不同的問題’因此不會產生習知C B C Μ測試結構發生的誤差。【較佳實施例之詳細說明】以下將參照相關圖式，說明依本發明較佳實施例之電容量測電路與方法，其中相同的元件將以相同的參照符號加以說明。請參照圖2所示，依本發明較佳實施例之電容量測電路2包含一 PM0S元件21、一 NM0S元件22、一第一端子23以及一第二端子24，以應用於量測一電容元件2〇1的電容值。 PM0S元件21之源極與閘極分別電連接至一第一電壓源 Vdd與一第二電壓源Vp，PM0S元件2丨之汲極與關⑽元件22'' 之汲極電連接，NM0S元件22之閘極與源極分別電連接至一第三電壓源Vn與一接地端Gnd，第一端子23之一端電連接V. Description of the invention (4) According to the capacitance measurement method of the present invention, when the PMOS element is on, the NMOS element is off, and when the NMOS element is on, the pMOS element is off. As mentioned above, according to the first current value, the second current value, the voltage value, and the voltage pulse period ', the capacitance value of the capacitor can be calculated by using formula (丨). The formula (1) is as follows: value-ί second current value-first current value) χ voltage pulse imitating the first-the voltage value of the electricity-(work) Because the capacitance measuring circuit and method of the present invention only use -PM0S element and an NMOS element are used to measure the small capacitance 'so there is no problem with different parasitic capacitance', so no errors occur in the conventional CBC M test structure. [Detailed description of the preferred embodiment] The capacitance measuring circuit and method according to the preferred embodiment of the present invention will be described below with reference to related drawings, in which the same components will be described with the same reference symbols. Please refer to FIG. 2. A capacitance measuring circuit 2 according to a preferred embodiment of the present invention includes a PM0S element 21, an NMOS element 22, a first terminal 23 and a second terminal 24 for measuring a capacitance. The capacitance value of the device 201. The source and gate of the PM0S element 21 are electrically connected to a first voltage source Vdd and a second voltage source Vp, respectively. The drain of the PM0S element 2 丨 is electrically connected to the drain of the switching element 22 '', and the NMOS element 22 The gate and source are electrically connected to a third voltage source Vn and a ground terminal Gnd, respectively, and one terminal of the first terminal 23 is electrically connected.

520442 五、發明說明（5) 至PM0S元件21之汲極與NM0S元件22之沒極間，第一端子23 之另一端與第二端子24之一端分別電連接至電容元件2〇1 之二側，第二端子24之另一端電連接至一金屬墊241，以便一第四電壓源Vt能夠從金屬墊241輸入。在本實施例中，前述之所有元件可以是形成於一半導體晶片中的積體電路之部分，其中，第一端子23與第二端子24可以是金屬線，PM0S元件21與NM0S元件22可以分別是 PM0S場效電晶體（PM0SFET)與NM0S場效電晶體（NM0SFET )。而PM0S元件21、NM0S元件22、第一端子23以及第二端子2 4可以分別形成於半導體晶片中，且電容元件2 〇 1可以是半導體晶片中任意二電離之金屬元件。電壓源Vdd為一穩定電壓第例在本實施例中如’ 5伏特或是1 2伏特的電壓。第二電壓源Vp與第三電壓源Vn具有相同之一電壓脈衝週期ρ，例如，如圖3所示，二電壓源Vp與第三電壓源vn之電壓脈衝週期F可以分為五階段，其中，第二電壓源Vp於第一階段與第五階段時位準，而於第二階段、第三階段與第四階段時為高位進-第三電壓源Vn於第三階段時為高位準，而於第一階段+笛二階段、第四階段與第五階段時為低位準。如上所本實施例中，第二電壓源Vp與第三電壓源Vn之高位；2 第一電壓源Vdd，而其低位準為零。寺於如圖3所不，第四電壓源v t之電壓脈衝週期f盥壓源Vp以及第三電壓源Vn相同，而第四電壓源以^-電段與第五階段時為高位準，於第三階段時為低位準。P白520442 V. Description of the invention (5) Between the drain of PM0S element 21 and the end of NM0S element 22, the other end of the first terminal 23 and one end of the second terminal 24 are electrically connected to the two sides of the capacitor element 201 The other end of the second terminal 24 is electrically connected to a metal pad 241 so that a fourth voltage source Vt can be input from the metal pad 241. In this embodiment, all the aforementioned components may be part of an integrated circuit formed in a semiconductor wafer, wherein the first terminal 23 and the second terminal 24 may be metal wires, and the PMOS device 21 and the NMOS device 22 may be respectively It is PM0S field effect transistor (PM0SFET) and NM0S field effect transistor (NM0SFET). The PMOS element 21, the NMOS element 22, the first terminal 23, and the second terminal 24 can be formed in a semiconductor wafer, respectively, and the capacitor element 201 can be any two ionized metal elements in the semiconductor wafer. The voltage source Vdd is a stable voltage. Example In this embodiment, the voltage is 5 V or 12 V. The second voltage source Vp and the third voltage source Vn have the same voltage pulse period ρ. For example, as shown in FIG. 3, the voltage pulse period F of the second voltage source Vp and the third voltage source vn can be divided into five stages, where The second voltage source Vp is at a high level during the first and fifth stages, and is high during the second, third, and fourth stages-the third voltage source Vn is at a high level during the third stage. The low level is in the first stage + the second stage, the fourth stage and the fifth stage. As in the above embodiment, the high level of the second voltage source Vp and the third voltage source Vn; 2 the first voltage source Vdd, and its low level is zero. As shown in Figure 3, the voltage pulse period f of the fourth voltage source vt is the same as the voltage source Vp and the third voltage source Vn, and the fourth voltage source is at a high level in the ^ -electric stage and the fifth stage. Low in the third stage. P white

第8頁Page 8

DZU44Z 五、發明說明（6) V t依據第由低位準變為 = 第二階段與第四階段時，第四電㈣佩弟一知子2 3之電壓，分則山_ 电雙源电座刀別由鬲位準變成低位準上所述，由於第==:第第-端子23之電壓相同。: 同，所以，電容元在低：ΐ:: Γ壓所:/，不:電？”四電壓源vt設定維持等於第-端子23的ί壓值則電各元件201二端的電壓差即為使本發明之内容更容易理解，杏說明：：= 圭實施例之電容量測方Si: 以，參π圖3所不，依本發明較佳實施例之電法3係利用電容量測電路2來測量值方在本侧輸入第一電壓咖至ρΜ〇 = 源極，其中’尺-電壓源Vdd之電壓為穩定之一電壓值，例如，5伏特或是1 2伏特。步驟302輸入第二電壓源”至”⑽元件21之閘極，其中，第二電壓源Vp之電壓脈衝週期F係如圖3所示，換言、之，在步驟302中，先於第一階段輸入低位準至第二電壓源Vp，然後於第二階段、第三階段與第四階段輸入高位準至第二電壓源Vp，最後於第五階段輸入低位準至第二電壓源Vp，並重複依序執行第一階段至第五階段。上述的低位準可以是〇伏特’而高位準則與第一電壓源Vdd之電壓相等。步驟3 0 3輸入第三電壓源Vn至NMOS元件22之閘極，其DZU44Z V. Description of the invention (6) V t changes from the low level to the second stage and the fourth stage. The voltage of the fourth electric ㈣ Pei Yizhizi 2 3, divided by the mountain _ electric double source electric seat knife Do not change from 鬲 level to low level, as the voltage at the ==: th-terminal 23 is the same. : Same, so, the capacitor element is low: ΐ :: ΓPressure: /, not: electricity? "The four voltage sources vt are set equal to the voltage value of the-terminal 23, and the voltage difference between the two ends of each element 201 is to make the content of the present invention easier to understand. : As shown in Fig. 3, the electric method 3 according to the preferred embodiment of the present invention uses the capacitance measurement circuit 2 to measure the value, and then inputs the first voltage to ρΜ〇 = the source electrode, where -The voltage of the voltage source Vdd is a stable voltage value, for example, 5 volts or 12 volts. Step 302 inputs the second voltage source "to" the gate of the element 21, wherein the voltage pulse of the second voltage source Vp The period F is shown in FIG. 3, in other words, in step 302, the low level is input to the second voltage source Vp before the first stage, and then the high level is input to in the second, third, and fourth stages. In the second voltage source Vp, the low level is input to the second voltage source Vp in the fifth stage, and the first stage to the fifth stage are repeatedly performed in sequence. The above low level may be 0 volts, and the high level criterion is the same as the first voltage. The voltages of the sources Vdd are equal. Step 3 0 3 Input the third voltage source Vn to the gate of the NMOS element 22, which

520442 五、發明說明（7) " ----- 中’第三電壓源Vn之電壓脈衝週期F係如圖3所示，換言之，在步驟3 03中，先於第一階段與第二階段輸入低位準至第三電壓源Vn，然後於第三階段輸入高位準至第三電壓源Vn，最後於第四階段與第五階段輸入低位準至第三電^ ，並重複依序執行第一階段至第五階段。上述的低位準可以是〇伏特，而高位準則與第一電壓源Vdd之電壓相等。如上所述，依據圖3所示之電壓脈衝，故，當pM〇s元 =21為導通時，NM〇s元件22為不導通，而當題⑽元件u為導通時，PM0S元件21為不導通，因此，在步驟3〇2與步驟 303中，pm〇s元件21之源極與接地端Gnd之間形成一容。了土电步驟304輸入第四電壓源”至第二端子24。在本實施例中，當第四電壓源vt之電壓值維持與第一端子23的電壓 ^相同時，量測PMOS元件21之源極與接地端Gnd之間的電流為一第一電流值，為維持第四電壓源v t之電壓值與第一端子23的電壓值相同，第四電壓源vt之電壓變化如圖3所示’當第四電壓源V t的電壓值恆為零時，量測p M Q g元件2 1 之源極與接地端Gnd之間的電流為一第二電流值。如上所述’第一電流值是流經PMqs元件2 1之源極與接地端Gnd間形成之寄生電容的電流；而第二電流值是流經 PMOS元件21之源極與接地端〇11(1間形成之寄生電容與電容元件2 0 1之並聯電容的電流。步驟3 0 5依據第一電流值、第二電流值、第一電壓源520442 V. Description of the invention (7) " ----- The voltage pulse period F of the third voltage source Vn is shown in FIG. 3, in other words, in step 03, it precedes the first stage and the second Input the low level to the third voltage source Vn in the third stage, then input the high level to the third voltage source Vn in the third stage, and finally input the low level to the third voltage in the fourth and fifth stages, and repeatedly execute the first step in sequence. Phases I to Fifth. The above low level may be 0 volts, and the high level criterion is equal to the voltage of the first voltage source Vdd. As described above, according to the voltage pulse shown in FIG. 3, when pM0s element = 21 is on, NM0s element 22 is not on, and when element u is on, PM0S element 21 is off. As a result, during step 302 and step 303, a capacitance is formed between the source of the pMOS device 21 and the ground terminal Gnd. The step 304 of the earth-electricity step 304 inputs the fourth voltage source to the second terminal 24. In this embodiment, when the voltage value of the fourth voltage source vt remains the same as the voltage of the first terminal 23, the voltage of the PMOS element 21 is measured. The current between the source and the ground terminal Gnd is a first current value. In order to maintain the voltage value of the fourth voltage source vt the same as the voltage value of the first terminal 23, the voltage change of the fourth voltage source vt is shown in FIG. 'When the voltage value of the fourth voltage source V t is constant to zero, measure the current between the source of the p MQ g element 2 1 and the ground terminal Gnd to be a second current value. As described above,' the first current value Is the current flowing through the parasitic capacitance formed between the source of PMqs element 21 and the ground terminal Gnd; and the second current value is the parasitic capacitance and capacitance formed between the source and ground terminal of PMOS element 21 The current of the parallel capacitor of the component 2 0. Step 3 0 5 is based on the first current value, the second current value, and the first voltage source.

第10頁件201的電容值。在本流值、第一電壓源Vdd 以求得電容元件2〇1的第一電流值與第二電流衝週期F，然後，取得之平均值以進行電容的以增加電容量測的精準述依據本發明之實施例與範疇。因此，以上所任何不脫離其精神與範均應包括於後述之申請 ^20442 五、發明說明（8)Page 10 The capacitance value of the device 201. The current value and the first voltage source Vdd are used to obtain the first current value and the second current pulse period F of the capacitor element 201. Then, the average value obtained is used to accurately measure the capacitance to increase the capacitance measurement. Examples and scope of the invention. Therefore, any of the above without departing from its spirit and scope should be included in the application described below ^ 20442 V. Description of the invention (8)

Vdd以及電塵脈衝週期F計算電容元實施例t，將第—電流值、第二電以及電壓脈衝週期F代入式（丨）可電容值。另外’在本實施例中，當量測值時，可以利用量測複數個電壓脈第:電流值之平均值與第二電流值計算，俾使減少電容量測的誤差，度。、任何熟悉5亥項技術者均可進行等效之修改’而不脫離其精神述僅為舉例性’而非為限制性疇而對其進行之等效修改或 : 專利範圍中。The capacitor element is calculated by Vdd and the period of the electric dust pulse F. In the embodiment t, the first current value, the second electric voltage, and the voltage pulse period F are substituted into the formula (丨) capacitance value. In addition, in this embodiment, when measuring the measured value, it is possible to calculate by measuring a plurality of voltage pulses: the average value of the current value and the second current value, so as to reduce the error and degree of capacitance measurement. 2. Anyone familiar with the technology can make equivalent modifications ’without departing from the spirit. The description is merely exemplary and not a limitation of equivalent modifications or: within the scope of patents.

II 第11頁 520442 圖式簡單說明【圖式簡單說明】圖1為一電路圖，顯示CBCM測試結構的電路圖。圖2為一電路圖，顯示依本發明較佳實施例之電容量測電路的電路圖。圖3為一曲線圖，顯示依本發明較佳實施例之電容量測電路中施加於各電壓源的電壓變化。圖4為一流程圖，顯示依本發明較佳實施例之電容量測方法。【圖式符號說明】 2 電容量測電路 201 電容元件 21 PMOS元件 22 NMOS元件 23 第一端子 24 第二端子 241 金屬墊 3 電容量測方法 301 〜305 電容量測方法的流程 Vdd 第一電壓源 Vp 第二電壓源 Vn 第三電壓源 Vt 第四電壓源 Gnd 接地端II Page 11 520442 Schematic description [Schematic description] Figure 1 is a circuit diagram showing the circuit diagram of the CBCM test structure. Fig. 2 is a circuit diagram showing a circuit diagram of a capacitance measuring circuit according to a preferred embodiment of the present invention. Fig. 3 is a graph showing changes in voltage applied to each voltage source in a capacitance measuring circuit according to a preferred embodiment of the present invention. Fig. 4 is a flowchart showing a method for measuring a capacitance according to a preferred embodiment of the present invention. [Symbol description] 2 Capacitance measuring circuit 201 Capacitance element 21 PMOS element 22 NMOS element 23 First terminal 24 Second terminal 241 Metal pad 3 Capacitance measurement method 301 to 305 Process of capacitance measurement method Vdd First voltage source Vp second voltage source Vn third voltage source Vt fourth voltage source Gnd ground terminal

第12頁 520442 圖式簡單說明 c 待測電容Page 12 520442 Schematic description c Capacitance under test

IHBI 第13頁IHBI Page 13

Claims

520442 六、申請專利範圍 1、一種電容量測電路，其係應用於量測一電容元件的電容值，該電容量測電路包含：一PM0S元件；一NM0S元件，該NM0S元件之汲極係電連接至該PM0S元件之汲極；一第一端子，其一端係電連接至該PM0S元件之汲極與該NM0S元件之沒極間，其另一端係電連接至該電容元件之一側；以及一第二端子，其一端係電連接至該電容元件之另一側。 2、如申請專利範圍第1項所述之電容量測電路，其中該第一端子與該第二端子係金屬線，該PM0S元件、該NM0S元 I 件、該第一端子以及該第二端子係形成於一半導體晶片中，且該電容元件係於該半導體晶片中電離之任意二金屬元件。 3、如申請專利範圍第1項所述之電容量測電路，其中該 PM0S元件之源極係電連接至一第一電壓源，該PM0S元件之閘極係電連接至一第二電壓源，該NM0S元件之閘極係電連接至一 _三電壓源，該NM0S元件之源極係電連接至一接地端.，該第二端子之另一端係電連接至一第四電壓源。 4、如申請專利範圍第3項所述之電容量測電路，其中該第520442 VI. Application for Patent Scope 1. A capacitance measuring circuit, which is used to measure the capacitance of a capacitive element. The capacitance measuring circuit includes: a PM0S element; an NMOS element, and the drain of the NMOS element is electrically Connected to the drain of the PM0S element; a first terminal, one end of which is electrically connected between the drain of the PM0S element and the pole of the NM0S element, and the other end of which is electrically connected to one side of the capacitive element; and A second terminal has one end electrically connected to the other side of the capacitor element. 2. The capacitance measuring circuit according to item 1 of the scope of patent application, wherein the first terminal and the second terminal are metal wires, the PM0S element, the NMOS element, the first terminal, and the second terminal Is formed in a semiconductor wafer, and the capacitor element is any two metal elements ionized in the semiconductor wafer. 3. The capacitance measuring circuit according to item 1 of the scope of the patent application, wherein the source of the PM0S element is electrically connected to a first voltage source, and the gate of the PM0S element is electrically connected to a second voltage source. The gate of the NMOS device is electrically connected to a voltage source, the source of the NMOS device is electrically connected to a ground terminal, and the other end of the second terminal is electrically connected to a fourth voltage source. 4. The capacitance measuring circuit as described in item 3 of the scope of patent application, wherein the first

第14頁 520442 六、申請專利範圍四電壓源的電壓值維持與該PM0S元件之汲極與該NM0S元件之〉及極間的電壓值相同。 5 .、如申請專利範圍第3項所述之電容量測電路，其中該第四電壓源的電壓值恆為零。 6、如申請專利範圍第3項所述之電容量測電路，其中該第一電壓源之電壓為穩定之一電壓值。 7、如申請專利範圍第3項所述之電容量測電路，其中該第一電壓源與该第三電壓源具有相同之一電壓脈衝週期。 8、種電谷量測方法，其係利用一電容量測電路來測量一電容元件的電容值，該電容量測電路包含一PM0S元件、一 NM0S元件、—第一端子以及一第二端子，該pM〇s元件之没極係電連接至該NM0S元件之汲極，該第一端子之一端係電連接至该PM0S元件之汲極與該NM0S元件之沒極間，該第一端子之另一端係電連接至該電容元件之一側，該第二端子係電連接至該電容元件之另一側，該NM〇s元件之源極係電連接至一接地端，該電容量測方法包含：輸入一第一電壓源至該PM0S元件之源極，該第一電壓源之電壓為穩定之一電壓值；輸入一第二電壓源至該PM0S元件之閘極；輸入一第三電壓源至該NM0S元件之閘極，該第二電壓Page 14 520442 6. Scope of patent application The voltage value of the four voltage sources remains the same as the voltage between the drain of the PM0S element and the voltage between the PM0S element and the NM0S element. 5. The capacitance measuring circuit as described in item 3 of the scope of patent application, wherein the voltage value of the fourth voltage source is constant to zero. 6. The capacitance measuring circuit as described in item 3 of the scope of patent application, wherein the voltage of the first voltage source is a stable voltage value. 7. The capacitance measuring circuit as described in item 3 of the scope of patent application, wherein the first voltage source and the third voltage source have the same voltage pulse period. 8. An electric valley measurement method, which uses a capacitance measurement circuit to measure the capacitance value of a capacitive element. The capacitance measurement circuit includes a PM0S element, an NMOS element, a first terminal and a second terminal. The pole of the pM0s element is electrically connected to the drain of the NMOS element, and one end of the first terminal is electrically connected between the drain of the PM0S element and the pole of the NMOS element. One end is electrically connected to one side of the capacitor element, the second terminal is electrically connected to the other side of the capacitor element, and the source of the NMOS element is electrically connected to a ground terminal. The capacitance measurement method includes : Input a first voltage source to the source of the PM0S element, and the voltage of the first voltage source is a stable voltage value; input a second voltage source to the gate of the PM0S element; input a third voltage source to The gate of the NMOS device, the second voltage

第15頁 520442 六、申請專利範圍源與該第三電壓源具有相同之一電壓脈衝週期；輸入一第四電壓源至該第二端子；當該第四電壓源的電壓值維持與該PM0S元件之汲極與該NM0S元件之汲極間的電壓值相同時，量測該PM0S元件之源極與該接地端之間的電流為一第一電流值；當該第四電壓源的電壓值恆為零時，量測該PM0S元件之源極與該接地端之間的電流為一第二電流值；以及依據該第一電流值、該第二電流值、該電壓值以及該電壓脈衝週期計算該電容元件的電容值。 9、如申請專利範圍第8項所述之電容量測方法，其中當該 P Μ 0 S元件為導通時’該N Μ 0 S元件為不導通。 f 1 0、如申請專利範圍第8項所述之電容量測方法，其中當該NM0S元件為導通時，該PM0S元件為不導通。Page 15 520442 6. The patent application source has the same voltage pulse period as the third voltage source; input a fourth voltage source to the second terminal; when the voltage value of the fourth voltage source is maintained in line with the PM0S element When the voltage between the drain of the NMOS device and the drain of the NMOS device is the same, measure the current between the source of the PM0S device and the ground terminal as a first current value; when the voltage value of the fourth voltage source is constant When it is zero, measure the current between the source of the PM0S element and the ground terminal as a second current value; and calculate based on the first current value, the second current value, the voltage value, and the voltage pulse period The capacitance value of the capacitive element. 9. The capacitance measuring method according to item 8 of the scope of the patent application, wherein when the P M 0 S element is on, the N M 0 S element is not on. f 1 0. The capacitance measuring method as described in item 8 of the scope of patent application, wherein when the NMOS element is on, the PMOS element is not on.

第16頁Page 16