TW518760B - Solution processing - Google Patents

Abstract

A method for forming an electronic device including an electrically conductive or semiconductive material in a plurality of regions on a substrate, the method comprising: forming a mixture by mixing the material with a liquid; forming on the substrate a confinement structure including a first zone in a first area of the substrate and a second zone in a second area of the substrate, the first zone having a greater repellence for the mixture than the second zone; and depositing the material on the substrate by applying the mixture over the substrate; whereby the deposited material may be confined by the relative repellence of the first zone.

Description

518760 A： 五、發明說明（ 本發明係有關溶液加工處理裝置與用以形成該項 裝置的方法。 半導體共軛聚合物薄膜電晶體（TFTs)近來已應用 於塑膠基體上所整合的便宜、邏輯電路（由C.Drury等 人於1998年發表之第73期APL第108頁），並且也應 用於高解析度主動矩陣顯示器的光電集成裝置與像 素電晶體開關。（由H.Sirringhaus等人於1998年發表 之第 280期 Science 第 1741 頁以及由 A· Dodabalapur 等人於1998年發表之第73期Appl. Phys. Lett·第142 頁）。在具有聚合物半導體與無機金屬電極和閘極介 電層的測試裝置組態中，高效能TFTs已經出現。相 較於非晶矽TFTs的效能，高效能TFTs已達成高達 〇· 1 cm2/Vs的電荷載子流動性與1 〇6_ι 〇8的開-關電流 比（由H· Sirringhaus等人於1999年發表之第39期 Advances in Solid State Physics第 101 頁）。 共軛聚合物半導體的裝置品質薄膜可以藉由塗敷 有機溶劑中的一種聚合物溶液至基體上的方式來形 成。该種技術因此適合於與彈性、塑膠基體相容的 便宜、大區域溶液加工處理。為了要充分利用便宜 且簡易加工處理技術的優點，較佳地，該種裝置中 的所有組件，包括半導體層、介電層以及傳導電極 與互連體便從溶劑中沉積而來。 為了製造全聚合物TFT裝置與電路，必須要克服 的問題如下： 本紙張尺度^ (CNS)A4賴⑵〇 χ 297·^ 頁 部 智 慧 員 工 消 費 印 518760 A7 五、發明說明（ 智 慧 財 員 工 消 費 -多層體結構的完整性：在後續料導體、絕緣 或傳導層的溶液沉積過程中，下墊層不應該藉 由用以在後續層體中沉積的溶劑而被溶解或被 膨脹。如果溶劑無法注入導致該層體性質退化 的下塾層的話，將發生膨脹。 -電極的高解析度型樣化：傳導層必須被型樣化 以形成界定良好的互連體與具有通道長度 Ι^ΙΟμηι的 TFT通道。 -為了要製造TFT電路，必須形成垂直互連區（通 孔）以電氣性地連接該裝置之不同層體中的電 才虽° 在WO99/10939 A2專利申請案中，揭露了一種用 以製造全聚合物TFT的方法，其在該裝置之後續層體 進行沉積之前，藉由轉換裝置的溶液加工處理層為 一種不溶解形式。這項方法可以解決下墊層的溶解 與膨脹問題。然而，它卻嚴重地限制了可使用之半 導體材質的選擇，即僅能使用某些部分不欲的小先 驅物聚合物群。再者，介電閘極絕緣層的互聯使透 過介電層來製造通孔成為難事，因此便需要使用如 機械式穿孔的技術（wo 99/10939 A1)。 根據本發明的第一方面，備置了如附錄之申請專 利範圍中說明的裝置與方法。在獨立申請專利範圍 中亦將說明本發明之較佳特徵。 根據本發明的一方面，備置了一種用以形成一電 訂 I 3 氏張尺度標準（CNS)A4規格⑵Q χ视公[518760 A: 5. Description of the invention (The present invention relates to a solution processing device and a method for forming the device. Semiconductor conjugated polymer thin film transistors (TFTs) have recently been applied to inexpensive, integrated logic integrated on plastic substrates. Circuit (issued by C. Drury et al., No. 73, APL, page 108, 1998), and also applied to optoelectronic integrated devices and pixel transistor switches in high-resolution active matrix displays. (Contributed by H. Sirringhaus et al. In Science Issue No. 280 (1998, page 1741, 1998, and Issue 73 Appl. Phys. Lett, page 142, published by A. Dodabalapur et al. 1998). In polymer semiconductors and inorganic metal electrodes and gate dielectrics In the test device configuration of the electrical layer, high-performance TFTs have emerged. Compared to the performance of amorphous silicon TFTs, high-performance TFTs have achieved charge carrier mobility of up to 0.1 cm2 / Vs and a 〇6_ι 〇8 On-off current ratio (Advances in Solid State Physics, Issue 39, 1999 by H. Sirringhaus et al., Page 101). Device-quality films of conjugated polymer semiconductors can be coated with A polymer solution in a solvent is formed on the substrate. This technology is therefore suitable for cheap, large-area solution processing compatible with elastic, plastic substrates. In order to take full advantage of the advantages of cheap and simple processing technology, Preferably, all components in the device, including the semiconductor layer, the dielectric layer, and the conductive electrodes and interconnects, are deposited from the solvent. In order to manufacture all-polymer TFT devices and circuits, the problems that must be overcome are as follows ： This paper size ^ (CNS) A4 Lai ⑵〇χ 297 · ^ Page of the smart employee consumption stamp 518760 A7 V. Description of the invention (Smart employee consumption-the integrity of the multilayer structure: in the subsequent material conductor, insulation or conductive layer During the solution deposition process, the underlying layer should not be dissolved or expanded by the solvent used to deposit it in the subsequent layer. If the solvent cannot be injected into the underlying layer that degrades the properties of the layer, expansion will occur. -High-resolution patterning of electrodes: the conductive layer must be patterned to form well-defined interconnects with channel lengths I ^ ΙΟ η channel of TFT.-In order to manufacture TFT circuits, vertical interconnect regions (vias) must be formed to electrically connect electricity in different layers of the device. Although disclosed in WO99 / 10939 A2 patent application, A method for manufacturing an all-polymer TFT is provided, in which the processing layer is converted to an insoluble form by converting the solution of the device before the subsequent layers of the device are deposited. This method can solve the dissolution of the underlying layer and the Bloat problem. However, it severely restricts the choice of semiconductor materials that can be used, that is, only certain groups of small precursor polymers that are not desired can be used. Furthermore, the interconnection of dielectric gate insulating layers makes it difficult to make through-holes through the dielectric layer, so technologies such as mechanical perforations (wo 99/10939 A1) are required. According to a first aspect of the present invention, a device and method are provided as described in the scope of the appended patent application. Preferred features of the invention will also be described in the scope of the independent patent application. According to an aspect of the present invention, an I 3 scale standard (CNS) A4 specification ⑵Q χ as a public order is formed to form an electrical order [CNS]

I 518760I 518760

"發明説明（ 特徵，其以具有不同比例之二電晶體的尺寸W/L的印刷全 聚合物TFTs來製造； 第1 7圖顯示替代底閘極裝置組態； 第18(a)-(b)圖為主動矩陣像素的結構圖，其中顯 示器或記憶體元件由一電壓（a)或一電流（b)所控制； 第19(a)-(c)圖顯示一主動矩陣之像素的可能組 態； 第20圖顯示一對準F8T2 TFT的極化光學吸收； 第21圖顯示（a)藉由半導體與介電層印製法來製造之 具有型樣化主動層島狀物的聚合物TFTs;以及（b)由印 刷絕緣島狀物所分開之傳導互連體之間的重疊區域； 第22圖顯示由|jp互連體網路所連接之電晶體裝 置的矩陣，以製造使用者定義之電子電路。 在此所說明之較佳製造方法將允許製造全有機、 溶液加工處理薄膜電晶體，其中沒有任何層體將被 轉換或互連為不溶解形式。該裝置中的每層體可維 持在可溶解於所沉積之溶劑的形式。如將以下將詳 細說明的，這將可以根據局部溶劑沉積，透過介電 絕緣層以簡單的方式來製造通孔。例如，該項裝置 將包含一個或多個以下的組件： -已型樣化之傳導源極·沒極與閘極與互連體。 半導體層’其具有超過〇.〇1(：1712/>^的電荷載 子流動性與超過1 〇4之高開-關電流轉換比。 -一薄閘極絕緣層。 (請先閲讀背面之注意事項再填寫本頁) -裝丨 訂— :線丨 518760 A7 五、發明說明（ --擴散屏障層’其保護該半導體層與絕緣層， 使它們免於因著雜質與離子擴散而引起的意外 推雜。 -一表面改造層，其利用印製技術可以達成閘極 的高解析度型樣化。 -透過介電層對互連體的通孔。 然而，所欲的是此處所說明之方法並不限於具有 上述所有特徵之裝置的製造方法。 現在將參照第1圖來說明第一例示裝置的製造方 法。第1圖中的裝置為一薄膜場效電晶體（丁FT)，其 被組配以具有一頂閘極結構。 在已清除7059玻璃基體1的頂端，源極_没極2與 3 ’以及電極與接觸襯塾（未顯示）之間的互連線將利 用噴墨印製法來沉積一種水性傳導聚合物聚乙烯二 氧噻吩/聚苯乙烯基磺酸（PEDOT (0.5重量比）/PSS (0·8重量比））的溶液。其他的溶劑，例如甲醇、乙醇、 異丙醇或丙酮也可以加入以影響油墨的表面張力、 黏性與濕潤性質。PEDOT/PSS可以從Bayer公司（如 "Baytron P")商用性地取得。丨jp列印機為壓電型。 它設備有準確度二維轉換台以及顯微台，其使後續 印刷型樣可以相互對準。丨JP列印頭利用電壓脈衝來 驅動。在20V脈衝高度下，上升時間為10PS，且下 降時間為10ps時，可以達成注入每滴〇.4ng之典型固 體含量的適當驅動條件。在玻璃基體上進行乾燥之 (請先閱讀背面之注意事項再填寫本頁) --------訂---------線 0 經濟部智慧財產局員工消費合作社印製 10 518760 A7 B7" Explanation of the invention (characteristics, which are made of printed all-polymer TFTs with different ratios of two transistor sizes W / L; Figure 17 shows an alternative bottom gate device configuration; Figures 18 (a)-( b) The figure shows the structure of an active matrix pixel, in which the display or memory element is controlled by a voltage (a) or a current (b); Figures 19 (a)-(c) show the possibility of pixels of an active matrix Configuration; Figure 20 shows a polarized optical absorption aligned with F8T2 TFT; Figure 21 shows (a) polymer TFTs with patterned active layer islands manufactured by semiconductor and dielectric layer printing And (b) overlapping areas between conductive interconnects separated by printed insulating islands; Figure 22 shows a matrix of transistor devices connected by the | jp interconnect network to create user-defined Electronic circuits. The preferred manufacturing method described here will allow the manufacture of fully organic, solution-processed thin film transistors where no layers will be converted or interconnected to an insoluble form. Each layer in the device can Maintain in a form that is soluble in the deposited solvent. As will be explained in detail, this will allow the vias to be made in a simple manner through a dielectric insulation layer based on local solvent deposition. For example, the device will contain one or more of the following components:-a patterned conductive source Electrode, electrode and gate, and interconnect. The semiconductor layer has a charge carrier mobility exceeding 0.011 (: 1712 / > ^) and a high on-off current conversion ratio exceeding 104.- A thin gate insulation layer. (Please read the precautions on the back before filling out this page)-Binding 丨 Binding:: Line 518760 A7 V. Description of the invention (--Diffusion barrier layer 'which protects the semiconductor layer and the insulation layer, Protect them from accidental impurities caused by the diffusion of impurities and ions.-A surface modification layer, which uses printing technology to achieve high-resolution patterning of the gate.-The dielectric layer is used to interconnect the interconnects. However, what is desired is that the method described here is not limited to a method of manufacturing a device having all of the features described above. A method of manufacturing a first exemplary device will now be described with reference to FIG. 1. The device in FIG. 1 is A thin film field effect transistor (DFT) It is assembled with a top gate structure. At the top of the cleared 7059 glass substrate 1, the interconnections between the source electrodes _ 2 and 3 ′ and the electrodes and the contact lining (not shown) will use spray Ink printing method to deposit a solution of water-conductive polymer polyethylenedioxythiophene / polystyrenesulfonic acid (PEDOT (0.5 weight ratio) / PSS (0 · 8 weight ratio)). Other solvents, such as methanol, ethanol , Isopropyl alcohol or acetone can also be added to affect the surface tension, viscosity and wetting properties of the ink. PEDOT / PSS can be commercially obtained from Bayer (such as " Baytron P "). Jp printer is piezoelectric type. Its equipment has a precision 2D conversion stage and a micro stage, which enables subsequent printing patterns to be aligned with each other.丨 JP print head is driven by voltage pulse. At 20V pulse height, when the rise time is 10PS and the fall time is 10ps, an appropriate driving condition for a typical solid content of 0.4 ng per drop can be achieved. Drying on the glass substrate (please read the precautions on the back before filling this page) -------- Order --------- line 0 10 518760 A7 B7

經 濟- 部 智 慧- 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（ 後’它們將產生具有典型直徑為5〇μηι的與典型厚度 為500Α的PEDOT點狀物。 源極-汲極的IJP於空中進行。此後，樣本將轉移 到一惰性氣體乾燥箱中。基體將隨後在有機溶劑中 進行旋轉式脫水，該溶劑隨後將用來進行主動半導 體層的沉積，例如在聚苟聚合物中的混合二甲笨。 它們隨後將在200°c的惰性氮氣體中進行退火2〇分 鐘，以移除PEDOT/PSS電極中的殘餘溶劑與其他揮 發性物質。隨後’該主動半導體聚合物4的2〇〇_ι 〇〇〇a 厚膜將利用旋轉式塗敷法來進行沉積。已經使用多 種不同半導體聚合物，例如正常位向聚-3_乙基噻吩 (P3HT)，以及例如聚_9,9，-二辛芴·共-二噻吩（FBT2) 的聚芴共聚合物。FBT2為一較佳的選擇，因為當在 空氣中進行閘極的沉積時，它在空氣中可呈現良好 穩定性，。一無水、混合二曱苯（自R〇mi丨購得）之5_ 1〇mg/ml的FBT2溶液，將於1500_2〇〇〇rpm進行旋轉 塗敷。以P3HT而言，將使用混合二甲笨中重量百分 比為1的溶液。下墊PEDOT電極不溶解於非極性有機 溶劑中，例如二甲苯。膜體隨後在溶劑中進行旋轉 式脫水，而該溶劑為稍後將用以進行閘極絕緣層5沉 積的溶劑，例如異丙醇或曱醇。 後續退火步驟將隨後進行，以提昇半導體聚合物 的電荷傳輸性質。對在高溫中呈現液晶狀相的聚合 物來說，在高於液晶狀轉換的溫度下進行退火將導 11Economy-Ministry of Wisdom-Property Bureau Printed by Consumer Cooperatives V. Invention Description (After 'they will produce PEDOT dots with a typical diameter of 50 μηι and a typical thickness of 500 A. Source-drain IJP in the air After that, the sample will be transferred to an inert gas drying box. The substrate will then be spin-dehydrated in an organic solvent, which will then be used to deposit active semiconductor layers, such as in polymer 2 Jiaben. They will then be annealed in an inert nitrogen gas at 200 ° C for 20 minutes to remove residual solvents and other volatile substances in the PEDOT / PSS electrode. Subsequently, the '200 of the active semiconductor polymer 4 _ι 〇〇〇〇a thick film will be deposited using a spin-on coating method. A number of different semiconductor polymers have been used, such as normal-orientation poly-3_ethylthiophene (P3HT), and for example poly_9,9, -Dioctylpyrene-co-dithiophene (FBT2) polyfluorene copolymer. FBT2 is a better choice because it exhibits good stability in air when the gate electrode is deposited in air. A 5-10 mg / ml FBT2 solution of anhydrous, mixed xylene (commercially available from Romi) will be spin-coated at 1500-200 rpm. For P3HT, mixed xylene The solution is a weight percentage of 1. The underlying PEDOT electrode is not dissolved in a non-polar organic solvent, such as xylene. The membrane is subsequently spin-dehydrated in a solvent that will be used later for gate insulation Solvent deposited in layer 5, such as isopropanol or methanol. Subsequent annealing steps will be performed subsequently to improve the charge transport properties of the semiconducting polymer. For polymers that exhibit a liquid-crystalline phase at high temperatures, Annealing at the transition temperature will lead to 11

經濟部智慧財產局員工消費合作社印製 518760 A7 ------------ 五、發明說明（会 致聚合物鏈相互平行。以F8T2而言，退火過程在惰 性N2氣體中於285X進行20分鐘。樣本將隨後快速 地冷卻至室溫’以凝固鏈向並產生一種非晶玻璃。 如果樣本配製於平面玻璃基體上且沒有對準層的 活，聚合物將採用一種多缚組態，其中具有隨機向 之多種液晶狀疇將位於TFT通道中。利用從液晶狀相 的冷卻來配製其中之F8T2於玻璃化狀態中的電晶體 裝置，將呈現5.1〇-3cm2/Vs等級的流動性，其將不只 高於具有旋轉性F8T2膜之裝置上所測量的流動性一 個數量級。已沉積裝置同時呈現較高的開啟電壓v。。 這將歸因於玻璃化相位中，定域電子補集態的較低 密度’相較於部分晶狀之沉積相位。 如果聚合物配製於具有平行於電晶體通道之聚合 物鏈的單軸調整的一種單疇狀態中，藉由典型的3_5 因數便可以得到流動性的更進一步改良。這可藉由 塗敷具備適當調整層於玻璃基體上來達成，例如機 械式摩擦的聚醯亞胺層（第1圖（b)中的9)。在單疇狀 態中，聚合物鏈單軸地以平行於下墊聚醯亞胺層的 摩擦方向來進行對準。這將導致裝置中電荷載子流 動性的再次增強’其中TFT通道平行於該鏈的調整方 向。該項過程將在申請中之英國專利申請案 9914489.1中作更詳細的說明。 在半導體層的沉積後，閘極絕緣層5利用旋轉塗 敷一種極性溶劑的聚烴基笨烯（又稱聚乙烯酚（PVP)) 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線 « 518760Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 518760 A7 ------------ V. Description of the invention (will cause the polymer chains to be parallel to each other. In the case of F8T2, the annealing process is performed in an inert N2 gas. 285X for 20 minutes. The sample will then be quickly cooled to room temperature 'to freeze the chain and produce an amorphous glass. If the sample is formulated on a flat glass substrate without an alignment layer, the polymer will use a multi-binding group State, in which a variety of liquid crystal-like domains with random orientations will be located in the TFT channel. Using cooling from the liquid crystal-like phase to prepare the transistor device in which F8T2 is in the vitrified state, it will present a flow of 5.10-3cm2 / Vs level. It will not only be an order of magnitude higher than the flowability measured on a device with a rotating F8T2 film. The deposited device also exhibits a higher opening voltage v at the same time. This will be attributed to the localized electronic compensation in the glass transition phase. The lower density of the aggregate state is compared to the partially crystalline deposition phase. If the polymer is formulated in a single domain state with uniaxial adjustment of the polymer chain parallel to the transistor channel, by a typical A further improvement in fluidity can be obtained by a factor of 3_5. This can be achieved by coating a glass substrate with a suitable adjustment layer, such as a mechanically rubbed polyimide layer (9 in Figure 1 (b)). In the single-domain state, the polymer chains are aligned uniaxially parallel to the rubbing direction of the underlying polyimide layer. This will cause the charge carrier mobility in the device to be enhanced again, where the TFT channels are parallel to the The adjustment direction of the chain. This process will be described in more detail in the pending British patent application 9914489.1. After the semiconductor layer is deposited, the gate insulating layer 5 is spin-coated with a polar solvent of polyalkylene styrenic ( Also known as Polyvinylphenol (PVP)) 12 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order ------- -Line «518760

五、發明說明（抝 經濟部智慧財產局員工消費合作社印製 的一種溶液來沉積，其中下墊半導體聚合物是不溶 解的。溶劑的較佳選擇為醇類，例如甲、2_丙醇戈 丁醇，其中例如FBT2非極性聚合物具有意想不到的 低溶解度，並且不會膨脹。閘極絕緣層的厚度介於 300nm之間（溶液濃度為30mg/m丨）與彳3μηι(溶液濃度 為100mg/ml)。也可以使用滿足溶解度要件的其他的 絕緣聚合物與溶劑，例如水性聚乙烯醇（PVA)或丙烯 乙一醇甲基酯乙酸鹽性的聚-異丁稀鹽甲酉旨 (PMMA) 〇 閘極6隨後將在閘極絕緣層上沉積。該閘極絕緣 層可以直接地沉積在閘極絕緣層上（參看第1圖（c))， 或者例如因著表面改造、擴散屏障或如溶劑相容性 的過程因素等’可有一層或多層的中間層體（參看第 1 圖（a)與（b))。 為了形成第1圖（c)中較簡單的裝置，PEDOT/PSS 閘極6可以直接地印刷在p v P絕緣層5的頂部。基體 將再次的轉換到空中的丨JP台，其中PEDOT/PSS閘 極型樣將自一種水性溶液中印刷。下墊PVP閘極絕 緣層在水中具有低溶解度，以使閘極電介的整合在 PEDOT/PSS閘極的印刷過程中被保留。雖然pvp含 有咼密度的極性烴基，其在水中的溶解度是低的， 因著相當非極性聚苯乙烯類之骨架的因素。第2圖顯 示具有一 FBT2半導體層、一 PVP閘極絕緣層與|jp PEDOT/PSS源極·沒極與閘極之一丨JP TFT的轉換特 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------1---------^ (請先閱讀背面之注意事項再填寫本頁) 518760V. Description of the invention (拗 A solution printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs for deposition, in which the underlying semiconductor polymer is insoluble. The preferred choice of solvent is alcohol, such as formazan and 2-propanol. Butanol, of which, for example, FBT2 non-polar polymer has unexpectedly low solubility and does not swell. The thickness of the gate insulation layer is between 300nm (solution concentration is 30mg / m 丨) and 彳 3μηι (solution concentration is 100mg / ml). Other insulating polymers and solvents that meet the solubility requirements can also be used, such as water-based polyvinyl alcohol (PVA) or propylene glycol monomethyl acetate acetate poly-isobutylene salt methyl ester (PMMA) 〇Gate 6 will then be deposited on the gate insulating layer. The gate insulating layer can be deposited directly on the gate insulating layer (see Figure 1 (c)), or for example due to surface modification, diffusion barrier or such as There may be one or more interlayers in the process factors of solvent compatibility (see Figure 1 (a) and (b)). In order to form the simpler device in Figure 1 (c), the PEDOT / PSS gate Pole 6 can be printed directly on pv P The top of the edge layer 5. The substrate will be converted to the airborne JP station again, in which the PEDOT / PSS gate pattern will be printed from an aqueous solution. The underlying PVP gate insulation layer has low solubility in water to make the gate The integration of the polar dielectric is preserved during the printing process of the PEDOT / PSS gate. Although pvp contains a polar hydrocarbon group with a fluorene density, its solubility in water is low due to the relatively non-polar polystyrene backbone. Figure 2 shows an FBT2 semiconductor layer, a PVP gate insulation layer and | jp PEDOT / PSS source, non-pole and gate 丨 JP TFT conversion feature 13 This paper standard applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) ^ -------- 1 --------- ^ (Please read the notes on the back before filling this page) 518760

五、發明說明（t 經濟部智慧財產局員工消費合作社印製 徵。該裝置的特徵在氮氣中進行測量。連續測量值 將分別顯示增強（向上三角形）與減弱（向下三角形）的 閘極電壓。該特徵屬於用新配置批料與一年前之 PEDOT/PSS (Baytron P)的批料所製成的裝置。然 而，電晶體動作是清晰可見的，該裝置將呈現一種 具有正極定限電壓V〇>10V的不尋常通常開啟狀態， 而以已蒸發金源極-汲極與閘極製成的參考裝置將呈 現通常關閉的狀態（vo<0)。在以pED0T(第2圖（b))之 "一年前"批料形成的裝置中，將觀察到大滯變效應， 其將歸因於移動性離子雜質（請看以下）的高濃度。如 果掃掠動作開始於極盡空乏狀態（Vg=+40v)，該電晶 體將於vfe+2〇v時（向上三角形）開啟。然而，在相反 掃掠動作中（向下三角形），該電晶體只在▽「。>+35乂時 關閉。 因著該裝置中之一層體的離子物質擴散，通常開 啟狀態與滯變效應將可能發生。通常大正值的V。暗 示著離子是負極的。一正極物質可被預期，以補償 累積層中某些移動電荷，並且將V。轉換到較負極的 數值。為了要鑑別離子物質的來源，便製造裝置， 其中頂閘極丨JP PEDOT由一已蒸發金極來替代，而 其他層體與PEDOT源極/沒極都如上述方式製造。已 發現的是，在此組態中，裝置是通常關閉的，並且 呈現穩定的定限電壓。此將暗示著在全聚合物裝置 中的摻雜與滯變效應都將相關於傳導聚合物頂閘極 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (t Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The characteristics of this device are measured in nitrogen. Continuous measurement values will show the gate voltage increased (upward triangle) and weakened (downward triangle) respectively. This feature belongs to the device made with the new configuration batch and the PEDOT / PSS (Baytron P) batch one year ago. However, the transistor action is clearly visible, and the device will present a positive voltage with a fixed limit V0> 10V is usually turned on normally, while a reference device made of evaporated gold source-drain and gate will show a normally closed state (vo < 0). In pED0T (Figure 2 ( b)) In the device of "one year ago" batch formation, a large hysteresis effect will be observed, which will be attributed to the high concentration of mobile ionic impurities (see below). If the sweeping action starts at In the extremely empty state (Vg = + 40v), the transistor will turn on at vfe + 20v (upward triangle). However, in the opposite sweeping action (downward triangle), the transistor is only in the "▽". > Close at +35 乂. The diffusion of ionic species in one of the layers will usually occur and the hysteresis effect may occur. Usually a large positive value of V. It implies that the ions are negative. A positive substance can be expected to compensate for some moving charges in the accumulated layer And convert V. to a more negative value. In order to identify the source of ionic substances, a device is manufactured, in which the top gate electrode JP PEDOT is replaced by an evaporated gold electrode, and the other layers and the PEDOT source electrode are not The poles are manufactured as described above. It has been found that in this configuration, the device is normally turned off and presents a stable constant voltage limit. This would imply both doping and hysteresis effects in all-polymer devices Will be related to conductive polymer top gate 14 This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm)

518760 A7 經 濟 部 智 慧 財 產 局 員 工 消 f 合 作 社 印 製 五、發明說明（^2 的溶液沉積，並且PED〇T溶液/膜中的之移動、離子 雜質將可能擴散到到裝置下墊層體。 已發現的是，藉由在已加熱基體上沉積閘極，可 能可以控制定限電壓的數值並且減低滯變量。這將 減低基體上微滴的乾燥時間。第3圖（b)顯示一 TFT裝 置的轉換特徵，其中在閘極的沉積過程中，基體將 加熱到50°c的溫度。可以看見的是，滯變效應將遠 小於至溫中的閘極（第3b圖），並且V。具有相對小的6V 正值。藉由控制沉積溫度，該定限電壓可以在 20V的範圍中進行調整。 如第1圖（c)所示之直接沉積在pvp層上面且具有 閘極的裝置為空乏型態。對空乏_型態邏輯電路，例 如簡單空乏-載入邏輯轉換器（第14圖0))來說，通常 開啟狀態是有用的。 為了要製造增強·型態通常關閉TFTs，在閘極的 沉積過程中，藉由合併擴散屏障層，可避免半導體 的摻雜將。在第1圖（a)與（5)的裝置中，在傳導聚合 物閘極進行沉積之前，一非極性聚合物將沉積在pvp 閘極絕緣層的頂部。該層體可以作為擴散屏障，以 阻礙離子物質擴散到適度極性PVP絕緣體。PVP包含 高密度的極性烴基，其將易於增強離子傳導且擴散 至該薄膜的的傳導性與擴散性。數個非極性聚合物 已經被使用，例如聚_9,9，_二辛基苟（F8)、聚苯乙烯 (PS)、t(9,9·二辛基苟·共(‘丁基苯基）二苯胺） ^--------^---------^ (請先閱讀背面之注意事項再填寫本頁) 15518760 A7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs printed by the cooperative. V. Invention description (^ 2 solution deposition, and the movement of PEDOT solution / membrane, ionic impurities may spread to the underlying body of the device. It was found that by depositing a gate electrode on a heated substrate, it is possible to control the value of the limiting voltage and reduce the hysteresis. This will reduce the drying time of the droplets on the substrate. Fig. 3 (b) shows a TFT device. Conversion characteristics, in which the substrate will be heated to a temperature of 50 ° C during the deposition of the gate. It can be seen that the hysteresis effect will be much smaller than that of the gate to mid-temperature (Figure 3b), and V. has a relative A small positive value of 6V. By controlling the deposition temperature, the fixed limit voltage can be adjusted in the range of 20V. As shown in Figure 1 (c), the device with a gate electrode directly deposited on the pvp layer is empty. For empty-type logic circuits, such as simple empty-load logic converters (Figure 14 Figure 0)), the on-state is usually useful. In order to make enhancements, TFTs are usually turned off. During the gate deposition process, the semiconductor can be avoided by incorporating a diffusion barrier layer. In the device of Figures 1 (a) and (5), a non-polar polymer is deposited on top of the pvp gate insulation layer before the conductive polymer gate is deposited. This layer can act as a diffusion barrier to prevent ionic species from diffusing into moderately polar PVP insulators. PVP contains a high density of polar hydrocarbon groups that will easily enhance the conductivity and diffusivity of ionic conduction and diffusion into the film. Several non-polar polymers have been used, such as poly-9,9, -dioctylgo (F8), polystyrene (PS), t (9,9 · dioctylgo * co ('butylbenzene Based) diphenylamine) ^ -------- ^ --------- ^ (Please read the notes on the back before filling out this page) 15

經濟部智慧財產局員工消費合作社印製 (TFB)或F8T2。5(M〇〇nm等級之聚合物薄膜可以從 如一甲苯的非極性有機溶劑的溶液，沉積在pvp閘 極絕緣層的表面上，其中PVP為不溶解的。 已經發現的是，因為極差濕潤性質與大接觸角度 的關係，直接從水性極性溶液將PED0T/PSS印刷在 非極性擴散屏障層的頂部是有問題的。為了要解決 此問題，表面改造層8將沉積在非極性聚合物的頂 邛。該層體提供一親水表面而不是忌水表面，在該 表面上PEDOT/PSS可以更輕易的形成。這將允許閘 極型樣的高解析度印製。為了形成表面改造層，pvp 薄層可以從異丙醇溶液中沉積，其中下墊擴散屏障 層為不溶解的。PVP層的厚度較佳地少於5〇nm。 PEDOT/PSS的高解析度印製在pvp表面是可能的。 也可以使用替代表面改造層。這包含如類皂表面活 化劑的薄層，或者包含親水與忌水官能基的聚合物。 這些分子將傾向於與忌水與親水基分開相位，其分 別被吸引至具備下塾非極性聚合物與空白表面的介 面。另一可能性是，非極性擴散屏障的表面將暴露 在輕度〇2氣體中，使得表面成為親水性的。 如果閘極電極是從極性少於水之溶劑印製而來， 例如包含醇類（異丙醇、甲醇等）的配方，非極性擴散 屏障體上的表面改造層可以不需要。 層體順序的整合將依賴於來自極性與非極性溶劑 之聚合物材質的交替沉積。所欲的是，使用為第二 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事項再 --- t填寫本頁) · -·1 n n . 經濟部智慧財產局員工消費合作社印製 518760 A7 B7 五、發明說明（i4 層體沉積之溶劑中的第一層溶解度將小於每容積0.1 重量百分比，較佳地小於每容積0.01重量百分比。 同時所欲的是，Hildebrand溶解度參數中的差異， 其中介於第一層體材質與用以沉積第二層體的溶劑 之間的合格極性度將盡可能大（由D.W· van Krevelen 於1990年在阿姆斯特丹市Elsevier所發表之 Properties of Polymer) 〇 b 對某些裝置組態來說，利用聚合物的替換順序可Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (TFB) or F8T2.5. Polymer films of 5,000 nm grade can be deposited on the surface of pvp gate insulation layer from a solution of a non-polar organic solvent such as toluene. Among them, PVP is insoluble. It has been found that it is problematic to print PEDOT / PSS directly on top of the non-polar diffusion barrier layer from an aqueous polar solution because of the poor wetting property and large contact angle. In order to solve For this problem, the surface modification layer 8 will be deposited on top of the non-polar polymer. The layer body provides a hydrophilic surface instead of a water-repellent surface on which PEDOT / PSS can be formed more easily. This will allow a gate type In order to form a surface modification layer, a thin pvp layer can be deposited from an isopropanol solution, wherein the underlying diffusion barrier layer is insoluble. The thickness of the PVP layer is preferably less than 50 nm. High-resolution PEDOT / PSS printing is possible on pvp surfaces. Alternative surface modification layers can also be used. This includes thin layers such as soap-like surfactants, or polymerizations that include hydrophilic and water-repellent functional groups These molecules will tend to be separated from the water-repellent and hydrophilic groups, which will be attracted to the interface with the lower non-polar polymer and the blank surface. Another possibility is that the surface of the non-polar diffusion barrier will be exposed to mild 〇2 gas, make the surface hydrophilic. If the gate electrode is printed from a solvent with less polarity than water, such as a formula containing alcohols (isopropyl alcohol, methanol, etc.), on a non-polar diffusion barrier The surface modification layer may not be required. The integration of the layer sequence will depend on the alternate deposition of polymer materials from polar and non-polar solvents. What is desired is that the second paper size applies the Chinese National Standard (CNS) A4 Specifications (210 χ 297 mm) (Please read the notes on the back before t-fill this page) ·-· 1 nn. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 518760 A7 B7 V. Invention Description (i4 The solubility of the first layer in the layer-deposited solvent will be less than 0.1 weight percent per volume, preferably less than 0.01 weight percent per volume. What is desired is the Hildebrand solubility parameter The difference between the first layer material and the solvent used to deposit the second layer will be as high as possible (Properties of Polymer, published by DW van Krevelen in Elsevier, Amsterdam, 1990 ) 〇b For some device configurations, the polymer replacement sequence can be used

以建立全多層體結構，該聚合物主要包含極性基且 可溶解於如水的高度極性溶劑中，以及只包含一些 或者不包含任何極性基且溶解於如二甲苯之非極性 溶劑中的聚合物。實例之一為電晶體裝置，其包含 PED0T/PSS的高度極性源極汲極、如FBT2非極性 半導體層、如從水沉積而來之聚乙烯醇的高度極性 閘極介電層、同時可作為一緩衝層以允許層體順序 | 的沉積的TFB非極性擴散屏障層，以及PED0T/PSS 閘極。 然而，也有可能建立一層體順序，其包含夾在一 高度極性與一非聚合物之聚合物層中間並且自一適 度極性溶劑中沉積的一適度極性聚合物層。一適度 ' 極性聚合物為一種聚合物，其包含極性與非極性基， 並且實質上是不溶解於一高度極性溶劑中。相似地， 一適度極性溶劑包含極性與非極性基，但實質上並 不溶解一非極性聚合物。該適度極性聚合物可同時 17 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------^---------^ (請先閱讀背面之注意事項再填寫本頁) 五、發明說明（j|5 包含一特定官能基，例如一烴基，其使它溶解於一 種包含一官能基的溶劑中，且該官能基將被吸引至 該聚合物。該聚合物的功能性可以被用來增進適度 極性溶劑中的溶解度，且降低在極性溶劑中的溶解 度。該適度極性聚合物的實例之一為一 pVp閘極介 電層’其灸在一非極性半導體層與一 PEDOT/PSS閘 極電極層之間（第伙圖）。適度極性溶劑的一實例為烷 醇。 第4圖顯示具有PVP閘極絕緣層、F8擴散屏障層 與PVP表面改造層之全聚合物F8T2 UP TFT的輸出 端（a)與轉換特徵（b)，如第1圖（a)所顯示（L=5〇fJm)。 該裝置呈現乾淨、近乎理想的通常關閉電晶體動作， 其在v0^ov開啟。介於向上（向上三角形）與向下（向下 三角形）電壓掃掠動作之間的定限電壓轉換為UV。 該裝置的特徵相當相似於在惰性氣體環境下製造且 具備金源極-汲極與閘極之標準裝置的特徵。場效流 動性的等級為0·005-0·01 cm2/vs，並且在Vg=0與-6〇v 之間所測量到的開-關電流比例為1 Ο4” 〇5等級。 裝置已經被製造為具有大範圍非極性擴散屏障 層，例如FB、TFB(第5(a)圖顯示轉換特徵）、ps(第5(b) 顯示轉換特徵）與FBT2。在每種狀況下，將觀察乾淨 且通常關閉的狀況、小滯變效應與定限電壓轉換， 其與具有金源極_沒極之參考裝置有相同重量級。這 將支持在閘極絕緣層的溶液沉積過程中與其後，在 518760 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 A7 閘極下之***非極性聚合物會阻擋離子雜質擴散的 數據整理分析。已將發現會產生再現丁[::丁定限電壓與 良好操作定性。 包含一擴散屏障的通常關閉裝置較佳地比較於上 述的二乏_型悲裝置，因為已期望前者可呈現較長時 間定限電壓穩定性與較長壽命，因為離子擴散已受 到抑制。 對半導體層來說，可使用任何可處理共軛聚合物 或寡聚物材質的溶液，其呈現超過1〇-3cm2/Vs，較佳 地超過10-2Cm2/VS的足夠的場效流動性。適當材質將 在貫例中檢驗，例如由H_E_ Katz與J· Mater二人在 1997年所發表之第7期Chem·第369頁，或由ζ· Bao 於2000年所發表之第12期Advanced Materials第 227 頁。 製造具有良好穩定性與高開-關電流比之印刷 TFTs的重要要件之一便是半導體材質的良好穩定 性，其可抵抗在加工處理與印製步驟中氧氣與水的 非意圖摻雜。已經利用多種半導體聚合物來製造印 刷TFTs，作為主動半導體層，例如FBT2(參看上述 說明），或從混合二曱苯溶液中沉積的正常位向 P3HT。以P3HT來說，對在惰性氣體下以測試裝置 組態配置的TFTs而言，〇.05_〇1cm2/Vs的場效流動 性是稍高於利用F8T2的狀況。然而，對於氧或水的 摻雜來說，正常位向P3HT是不穩定的，將導致在印 19In order to establish a full multilayer structure, the polymer mainly contains polar groups and is soluble in a highly polar solvent such as water, and a polymer containing only some or no polar groups and dissolved in a non-polar solvent such as xylene. One example is a transistor device, which contains a highly polar source drain of PEDOT / PSS, such as a non-polar semiconductor layer of FBT2, a highly polar gate dielectric layer such as polyvinyl alcohol deposited from water, and can also be used as A buffer layer with a deposited TFB non-polar diffusion barrier layer and a PEDOT / PSS gate to allow the layer sequence. However, it is also possible to establish a bulk sequence comprising a moderately polar polymer layer sandwiched between a highly polar and a non-polymeric polymer layer and deposited from a moderately polar solvent. A moderately polar polymer is a polymer that contains polar and non-polar groups and is substantially insoluble in a highly polar solvent. Similarly, a moderately polar solvent contains polar and non-polar groups, but does not substantially dissolve a non-polar polymer. This moderately polar polymer can be used simultaneously on 17 paper sizes in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) ^ -------- ^ --------- ^ (please first Read the notes on the back and fill in this page again.) 5. Description of the invention (j | 5 contains a specific functional group, such as a hydrocarbon group, which makes it dissolve in a solvent containing a functional group, and the functional group will be attracted to The polymer. The functionality of the polymer can be used to increase the solubility in moderately polar solvents and reduce the solubility in polar solvents. One example of a moderately polar polymer is a pVp gate dielectric layer. Moxibustion is between a non-polar semiconductor layer and a PEDOT / PSS gate electrode layer (figure). An example of a moderately polar solvent is alkanol. Figure 4 shows a PVP gate insulation layer, an F8 diffusion barrier layer, and The output end (a) and conversion characteristics (b) of the all-polymer F8T2 UP TFT of the PVP surface modification layer are as shown in Figure 1 (a) (L = 50fJm). The device presents a clean, almost ideal, and usually Turn off the transistor action, which is turned on at v0 ^ ov. Between the upward (upward triangle) and The fixed voltage between the down (down triangle) voltage sweeping action is converted to UV. The characteristics of this device are quite similar to those of a standard device manufactured in an inert gas environment and equipped with a gold source-drain and gate. The level of field effect fluidity is 0 · 005-0 · 01 cm2 / vs, and the on-off current ratio measured between Vg = 0 and -60 volts is a level of 104 ″ 〇5. The device has been Manufactured with a wide range of non-polar diffusion barrier layers, such as FB, TFB (figure 5 (a) shows transition features), ps (figure 5 (b) shows transition features), and FBT2. In each case, you will observe a clean And the normally closed condition, small hysteresis effect, and fixed voltage switching are of the same weight as a reference device with a gold source electrode. This will support the solution deposition process of the gate insulation layer and thereafter, in the 518760 V. Description of the invention (Data printed and analyzed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs printed A7. Insertion of non-polar polymer under the gate will block the diffusion of ionic impurities. It has been found that it will produce a reproducible voltage [:: 丁 定 定 值Qualified with good operation. Includes an expansion The normal closing device of the barrier is better compared with the above-mentioned two-type device, because it has been expected that the former can exhibit longer time-limited voltage stability and longer life because ion diffusion has been suppressed. For the semiconductor layer Any solution that can process conjugated polymer or oligomer materials can be used, which exhibits sufficient field effect fluidity in excess of 10-3cm2 / Vs, preferably more than 10-2Cm2 / VS. Appropriate materials will be used throughout Examination in the example, for example, H_E_ Katz and J. Mater, published in 1997 in the seventh issue of Chem. P. 369, or by z. Bao in 2000, published in the 12th issue of Advanced Materials, p. 227. One of the important requirements for manufacturing printed TFTs with good stability and high on-off current ratio is the good stability of the semiconductor material, which can resist the unintentional doping of oxygen and water during processing and printing steps. Various semiconductor polymers have been used to make printed TFTs as active semiconductor layers, such as FBT2 (see above), or normal orientation P3HT deposited from a mixed xylene solution. In the case of P3HT, the field effect fluidity of 0.05 to 0.01 cm2 / Vs for TFTs configured in a test device configuration under inert gas is slightly higher than that of F8T2. However, for oxygen or water doping, the normal orientation of P3HT is unstable and will cause

III — — — · I I (請先閱讀背面之注意事項再填寫本頁) ί線· 518760 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（fj 製步驟中空氣與不佳開-關電流比之膜體傳導性的增 加。這有關於P3HT的相對低電離勢，|ρ^4·9 eV。小 於106之高開-關電流比例已為P3HT顯示，但在進行 沉積之後，需要一還原去除摻雜步驟，例如暴露在 肼蒸氣下（由H· Sirringhaus等人於1999年所發表之 第 39期 Advances in Solid State Physics第 頁）。 然而，在上述的UP TFTs上，該還原後加工處理步 驟不能進行，因為它將同時導致PED〇T電極的去除 摻雜，並且大量地減低其傳導性。因此，為了要達 成高電流轉換比，重要的是要使用可對抗氧或水的 非故意摻雜之具有良好穩定性的一種聚合物半導 達成良好環境穩定性與高流動性之較佳種類材質 為A-B硬針成塊共聚物，其包含一八與8塊狀物的正 常等級順序。適合的A塊狀物為結構上界定良好且具 有高帶隙的階梯型態部分，其具有高於5 5eV的高電 離勢，以作為同聚物與良好環境穩定性。適當A成塊 物的實例為苟衍生物（美國專利案號5,777,〇7〇)、茚 並芴衍生物（由S· Setayesh於2000年所發表之第33 期Macromolecules第2016頁）、次笨基或梯形次苯基 衍生物（由J_ Grimme等人於1995年所發表之第7期 Adv· Mat·地292頁）。適當3成塊物為具有低帶隙的 孔傳輸部分，其包含雜原子，例如硫或氮，並且作 為具有低於5.5eV之電離勢的同聚物。孔傳輸B成塊 20 本紙張尺度適用中國國豕彳*準（CNS)A4規格（210 X 297公爱)—_ —III — — — · II (Please read the precautions on the back before filling out this page) 线 Line 518760 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (air and poor opening in the fj system steps- The increase in the off-state current ratio compared with the membrane conductivity. This is related to the relatively low ionization potential of P3HT, | ρ ^ 4 · 9 eV. The high on-off current ratio of less than 106 has been shown for P3HT, but after deposition, it is required A reduction to remove the doping step, such as exposure to hydrazine vapor (H. Sirringhaus et al., Issue 39 Advances in Solid State Physics, 1999). However, on the above-mentioned UP TFTs, after this reduction, The processing step cannot be performed because it will simultaneously lead to the dedoping of the PEDOT electrode and greatly reduce its conductivity. Therefore, in order to achieve a high current conversion ratio, it is important to use a non-oxidizing agent that is resistant to oxygen or water. A kind of polymer semiconductor that is intentionally doped with good stability to achieve good environmental stability and high fluidity. The preferred kind of material is AB hard needle block copolymer, which contains one and eight blocks. Normal grade sequence. A suitable A block is a stepped part with a well-defined structure and a high band gap, which has a high ionization potential higher than 5 5eV for homopolymer and good environmental stability. Appropriate A Examples of agglomerates are Gou derivatives (U.S. Pat. No. 5,777, 〇07), indenofluorene derivatives (Macrolecules, Issue 33, published by S. Setayesh, 2000, page 2016), subbenzyl or Trapezium phenylene derivative (No. 7 Adv. Mat., P. 292, published by J_ Grimme et al., 1995). A suitable 3 block is a pore-transporting part with a low band gap, which contains heteroatoms, For example, sulfur or nitrogen, and as a homopolymer with an ionization potential below 5.5eV. Pore Transport B Block 20 This paper size is applicable to China National Standard * CNS A4 (210 X 297 public love) —_ —

518760 A7 B7 ϋ_W._ί_Γ 經濟部智慧財產局員工消費合作社印製 五、發明說明（金8 物的貫例是噻吩衍生物或三芳基胺衍生物。8成丨鬼物 的效用是要降低成塊共聚物的電離勢。成塊共聚物 的電離勢較佳地在4.9eVdp 5.5eV的範圍内。該共聚 物的實例為F8T2 (電離勢為5.5eV)或TFB(美國專利 案號5,777,070)。 其他適合的孔傳輸聚合物為具有大於5eV電離勢^ 之聚噻吩衍生物的同聚物，例如具有烷氧基的聚嗔 吩或氟化側鏈（由R.D.McCullough於1998年發表之第 10期 Advanced Materials 第 93 頁）。 除了孔傳輸半導體聚合物之外，也可使用可溶解 電子傳輸材質。這需要大於3eV的高電子親和性，較 佳地大於3.5eV，以避免如氧的殘餘氣體雜質將作為 載體捕集物。適合的材質可包含溶液可處理電子傳 輸小分子半導體（由H_E. Katz等人於2000年發表之第 404期Nature雜誌478頁），或具有電子不完全氟化側 鏈的聚σ塞吩衍生物。具有結構上良好界定之梯形A成 塊物且具有高於5.5eV高電離勢的AB-型態成塊共聚 物，以及增加共聚物的電子親和性至高於3eV的數值 的一電子傳輸B成塊物來說，較佳地高於3.5eV也是 同時適當的。適當A成塊物實例為芴衍生物（美國專 利案號5,777,070)、節並苟衍生物（2000年由S. Setayesh 所著之第 33 期 Macromolecules 的第 2016 頁）、次苯基或梯形次笨基衍生物（由丄Grimme等人 於1995年所著之第7期Adv· Mat·第292頁）。電子傳 21 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 518760 經濟部智慧財產局員工消費合作社印製 A7 ___B7____ 五、發明說明（金9 輸B成塊物的實例為苯並噻二唑衍生物（美國專利案 號5,777,070)、二萘嵌苯衍生物、萘四羧酸二醯亞胺 衍生物（由Η·Ε· Katz等於於2000年所發表之 Nature404期478頁）或氟化噻吩衍生物。 為了快速操作邏輯電路，電晶體的通道長度以及 源極/没極與閘極之間的重疊要越小越好，其典型的 為幾微米。最重要的尺寸為L，因為電晶體電路的操 作速度約為L·2的比例。這對具有相對低流動性的半 導體層來說尤其重要。 以現今的噴墨印製技術並無法達成高解析度型樣 化，即使是具備現有技術水準的IJP技術也被限定在 10-20μηι的外觀尺寸上（第6圖）。如果需要較快速的 操作與較密集的外貌封裝時，那麼一種允許較細外 • 貌解析度的技術便必須運用。以下要說明的技術將 利用油墨表面的交互作用來限定基體表面上的噴墨 微滴。這項技術可以被用來達成比習知喷墨印製法 可達成之更小通道長度。 這項限定技術可以用來允許一種沉積材質在一基 體上之優良解析度沉積。基體的表面首先被處理， 以便使其選出部分對所欲之沉積材質呈現相對吸引 人的且相對防水。例如，基體可以被事先型樣化， 以便在某些區域呈現部分忌水的，且在其他區域呈 現部分親水的。因著在高解析度與正確讀取下進行 事先型樣化步驟，便可對後續沉積進行正確的界定。 22 ^張尺度適时關家標準（CNS)A4規格（21() χ 297公餐）---- (請先閱讀背面之注意事項再填寫本頁) 訂---------線 «· 518760 Α7 Β7 ϋ_0i / 經濟部智慧財產局員工消費合作社印製 五、發明說明（如 在第7圖中將顯示事先型樣化的一實施例。第了圖 顯示第1(c)圖中相同裝置的形成，但另具有一特別細 的通道長度。相同的元件則以與第1(c)圖相同的編號 來表不。第7(a)圖顯示一種製造事先圖形化基體的方 法。第7(b)圖則顯示在該事先圖形化基體上的印製方 法與油墨限定。 在源極-汲極2與3的沉積之前，一薄聚醯亞胺層1〇 將形成在玻璃片1上。該聚醯亞胺層是極佳地型樣化 的’以在源極-汲極形成的地方移除它。移除的步驟 可以藉由一種照相平版印刷過程來完成，以允許優 良的外貌界定與正確的讀取。該過程的一實例中， 聚醯亞胺可以用一層光阻材料11來覆蓋。該光阻材 料可以利用照相平版印刷的方式來型樣化，以在聚 醯亞胺被移除的地方移除它。接下來，利用一種對 光阻材料呈現堅固的過程來移除聚醯亞胺。隨後， 光阻材料可以被移除，以留下正確型樣化的聚醯亞 月女。將選出聚醢亞胺’因為它是相對忌水的，而該 玻璃基體則是相對親水的。在接下來的步驟，形成 源極-汲極的PEDOT材質將利用喷墨印製法沉積在親 水基體區域12上。當擴散在玻璃基體區域的油墨微 滴碰到忌水聚酿亞胺區域1 〇的邊緣時，油墨將被排 開並且不會流到該忌水表面區域。透過該種限定效 應，油墨只在親水表面區域中沉積，並且具有小帶 隙之高解析度型樣與少於10μηι的電晶體通道長度便 23 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 518760518760 A7 B7 ϋ_W._ί_Γ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (The conventional examples of gold 8 are thiophene derivatives or triarylamine derivatives. 80% 丨 The effect of ghosts is to reduce block copolymerization. The ionization potential of the block copolymer is preferably in the range of 4.9eVdp 5.5eV. Examples of the copolymer are F8T2 (ionization potential is 5.5eV) or TFB (US Patent No. 5,777,070). Other suitable Pore-transporting polymers are homopolymers of polythiophene derivatives with ionization potentials greater than 5 eV, such as polyfluorene with alkoxy groups or fluorinated side chains (No. 10 Advanced Materials, published by RDMcCullough in 1998) Page 93). In addition to hole-transporting semiconducting polymers, dissolvable electron-transporting materials can also be used. This requires a high electron affinity of greater than 3eV, preferably greater than 3.5eV, to avoid residual gas impurities such as oxygen from being used as Carrier traps. Suitable materials can include solution-handling electron-transporting small-molecule semiconductors (Page 478, Nature, 404, Nature, 404, published by H_E. Katz et al., 2000), or have incomplete electron fluorine Polysigmathiophene derivatives with side chains. AB-type block copolymers with a well-defined trapezoidal A block and a high ionization potential above 5.5eV, and increase the electronic affinity of the copolymer to the highest For an electron-transporting B block having a value of 3eV, preferably higher than 3.5eV is also appropriate at the same time. Examples of suitable A block are fluorene derivatives (U.S. Patent No. 5,777,070), hydrazone derivatives (2000 by S. Setayesh, No. 33 Macromolecules, 2016), phenylene or trapezoidal phenylene derivatives (by Grimme et al., No. 7 Adv · Mat · No. 292 pages. E-Book 21 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ^ -------- ^ --------- line (please read first Note on the back, please fill out this page again) 518760 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7____ V. Description of the invention (Gold 9 is an example of a block of B is a benzothiadiazole derivative (U.S. Patent No. 5,777,070 ), Perylene derivatives, naphthalene tetracarboxylic acid diamidine derivatives (equated by Η · Ε · Katz equal to Nature 404, page 478) or fluorinated thiophene derivatives published in 2000. In order to operate logic circuits quickly, the channel length of the transistor and the overlap between the source / non-pole and gate should be as small as possible. It is a few microns. The most important dimension is L, because the operating speed of the transistor circuit is about L · 2 ratio. This is especially important for semiconductor layers with relatively low fluidity. With today's inkjet printing technology, it is not possible to achieve high-resolution prototypes, and even IJP technology with the current level of technology is limited to 10-20 μm appearance dimensions (Figure 6). If faster operation and denser appearance packaging are required, then a technique that allows for finer appearance resolution must be applied. The technique described below will use the interaction of the ink surface to define inkjet droplets on the substrate surface. This technique can be used to achieve smaller channel lengths than can be achieved with conventional inkjet printing methods. This qualification technique can be used to allow a fine resolution deposition of a deposition material on a substrate. The surface of the substrate is first treated so that selected portions thereof are relatively attractive and relatively waterproof to the desired deposition material. For example, the matrix can be patterned in advance so that it is partially water-repellent in some areas and partially hydrophilic in other areas. Due to the high-resolution and correct-reading pre-modeling steps, subsequent depositions can be correctly defined. 22 ^ Zhang scale timely family care standard (CNS) A4 specifications (21 () χ 297 meals) ---- (Please read the precautions on the back before filling this page) Order --------- Line «· 518760 Α7 Β7 ϋ_0i / Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employee Consumer Cooperative, V. Invention Description (As shown in Figure 7, an example of prior styling is shown. Figure 1 shows Figure 1 (c) The same device is formed, but with a particularly thin channel length. Identical components are represented by the same numbers as in Figure 1 (c). Figure 7 (a) shows a method for making a pre-patterned substrate Figure 7 (b) shows the printing method and ink definition on the pre-patterned substrate. Before the source-drain electrodes 2 and 3 are deposited, a thin polyimide layer 10 will be formed on the glass On sheet 1. The polyimide layer is very well patterned to remove it where the source-drain is formed. The removal step can be done by a photolithography process to allow Excellent appearance definition and correct reading. In one example of this process, polyimide can be covered with a layer of photoresist material 11. The light The material can be patterned using photolithography to remove the polyimide where it was removed. Next, the polyimide is removed using a process that renders the photoresist material strong. Subsequently The photoresist material can be removed to leave the correctly shaped polyfluorene. Female polyimide will be selected because it is relatively water-repellent and the glass substrate is relatively hydrophilic. In the next step, the source-drain PEDOT material will be deposited on the hydrophilic substrate region 12 by inkjet printing. When the ink droplets diffused in the glass substrate region touch the edge of the water-resistant polyimide region 10 At this time, the ink will be drained and will not flow to the water-repellent surface area. Through this limiting effect, the ink is deposited only in the hydrophilic surface area, and has a high-resolution pattern with a small band gap and an electricity of less than 10 μηι. The length of the crystal channel is 23. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Note: Please fill out this page again) 518760

、發明說明（釘 經濟部智慧財產局員工消費合作社印製 可以被界定（第7(b)圖）。 在移除聚醯亞胺後，聚醯亞胺被移除之過程的一 實例’或可被應用以增進相對表面效應，將顯示在 第7(a)圖中。聚醯亞胺層1〇與光阻材料11將暴露在 氧氧中。氧氣餘刻薄聚醯亞胺層（5〇〇 A)的速度將快 於ϋ刻厚（1·5μηι)光阻材料層的速度。在移除光阻材 料之前，藉由暴露在氧氣中，在源極-汲極區域中已 暴露裸玻璃表面12將呈現相當親水性的。要注意的 疋在移除聚酿亞胺的過程中，聚酿亞胺的表面被 光阻材料保護並且維持忌水。 如果需要的話，藉由另外暴露在cf4氣體中，聚 醯亞胺的表面可以成為更加忌水的。cf4氣體將氟化 聚醯亞胺的表面，但並不與親水玻璃基體產生交互 作用。該額外的氣體處理方法可以在移除該光阻材 料之前進行，這樣一來，只有聚醯亞胺型樣彳0的側 壁將被氟化，或者在移除該光阻材料後。 水中PEDOT/PSS與〇2等離子處理7059玻璃的接 觸角度為0 glass »20。，相較於在聚醯亞胺表面上0 Pl»70°〜80°的接觸角度。水中PEDOT/PSS與敦化聚 醯亞胺的接觸角度為120。。 當如所述的，PEDOT/PSS從一種水性溶液沉積 到事先型樣化的聚醯亞胺層上時，PEDOT/PSS油墨 將被限定在源極·沒極區域，即使通道長度L僅為幾 微米（第7(b)圖）。 242. Description of the invention (It can be defined as printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (Figure 7 (b)). An example of the process of removing polyimide after removing polyimide 'or Can be applied to enhance the relative surface effect, which will be shown in Figure 7 (a). The polyimide layer 10 and the photoresist material 11 will be exposed to oxygen and oxygen. The oxygen will thin the polyimide layer (50%). 〇A) will be faster than the thickness of the thick (1.5μm) photoresist material layer. Before removing the photoresist material, by exposing to oxygen, bare glass has been exposed in the source-drain region. Surface 12 will appear quite hydrophilic. It should be noted that during the removal of polyimide, the surface of the polyimide is protected by a photoresist material and maintained water-resistant. If necessary, by additional exposure to cf4 In gas, the surface of polyimide can become more water-repellent. Cf4 gas will fluorinate the surface of polyimide, but does not interact with the hydrophilic glass substrate. This additional gas treatment method can remove the Photoresist material before, so that only polyimide The side wall of sample 彳 0 will be fluorinated, or after removing the photoresist material. The contact angle of PEDOT / PSS in water with 〇2 plasma-treated 7059 glass is 0 glass »20. Compared to the surface of polyimide The contact angle of 0 Pl »70 ° ~ 80 °. The contact angle of PEDOT / PSS in water with Dunhua polyimide is 120. As described, PEDOT / PSS is deposited from an aqueous solution to a previously patterned For polyimide layers, PEDOT / PSS inks will be limited to the source and electrode regions, even if the channel length L is only a few micrometers (Figure 7 (b)).

(請先閱讀背面之注意事項再填寫本頁)(Please read the notes on the back before filling this page)

-I I I I I I I 訂·11111111 ^^ _ 518760 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明（尨 油墨微滴的限定取決於介於忌水與親水表面區域 之邊緣的接觸角度0，並且將相關於分別在於空氣/ 聚龜亞胺與油墨/玻璃介面的面際張力口彳與口^，以 及在油墨/空氣介面的表面張力口3。忽略了聚醯亞胺 側壁的效應，一預估值將可以從Y〇ung的公式c〇s0 =(匚]1_口2)/匚]3中取得（第7(b)圖）。 較佳地’油墨微滴13的沉積將出現在親水基體區 域12上’介於微滴中心與聚醯亞胺邊際之間的距離 d。一方面來說，d必須是夠小的，以利用擴展油墨 來達到邊緣，並且PEDOT膜將直接延伸到聚醯亞胺 邊緣。另一方面來說，d也必須夠大，才可使快速擴 展的油墨不會溢出到忌水表面區域。這將增加PEd〇t 沉積在界定TFT通道之聚醢亞胺區域1〇頂部的危險 性，並且將引起源極與汲極之間的短路。對具有〇.4ng 固體含量、以12_5μΓΤΐ之橫向節距介於二連續微滴之 間、在〇2氣體等離子處理的7059玻璃上沉積的 PEDOT微滴而言，〜30·40μΓτι的一數值已經為適合 的。最佳數值d依賴表面上的濕潤性質，也同時依賴 為後續已沉積微滴之間之橫向距離的沉積節距，以 及依賴溶液的乾燥時間。 聚醯亞胺層10可以同時被用來作為調整層9(第 1 (b)圖），在如液晶狀半導體聚合物4的實例中。聚醯 亞胺層可以機械式的摩擦。 閘極電極6可以藉由形成在閘極絕緣層5頂部的一 I I I I I ·1111111 ^ ·1111111« (請先閱讀背面之注意事項再填寫本頁) 25 518760 A7-IIIIIII Order · 11111111 ^^ _ 518760 A7 B7 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (尨 The limitation of ink droplets depends on the contact angle between the edge of the water-repellent surface and the hydrophilic surface area 0, and It will be related to the interfacial tension port 彳 and ^ of the air / polyimide and ink / glass interfaces, and the surface tension port 3 of the ink / air interfaces. Ignoring the effect of the polyimide sidewall, a preliminary The estimate will be obtained from Young's formula c0s0 = (匚) 1_ 口 2) / 匚] 3 (Figure 7 (b)). Preferably, the 'ink droplet 13 deposition will appear in The distance d between the center of the droplet and the margin of the polyimide on the hydrophilic matrix region 12. On the one hand, d must be small enough to reach the edge using the extended ink, and the PEDOT film will extend directly to Polyimide edge. On the other hand, d must also be large enough so that the rapidly expanding ink does not overflow into the water-repellent surface area. This will increase the PEdOt deposited on the polyimide that defines the TFT channel Danger at the top of zone 10 and will lead to Short-circuit between source and drain. For PEDOT droplets with a solid content of 0.4 ng, between two consecutive droplets with a lateral pitch of 12_5 μΓΤΐ, deposited on 7059 glass treated with 0 2 gas plasma A value of ~ 30 · 40μΓτι is already suitable. The optimal value d depends on the wetting properties on the surface, but also on the deposition pitch, which is the lateral distance between subsequent deposited droplets, and on the drying time of the solution. The polyimide layer 10 can be used simultaneously as the adjustment layer 9 (FIG. 1 (b)), in the example of a liquid crystal-like semiconductor polymer 4. The polyimide layer can be mechanically rubbed. Gate electrode 6 You can use a IIIII formed on top of the gate insulation layer 5 · 1111111 ^ · 1111111 «(Please read the precautions on the back before filling this page) 25 518760 A7

型樣化層14來進行相似限定，其提供吸引且排開的 表面區域給閘極電極所沉積的溶液。該型樣化層6可 以用源極-汲極的型樣調整，以最小化源極/汲極與閘 極的重g區域（第7(c)圖）。 除了聚醯亞胺以外的其他材質也可使用於預型樣 化層。也可以使用除了照相平版印刷術以外的其他 適當預型樣化技術。 第8圖顯示相對忌水與親水層的結構能力，以限 定利用喷墨印製法所沉積的液狀”油墨，，。第8圖顯示 包含細長條聚醯亞胺10之基體的光顯微圖，其已如 上述方法處理而成為相對忌水’並且使已如上述方 法處理之裸玻璃基體12的較大區域成為相對親水。 PEDOT材質的源極與汲極已經利用噴墨印製法來沉 積，其為接近條狀物10之在線2與線3中流動的一串 微滴。雖然已喷墨材質將顯示低對比，可以從沉積 材質的末端表面2與3的突然終結形式中看出的是， 該沉積材質已被條狀物1 0限定，即使條狀物的厚度 為1·=5μηι以下。 經濟部智慧財產局員工消費合作社印製 第9圖顯示在聚醯亞胺條狀物10周圍區域之喷墨 沉積過程的相片。影像將利用固定在透明基體下面 的頻閃相機拍攝。聚醯亞胺型樣10的邊緣呈現白線。 油墨微滴21從喷墨頭20的喷嘴中注入，且停留在與 聚醯亞胺條狀物10之間距離為d的中心。類似這樣的 影像可以用來進行對應條狀物型樣1 〇之喷墨沉積的 26 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 丄 〇/ου Α7 經濟部智慧財產局員工消費合作社印製 、發明說明（立4 正確區域調整，並且可 』以用來自動化利用型樣辨識 、區域調整程序（請參看以下說明）。 第10圖與第11圖顯示如第7圖⑷方式形成且分別 具有通道長度[=2(^與_之電晶體的輸出端與轉 換特徵，其利用上述的差分濕潤過程來界定。在二 個案例中，通道寬度料3_。㈣圖⑷顯示 裝置的輸出端特徵。第10圖（b)顯示7Mm裝置的輸出 端特徵。第11圖（a)顯示20μΓΤΊ裝置的轉換特徵。第W 圖（b)顯示7μΓΠ裝置的轉換端特徵。該7pm裝置顯示 在小源極·汲極電壓具有已減低電流之特徵化短通道 狀態，以及在飽和狀態具備限定的輪出傳導性。短 通道裝置的流動性與開-關電流比將相似於上述之長 通道裝置的流動性與開-關電流比，即μ=〇 〇〇5-〇.〇1cm2/Vs，且ION/|OFF=1〇4-1〇5。 製造基體預型樣的一替代技術為具有型樣化自組 裝單層體（SAM)之玻璃基體表面的功能化，例如 SAM，其包含如三-氟乙酸-三-曱氧基矽烷的忌水烷 基或氟基，或包含如烧氧基的極性基。SAM可以利 用適當方法來型樣化，例如透過陰罩的UV光線曝曬 (由H. Sugimura等人於2000年所發表之Langmuir 2000第855頁），或微接觸印製法（由Brittain等人於 1998年所發表之1998年五月號Physics World May 第31頁）。 基體的預型樣化可相容於上述的過程流程，因為 27 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 518760 A7 五、發明說明（知 預型樣化是在TFT的層體沉積之前進行。 在閘極沉積之前，可以運用相似技術以預型樣化 閘極絕緣層的表面或表面改造層，以達成較小的重 電谷。如第7(c)圖所示，閘極電極6可以利用型樣 化層14來限疋。該預型樣化的一可能實施例是微接 觸印製法，或自組裝單層體的UV光型樣化，其包含 黏合至PVP閘極絕緣層之烴基的氯矽烷或甲氧矽烷 基。 因著具有預型樣化基體，便可能根據本發明所揭 示之TFT與通孔製造過程來製造出高速的邏輯電路。 在大£域上製造電晶體電路的重要要件之一是對 妝於基體型樣的沉積來進行紀錄與調整。要在彈性 基體上進行足夠紀錄是特別困難的，因為將在大區 域上呈現失真。在此所發展的高解析度喷墨印製過 程將適合在大區域上進行正確紀錄，即使是在塑膠 基體上’因為喷墨列印頭的位置可對照於基體上的 型樣進行局部調整（第9圖）。該局部調整過程可以利 用型樣辨識技術自動化進行，其利用如第9圖中的影 像。 員 為了要利用上述的裝置來形成多重電晶體積體電 路，所欲的是能夠直接透過裝置厚度來製作通孔互 連體。這可使該項電路能夠特別緊密地形成。製作 該互連體的方法之一便是使用溶劑所形成的通孔， 如下所說明的。該方法利用上述TFTs的溶液加工處 28 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 518760 B7The patterning layer 14 is similarly defined, which provides an attractive and evacuated surface area for the solution deposited by the gate electrode. The patterning layer 6 can be adjusted with the source-drain pattern to minimize the heavy g area of the source / drain and gate (Figure 7 (c)). Materials other than polyimide can also be used for the preformed layer. Other suitable pre-modeling techniques other than photolithography can also be used. Figure 8 shows the structural capabilities of a relatively water-repellent and hydrophilic layer to limit the liquid "ink" deposited by inkjet printing. Figure 8 shows a light micrograph of a substrate containing elongated polyimide 10 It has been treated as described above to become relatively water-repellent 'and made a relatively large area of the bare glass substrate 12 treated as described above relatively hydrophilic. The source and drain of the PEDOT material have been deposited using inkjet printing, It is a series of droplets flowing in lines 2 and 3 close to the strip 10. Although the inkjet material will show a low contrast, it can be seen from the abrupt termination of the end surfaces 2 and 3 of the deposited material that The deposition material has been limited by the strips 10, even if the thickness of the strips is 1 · = 5μηι or less. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 9 shows around the polyimide strips 10. Photograph of the inkjet deposition process of the area. The image will be taken with a stroboscopic camera fixed below the transparent substrate. The edges of the polyimide pattern 10 are white lines. Ink droplets 21 are injected from the nozzles of the inkjet head 20, and Stay with The distance between the polyimide strips 10 is the center of d. An image similar to this can be used for inkjet deposition of 26 corresponding strip patterns 10. The paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 丄 〇 / ου Α7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and a description of the invention (4 correct regional adjustments, and can be used to automate the use of pattern identification, regional adjustment procedures (see Figures 10 and 11 show the output terminals and switching characteristics of the transistors formed as shown in Figure 7 and with channel lengths [= 2 (^ and _, respectively), which are defined using the differential wetting process described above. In the two cases, the channel width is 3 mm. Figure ⑷ shows the output characteristics of the device. Figure 10 (b) shows the output characteristics of the 7Mm device. Figure 11 (a) shows the conversion characteristics of the 20μΓΤΊ device. Figure W (b) shows the characteristics of the conversion side of a 7μΓΠ device. The 7pm device shows a characteristic short-channel state with reduced current at the small source and drain voltages, and a limited wheel-out conductivity in the saturated state The flowability and on-off current ratio of the short-channel device will be similar to the flowability and on-off current ratio of the above-mentioned long-channel device, that is μ = 〇〇〇〇〇〇〇〇cm1 / Vs, and ION / | OFF = 1〇4-1〇5. An alternative technique for making a matrix pre-type is the functionalization of a glass substrate surface with a patterned self-assembled monolayer (SAM), such as SAM, which contains, for example, tri-fluoroacetic acid- Tri-methoxysilane is a water-repellent alkyl or fluoro group, or contains a polar group such as alkoxy. SAM can be modeled by an appropriate method, such as exposure to UV light through a shadow mask (by H. Sugimura et al. Langmuir 2000, p. 855, published in 2000), or the microcontact printing method (May 1998, Physics World May, p. 31, published by Brittain et al., 1998). The pre-formation of the substrate is compatible with the above process, because 27 paper sizes are applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) ------------- -------- Order --------- line (please read the precautions on the back before filling this page) 518760 A7 V. Description of the invention (I know that the pre-modeling is in the TFT layer body Before the deposition, before the gate is deposited, a similar technique can be used to pre-type the surface of the gate insulation layer or the surface modification layer to achieve a small valley of heavy electricity. As shown in Figure 7 (c), the gate The electrode 6 can be limited by the patterning layer 14. One possible embodiment of the pre-modeling is a micro-contact printing method or a UV light patterning of a self-assembled single-layer body, which includes bonding to a PVP gate Hydrocarbon-based chlorosilane or methoxysilyl group of the insulating layer. Due to the preformed substrate, it is possible to manufacture high-speed logic circuits according to the TFT and via manufacturing process disclosed in the present invention. Manufactured on a large scale One of the important elements of the transistor circuit is to record and adjust the deposition on the substrate shape. It is necessary to make enough on the elastic substrate. Recording is particularly difficult because distortion will appear over a large area. The high-resolution inkjet printing process developed here will be suitable for correct recording over a large area, even on a plastic substrate 'because of inkjet printing The position of the head can be adjusted locally according to the pattern on the substrate (Figure 9). The local adjustment process can be automated using pattern recognition technology, which uses the image as shown in Figure 9. In order to use the above device In order to form a multiple transistor volume circuit, the desire is to be able to make a through-hole interconnect directly through the thickness of the device. This allows the circuit to be formed particularly closely. One of the methods of making this interconnect is to use The through-holes formed by the solvent are described below. This method uses the solution processing of the above TFTs. The paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm 518760 B7).

I 局 員 工 消 費 合 作 社 印 五、發明說明（如 理層並未被轉換成不溶解形式的事實。這可藉由溶 劑局部沉積來形成通孔的開口。 為了要製作溶劑形成的通孔（第12(句圖），定量的 適當溶劑29將局部沉積在該層體頂端，且透過該頂 端來形成通孔。選用溶劑，以使它能夠如溶解下墊 層，且透過該下墊層可形成該通孔。藉由連續溶解 的方法，該溶劑將滲透該層體，直到通孔形成為止。 已溶解材質將沉積到通孔的測壁w。溶劑的型態與 /儿積的方法可以依照個別的應用來選擇。然而，三 個較佳的選擇為： 1·溶劑與過程狀況為溶劑將蒸發或者可以輕易移 除的，以使其不致干擾後續的加工處理，並且 不會導致該裝置之過多或不正確的溶解；以及 2·溶劑的沉積是藉由一選擇性的過程，例如|jp， 其中正確溶劑控制量可以正確地應用到基體的 所欲區域；以及 3·通孔的直徑將受到溶劑微滴的表面張力與溶劑 濕潤該基體的能力所影響；以及 4·溶劑並不能溶解下墊層，其為電子連接產生之 處。 第12圖（a)顯示如第1 圖一般型態之部分形成的 電晶體裝置上之甲醇溶劑的微滴29的沉積（每微滴包 含20ng)。第12圖（a)的部分裝置包含彳3|Jm厚的pvp 絕緣層28、F8T2半導體層27、pED〇T電極層％與玻 29 本紙張尺度適用中國國家標準（CNS)A4規格公爱）_ 裝--------tT---------^ (請先閱讀背面之注音？事項再填寫本頁) 518760 A7 B7 五、發明說明（立7 璃基體25。在此實例中，所欲的是透過絕緣pvp層 形成一通孔。甲醇被選為溶劑，因為它容易溶解 PVP ;因為它可以容易蒸發，便不至於阻礙後續的 加工處理；並且因為它令人滿意之對pvp的濕潤性 質。為了要在此實例中形成通孔，一丨Jp列印頭便被 移動到基體上的位置，其為通孔所欲形成的位置。 隨後，來自IJP列印頭之適當大小必要數量之甲醇微 滴便一直被滴落，直到通孔完成為止。將選出連續 微滴之間的期間，以相容於甲醇溶解該裝置層體的 速率。較佳的是，在下一微滴沉積之前，每微滴均 能完全蒸發或幾近完全蒸發。要注意的是，當通孔 達到底部非極性半導體層時，蝕刻動作將停止，以 使下墊層不會被移除。其他的溶劑，如異丙醇、乙 醇、丁醇或丙醇也可以使用。為了要達成高產量， 所欲的是要藉由單一溶劑微滴來完成通孔。對3〇〇nm 厚膜與具有30pi量的微滴以及50μm直徑來說，溶劑 中之層體的溶解度需要高於每量1-2重量。/。。如果需 要形成具有單一微滴之通孔的話，高沸騰點同時也 是所欲的。若使用PVP 1,2-二甲基-2-咪唑烷酮 (DMI)，可以使用225°C的沸騰點。 第12(b)圖顯示依序滴落在通孔位置之多滴曱醇 的效應。右邊面板顯示在1、3與10微滴滴落之後的 裝置顯微圖。左邊面板顯示形成時，越過通孔的 Dektak表面輪廓測量的相同裝置（在每個面板中通孔 30 本紙張尺度適用中國國家標準（CNS)A4猙格（210 X 297公釐） 請 先 閱， 讀 背 面 · 之 注 意 事· 項 經濟部智慧財產局員工消費合作社印製Bureau I Consumer Cooperatives Co., Ltd. V. Invention Description (such as the fact that the physical layer has not been converted to an insoluble form. This can be achieved by the local deposition of the solvent to form the openings of the through-holes. (Sentence diagram), a proper amount of a suitable solvent 29 will be locally deposited on the top of the layer, and through-holes will be formed through the top. A solvent is selected so that it can dissolve the underlayer as it is, and the underlayer can be formed through the underlayer. Through-hole. By continuous dissolution, the solvent will penetrate the layer until the through-hole is formed. The dissolved material will be deposited on the wall of the through-hole w. The type and / or volume of the solvent can be determined individually. However, the three better choices are: 1. The solvent and process conditions are such that the solvent will evaporate or can be easily removed so that it will not interfere with subsequent processing and will not cause too much of the device Or incorrect dissolution; and 2. the deposition of the solvent is through a selective process, such as | jp, where the correct solvent control amount can be correctly applied to the desired area of the substrate; and 3. The diameter of the through hole will be affected by the surface tension of the solvent droplets and the ability of the solvent to wet the substrate; and 4. The solvent cannot dissolve the underlayer, which is where the electronic connection occurs. Figure 12 (a) shows Deposition of droplets 29 of methanol solvent on a partially formed transistor device as shown in Figure 1 (each droplet contains 20ng). Part of Figure 12 (a) contains 彳 3 | Jm thick pvp insulation Layer 28, F8T2 semiconductor layer 27, pED〇T electrode layer% and glass 29 This paper standard applies to China National Standard (CNS) A4 specifications. -^ (Please read the note on the back? Matters before filling out this page) 518760 A7 B7 V. Description of the invention (Li 7 glass substrate 25. In this example, the desire is to form a through hole through the insulating pvp layer. Methanol is It is selected as a solvent because it easily dissolves PVP; because it can be easily evaporated, it does not hinder subsequent processing; and because it is satisfactory for the wettability of pvp. In order to form a through hole in this example, a 丨The Jp print head is moved to the position on the substrate, which is the position to be formed by the through hole. Subsequently, the necessary amount of methanol droplets of the appropriate size from the IJP print head will be dripped until the through-hole is completed. The period between successive droplets will be selected to dissolve the device layer with compatibility with methanol It is preferable that before the next droplet is deposited, each droplet can be completely evaporated or nearly completely evaporated. It should be noted that when the via hole reaches the bottom non-polar semiconductor layer, the etching action will stop to The underlayer will not be removed. Other solvents such as isopropanol, ethanol, butanol or propanol can also be used. In order to achieve high yields, it is desirable to complete the pass through a single solvent droplet. For a 300 nm thick film with droplets of 30 pi and a diameter of 50 μm, the solubility of the layer in the solvent needs to be higher than 1-2 weight per volume. /. . If it is necessary to form a through hole with a single droplet, a high boiling point is also desirable. With PVP 1,2-dimethyl-2-imidazolidinone (DMI), a boiling point of 225 ° C can be used. Figure 12 (b) shows the effect of multiple drops of methanol which are sequentially dropped on the position of the through hole. The right panel shows micrographs of the device after 1, 3, and 10 microdrops. The left panel shows the same device for measuring the Dektak surface profile across the through hole when formed (30 through holes in each panel. The paper size applies to the Chinese National Standard (CNS) A4 grid (210 X 297 mm). Please read first, Read the back · Notes · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

518760 A7 B7 ϋ. 經濟部智慧財產局員工消費合作社印製 五、發明說明（龙 的位置通常標示在"V”位置）。當數滴曱醇依序的沉積 在相同位置時，一陷坑將在pvp膜開啟。當後續的 微滴進行時，該陷坑的深度將增加，並且在大約6滴 之後’下塾FBT2層的表面將被揭開。已溶解的pvp 材質則沉積在通孔的側壁W。通孔的直徑為50pm等 、、及其由微滴的大小限制。該大小對許多應用來說 是恰當的，例如邏輯電路與大顯示區域顯示器。對 一些應用來說，更小的通孔也將需要，例如高解析 度顯示器，便可以使用較小的微滴尺寸，或者基體 表面可以藉由一適當技術來預型樣化，以限定表面 上的微滴，如上所述。也可以使用其他的溶劑。 將可以從表面輪廓測量看出來，通孔的形成將導 致材質的溶解，並且被偏移至通孔的邊緣，其中在 溶劑已被蒸發後將維持（顯示在第12(b)圖中的w)。 應該要注意的是，相較於第12(b)圖所顯示，偏移材 質的形成是較光滑的，第12(b)輪廓圖中的X與y軸將 為不相似的標度（X的單位為μ m，而y的單位為A)。 利用滴落之溶劑滴的數量以及溶劑蒸發速度與溶 解基體速度之比較的結合，可以控制通孔的深度。 沉積產生的環境與基體溫度可能會影響蒸發速度。 不溶解或只緩慢溶解於溶劑的材質層體將可用來限 制溶解的深度。 由於TFT的層體順序包含替換極性與非極性層 體’便有可能選擇溶劑與溶劑的混合，以使蝕刻停 31518760 A7 B7 ϋ. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (the position of the dragon is usually marked at the "V" position. When a few drops of alcohol are sequentially deposited at the same position, a trap The pvp film is turned on. When subsequent droplets are performed, the depth of the pit will increase, and after about 6 drops, the surface of the 'bottomed FBT2 layer will be uncovered. The dissolved pvp material is deposited on the side wall of the through hole W. The diameter of the through hole is 50pm, etc., and its size is limited by the size of the droplet. This size is appropriate for many applications, such as logic circuits and large display area displays. For some applications, smaller vias Wells will also be required, such as high-resolution displays, where smaller droplet sizes can be used, or the substrate surface can be pre-shaped by an appropriate technique to define the droplets on the surface, as described above. It is also possible Use other solvents. It will be seen from the surface profile measurement that the formation of the through hole will cause the material to dissolve and be shifted to the edge of the through hole, which will be maintained after the solvent has been evaporated (shown W) in Fig. 12 (b). It should be noted that the offset material formation is smoother than that shown in Fig. 12 (b), and X in the outline drawing of 12 (b) It will be a scale that is not similar to the y-axis (the unit of X is μm and the unit of y is A). The combination of the number of dripping solvent droplets and the comparison of the solvent evaporation speed and the dissolution matrix speed can control the The depth of the hole. The environment and substrate temperature generated by the deposition may affect the evaporation rate. The material layer that does not dissolve or only slowly dissolves in the solvent will be used to limit the depth of dissolution. Because the TFT layer sequence includes replacement of polar and non-polar layers It is possible to select a solvent and a solvent mixture to stop the etching.

518760 五、發明說明（的 經濟部智慧財產局員工消費合作社印製 A7 B/ 止在已良好界定的深度。 為了要透過通孔產生接觸，一傳導層可被沉積在 其上’以使它延伸進入通孔，並且在通孔的底部材 質進行電子連接。第13(a)圖顯示第12圖（a)的裝置， 但不包括如上所述之在通孔製造之後所形成的金極 25 ° 第13圖顯示在曲線3〇，介於底部ped〇T電極25 與沉積在PVP閘極絕緣層28頂部的一傳導電極29之 間所測量到之電流電壓特徵。該通孔的直徑為 50μηι。為了進行比較，曲線31顯示一參考樣本，其 中在位於電極的頂部與底部之間的重疊部分並沒有 通孔存在。該項特徵清楚地顯示在沒有通孔的狀況 下，通過通孔的電流將高於通過閘極絕緣體之洩漏 電流的數倍。藉由PEDOT電極的傳導性，測量到之 通過該通孔的電流被限制，如進行個別PEd〇t電極 之傳導性測量所見到的一般。它並不會被通孔的阻 性所限制，以使對通孔阻性Rv的較低限制估算可從 這些測量中取得：Rv<5〇〇kQ。 上述有關於第12圖之通孔形成的方法，將直接適 用於沒有擴散屏障的空乏-型態裝置（如第1(c)圖）與在 通孔開啟之後當中沒有擴散屏障沉積的裝置。第14(a) 圖顯示其中通孔已經形成的一裝置，且隨後在沒有 中間擴散屏障層的情況下，閘極將沉積。第u(b)圖 顯示一相似的裝置，其中在通孔形成之後，在閘極 32 (請先閱讀背面之注咅？事項再填寫本頁)518760 V. Description of the invention (A7 B / printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs / is printed to a well-defined depth. In order to make contact through the through hole, a conductive layer can be deposited on it to extend it Enter the through hole and make the electrical connection at the bottom of the through hole. Figure 13 (a) shows the device of Figure 12 (a), but does not include the gold electrode formed after the through hole manufacturing as described above 25 ° FIG. 13 shows the current-voltage characteristics measured on the curve 30 between the bottom pedOT electrode 25 and a conductive electrode 29 deposited on top of the PVP gate insulating layer 28. The diameter of the through hole is 50 μm. For comparison, curve 31 shows a reference sample in which there is no through hole in the overlap between the top and bottom of the electrode. This feature clearly shows that the current through the through hole will be Several times higher than the leakage current through the gate insulator. With the conductivity of the PEDOT electrode, the current measured through the via is limited, as seen in the conductivity measurement of individual PEdOT electrodes It is not limited by the resistivity of the via, so that a lower limit estimate of the resistivity Rv of the via can be obtained from these measurements: Rv < 500kQ. The method of via formation will be directly applicable to empty-type devices without diffusion barriers (such as Figure 1 (c)) and devices without diffusion barrier deposition after the vias are opened. Figure 14 (a) shows which A device in which a via has been formed, and the gate will then be deposited without an intermediate diffusion barrier. Figure u (b) shows a similar device in which after the via is formed, the gate 32 (please Read the note on the back? Matters before filling out this page)

518760518760

經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

電極6的沉積之前，一擴散屏障聚合物7已經形成。 在此狀況下，擴散屏障層需要呈現良好的電荷傳輪 性貝，則更最小化通孔阻性Rv。一適當擴散屏障為 一薄層TFT，如第5(a)圖所示。 如果需要一個較低接觸阻性的話，那麼隨後也將 在通孔的位置移除半導體層。在擴散屏障形成之後， 可較佳地完成。擴散屏障7與半導體聚合物4可以利 用良好溶劑的IJP沉積來進行局部溶冑，例如在此實 例中為二甲苯。藉由為半導體與絕緣材質混合優良 的溶劑，二層體可在同時溶解。第14(c)圖將顯示接 在閘極的沉積之後，進行上述過程的一裝置。 藉由增加層體上之預溶解溶劑混合的接觸角度， 溶劑的混合同時可以用來減少通孔的半徑。 形成通孔互連體且隨後沉積傳導材質以進行橋接 的一替代方法，是將局部地沉積一材質，其可以局 部地改造下墊層基體，以便使它們成為傳導性的。 貫例之一便是包含移動摻雜之溶液局部丨Jp沉積，其 可以擴散到一層體或多層體。這將在第14(d)圖顯 示，其中區域32顯示利用一種摻雜質處理之具有傳 導性的材質。該摻雜質可為小共軛分子，例如如n，n，_ 二苯基-N，N··雙（3-甲基苯基）_(11、聯苯基）4 4、雙胺 (TPD)的二芳基胺。該摻雜質較佳地在溶劑狀態下被 傳輸。 透過PVP介電層來形成通孔的方法可以用來連接 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱了Before the electrode 6 is deposited, a diffusion barrier polymer 7 has been formed. Under this condition, the diffusion barrier layer needs to exhibit good charge transfer properties, and the through-hole resistance Rv is further minimized. A suitable diffusion barrier is a thin layer TFT, as shown in Figure 5 (a). If a lower contact resistance is required, then the semiconductor layer will also be removed at the location of the via. After the formation of the diffusion barrier, it can be done better. The diffusion barrier 7 and the semiconducting polymer 4 can be dissolved locally using a good solvent IJP deposition, such as xylene in this example. By mixing an excellent solvent for the semiconductor and the insulating material, the two-layer body can be dissolved at the same time. Figure 14 (c) shows a device that performs the above process following the deposition of the gate. By increasing the contact angle of the pre-dissolved solvent mix on the layer, the solvent mix can also be used to reduce the radius of the through holes. An alternative method of forming through-hole interconnects and subsequently depositing conductive materials for bridging is to locally deposit a material that can locally modify the underlying substrate so that they become conductive. One of the examples is localized Jp deposition containing a mobile doping solution, which can diffuse into one or more layers. This is shown in Figure 14 (d), where region 32 shows a conductive material treated with a dopant. The dopant may be a small conjugated molecule, for example, such as n, n, _diphenyl-N, N ·· bis (3-methylphenyl) _ (11, biphenyl) 4 4, bisamine ( TPD). The dopant is preferably transported in a solvent state. The method of forming through-holes through the PVP dielectric layer can be used to connect. This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297).

I — (請先閱讀背面之注意事項再填寫本頁) 訂· -·線· 51876〇 A7 B7 五、 發明說明（幻 經濟部智慧財產局員工消費合作社印製 TFT的閘極至下墊層體中的源極或汲極，例如，如第 15圖所示之邏輯轉換器裝置。在大部分的邏輯電晶 體電路中，相似的通孔連接是需要的。第彳6圖顯示 以二個通常關閉之電晶體裝置來形成之增強-载入轉 換器裝置的特徵。具有二個電晶體之不同通道寬度 對通道長度比例（W/L)的二個轉換器將顯示（圖35為 3 : 1的比例，圖36為5 : 1的比例）。可以看出的是， 當輸入電壓從邏輯低電壓轉換到邏輯高電壓時，輸 出電壓從一邏輯高電壓（-20 V)轉換到邏輯低電壓（&QV) 狀悲。轉換器的增益，即特徵的最大坡度將大於1， 其為以製造更複雜的電路’如環振盈器的必要狀態。 如上所述之通孔也可以用來提供介於不同層體中 的互連線之間的電子連接。對複雜電子電路來說， 需要多重位準互連圖形。這可藉由沉積一連串的互 連體72與不同介電層70、71的方式被製造，其從相 容溶劑中沉積（第15(d)圖。通孔73可以用上述的方法 隨後形成’以提供自動的餘刻停止指令的互連線。 適合介電材質的例子有例如PVP的極性聚合物 (70)，以及例如聚苯乙烯的非極性介電聚合物（71)。 它們可以從極性與非-極性溶劑進行替換沉積。藉由 對個別介電層之良好溶劑的局部沉積，可以打開通 孔，而下墊介電層將備置一蝕刻停止層。 在為上述型態裝置選擇材質與沉積過程時，應該 要注意的是，如果每層體是從實質上並不能溶解隨 34 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) --------訂---------線 « A7I — (Please read the precautions on the back before filling this page) Order ·-· Line · 51876〇A7 B7 V. Description of the invention (Printed TFT gate to underlayer by the Consumer Cooperative of Intellectual Property Bureau, Ministry of Magic Economy The source or sink, for example, a logic converter device as shown in Figure 15. In most logic transistor circuits, similar via connections are required. Figure 6 shows two common Features of the enhanced-load converter device formed by the closed transistor device. Two converters with different channel width to channel length ratio (W / L) of the two transistors will be displayed (Figure 35 is 3: 1 The ratio is shown in Figure 36 as a 5: 1 ratio.) It can be seen that when the input voltage changes from a logic low voltage to a logic high voltage, the output voltage changes from a logic high voltage (-20 V) to a logic low voltage. (&Amp; QV). The gain of the converter, that is, the maximum slope of the feature will be greater than 1, which is necessary to make more complex circuits, such as ring resonators. The through holes can also be used as described above. Provides interconnection between interconnects in different layers Electronic connections. For complex electronic circuits, multilevel interconnect patterns are required. This can be fabricated by depositing a series of interconnects 72 and different dielectric layers 70, 71, which are deposited from a compatible solvent ( Figure 15 (d). Through-holes 73 can be subsequently formed using the method described above to provide interconnects with automatic time-out instructions. Examples of suitable dielectric materials are polar polymers (70) such as PVP, and for example Polystyrene non-polar dielectric polymers (71). They can be deposited from alternative polar and non-polar solvents. By local deposition of a good solvent for individual dielectric layers, the vias can be opened and the underlying dielectric The electrical layer will be provided with an etch stop layer. When selecting materials and deposition processes for the above-mentioned type of devices, it should be noted that if each layer is essentially insoluble, the Chinese national standard (CNS ) A4 size (210 X 297 public love) (Please read the precautions on the back before filling this page) -------- Order --------- line «A7

經濟部智慧財產局員工消費合作社印製 4規格（210 X 297公釐） 518760 五、發明說明（七 之而來之下塾層的溶劑中沉積的話，便可以得到許 多優點。如此-來，藉由溶液加工處理方法，可以 ， 建立後續層體。選擇簡化材質與過程步驟的方法之 -是要交替地從極性與非_極性溶劑中沉積二層或多 • 層，如上述例示之層體順序。如此一來，多層體裝 • £，包含可溶解的、傳導的、半導體與絕緣的層體， φ 可以容易的形成。這將解決溶解問題以及下塾層膨 脹的問題。 上述的裝置結構、材質與過程都為例示用。它們 也可以變化。 除了第1圖所顯示之頂閘極組態之外的其他裝置 組態也可以使用。替代的組態為第彳7圖所顯示之更 標準底部閘極組態，其中如果需要的話，可能可以 合併擴散屏障7與表面改造層8。在第17圖中，與第1 圖相似的元件將以相同的元件編號代表。具有不同 • 層體順序的其他裝置組態也可以運用。不同於電晶 體的裝置也可以用類似的方式形成。 藉由任何傳導聚合物，可以替代PEDOT/PSS， • 其可以從溶液中沉積。實例包含聚苯胺或聚吡咯。 然而’ PED0T/pSS的某些吸引特徵包含：（a)具有 低擴散性之聚合物的摻雜質（PSS) ; (b)優良的熱穩 疋性與空氣中穩定性，以及（c)»5.1 eV的工作功性， 其相當符合於共同孔傳輸半導體聚合物的電離勢， 其允許射出有效孔狀電荷載體。 35 本紙張尺度適用中國國家標準（Cns)a&lt; ^--------^---------線 (請先閱讀背面之注意事項再填寫本頁) 518760 A7 五、發明說明（兔 有效的電荷載體射出是重要的，特別是對具有通 道長度L&lt;10Mm的短通道電晶體裝置。在該裝置中， 源極-汲極接觸阻性效應可能會限制TFT電流於小源 極-汲極電壓（第10圖（b))。在具有對照通道長度的裝 置中，已發現到來自PEDOT源極/汲極的射出將比來 自無機金極的射出更有效率。這說明了具有相當符 合於半導體之電離勢的聚合物源極_汲極的電離勢將 較佳的為一種無機電極材質。 從一種水溶液（Saytron P)沉積之PED〇T/pss的 傳導性將為0·1-1 s/cm等級。#用包含溶劑混合物 的配方，可取得高達100 S/cm的較高傳導性（Saye「 CPP 105T,包含異丙醇與N_甲基_2_咄咯烷酮 (NMP))。在後者的狀態中，將需要注意的是，溶劑 組合配方將相容於層體順序的溶解度要件。對需要 較高傳導性的應用來說，將可使用其他傳導聚合物 或溶液-可處理理無機導體，例如液狀之金屬無機粒 子的膠態旋浮體。 在此所說明的過程與裝置並不限於以溶液-加工 處理聚合物所製造的裝置。在電路或顯示器裝置中 (請參看以下），TFT與互連體的一些傳導電極可從無 機導體中形成，例如藉由膠狀懸浮物的印製來沉積 或利用在預型樣化基體上進行電鍍。在當中並非所 有層體都從溶液沉積的裝置中，一個或多個 PED0T/PSS部份可置換為一種可溶解傳導材質，例 製 36 本紙張尺度適用中國國家標準（CNS)A4 公釐Printed in 4 specifications (210 X 297 mm) by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 518760 V. Description of the invention (seventh, if deposited in the solvent of the lower layer, many advantages can be obtained. So-come, borrow The solution processing method can be used to create subsequent layers. One of the methods to choose simplified materials and process steps is to alternately deposit two or more layers from polar and non-polar solvents, as shown in the layer sequence above. . In this way, the multilayer body pack includes soluble, conductive, semiconductor and insulating layers, and φ can be easily formed. This will solve the problem of dissolution and the expansion of the lower layer. The above device structure, The materials and processes are for illustration. They can also be changed. Other device configurations besides the top gate configuration shown in Figure 1 can also be used. The alternative configuration is more standard as shown in Figure 7 Bottom gate configuration, where diffusion barrier 7 and surface modification layer 8 may be combined if needed. In Figure 17, components similar to Figure 1 will be compiled with the same components No. Representation. Other device configurations with different layer sequences can also be used. Devices different from transistors can also be formed in a similar way. PEDOT / PSS can be replaced by any conductive polymer, • It can be used from solution Examples include polyaniline or polypyrrole. However, some attractive features of PEDOT / pSS include: (a) dopants (PSS) of polymers with low diffusivity; (b) excellent thermal stability And stability in the air, and (c) »5.1 eV work function, which is quite in line with the ionization potential of the common hole transporting semiconductor polymer, which allows the effective hole-like charge carrier to be ejected. 35 This paper scale applies Chinese national standards ( Cns) a &lt; ^ -------- ^ --------- line (please read the precautions on the back before filling this page) 518760 A7 V. Description of the invention (rabbit effective charge carrier injection Is important, especially for short-channel transistor devices with a channel length L <10Mm. In this device, the source-drain contact resistive effect may limit the TFT current to a small source-drain voltage (10th Figure (b)). With control channel length In the device, it has been found that the emission from the PEDOT source / drain will be more efficient than the emission from the inorganic gold electrode. This shows that the ionization potential of the polymer source_drain, which has a semiconductor ionization potential quite appropriate An inorganic electrode material is preferred. The conductivity of PEDOT / pss deposited from an aqueous solution (Saytron P) will be on the order of 0 · 1-1 s / cm. # With a formulation containing a solvent mixture, up to 100 can be obtained S / cm higher conductivity (Saye "CPP 105T, containing isopropanol and N_methyl_2_pyrrolidone (NMP)). In the latter state, it will be noted that the solvent combination formula The solubility requirements will be compatible with the layer order. For applications that require higher conductivity, other conductive polymers or solution-processable inorganic conductors, such as colloidal levitation bodies of liquid metal inorganic particles, will be used. The processes and devices described herein are not limited to devices made from solution-processed polymers. In a circuit or display device (see below), some conductive electrodes of TFTs and interconnects can be formed from inorganic conductors, for example, by printing on a colloidal suspension or depositing on a preformed substrate plating. In a device in which not all layers are deposited from a solution, one or more PED0T / PSS parts can be replaced with a soluble conductive material. Example 36 This paper size applies to Chinese National Standard (CNS) A4 mm

A 經濟部智慧財產局員工消費合作社印製 518760 A7 ________B7 五、發明說明（含4 如真空沉積導體。 利用其他溶液可處理的半導體材質，可以同時置 換半導體層。可能性包含小共軛分子，其具有增溶 側鏈（由J.G. Laquindanum等人於1998年發表之第 120期J. Am. Chem· Soc.第664頁）；半導體有機-無 有機混成材料，其在溶液中自組裝（由C.R. Kagan等 人於1999年所發表之第286期Science雜誌第946 頁）；或溶液·沉積無機半導體，例如CdSe毫微粒子(由 B_ A_ Ridley等人於1999年所發表之第286期Science 雜誌第746頁）。 利用除了噴墨印製以外的技術，可型樣化電極。 適當的技術包含軟石版印刷印製法（由j.A. Rogers等 人於1999年發表之第75期Appl. Phys. Lett·第1010 頁；由S· Brittain等人於1998年發表之Physics World 五月號第31頁）、筛網印製法（由ζ· Bao等人於1997 年發表之第9期Chem· Mat.第12999頁），以及光石版 印刷型樣化法（請參看W〇99/10939)或鍍敷法。喷墨 印製被視為是最適合於具有以優良讀取型樣化的大 區域，特別是對彈性的塑膠基體。 除了玻璃板之外，裝置可以沉積在其他基體材質 上’例如有機玻璃或一彈性塑膠的基體，例如聚醚 颯。該項材質較佳地為平板形式，且較佳地為聚合 物材質，並可為透明或有彈性的。 雖然較佳地，利用溶液加工處理與印製技術，可 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 37A Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 518760 A7 ________B7 V. Description of the invention (including 4 such as vacuum deposition of conductors. Using semiconductor materials that can be processed by other solutions, the semiconductor layer can be replaced at the same time. Possibility includes small conjugate molecules, Has solubilizing side chains (J. Am. Chem. Soc., Issue 120, 1998, published by JG Laquindanum et al., 1998); semiconductor organic-organic-free hybrid materials, which self-assemble in solution (by CR Kagan (Science Magazine, Issue 286, 1999, p. 946); or solution-deposited inorganic semiconductors, such as CdSe nanoparticle (Science Magazine, Issue 286, B_A_Ridley et al., 1999, p. 746). ). Electrodes can be modeled using techniques other than inkjet printing. Suitable techniques include soft lithographic printing (No. 75, Appl. Phys. Lett, page 1010, published by jA Rogers et al., 1999) ; Physics World May Issue, 1998, published by S. Brittain et al., Page 31; Screen printing method (9th Chem. Mat., Published by Ze · Bao et al., 1997, page 12999) And light lithography patterning (see WO99 / 10939) or plating. Inkjet printing is considered to be best suited for large areas with good read patterns, especially for elastic Plastic substrate. In addition to glass plates, the device can be deposited on other substrate materials, such as organic glass or a flexible plastic substrate, such as polyether. This material is preferably in the form of a flat plate, and is preferably a polymer. Material, and can be transparent or flexible. Although preferably, the use of solution processing and printing technology, can be ------------- installed -------- order- -------- Line (Please read the notes on the back before filling out this page) 37

518760 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（知 沉積並型樣化所有裝置與電路的層體與組件，一個 或多個組件，例如半導體層，可以利用真空沉積技 術來沉積，以及利用光石版印刷過程來型樣化。 如上所述之TFT裝置可以為複雜電路或裝置的一 部份，其中一個或多個該種裝置可以彼此或與其他 裝置整合。應用的貫例包含顯示器或記憶體裝置的 邏輯電路與主動矩陣電路，或使用者界定之閘極陣 列電路。 邏輯電路的基本組成為第15圖中的轉換器。如果 基體上所有的電晶體為空乏或為累積型態的話，便 有三種可能組態。空乏-載入轉換器（第15(幻圖）適用 於通常開啟的裝置（第1(c)圖與第3圖），而增強-載入 組態（第15(b)圖）則用於通常關閉電晶體（第圖 與第4圖）。二種組態需要一通孔，其分別介於載入 電晶體的閘極與其源極和汲極之間。替代的組態為 阻性載入轉換器（第15(c)圖）。後者裝置可以利用印 刷具有足夠長度與傳導性之薄窄的PEDot線作為載 入電阻。藉著減少PEDOT的傳導性，例如，藉著增 加PSS比例至PEDOT，電阻線的長度可被最小化。 很清楚的是，利用上述的TFT與通孔製造過程，可 能可以製造轉換器裝置與較複雜的邏輯閘極。 如上所述的溶液-加工處理TFTs可以作為主動矩 陣顯示器的像素開關電晶體，例如液晶顯示器（lcd) 或電泳顯示器（由B.Comiskey等人於1998年發表之第 38 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） ^N請先閱讀背面之注音？事項再本頁} 本 訂： .線 518760 經濟部智慧財產局員工消費合作社印製 A7 ___B7__ 五、發明說明（知 394期Nature雜誌第253頁），其中一適當電路將顯示 在第18 (a)圖’以及發光二極體顯示器（由η Sirringhaus等人於1998年所發表之第28〇期Sdence 第1741頁），其中一適當電路顯示在第18(b)圖；或 δ己憶體裝置的主動矩陣哥址元件，例如一隨機存取 記憶體（RAM)。在第18(a)與（b)圖中，可以形成從上 | 述的電晶體T1與電晶體T2。外貌特徵4〇代表一顯示 器或一記憶體元件，其具有電流與電壓供應襯墊。 控制LCD顯示器或電泳顯示器之電極電壓的可能 裝置組悲將顯示在第19圖’其中相似於第1圖中的元 件將以相同的元件編號代表。在第19圖中（例如第7、 14與1 7圖），閘極絕緣層可包含一多層體結構，其包 含擴散屏障與表面改造層，如第1(a)圖所示。518760 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (Know how to deposit and model the layers and components of all devices and circuits. One or more components, such as semiconductor layers, can be deposited using vacuum deposition technology. , And the use of light lithography printing process to type. As mentioned above, the TFT device can be part of a complex circuit or device, one or more of these devices can be integrated with each other or with other devices. Application examples include The logic circuit and active matrix circuit of the display or memory device, or the gate array circuit defined by the user. The basic composition of the logic circuit is the converter in Figure 15. If all the transistors on the substrate are empty or accumulation type State, there are three possible configurations. The empty-load converter (figure 15 (magic) is suitable for devices that are normally turned on (figure 1 (c) and 3)), while the enhanced-load configuration ( (Figure 15 (b)) is used to normally turn off the transistor (Figures 4 and 4). Two configurations require a through-hole, which is located between the gate of the transistor and its source and drain. The alternative configuration is a resistive load converter (Figure 15 (c)). The latter device can use a printed PEDot line with sufficient length and conductivity as the load resistance. By reducing the PEDOT's Conductivity, for example, by increasing the PSS ratio to PEDOT, the length of the resistance line can be minimized. It is clear that using the TFT and via manufacturing process described above, it may be possible to manufacture converter devices and more complex logic gates The solution-processed TFTs described above can be used as pixel switching transistors for active matrix displays, such as liquid crystal displays (lcds) or electrophoretic displays (the 38th paper standard published by B.Comiskey et al. In 1998 is applicable to China) Standard (CNS) A4 specification (210 X 297 public love) ^ N Please read the phonetic on the back? Matters on this page} This order: .line 518760 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7__ 5. Description of the invention ( (Issue 394, Nature Magazine, p. 253), one of the appropriate circuits will be shown in Figure 18 (a) 'and a light emitting diode display (published in 1998 by η Sirringhaus et al. Issue 28 (page 1741), where a suitable circuit is shown in Figure 18 (b); or the active matrix addressing element of a delta memory device, such as a random access memory (RAM). In the figures a) and (b), the transistor T1 and the transistor T2 described above can be formed. The physical feature 40 represents a display or a memory element with current and voltage supply pads. Controlling the LCD display or The possible device group of the electrode voltage of the electrophoretic display will be shown in Fig. 19, where components similar to those in Fig. 1 will be represented by the same component numbers. In Fig. 19 (for example, Figs. 7, 14 and 17) The gate insulating layer may include a multilayer body structure including a diffusion barrier and a surface modification layer, as shown in FIG. 1 (a).

請參看第18圖，TFT的源極與閘極電極2、3均連 接到可由不同傳導材質製成之主動矩陣的資料線44 | 與尋址線43，以達成較長長度的足夠傳導性。TFT 的汲極3可以為像素電極41。從不同傳導材質，該像 素電極可以形成，如第19圖。在依賴電場之應用而 非依賴電荷載體射出的裝置中，並不需要電極41直 接接觸於顯示器元件40，例如液晶顯示器或電泳顯 不器等。在此組態中，TFT與互連線所佔據之所有像 素區域必須維持很小以達成足夠的孔徑率並減低資 料線43與尋址線44上之顯示器元件40與信號之間的 電位相互干擾。 39 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------^--------- (請先閱讀背面之注意事項再填寫本頁) 518760 A7Referring to FIG. 18, the source and gate electrodes 2 and 3 of the TFT are connected to the data line 44 | and the address line 43 of the active matrix made of different conductive materials to achieve sufficient conductivity of a longer length. The drain electrode 3 of the TFT may be a pixel electrode 41. This pixel electrode can be formed from different conductive materials, as shown in Figure 19. In a device that relies on an electric field instead of the charge carrier emission, it is not necessary for the electrode 41 to directly contact the display element 40, such as a liquid crystal display or an electrophoretic display. In this configuration, all pixel areas occupied by TFTs and interconnects must be kept small to achieve sufficient aperture ratios and reduce potential interference between the display elements 40 and signals on data lines 43 and address lines 44 . 39 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------- ^ --------- (Please read the precautions on the back before filling this page ) 518760 A7

五、發明說明（37 第19(b)圖中的組態較複雜。然而，整體像素咬 像素區域的大部分對TFTs與互連線是可得的，並且 藉由像素電極41，顯示器元件將被屏蔽於資料線43 與尋址線44上的信號。組態的製造需要填滿傳導材 質45的一額外介電層42與一通孔，以連接像素電極41 至TFT的汲極3。利用上述的程序，可以製成該通孔。 經濟部智慧財產局員工消費合作社印製 要注意的是，在此組態中，孔徑率將被最大化並 且可以達到100〇/〇。此組態可以同時用於具有背光的 顯示器應用中，例如傳輸性的LCD顯示器，因為在 此所製成的全聚合物丁「丁3在可見光範圍中，是高度 透明的。第20圖顯示在F8T2聚合物TFT上測量的光 學吸收光譜，其中利用沉積液晶狀半導體聚合物， 在一摩擦的聚醯亞胺調整層上，聚合物鏈呈現是單 軸對準的，其同時可作為高解析度印製法的與型樣 化。可以看出的是，由於F8T2的相對高帶隙，該裝 置在大部分可見光範圍中是高度透明的。如果半導 體層，如F8或TFB或其他聚芴衍生物（美國專利證號 5,777,070)，具有高於所使用的帶隙，便可以達成更 南的透明度。聚合物鏈的調整將提昇光線的各色異 性，以使極化平行於調整方向的光線（圖中以••丨丨&quot; 表不）可以被更強烈的吸收，相較於極化垂直於調整 方向的光線（圖中以&quot;丄&quot;表示）。利用引導對極化器來 說是正常的聚合物鏈調整方向，其介於玻璃底板與 笨光之間，光線的各色異性可用於LCD顯示器，以 297公釐） 本紙張尺度_巾_家標準（CNS)A4規格（210 518760 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（如 更進一步的增加TFTs的光透明度。在極化光下，電 晶體裝置在可見光中將呈現幾乎無色，如果厚度F8T2 層的厚度低於500A的話。包含PEDOT之TFT的所有 其他層體，將具有可見光譜範圍内的低光吸收度。 半導體層之低光吸收度的其他優點為TFT特徵對 可見光的降低光感度。非晶矽TFTs的實例中，必須 使用黑色矩陣，以避免在光照射下的大幅關閉電流。 在具有寬帶隙之聚合物TFTs的實例中，並不需要保 護TFTs免於周圍的光照射與免於顯示器的背光。 第19(b)圖中的組態同時也是適合於LED顯示器 (第18(b)圖）的驅動電晶體T1，因為藉由具有大通道 寬度W之源極·汲極的指間陣列的製造，利用像素電 極41下面的的全部區域，它將允許TFT的驅動電流 增加。 或者，第17圖中的底部閘極TFT組態也可以用在 上述所有的應用中（第19(c)圖）。 對製造主動矩陣電路的重要技術課題之一是 PEDOT/PSS TFT與像素電極2、3、6與金屬互連線 43、44、及41之間的接觸。由於其強酸性，PEDOT/PSS 並無法與任何普通的無機金屬相容，例如鋁。在與 PEDOT/PSS接觸時，鋁容易氧化。可能的溶液之一 是從銦錫氧化物（IT〇）製造互連線與像素電極43、44 及41，或從在此環境中具有較穩定性的其他材質， 或者使用一適當的屏障層。 41 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 518760 五、發明說明（的 經濟部智慧財產局員工消費合作社印製 A7 B7 子應用顯示器來說，同時較佳的是製造具有小通 道長度的TFTs，利用在第19圖顯示為1〇的預型樣化 基體上進行印製，如上所述。 如果預控制之像素元並不是一顯示器元件，而是 一 5己憶體元件的話，也可以使用主動矩陣電晶體開 關之相似的裝置組態，例如電容器或二極體，至於 動態隨機存取記憶體中的實例。 除了傳導電極之外，利用直接印製方法，TFTs的 一些層體也可以被型樣化，例如篩網印製法或|jp。 第21 (a)圖（其中與第1圖相同的元件用相同的元件編 號代表）顯示一種裝置，其中半導體層4的主動層島 狀物與閘極絕緣層5可被直接印刷。在此例中並不需 要通孔，但必須利用直接印刷來製成適當閘極電極 型樣6的連接。在尋址線或互連線43、44重疊於介電 聚合物46的厚島狀物的區域中，可能必須被印刷以 提供電子絕緣（第21(b)圖）。 如上所述而形成的多個裝置可以形成在單一層體 上且藉由傳導層來互連。該等裝置可以形成在單一 位準或超過一個位準上，某些裝置則形成在其他裝 置的頂部。利用上述的互連條狀物與通孔，可以來 成緊密的電路配置。 在此發展以製造喷墨印製電晶體、通孔與互連線 的技術可以用在利用噴墨印製法來製造積體電子電 路。可以使用包含親水與忌水表面區域的陣列的預 42V. Description of the invention (37 The configuration in Figure 19 (b) is more complicated. However, most of the overall pixel-biting pixel area is available to TFTs and interconnects, and by the pixel electrode 41, the display element will be The signals are shielded on the data line 43 and the address line 44. The fabrication of the configuration needs to fill an additional dielectric layer 42 and a through hole of the conductive material 45 to connect the pixel electrode 41 to the drain electrode 3 of the TFT. Using the above The program can be made into this through-hole. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It should be noted that in this configuration, the aperture ratio will be maximized and can reach 100/0. This configuration can be simultaneously Used in display applications with backlight, such as transmissive LCD displays, because the all-polymer Ding 3 made here is highly transparent in the visible light range. Figure 20 shows the F8T2 polymer TFT The measured optical absorption spectrum, in which a liquid crystal-like semiconductor polymer is deposited, on a friction polyimide adjustment layer, the polymer chains appear to be uniaxially aligned, which can also be used as a high-resolution printing method. Like It can be seen that due to the relatively high band gap of F8T2, the device is highly transparent in most visible light ranges. If a semiconductor layer such as F8 or TFB or other polyfluorene derivative (US Patent No. 5,777,070), With a band gap higher than that used, more southern transparency can be achieved. The adjustment of the polymer chain will increase the anisotropy of the light, so that the polarization of the light parallel to the direction of the adjustment (in the picture with the •• 丨 丨 &quot; table No) can be absorbed more strongly than polarized light perpendicular to the adjustment direction (indicated by &quot; 丄 &quot; in the figure). The use of guidance is the normal polymer chain adjustment direction for polarizers, and Between the glass substrate and stupid light, the anisotropy of light can be used for LCD displays, at 297 mm. Paper size _ towel _ home standard (CNS) A4 specification (210 518760 Α7 Β7 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing 5. Description of the invention (such as further increasing the light transparency of TFTs. Under polarized light, the transistor device will appear almost colorless in visible light. If the thickness of the F8T2 layer is less than 50, 0A. All other layered TFTs containing PEDOT will have low light absorption in the visible spectral range. Another advantage of the low light absorption of the semiconductor layer is the reduced light sensitivity of the TFT characteristics to visible light. Amorphous silicon TFTs In the example, a black matrix must be used to avoid a large turn-off current under light irradiation. In the case of polymer TFTs with a wide band gap, it is not necessary to protect the TFTs from the surrounding light and the backlight of the display. The configuration in Fig. 19 (b) is also suitable for the driving transistor T1 of the LED display (Fig. 18 (b)), because it is manufactured with an inter-finger array of source and drain electrodes with a large channel width W. Using the entire area under the pixel electrode 41, it will allow the driving current of the TFT to increase. Alternatively, the bottom gate TFT configuration in Figure 17 can be used in all of the above applications (Figure 19 (c)). One of the important technical issues for manufacturing active matrix circuits is the contact between the PEDOT / PSS TFT and the pixel electrodes 2, 3, 6 and the metal interconnection lines 43, 44, and 41. Due to its strong acidity, PEDOT / PSS is not compatible with any common inorganic metals, such as aluminum. Aluminum is susceptible to oxidation when in contact with PEDOT / PSS. One of the possible solutions is to fabricate interconnects and pixel electrodes 43, 44 and 41 from indium tin oxide (IT0), or from other materials that are more stable in this environment, or use an appropriate barrier layer. 41 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------- Installation -------- Order ------ --- line (please read the precautions on the back before filling this page) 518760 V. Description of the invention (for the A7 B7 sub-application display printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, it is also better to manufacture Channel-length TFTs are printed on a pre-modeled substrate shown as 10 in Figure 19, as described above. If the pre-controlled pixel element is not a display element, but a 5th memory element It is also possible to use similar device configurations of active matrix transistor switches, such as capacitors or diodes, as for examples in dynamic random access memory. In addition to conductive electrodes, some layers of TFTs are made using direct printing methods The body can also be modeled, such as screen printing or | jp. Figure 21 (a) (where the same components as in Figure 1 are represented by the same component numbers) shows a device in which the active layer of semiconductor layer 4 The islands and the gate insulating layer 5 can be directly printed. In this example, Through-holes are required, but direct printing must be used to make the appropriate gate electrode pattern 6. In areas where the addressing or interconnecting lines 43, 44 overlap the thick islands of the dielectric polymer 46, it is possible Must be printed to provide electrical insulation (Figure 21 (b)). Multiple devices formed as described above can be formed on a single layer and interconnected by a conductive layer. These devices can be formed at a single level Or more than one level, some devices are formed on top of other devices. Using the interconnecting strips and through-holes described above, compact circuit configurations can be made. Developed here to make inkjet printed transistors, Via and interconnect technology can be used to make integrated electronic circuits using inkjet printing. Pre-42 can be used with arrays of hydrophilic and water-repellent surface areas.

本紙張尺度適用中國國家標準（CNS)A4規格（210This paper size applies to China National Standard (CNS) A4 specifications (210

川760 ------ B7_ 發明說明（扣 ^基體’其界定電晶體的通道長度以及互連線的寬 又該基體可同日寺包含高度傳導金屬互連線的陣列。 =用噴墨印製與從溶液沉積連續層體二種技術的混 〇電晶體裝置陣列可在定製地點以定製的通道寬 度進仃界定。藉由在電晶體對與是當互連體之間形Chuan 760 ------ B7_ Description of the invention (the substrate of the buckle ^ defines the channel length of the transistor and the width of the interconnection line. The substrate can also include an array of highly conductive metal interconnection lines in the same temple. = Inkjet printing Arrays of mixed transistor devices, which are two technologies of manufacturing and depositing continuous layers from solution, can be defined at custom locations with custom channel widths. By forming a shape between the transistor pair and the interconnect

A 成電子連接，利用通孔與傳導線的噴墨印製法，可 隨後製造一積體電路。 同時可能的是，預製基體可能已包含一個或多個 ::曰體裝置的組件。該基體可包含，例如完整無機 電晶體農置的陣列，豸裝置具有至少一個I露電極。 在此例中，積體電路的喷墨製造過程可包含利用喷 土印刷通孔、互連線與隔離襯塾，在電晶體對與單 或夕重位準互連方案的沉積之間之形成電子連接 (請參看第15(d)圖）。 除了電晶體置之外，電子電路可同時包含其他主 動與被動電路元件，例如顯示器或記憶體元件或電 容的或電阻元件。 經濟部智慧財產局員工消費合作社印製 利用上述的技術，具有多個電晶體的單位可以形 成且隨後組態，以進行後續的使用，利用溶液基礎 的加工處理方法。例如，具有多個電晶體5〇的一基 體，如第1(a)、（b)或（c)圖之在閘極陣列的形式中顯 不的型態，可形成在一塑膠板上（第22圖）。其他裝置， 例如二極體或電容器，可同時形成在該板上。隨後， 該板可被放置於一噴墨列印機中，其具有用以形成 43 518760 A7 五、發明說明（知 經濟部智慧財產局員工消費合作社印製 通孔52之適當溶劑（如曱醇）的列印頭，或具有用以形 成傳導的痕跡53與填滿通孔的適當材質(例如 )該噴墨列印機可在已適當程式化電腦的控 ^下來#作’該電腦具有該塑膠板上之電晶體的組 態與位置的資訊。隨後，藉由通孔形成與互連體步 驟的口併’喷墨列印機可以組配電路，利用所欲的 ^式來互連電晶體’以進行所欲的電子或邏輯功能。 这項技術因此允許利用小且便宜的裝置來在基體上 形成邏輯特定電路。 該種電路的應用實例為主動電子票卷、行李卡與 身分鑑別卡的印製。票卷或卡印製裝置可以載入 種非組配單位，每個單位包含載有多個電晶體的公 體。票卷印製裝置包含-電腦，其可❹上所述的 控制一噴墨列印機’並且可以鑑別指示票卷的有 功能的一電子電路。當需要印製票卷時，印製裝 將利用印製通孔與傳導材質，對適當的電子電路 組悲一基體，以使基體上的電晶體被適當的組配 遠基體可被隨後封裝，例如利用黏合塑膠板來密封 使電子連接端54與55暴露在外。票卷將稍後被分配 當票卷將被驗證時，將應用輸入到一個或多個輸· 端’且在-個或多個輸出端上的電路輸出端將被監 看，以驗證其功能。票卷可以較佳地印製在彈 膠基體上，以使他們方便使用作為票卷。 除了“饧或者貼標籤用途之外的使用者定義 多 基 效 置 來 入 性塑 電路A is electrically connected, and an integrated circuit can be subsequently manufactured by using an inkjet printing method of a through hole and a conductive line. It is also possible that the prefabricated matrix may already contain one or more components of a :: body device. The substrate may include, for example, an array of complete inorganic transistor farms, and the plutonium device has at least one exposed electrode. In this example, the inkjet manufacturing process of the integrated circuit may include the use of blast-printed vias, interconnect lines, and isolation liners to form between the transistor pair and the deposition of a single or multiple-level interconnect scheme. Electrical connection (see Figure 15 (d)). In addition to transistors, electronic circuits can contain other active and passive circuit elements, such as displays or memory elements or capacitive or resistive elements. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Using the above-mentioned technology, units with multiple transistors can be formed and subsequently configured for subsequent use, using solution-based processing methods. For example, a substrate with a plurality of transistors 50, such as the pattern shown in Figure 1 (a), (b), or (c), which is not shown in the gate array form, can be formed on a plastic plate ( (Figure 22). Other devices, such as diodes or capacitors, can be formed on the board at the same time. The board can then be placed in an inkjet printer with a suitable solvent (such as methanol) used to form 43 518760 A7 ) Or a suitable material to form conductive traces 53 and fill through holes (for example) the inkjet printer can be controlled under a properly programmed computer Information on the configuration and location of the transistor on the plastic board. Then, the inkjet printer can be assembled with the circuit through the through-hole formation and interconnection step and the circuit can be interconnected using the desired method. A crystal is used to perform the desired electronic or logical function. This technology therefore allows the use of small and inexpensive devices to form logic-specific circuits on the substrate. Examples of such circuits are active electronic ticket rolls, luggage cards and identification cards The ticket or card printing device can be loaded with a variety of non-assembled units, each unit contains a body carrying multiple transistors. The ticket printing device includes a computer, which can be described above. Control an inkjet printer 'and And it can identify a functional electronic circuit indicating the ticket. When the ticket needs to be printed, the printed package will use printed through holes and conductive materials to form a substrate for the appropriate electronic circuit group, so that the The transistor is properly assembled and the remote substrate can be subsequently encapsulated, for example, by using an adhesive plastic sheet to seal the electrical connection terminals 54 and 55 to the outside. The ticket will be assigned later. When the ticket is to be verified, the application is input to One or more input terminals and circuit output terminals on one or more output terminals will be monitored to verify their function. Tickets can be better printed on the elastomer base to make them convenient Used as a ticket. User-defined multi-based effects other than "入" or labeling applications

(請先閱讀背面之注意事項再填寫本頁) •線· 518760 五、發明說明（42 也可：用相似的方式製造。利用例如無線段頻率轄 射，措由遠端探測法，電路的驗證與讀取也可以進 行（1_年三月號的PhysicsW〇r|d雜該第31頁）。 錯由在標準陣列上的進行簡單嘴墨印製，最終使 用者界定電路的此力’將提供比於1廠設計電路更 大的增進彈性。 本毛明並不限於上述的實例。本發明將包含所揭 露概念的所有新㈣與進步性，以及所有揭露特徵 之所有新穎與進步的混合。 本申吻人要凊各位注意的是，本發明可包含所 有明示或暗示的特徵及其組合，不限定於上述所揭 露之界定的範圍。综上所論，只要在不偏離本發明 的範圍之下’對熟知技藝者來說可有各種不同的改 變0 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 ϋ牛標號#照表 5 玻璃基體 源極 沒極 6 主動半導體聚合 7 物/液晶狀半導體 8 聚合物 9 45 閘極絕緣層/PVP 絕緣層 閘極/型樣化層 擴散屏障聚合物 表面改造層 5^酿·亞胺層 本紙張尺度適用中國國家標準（CNS)A4規格⑵G χ 297公髮） 518760 A7 B7 五、發明說明（43 經濟部智慧財產局員工消費合作社印製 10 薄聚醯亞胺層/聚 45 傳導材質 醯亞胺型樣 46 介電聚合物 11 光阻材料 50 電晶體 12 親水基體區域/裸 52 通孔 玻璃表面 53 痕跡 13 油墨微滴 54 電子連接端 14 型樣化層 55 電子連接端 20 喷墨頭 70 介電層 21 油墨微滴 71 介電層/介電聚合 25 玻璃基體/金極 物 26 PEDOT電極層 72 互連體 27 F8T2半導體層 73 通孑L 28 PVP絕緣層 T1 電晶體 29 適當溶劑/微滴/傳 T2 電晶體 導電極 30 曲線 31 曲線 32 區域 40 外貌特徵/顯示器 元件 41 像素電極 42 介電層 43 尋址線 44 資料線 46 (請先閱讀背面之注意事項再填寫本頁)(Please read the precautions on the back before filling this page) • Wire · 518760 V. Description of the invention (42 Can also be made in a similar way. Use, for example, wireless band frequency control, remote detection method, circuit verification And reading can also be performed (PhysicsWorr.d. Page 31 of March issue). By simple printing on the standard array, the end user will define the force of the circuit. Provide greater flexibility than the design circuit of the 1st factory. This Maoming is not limited to the above examples. The invention will include all new and progressive features of the disclosed concepts, and all novel and progressive mixtures of all disclosed features. The applicant of this application would like to remind everyone that the present invention may include all explicit or implicit features and combinations, and is not limited to the defined scope disclosed above. In summary, as long as it does not deviate from the scope of the present invention 'There can be various changes for those skilled in the art. 0 Yak markings printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. #Table 5 Glass substrate source electrode 6 Active semiconductor 7 materials / liquid-crystalline semiconductor 8 polymer 9 45 gate insulation layer / PVP insulation layer gate / patterning layer diffusion barrier polymer surface modification layer 5 ^ imine · imine layer This paper applies Chinese national standards (CNS ) A4 size ⑵G χ 297 issued) 518760 A7 B7 V. Description of the invention (43 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 10 Thin polyimide layer / poly45 Conductive material 醯 imine type 46 Dielectric polymer 11 Photoresist material 50 Transistor 12 Hydrophilic matrix area / bare 52 Surface of through-hole glass 53 Trace 13 Ink droplet 54 Electronic connection end 14 Patterned layer 55 Electronic connection end 20 Inkjet head 70 Dielectric layer 21 Ink droplet 71 Dielectric layer / dielectric polymerization 25 glass substrate / gold pole 26 PEDOT electrode layer 72 interconnect 27 F8T2 semiconductor layer 73 pass L 28 PVP insulating layer T1 transistor 29 suitable solvent / microdrop / T2 transistor conducting electrode 30 Curve 31 Curve 32 Area 40 Appearance / display element 41 Pixel electrode 42 Dielectric layer 43 Addressing line 44 Data line 46 (Please read the precautions on the back before filling This page)

本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

六、申請專利範圍 第90109544號專利申請案申請專利範圍修正本91.1〇 21 1· 一種用以形成電子裝置的方法，該裝置包含一基體 上之多個部位中的一導電或半導電材質，該方法包 含： ^ 藉由混合該材質與一液體來形成一混合物； 在該機體上形成一限定結構，該結構包含該基體 之第一區中的第一區域與該基體之第二區中的第二區 域，該第一區域對該混合物之排斥性高於第二區域對 该混合物的排斥性；以及 藉由在遠基體上塗敷該混合物，以在該基體上沉 積該材質； 儿 進而利用該第一區域的相對排斥性來限定該已沉 積材質。 ^ ^ 2· 如申請專利範圍第！項之方法，其中利用該第一區域 的相對排斥性可限定該材質為該基體之第一區中所缺 少的。 、 3. 如申請專利範圍第2項之方法，其包含在該基體中藉 由第-區而與第二區分開之第三區中形成第三區心 步驟，該第一區域對該混合物的排斥性高於第三區域 對該混合物的排斥性，其中該材質可被限定於被第— 區域之相對排斥性所隔開之多個分隔部位。 4· 如申請專利範圍第3項之方法，其中介於第一與第三 區之間的第二區的寬度小於2〇微米。 5. 如申請專利範圍第3項之方法，其中介於第一與第三 ΐ纸張尺度適用中國國家標準（CNS ) Μ規格（21〇&gt;&lt;297公黎丁 -47- 518760 ♦Sixth, the scope of application for patent No. 90109544 Patent application for amendment of patent scope 91.11021. A method for forming an electronic device, the device includes a conductive or semi-conductive material in a plurality of parts on a substrate, the The method includes: ^ forming a mixture by mixing the material and a liquid; forming a defined structure on the body, the structure including a first region in a first region of the substrate and a first region in a second region of the substrate Two regions, the first region being more repellent to the mixture than the second region; and coating the mixture on a distant substrate to deposit the material on the substrate; further utilizing the first region The relative repulsion of a region defines the deposited material. ^ ^ 2 · As for the scope of patent application! The method of item, wherein the relative repulsion of the first region can be used to define that the material is lacking in the first region of the substrate. 3. The method according to item 2 of the scope of patent application, which comprises the step of forming a third center in a third region separated from the second region by a-region in the matrix, and the first region is The repellency is higher than the repellency of the third region to the mixture, wherein the material may be limited to a plurality of partitions separated by the relative repulsion of the first region. 4. The method of claim 3, wherein the width of the second region between the first and third regions is less than 20 microns. 5. If the method of applying for the third item of the patent scope, in which the paper size is between the first and the third 适用 Chinese National Standard (CNS) M specifications (21〇 &gt; &lt; 297 Gong Liding -47- 518760 ♦ 〜，入’厂〜 i υ傲本。 如申請專利範圍第 y ^ ^ 1L 負之方法，其中形成在該分隔部 位中的材質將形成—a邮 &quot; 電日日脰的源極與汲極。 如申請專利範圍第6 θ3 ^ 員之方法，其包含在該分隔部位 之間的空間中沉籍Η ^ ^ 位 L積另一材質的步驟。 如申請專利範圍第7 甘 員之方法，其中沉積在該分隔部 位之間的空間的 、、 力 材貝將形成該電晶體的一通 道。 如申請專利範圍第8項之方法，其中該第一材質為導 電的，且該另一材質為半導體電的。 瓜如申請專利範圍w，其 聚合物材質。 ⑴如申請專利範圍第7項之方法，其中該另一材質 液中沉積。 12.如申請專利範圍第u項之方法，其中該另—材質從 液體中的溶液沉積，而該液體實質上與該第—區域 互斥。 6· 8. 9. 13.如申請專利範圍第}項之方法’其包含在該基體中藉 由第二區而與第一區分開之第三區中形成第三區域^ 步驟’該第三區域對該混合物的排斥性高於 ^ —'區域 對該混合物的排斥性，而該材質可利用第一與第二區 域之相對排斥性被限定於第二區中。 14·如申請專利範圍第13項之方法，其中介於第_ 三區之間的第二區的寬度小於20微米。 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐）~, Enter the 'factory ~ i υ proud. For example, if the method of applying for a patent is in the negative range of y ^ ^ 1L, the material formed in the partition will form a source and drain of the electric sundial. For example, the method of the 6th θ3 ^ member of the scope of patent application includes the step of sinking ^^^ L product of another material in the space between the partitions. For example, the method of the 7th member of the scope of the patent application, wherein the material deposited in the space between the partitions will form a channel of the transistor. For example, the method of claim 8 in which the first material is conductive, and the other material is semiconductor electrical. Guarau applies for patent scope w, its polymer material. For example, the method of claim 7 in which the other material is deposited in a liquid. 12. The method of claim u, wherein the additional material is deposited from a solution in a liquid, and the liquid is substantially mutually exclusive with the first area. 6. 8. 9. 13. A method according to item} of the patent application scope, which includes forming a third region in a third region separated from the first region by a second region in the substrate ^ step 'the third The region's repellency to the mixture is higher than the region's repulsion to the mixture, and the material can be limited to the second region using the relative repulsion of the first and second regions. 14. The method of claim 13 in which the width of the second region between the third region and the third region is less than 20 microns. This paper size applies to China National Standard (CNS) A4 (210X297 mm) 8760 A&lt;S C8 D8 、申請專利範圍 15·如申請專利範圍第i3 一 員之方法，其中介於第一與第 一Q之間的第二區的 ^ ^ ^ 旯度小於10微米。 16.如申凊專利範圍第 負之方法，其中該材質為導電 的0 17·如申請專利範圍第 方μ 員之方法，其中該材質形成一 互運體。 18·如申請專利範圍第16 員之方法，其中該材質形成一 電日日體的一閘極。 19·如申請專利範圍第1 七法，其中第一與第二區域 圯成，而該層體沉積在一平面 結構部件上。 「w 20·如申請專利範圍第1 M之方法，其中第一區中之混合 物的接觸角度將比第- 弟_ &amp;中之混合物的接觸20。。 如申請專利範圍第1 貝之方法，其中第一區中之混合 :。的接觸角度將比第二區中之混合物的接觸角度大 如申請專利範圍第1項之方法，其中第-區中之混合 物的接觸角度將比第二區中之混合物的接觸角度 80° 〇 如申凊專利範圍第1項之方法，其中該基體的表面 置有一非極性材質，並且該第一與第二區域中之至 一區域將由非極型聚合物的表面處理法來界定。 24.如申請專利範圍第23工員之方法，其中該非極性材 21 22. 23. 本紙張尺度適用中國國豕標準（CNS ) Α4規格（2 10X297公楚) 裝 訂 線 大 少 質 -49. 518760 Λ8 B8 C8 D88760 A &lt; S C8 D8, patent application scope 15. The method of the i3 member of the patent application scope, wherein the degree of ^ ^ ^ ^ of the second region between the first and the first Q is less than 10 microns. 16. A method as claimed in the patent application with the negative range, in which the material is conductive. 017. A method as applied in the patent application, in which the material forms an interoperable body. 18. The method of the 16th member of the scope of application for a patent, wherein the material forms a gate of an electric solar heliosphere. 19. The seventeenth method of the scope of patent application, wherein the first and second regions are formed, and the layer is deposited on a planar structural component. "W 20 · If the method of patent application scope 1M, the contact angle of the mixture in the first zone will be greater than the contact angle of the mixture in the first and the second domain. The contact angle of the mixture in the first zone will be larger than the contact angle of the mixture in the second zone, as in the method of the first patent application, wherein the contact angle of the mixture in the-zone will be greater than that in the second zone. The contact angle of the mixture is 80 °. As in the method of claim 1, the surface of the substrate is provided with a non-polar material, and one to one of the first and second regions will be made of a non-polar polymer. Surface treatment method to define. 24. If the method of applying for the 23rd worker in the scope of patent application, the non-polar material 21 22. 23. This paper size applies the Chinese National Standard (CNS) A4 specification (2 10X297). Quality-49.518760 Λ8 B8 C8 D8 六、申請專利範圍 為一聚酿亞胺。 25·如申請專利範圍第24項之方法，其包含機械式地摩 檫該聚醯亞胺以提昇該聚醯亞胺之分子調整的步驟。 26·如申請專利範圍第24項之方法，其包含光學性地處 理該聚醯亞胺以提昇該聚醯亞胺之分子調整的步驟。 27·如申請專利範圍第23項之方法，其中該表面處理法 為姓刻法。 28·如申請專利範圍第23項之方法 為等離子處理法。 29·如申請專利範圍第28項之方法 四氟化物及/或氧等離子體。 如申請專利範圍第23項之方法 露在紫外線下。 如申請專利範圍第23項之方法 區域。 A如申請專利範圍第！項之方法，其中該第一區域可以 感應該導電或半導電聚合物中的聚合物鏈㈣整。 33·如申請專利範圍第1項之方法，其中利用喷墨印製法 來沉積該導電或半導電聚合物。 34·如申請專利範圍第33項之方法，其中該第二部位的 寬度小於在該噴墨印製法步驟中形成的微滴直徑。 35·如申請專利範圍第33項之方法，其中第-區域與第 二區域之間的邊界為光學上清 Θ啊’亚且該方法包含光 學性地檢測第一區域與第二區 ^ ^ ^織之間之邊界的步驟， 其中該表面處理法 30 31 本紙張尺度適用中國國家標準 (CNS) A4规格（210X297^&quot;]- 其中該等離子為碳 其中處理法包含暴 該區域之一為第一 -50- 8760 六、申請專利範圍 以及包含:^ φ 製裝置的位置。目對於該基體獨立於該項檢測之噴墨印 36. 如申請專利範圚 合物。 項之方法’其中第一材質為-聚 37. 如:Γ專利範圍…之方法，其中該第一材&quot; 一共軛聚合物。 τ貝為 38·如申請專利範圍第丨項之方法，其中第一 浮在該液體中之—無機微粒狀材質。 39.=專利範圍第1項之方法，其係使用於形成—邏 40·申喷專利範圍第1項之方法，其係使用於形成〜顯 41 如申凊專利範圍第1項之方法，其係使用於形成… 憶體裝置。 A 42 如申凊專利範圍第1項之方法，其係使用於在 電路中形成多個電晶體的一主動矩陣陣列。 M 43· ^申請專利範圍第μ之方法，其係使用於在—顯示 器中开&gt; 成多個電晶體的一主動矩陣陣列。 八 44.如申請專利範圍第丨項之方法，其係使用於在—纪 體裝置中形成多個電晶體的一主動矩陣陣列。°思 本紙張尺度適用中@國家標準（CNS；) Α4規格—( 210)^^57 -51 518760Sixth, the scope of patent application is a polyimide. 25. The method of claim 24, comprising the step of mechanically rubbing the polyimide to enhance molecular adjustment of the polyimide. 26. The method of claim 24, comprising the step of optically processing the polyimide to enhance molecular adjustment of the polyimide. 27. The method of claim 23 in the scope of patent application, wherein the surface treatment method is a surname engraving method. 28. The method for applying item 23 in the scope of patent application is plasma processing. 29. The method according to item 28 of the patent application. Tetrafluoride and / or oxygen plasma. For example, the method in the scope of patent application No. 23 is exposed to ultraviolet rays. For example, the method area of the scope of patent application No. 23. AIf the scope of patent application is the first! The method of claim, wherein the first region can sense polymer chain trimming in the conductive or semi-conductive polymer. 33. The method according to the first claim, wherein the conductive or semi-conductive polymer is deposited by an inkjet printing method. 34. The method according to claim 33, wherein the width of the second portion is smaller than the diameter of the droplet formed in the inkjet printing step. 35. The method according to item 33 of the patent application range, wherein the boundary between the first region and the second region is an optical supernatant Θ ', and the method includes optically detecting the first region and the second region ^ ^ ^ Step of weaving the boundary between which the surface treatment method 30 31 paper size is applicable to Chinese National Standard (CNS) A4 specifications (210X297 ^ &quot;]-where the plasma is carbon and the treatment method contains one of the areas as the first I-50-8760 6. The scope of the patent application and the location of the device including: ^ φ system. The inkjet printing for the substrate is independent of the test. 36. For example, the patent application method. The material is -poly 37. For example, the method of Γ patent range, wherein the first material is a conjugated polymer. Τ shell is 38. The method of the first range of patent application, wherein the first floats in the liquid No.—inorganic particulate material 39. = The method of the first scope of the patent, which is used to form—The method of the first scope of the logic 40 · Shenfen patent, which is used to form ~ The method of item 1, which It is used to form a ... memory device. A 42 The method described in item 1 of the patent scope is used to form an active matrix array of multiple transistors in a circuit. M 43 · ^ Method, which is used to form an active matrix array of a plurality of transistors in a display. 44. The method according to item 丨 of the patent application scope, which is used to form a plurality of transistors in a body device. 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