TW513810B

TW513810B - Field effect transistor and process for fabricating same

Info

Publication number: TW513810B
Application number: TW90117572A
Authority: TW
Inventors: Kurt Eisenbeiser; James E Prendergast; Jamal Ramdani; William Jay Ooms; Ravindranath Droopad
Original assignee: Motorola Inc
Priority date: 2000-07-24
Filing date: 2001-07-18
Publication date: 2002-12-11
Also published as: WO2002009186A2; WO2002009186A3

Abstract

High quality epitaxial layers of compound semiconductor materials (26) can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (24) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Description

513810513810

發明範疇本專利申請於2_年7月24日提出美國專利申請，專利申請案號為09/625 100。發明範嘴本發明通常與半導體結構及裝置有_，並且與一種势造半導體結構的方法有關，尤其，本發明與至少部份在= 半導體結構内製造的場效電晶體有關，並且與包含一 ^結晶合成半導體材料之半導體結構、裝置及積體電路的：造及使用有關。發明背景装訂絕大部份的半導體離散裝置及積體電路都是_為材料所製造而&，至少在某種程度上是因為低成本、高品質單結晶矽基板的可用性所致。諸如所謂的合成半導體材料之類的其他半導體材料具有物理屬性包括比矽更寬的帶隙及/ 或更高的遷移率，或是使這些材料非常適用於特定半導體裝置的直接帶隙。可惜’合成半導體材料的成本通常高於矽，並且在大型晶圓中，不如矽那樣容易取得。晶圓中可取得的坤化鎵（Gallium arsenide ; GaAs)(最容易取得的合成半導體材料）的直徑最大只有大約15〇毫米（_)。相反地，可取得的矽晶圓具育最大大約300毫米（mm)的直徑，並且最廣泛使用的是200 mm。150 mm GaAs晶圓的成本高於對應的石夕晶圓許多倍。其他的合成半導體材料晶圓更不容易取得’並且成本比 GaAs更高。因為希望有合成半導體材料的特性，並且因為通常目前 -4 A7Scope of the Invention This patent application filed a US patent application on July 24, 2012. The patent application number is 09/625 100. The invention is generally related to semiconductor structures and devices, and is related to a method for forming semiconductor structures. In particular, the invention is related to field-effect transistors manufactured at least in part ^ Semiconductor structures, devices and integrated circuits of crystalline synthetic semiconductor materials: related to fabrication and use. BACKGROUND OF THE INVENTION Binding The vast majority of semiconductor discrete devices and integrated circuits are made of materials & at least in part due to the availability of low cost, high quality single crystal silicon substrates. Other semiconductor materials, such as so-called synthetic semiconductor materials, have physical properties including a wider band gap and / or higher mobility than silicon, or direct band gaps that make these materials well-suited for specific semiconductor devices. Unfortunately, the cost of synthetic semiconductor materials is usually higher than that of silicon, and in large wafers, it is not as easy to obtain as silicon. Gallium arsenide (GaAs) (the most easily available synthetic semiconductor material) available in wafers has a diameter of only about 150 mm (_). In contrast, available silicon wafers have diameters up to about 300 millimeters (mm), and the most widely used is 200 mm. The cost of a 150 mm GaAs wafer is many times higher than the corresponding Shixi wafer. Other synthetic semiconductor material wafers are less accessible and cost more than GaAs. Because the properties of synthetic semiconductor materials are desired, and because currently -4 A7

發明説明一成本咼及較無法取彳于大容積形式，所以許多年來已嘗試在異質基板上生長合成半導體材料薄膜。然而，為了實現取佳的合成半導體材料特性，需要高結晶品質的單結晶膜。例如，已嘗試在鍺、矽及各種隔離體上生長單結晶合成半導體材料層。這些嘗試尚未成功，因為主晶與生長晶間的晶格不匹配，導致所產生的合成半導體材料薄膜的結晶品質不佳。如果以低成本取得大面積高品質單結晶合成半導體材料溥膜，則有助於以低成本在該薄膜上製造各種半導體裝置，其成本低於在合成半導體材料的大容積晶圓上製造此類裝置的成本，或是低於在合成半導體材料之大容積晶圓上此類材料料的磊晶膜中製造此類裝置的成本。此外，如果能夠在諸如矽晶圓的大容積晶圓上體現高品質單結晶合成半導體材料的薄膜’則可利用矽及合成半導體材料的最佳特性來實現積體裝置結構，例如，包含場效電晶體（FE丁）。时因此，需要有一種半導體結構，其能夠提供優於另一種單紇aa材料的高品質單結晶合成半導體膜，以一種製造此類結構的方法。而要有圖式簡單描述本發明將藉由實例及在這些實例及附圖内，並且其中：附圖來進行解說，但本發明未限定其中相似的參照代表相似的元件，圖1至3顯示根據本發明各種具體實施例之裝置結構的斷 -5- 五發明説明（ #圖4以圖表顯示可獲得的最大膜厚度與主晶和生長結晶覆蓋層間晶格不匹配間的關係；是、圖）顯7F包括單結晶容納緩衝層之結構的高解析度透射式電子顯微照相（Transmisslon Electron Micrograph)圖；；圖6顯不包括單結晶容納緩衝層之結構的χ射線衍射譜；圖7顯不包括非結晶氧化物層之結構的高解析度透射式電子顯微照相（Transm;ssi〇n Eiectr〇n廳等响圖；圖8顯示包括非結晶氧化物層之結構的X射線衍射譜；、圖9顯示半導體結構川的斷面原理圖，其包括在單結晶合成半導體層上形成的源電極及汲電極，以及在單結晶基板中形成的閘電極；圖員不相似於圖9所示之半導體結構的斷面原理圖，用以解說摻雜雜質的源極和汲極區域，· 圖11顯示包含摻雜雜質的源極和汲極區域及一對閘極之半導體結構的斷面原理圖； r圖12顯示在單結晶半導體基板中摻雜雜質之源極和沒極斷面原理圖’其中單結晶半導體基板具有在單結晶 Q成半導體層中形成的附帶閘極；圖：顯示廣泛相似於圖12所示之半導體結構的斷面原理㈣以進一步解說在單結晶合成半導體層中形成之分隔的，原電極和及電極；Description of the invention One cost and less able to be obtained in a large volume form, so for many years, attempts have been made to grow synthetic semiconductor material films on heterogeneous substrates. However, in order to achieve excellent characteristics of a synthetic semiconductor material, a high-quality single crystal film is required. For example, attempts have been made to grow single crystal synthetic semiconductor material layers on germanium, silicon, and various separators. These attempts have not been successful because the lattice mismatch between the main crystal and the growing crystals results in poor crystal quality of the resulting thin film of the synthetic semiconductor material. If a large-area, high-quality single crystal synthetic semiconductor material film is obtained at a low cost, it will help to manufacture various semiconductor devices on the film at a lower cost, which is lower than manufacturing such a large-volume wafer on a synthetic semiconductor material. The cost of the device is lower than the cost of manufacturing such a device in an epitaxial film of such material on a large volume wafer of synthetic semiconductor material. In addition, if a thin film of high-quality single-crystal synthetic semiconductor material can be embodied on a large-volume wafer such as a silicon wafer, then the best characteristics of silicon and synthetic semiconductor materials can be used to implement a device structure that includes, for example, field effect Transistor (FE Ding). Therefore, there is a need for a semiconductor structure that can provide a high-quality single-crystal synthetic semiconductor film superior to another mono-aaa material, and a method for manufacturing such a structure. If the invention is to be briefly described with drawings, examples will be described in the examples and the drawings, and in which: The drawings are used to explain, but the invention is not limited in which similar references represent similar elements, and FIGS. 1 to 3 show Breaking of the device structure according to various specific embodiments of the present invention-5- Fifth invention description (# FIG. 4 shows the relationship between the maximum film thickness obtainable and the lattice mismatch between the main crystal and the growing crystal cover layer in a graph; ) Shows the high-resolution transmission electron micrograph (Transmisslon Electron Micrograph) of the structure including the single crystal accommodating buffer layer; FIG. 6 shows the x-ray diffraction spectrum of the structure excluding the single crystal accommodating buffer layer; High-resolution transmission electron microscopy of the structure excluding the amorphous oxide layer (Transm; ssion Eiectron) and other sound diagrams; Figure 8 shows the X-ray diffraction spectrum of the structure including the amorphous oxide layer; And FIG. 9 shows a schematic cross-sectional view of a semiconductor structure, including a source electrode and a drain electrode formed on a single crystal synthetic semiconductor layer, and a gate electrode formed in a single crystal substrate. The figure is not similar to the cross-sectional schematic diagram of the semiconductor structure shown in FIG. 9 to explain the source and drain regions of doped impurities, and FIG. 11 shows the source and drain regions containing doped impurities and a Sectional schematic diagram of the semiconductor structure of the gate electrode; r FIG. 12 shows the schematic diagram of the source and non-polarized section doped with impurities in a single crystal semiconductor substrate, where the single crystal semiconductor substrate has a single crystal Q semiconductor layer The formed gate electrode is shown; Figure: shows the cross-sectional principle of the semiconductor structure broadly similar to that shown in FIG. 12 to further explain the original electrode and the electrode formed in the single crystal synthetic semiconductor layer;

圖14至18顯示進—步包含非結晶氧他具體實施例的斷面原理圖。 H 熟知技藝人士應明白’圖中的元件是簡化的圖解，並且本紙張尺度適用中國國挪公爱） -6- 513810 A7 B7 五、發明説明（4 不需要按比例繪製。例如，相對於其他元件，圖中部份元的尺寸了肖b過度放大，以利於更容易瞭解本發明的具體實施例。圖式詳細說明圖1顯示根據本發明一項具體實施例之半導體結構2〇之一部份的斷面圖。半導體結構20包括單結晶基板22、包含單結晶材料的容納緩衝層24以及單結晶合成半導體材料層％在此上下文中9吾「單結晶」應具有半導體產業内常用的意義。術語「單結晶」應、代表屬於單晶或大體上屬於單晶的材料，並且應包含具有相當少量缺陷（諸如矽或矽化鍺或混合物之基板中常發現的位錯等等）的材料，以及半導體產業中常發現之此類材料的磊晶層。根據本發明—項具體實施例，結構還包括位於基板22 與容納緩衝層24之間的非結晶中間層28。結構2q還可包括位於容納緩衝層24與合成半導體層％之間的模板層 3〇。如下文中詳細的說明’模板層有助於在容納緩衝層上開始生長合成半導體層。非結晶中間層有助於減緩容納緩衝層應'變’並#此協助生長高結晶品質容納緩衝層。田根據本發明-項具體實施例，基板22是單結^晶圓，取好是大尺寸單結晶矽晶圓。晶圓可能屬於周期表第以族材料，並且最好是第IVA族材料。第IV族半導體材料的實例包括石夕、冑、混合梦與鍺、混切與破、混切、錯盘碳等等。基板22最好是包切或鍺的⑽，並且最好是如= 導體業產中使用的高品質單結晶石夕晶圓。容納緩衝居214 to 18 show schematic sectional views of specific embodiments which further include amorphous oxygen. H. Those skilled in the art should understand that 'the components in the figure are simplified diagrams, and this paper scale applies to China's national public love) -6- 513810 A7 B7 V. Description of the invention (4 does not need to be drawn to scale. For example, compared to other Components, the dimensions of some elements in the figure are exaggerated to facilitate understanding of specific embodiments of the present invention. DETAILED DESCRIPTION OF THE DRAWINGS FIG. 1 shows a part of a semiconductor structure 20 according to a specific embodiment of the present invention. The semiconductor structure 20 includes a single crystal substrate 22, a buffer layer 24 containing a single crystal material, and a single crystal synthetic semiconductor material layer. In this context, “single crystal” should have a meaning commonly used in the semiconductor industry. The term "single crystal" shall, represent a material that is single crystal or substantially single crystal, and shall include materials with a relatively small number of defects such as dislocations commonly found in substrates of silicon or germanium silicide or mixtures, and An epitaxial layer of such a material often found in the semiconductor industry. According to an embodiment of the present invention, the structure further includes a substrate 22 and a housing The amorphous intermediate layer 28 between the punching layers 24. The structure 2q may further include a template layer 30 between the containing buffer layer 24 and the synthetic semiconductor layer%. As explained in detail below, the 'template layer helps to contain the buffer layer A synthetic semiconductor layer begins to grow on top. The amorphous intermediate layer helps to slow down the containment buffer layer's 'change' and # assists in the growth of a high crystalline quality containment buffer layer. Tian According to one embodiment of the present invention, the substrate 22 is a single junction ^ The wafer is a large-size single crystal silicon wafer. The wafer may belong to Group I materials of the periodic table, and is preferably a Group IVA material. Examples of Group IV semiconductor materials include Shi Xi, Pu, Mixed Dream and Germanium, mixed-cut and broken, mixed-cut, staggered carbon, etc. The substrate 22 is preferably an overcut or germanium hafnium, and is preferably a high-quality monocrystalline stone wafer such as used in the conductor industry. Buffer Home 2

A7A7

好是基礎基板上磊晶+具& σσ & λ & 長的早、’、σ晶氧化物或氮^化物材料。根據本發明一項呈體营Fortunately, epitaxial + σσ & λ & long early, ', σ crystal oxide or nitride materials on the base substrate. A sports camp according to the present invention

〜、总貝軛例，非結晶中間層28係在基板U 、曰長並位於基板22與生長的容納緩衝層24之間，其方式是在生長容納緩衝層24期間氧化基板22。非結晶中間層係用來減緩由於基板與緩衝層間晶格常數差異而導致容納緩衝層可能會發生的«。在本文中，晶格常數代表在表面平面上所測量之細胞原子間的距離。如果非結晶中間層未減緩此類的應變，則應變會導致容納緩衝層中結晶結：中的缺陷。接著，纟納緩衝層中結晶結構中的缺陷將導致難以κ現單結晶兮戚半導體層26中的高品質結晶結構。备肩緩衝層24最好是選用與基礎基板結晶相容及與覆蓋 σ成半導體材料結晶相容的單結晶氧化物或氮化物材料。例如，此類的材料可能是具有大體上匹配基板及後續供應之半V肢材料之晶格結構的氧化物或氮化物。容納緩衝層所適用的材料包括氧化金屬，諸如鹼土金屬鈦酸鹽、鹼土金屬錘酸鹽、鹼土金屬铪酸鹽、鹼土金屬鉅酸鹽、鹼土金屬釘酸鹽、鹼土金屬鈮酸鹽、鹼土金屬釩酸鹽、如鹼土金屬竭基鈣鈦礦（alkaHne earth metal tin-based perovskite)之類的氧化鈣鈦礦、鹼土金屬鋁酸鹽、_鋁酸鹽、氧化鑭銳及氧化此。另外’容納緩衝層也可使用諸如氮化鎵、氮化鋁及氮化哪之類的氮化物。這些材料大部份是隔離體，雖然 (例如）4思、釕是導體。一般而言’這些材料是氧化金屬或氮化金屬，尤其，這些氧化金屬或氮化金屬包括至少兩個不同的金屬元素。在某些特定應用中’氧化金屬或氮化金屬本紙張尺度家標準(CNS) A4規格(21〇χ297公釐)In the example of the total yoke, the amorphous intermediate layer 28 is formed on the substrate U and is long and is located between the substrate 22 and the growing accommodating buffer layer 24 by oxidizing the substrate 22 during the growth of the accommodating buffer layer 24. The amorphous intermediate layer is used to mitigate the possible occurrence of the buffer layer due to the difference in lattice constant between the substrate and the buffer layer. In this paper, the lattice constant represents the distance between cell atoms measured on the surface plane. If the amorphous intermediate layer does not mitigate such strains, the strains can cause defects in the crystalline junction: in the containment buffer layer. Next, defects in the crystalline structure in the sonar buffer layer will cause it to be difficult to singly crystallize the high-quality crystalline structure in the semiconductor layer 26. The shoulder buffer layer 24 is preferably a single crystal oxide or nitride material that is compatible with the crystals of the base substrate and compatible with the crystals of the semiconductor material covering σ. For example, such materials may be oxides or nitrides that have a lattice structure that substantially matches the substrate and subsequent supply of half-limb materials. Materials suitable for containing the buffer layer include oxidized metals such as alkaline earth metal titanates, alkaline earth metal hammer salts, alkaline earth metal phosphonates, alkaline earth metal giant salts, alkaline earth metal nail salts, alkaline earth metal niobates, alkaline earth metals Vanadates, perovskites such as alkaHne earth metal tin-based perovskite, alkaline earth metal aluminates, aluminum oxides, lanthanum oxides, and oxides. In addition, the 'accommodating buffer layer may use nitrides such as gallium nitride, aluminum nitride, and nitride. Most of these materials are insulators, although (for example) Si, ruthenium is a conductor. Generally speaking, these materials are metal oxides or metal nitrides. In particular, these metal oxides or metal nitrides include at least two different metal elements. In some specific applications, ’Oxide or Nitride ’s Metal Paper Standard (CNS) A4 (21 × 297 mm)

裝訂Binding

k 513810 A7 B7 五、發明説明（6 包括至少三個或三個以上不同的金屬元素。非結晶中間層28最由是藉由將基板22表面氧化所形成的氧化物，尤其是由氧化矽所組成。非結晶中間層28的厚度足以減緩因基板22與容納緩衝層24的晶格常數間不匹配所導致的應變。通常，非結晶中間層28的厚度大約是〇5到5 毫微米（nm)。可按照特定半導體結構的需求，從第ΠIA與VA族元素 (III_V半導體合成物）、混合ΠΙ-V合成物、第ll(A與B)與 ▽^無疋素⑴^丨半導體合成物卜以及混合丨丨^^合成物中選用早結晶合成半導體層26的合成半導體材料。實例包括砷化鎵（GaAs)、砷化鎵銦（GaInAs)、砷化鎵鋁（GaAiAs)、磷化釦（InP)、硫化鎘（Cds)、碲化鎘汞、硒化鋅 (，）西化鋅(ZnSSe)等等。適合的模板材料以化學方式鍵：在容納緩衝層24表面上的選取部位，並提供後續合成半‘肖豆層26猫日日生長集結（nucieati〇n)的部位。下文中將說明適用於模板層3〇的材料。圖j顯不根據本發明另一項具體實施例之半導體結構邛伤的_面圖。結構4〇類似於前文說明的半導體結構 2〇，除了介於容納緩衝層24與單結構合成半導體材料層^ 間的額外緩衝層32以外。具體而言，額外緩衝層位於模板層3〇與覆蓋合成半導體材料層之間。當容納緩衝層無法適 *匹配覆蓋單結晶合成半導體材料層日寺，半導體或合成半導體材料所形成的額外緩衝層係用來提供晶格補償。圖3顯不根據本發明另一項示範性具體實施例之半導體結 -9 -k 513810 A7 B7 V. Description of the invention (6 includes at least three or more different metal elements. The amorphous intermediate layer 28 is most preferably an oxide formed by oxidizing the surface of the substrate 22, especially by silicon oxide. The thickness of the amorphous intermediate layer 28 is sufficient to reduce the strain caused by the mismatch between the lattice constants of the substrate 22 and the accommodating buffer layer 24. Generally, the thickness of the amorphous intermediate layer 28 is about 0.05 to 5 nanometers (nm). ). According to the requirements of specific semiconductor structures, from ΠIA and VA group elements (III_V semiconductor composition), mixed III-V composition, ll (A and B) and ▽ ^ 疋素疋 ^ 丨 semiconductor composition And mixed 丨丨 ^^ Synthetic semiconductor materials using early crystalline synthetic semiconductor layer 26 are used in the composition. Examples include gallium arsenide (GaAs), indium gallium arsenide (GaInAs), aluminum gallium arsenide (GaAiAs), phosphide button (InP), cadmium sulfide (Cds), mercury cadmium telluride, zinc selenide (,) zinc sulfide (ZnSSe), etc. Suitable template materials are chemically bonded: at selected locations on the surface of the containing buffer layer 24, and Provides follow-up synthetic half 'Xiaodou layer 26 cat day Parts of long assembly (nucieation). Materials suitable for the template layer 30 will be described below. FIG. J shows a surface view of a semiconductor structure that is not damaged according to another embodiment of the present invention. The structure 40 is similar In the semiconductor structure 20 described above, in addition to the additional buffer layer 32 interposed between the containing buffer layer 24 and the single-structure synthetic semiconductor material layer ^ Specifically, the additional buffer layer is located in the template layer 30 and covers the synthetic semiconductor material layer. Between. When the buffer layer cannot be properly matched to cover the single crystal synthetic semiconductor material layer, the extra buffer layer formed by the semiconductor or synthetic semiconductor material is used to provide lattice compensation. Figure 3 shows another aspect according to the present invention. Exemplary embodiment of semiconductor junction-9-

五、發明説明（7 ) 構34之一部份的斷面原理圖。結構34類似於結構2〇，除了結構34包括非結晶層36(而不是容納緩衝層24及非結晶介面層28)及額外半導體層38以外。如下文中的詳細說明，可用如上文所述的類似方法來形成非結晶層36 ,其方式是先形成一容納緩衝層及一非結晶介面層。然後，形成單結晶半導體層3 8，以覆蓋單結晶容、’、内緩衝層。然後’將容納緩衝層經過退火處理，以將單乡士晶容納緩衝層轉換為非結晶層。以此方式形成的非結晶層 36包括來自於容納緩衝層及介面層的材料，非結晶層可能是或不是混合物（ama丨gamate)。因此，層36可包括一層或兩層非結晶層。介於基板22與半導體層38間形成的非結晶層 36(接著層38形成）減緩介於層22與38間的應力，並且提供真正合乎標準的基板、以利後續處理—例如，合成半導體層 26形成。曰月il文中配合圖1及2所說明的製程適用於在一單結晶基板上生長單結晶合成半導體層。然而，配合圖3所說明之包括將單…aa谷納緩衝層轉換成非結晶氧化物層的製造更適合生長單結晶合成半導體層，因為其允許減緩層26中的任何應力。半導體層38可包括整份本說明書中配合合成半導體材料層26或額外緩衝脣32所說明的任何材料。例如，層 3 8可包括單結晶第IV族或單結晶合成半導體材料。根據本發明一項具體實施例，半導體層38於層％形成期間係作為退火罩（anneal cap)，並且於後續半導體層％形成 A7 B7 8 五、發明説明（期間作為模板。因此，層3 8的厚度最好是足以提供適合生長層26之模板的厚度（至少一單層），並且是允許形成作為無缺陷單結晶半導體合成物之層3 8的薄度。根據本發明另一項具體實施例，半導體層38包括合成半導體材料（例如，前文中配合合成半導體層26所說明的材料） ’其厚度足以在層3 8内形成裝置。在此情況下，根據本發明的半導體結構不包括合成半導體層26。換言之，根據此項具體實施例的半導體結構只包括佈置於非結晶氧化物層 36上的合成半導體層。下列非限制性、作例證的實例說明根據本發明各種替代具體實施例之結構20、40與結構34中可用的各種材料組合這些元全疋用來說明，並且本發明不限定於這些作例證的實例。實例1 根據本發明一項具體實施例，單結晶基板22係以（1〇〇) 方向為目的之矽基板。矽基板可能是（例如）用來製造直徑大約為200到300 mm之互補金屬氧化物半導體（CM〇s)積體電路中常用的石夕基板。根據本發明的此項具體實施例，容納緩衝層24是SrzBai_zTi〇3單結晶層，其中z介於〇到丨範圍内，而非結晶中間層是在介於矽基板與容納緩衝層間之界面上形成的氧化矽_χ)層。所選用的2值是為了獲得緊密匹配對應之後續形成層26之晶格常數的一個或一個以上晶格常數。例如，容納緩衝層的厚度大約在2_到⑽疆的範圍内一般而言，希望容納並且最好是大約10 nm的厚度 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱^ *----- 513810 A7 ___B7 五、發明説明（9 ) 緩衝層的厚度足以隔離合成半導體層與基板，以獲得所希望的電子及光學特性。厚度低於100 nm的層通常提供較少的額外優點，並增加不必要的成本；然而，若需要，可製造較厚的層。氧化矽非結晶中間層厚度大約在〇 5 ^爪到5 nm的範圍内，並且最好是大約1511111到251^的厚度。根據本發明的此項具體實施例，合成半導體材料層“是砷化鎵（GaAs)或砷化鋁鎵（A1GaAs)層，其厚度大約是i 到大約100微米（μιη)，並且最好是大約〇5 μη^η〇 pm的厚度。厚度通常視所準備之層的應用而定。為了促進在單結曰曰氧化物上磊晶生長砷化蘇或砷化鋁鎵，將藉由覆蓋氧化層來形成模板層。模板層最好是Ti_As、Sr-〇_As、Sr_Ga_〇或Sr-Al-Ο的1到i〇層單分子層（m〇n〇layer)。藉由較佳實例，已證實丁i-As或Sr-Ga-〇的1到2層單分子層可成功生長 GaAs 層。實例2 根據本發明進一步具體實施例，單結晶基板22是如上文所述的矽基板。容納緩衝層是立體或斜方晶相之勰或鋇鍅酸鹽或铪的單結晶氧化物，而非結晶中間層是在介於矽基板與容納緩衝層間之界面上形成的氧化矽層。容納緩衝層的厚度大約在2 nm到1〇〇 nm的範圍内，並且最好是至少5 n m的居度，以確保足夠的結晶及表面品質，並且是由單会士晶 SrZr03、BaZr03、SrHf03、BaSn〇3 或 BaHf〇3所組成。例如可在大約7〇〇度C的溫度下生長BaZr〇3單結晶氧化層。所產生之結晶氧化举；的晶格結構呈現相對於基板石夕晶格結 -12- ^紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公复）' ' ---- 513810 A7 _______Β7 五、發明説明（1〇 ) 構的4 5度旋轉。由廷些鎖錯酸鹽或給材料所形成的容納緩衝層適合在磷化銦（InP)系統中生長合成半導體材料。合成半導體材料可月b疋（例如）厚度大約是1〇 nm到10 μη!的鱗化銦（inP) 、石申化铜鎵（InGaAs)、砷化鋁銦（AiInAs)或磷砷化鋁銦鎵 (GainAsP)適用於此結構的模板層是錯-神（Zr-As)、錯- 磷（Zr-P)、給KHf_As)、铪KHf_p)、在思-氧_碎^卜〇七）、銘-氧-碟（Sr-0-Ρ)、鋇-氧-石申（Ba-〇-As)、銦，-氧（In-Sr_ 〇)或鋇氧(Ba-〇-P)的1到1〇層單分子層（m〇n〇iayer)，並且最好是這些材料箕中一個的丨到2層單分子層。藉由實例 ’就鋇錯酸鹽容納緩衝層而言，表面係以鍅的1到2層單分子層終止’之後接著沈澱砷的1到2層單分子層，以形成5. Description of the invention (7) A schematic sectional view of a part of the structure 34. The structure 34 is similar to the structure 20, except that the structure 34 includes an amorphous layer 36 (instead of containing the buffer layer 24 and the amorphous interface layer 28) and an additional semiconductor layer 38. As described in detail below, the amorphous layer 36 can be formed by a similar method as described above by first forming a receiving buffer layer and an amorphous interface layer. Then, a single-crystal semiconductor layer 38 is formed so as to cover the single-crystal volume, and the inner buffer layer. Then, the accommodating buffer layer is annealed to convert the single native crystal accommodating buffer layer into an amorphous layer. The amorphous layer 36 formed in this manner includes materials from the receiving buffer layer and the interface layer, and the amorphous layer may or may not be a mixture. Thus, layer 36 may include one or two amorphous layers. An amorphous layer 36 formed between the substrate 22 and the semiconductor layer 38 (formed after the layer 38) relieves the stress between the layers 22 and 38 and provides a truly standard substrate for subsequent processing—for example, a synthetic semiconductor layer 26formed. The process described in conjunction with FIGS. 1 and 2 in the Japanese text is suitable for growing a single crystal synthetic semiconductor layer on a single crystal substrate. However, the fabrication illustrated in conjunction with FIG. 3, including the conversion of a single ... aa valley buffer layer into an amorphous oxide layer, is more suitable for growing a single crystalline synthetic semiconductor layer because it allows any stress in the layer 26 to be mitigated. Semiconductor layer 38 may include any material described throughout this specification in conjunction with layer 26 of synthetic semiconductor material or additional buffer lip 32. For example, layer 38 may include a single crystalline Group IV or single crystalline synthetic semiconductor material. According to a specific embodiment of the present invention, the semiconductor layer 38 is used as an annealing cap during the formation of the layer%, and A7 B7 is formed during the subsequent semiconductor layer%. 5. Description of the invention (the period is used as a template. Therefore, the layer 3 8 The thickness is preferably sufficient to provide a thickness (at least one single layer) suitable for the template of the growth layer 26, and is thin enough to allow the formation of the layer 38 as a defect-free single crystal semiconductor composition. According to another embodiment of the present invention For example, the semiconductor layer 38 includes a synthetic semiconductor material (e.g., the material described above in conjunction with the synthetic semiconductor layer 26) 'is thick enough to form a device within the layer 38. In this case, the semiconductor structure according to the present invention does not include synthesis Semiconductor layer 26. In other words, the semiconductor structure according to this specific embodiment includes only a synthetic semiconductor layer disposed on an amorphous oxide layer 36. The following non-limiting, illustrative examples illustrate various alternative embodiments of the present invention. Combinations of various materials available in structures 20, 40 and 34 are used for illustration, and the invention is not limited These are illustrative examples. Example 1 According to a specific embodiment of the present invention, a single crystal substrate 22 is a silicon substrate with a (100) orientation. The silicon substrate may be, for example, used to make a diameter of about 200 to A 300-mm complementary metal oxide semiconductor (CM0s) integrated circuit commonly used in Shi Xi substrates. According to this embodiment of the present invention, the containing buffer layer 24 is a SrzBai_zTi03 single crystal layer, where z is between Within the range, the non-crystalline intermediate layer is a silicon oxide (x) layer formed on the interface between the silicon substrate and the containing buffer layer. The two values selected are used to obtain one or more lattice constants that closely match the lattice constants of the subsequent formation layer 26. For example, the thickness of the containing buffer layer is in the range of about 2 mm to about 10 mm. Generally speaking, it is desirable to hold and preferably a thickness of about 10 nm.-11-This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love ^ * ----- 513810 A7 ___B7 V. Description of the invention (9) The thickness of the buffer layer is sufficient to isolate the synthetic semiconductor layer from the substrate to obtain the desired electronic and optical characteristics. Layers with a thickness of less than 100 nm are usually Provides fewer additional advantages and increases unnecessary costs; however, thicker layers can be made if needed. The thickness of the silicon oxide amorphous intermediate layer is in the range of about 5 cm to 5 nm, and is preferably According to this embodiment of the present invention, the synthetic semiconductor material layer is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (A1GaAs) with a thickness of about i to about 100 microns ( μιη), and preferably a thickness of about 05 μη ^ η〇pm. The thickness usually depends on the application of the prepared layer. In order to promote the epitaxial growth of arsenide or aluminum arsenide on single-junction oxides Gallium will be covered by an oxide layer Form a template layer. The template layer is preferably a 1 to i0 monomolecular layer (monolayer) of Ti_As, Sr-〇_As, Sr_Ga_〇, or Sr-Al-O. With preferred examples, the It was confirmed that 1 to 2 monomolecular layers of D-i-As or Sr-Ga-O can successfully grow a GaAs layer. Example 2 According to a further specific embodiment of the present invention, the single crystal substrate 22 is a silicon substrate as described above. A buffer is accommodated The layer is a monocrystalline oxide of osmium or barium osmium salt or osmium in a three-dimensional or orthorhombic phase, and the non-crystalline intermediate layer is a silicon oxide layer formed on the interface between the silicon substrate and the containing buffer layer. The containing buffer layer The thickness is in the range of about 2 nm to 100 nm, and preferably at least 5 nm, to ensure sufficient crystal and surface quality, and is made of single crystal SrZr03, BaZr03, SrHf03, BaSn. 3 or BaHf〇3. For example, a BaZrO3 single crystal oxide layer can be grown at a temperature of about 700 degrees C. The resulting crystalline oxides; the lattice structure appears relative to the substrate Shi Xi lattice junction- 12- ^ Paper size applies to China National Standard (CNS) A4 (210 X 297 public copy) '' ---- 513810 A 7 _______ Β7 V. Description of the invention (45) Rotation of 45 degrees. The containing buffer layer formed by these salts of acid salts or materials is suitable for growing synthetic semiconductor materials in indium phosphide (InP) systems. Synthetic semiconductors The material may be, for example, indium indium (inP), copper gallium (InGaAs), indium aluminum arsenide (AiInAs), or aluminum indium gallium arsenide (inP) with a thickness of about 10 nm to 10 μη! GainAsP) suitable template layers for this structure are Zr-As, Zr-P, KHf_As), 铪 KHf_p), Si-Oxygen_Break ^ B07), Ming- 1 to 1 of oxygen-dish (Sr-0-P), barium-oxy-stone (Ba-〇-As), indium, -oxygen (In-Sr_ 〇), or barium oxygen (Ba-〇-P) Monolayers, and preferably one to two monolayers of these materials. By way of example, as far as the barium salt-acid-accommodating buffer layer is concerned, the surface is terminated with 1 to 2 monolayers of tritium followed by precipitation of 1 to 2 monomolecular layers of arsenic to form

Zr As模板。然後，在模板層上生長以填化銦系統為材料的合成半導體材料的單結晶層。所產生之合成半導體材料的晶格結構呈現相對於容納緩衝層晶格結構的45度旋轉，並且不匹配（ΙΟΟ)ΙηΡ的晶格小於2·5%，並且最好小於大約 1.0% 〇 ’ 實例3 根據本發明進一步具體實施例，假設結構適合生長Π-νι 材料磊晶膜，以覆蓋矽基板。如上文所述，基板最好是矽晶圓。適合的容納緩衝層材料是SrxBai xTi〇3，其中X介於〇到1範圍内’厚度大約在2 nm到100 nm的範圍内，並且最好是大約5 nm到15 nm的厚度。π-VI合成半導體材料可能是 (例如）鋅亞砸酸鹽（ZnSe)或鋅硫亞硒酸鹽（ZnSSe)。適用於 -13- 本紙張尺度適财國國家標準(CNS) Μ規格( χ 297公爱) - --- M3810 A7 B7 五、發明説明（” ) --- 此材料系統的模板層包括辞-氧（Zn_〇)的！到丨〇層單分子層，之後接著過量的鋅的1到2單分子層’之後接著位於表：上的鋅亞石西酸鹽。或者，模板層可能是（例如）錯LS)^ 到10層單分子層，之後接著ZnSeS。實例4 本务明的此項具體實施例是圖2所示之結構4〇的實例。基板22、單結晶氧化層24及單結晶合成半導體材料層％可能類似於實例K所說明對應項。此外，額外緩衝層32係用來減緩應變，其中應變是由於容納緩衝層晶格與單結晶半筹體材料間不匹配所致。緩衝層32可能是一層鍺或GAS、砷化鋁鎵（AlGaAs)、磷化銦鎵（InGaP)、磷化鋁鎵（Αΐ(^ρ)、砷化銦鎵（InGaAs)、磷化鋁銦（Allnp)、磷砷化鎵（GaAsp)或舛化銦鎵(InGaP)應' 力補償超晶格。根據此具體實施例的一項觀點，緩衝層32包括GaASxPix超晶格，其中χ值介於q 至1之間的範圍内。根據另一項觀點，緩衝層32包括inyGi_yP 超晶格，其中以直介於0至1之間的範圍内。藉由看情況來改變X值或y值，晶格常數會隨之橫跨超晶格從下到上變改，以產生基礎氧化物與覆蓋合成半導體材料之晶格常數間的匹配。諸如前面所列出之其他材料的合成物也同樣會改良，以用相似的方式來處理層32的晶格常數。超晶格的厚度大約在50 nm到500 0111的範圍内，並且最好是大約ι〇〇到200 nm的厚度。此結構的模板可能與實例}中說明的模板相同。或者，緩衝層32可能是厚度為！ nm到5〇 nm的的單結晶鍺，並且最好是大約2 niT^]20 nm的厚度。在使用鍺緩衝 -14 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 513810 A7 _________B7 五、發明説明（12 1 " -— 層的過程中，可使用厚度大約一個單分子層的鍺-錯（Ge_sr) 或鍺·鈦（Ge-Ti)的模板層，以作為後續生長單結晶合成半導體材料層的集結部位。形成氧化層的方式是覆蓋單分子層鏍或單分子層鈦，以作為後續沈澱單結晶鍺的集結部位。單分子層勰或單分子層鈦提供第一單分子層鍺可鍵合的集結部位。 σ 實例5 此實例還說明圖2所示之結構4〇中有用的材料。基板材料 22、容納緩衝層24及單結晶合成半導體材料層％及模板層 ^ 〇月b與貝例2中所说明對應項相同。此外，會在容納缓衝層與覆蓋單結晶合成半導體材料層之間***緩衝層32。緩衝層（進一步的單結晶半導體材料）可能是（例如）砷化銦鎵 (InGaAs)或石申化鋼舞（InA1As)的粒級層（㈣㈣一⑺。根據此具體實施例的-項觀點，緩衝層32包括InGaAs，其中銦合成物從0至大約47%間變化。緩衝層的厚度最好大約是1〇到30 nm。將緩衝層成份從GaAs變化成ΐη^Α5，以提供基礎單結晶氧化材料與單結晶合成半導體材料t蓋層間的晶格匹配。如果容納緩衝層24與單結晶合成半導體材料層％間晶格不匹配，則此類緩衝層的特別有利。實例6 此貫例提供結構14中使用的材料，如圖3所示。基板材料 22、模板層30及單結晶合成半導體材料層％可能與實例i 中所說明對應項相同。非結aa層3 6是由非結晶中間層材料（例如，如上文所述之 -15- I紙張尺度適用悄®家標準(CNS) A4規格(21G X 297公董) ------""""""'" 五、發明説明（13 層28材料）與容納緩衝層材何抖（例如，如上文所述之層24材料 )之組合所適當組成的非处曰 F m a曰乳化物層。例如，非結晶層 36可包括Si0鱼Sr Ba … 2 I-zTl〇3的組合（其中ζ介於〇至1的範圍内），其於退火製程湘門$ , Α 'a至 >、邓份組合或混合以形成非結晶氧化物層3 6。非結晶層36的厚度合閲座m λ 曰口應用而異，並且可依據如期望的層36隔離特性、包含層26 續26之+導體材料類型等等的因素。根據本具體貫施例一 jS + L - J項不靶性硯點，層36厚度為大約2 nmZr As template. Then, a single crystal layer of a synthetic semiconductor material using the indium system as a material is grown on the template layer. The lattice structure of the resulting synthetic semiconductor material exhibits a 45-degree rotation relative to the lattice structure of the containing buffer layer, and the mismatched (ΙΟΟ) ΙηΡ lattice is less than 2.5%, and preferably less than about 1.0%. 3 According to a further specific embodiment of the present invention, it is assumed that the structure is suitable for growing a Π-νι epitaxial film to cover the silicon substrate. As mentioned above, the substrate is preferably a silicon wafer. A suitable material for containing the buffer layer is SrxBai x Ti03, where X is in the range of 0 to 1 'and the thickness is in the range of about 2 nm to 100 nm, and preferably the thickness is about 5 nm to 15 nm. π-VI synthetic semiconductor materials may be, for example, zinc sulfite (ZnSe) or zinc sulfenite (ZnSSe). Applicable to -13- The national standard (CNS) of this paper standard M standard (χ 297 public love)---- M3810 A7 B7 V. Description of the invention (") --- The template layer of this material system includes the word- Oxygen (Zn_〇)! To the monolayer, followed by 1 to 2 monomolecular layers of excess zinc, followed by the zincite on the table: or the template layer may be ( For example) False LS) ^ to 10 monolayers, followed by ZnSeS. Example 4 This specific embodiment of the present invention is an example of the structure 40 shown in Figure 2. The substrate 22, the single crystal oxide layer 24, and the single The crystalline synthetic semiconductor material layer% may be similar to the corresponding item described in Example K. In addition, the additional buffer layer 32 is used to reduce the strain, where the strain is caused by the mismatch between the buffer layer lattice and the single crystal half-chip material. The buffer layer 32 may be a layer of germanium or GAS, aluminum gallium arsenide (AlGaAs), indium gallium phosphide (InGaP), aluminum gallium phosphide (Αΐ (^ ρ), indium gallium arsenide (InGaAs), indium aluminum phosphide ( Allnp), gallium arsenide (GaAsp) or indium gallium halide (InGaP) should be used to compensate the superlattice. According to this embodiment In one aspect, the buffer layer 32 includes a GaASxPix superlattice, where the value of χ is in the range of q to 1. According to another aspect, the buffer layer 32 includes an inyGi_yP superlattice, in which the range is from 0 to 1. By changing the X or y value depending on the situation, the lattice constant will change from bottom to top across the superlattice to produce a base oxide that covers the lattice constant of the synthetic semiconductor material. The composition of other materials such as those listed above will also be modified to handle the lattice constant of layer 32 in a similar manner. The thickness of the superlattice is in the range of about 50 nm to 500 0111, and It is preferably a thickness of about ιη to 200 nm. The template of this structure may be the same as that described in the example}. Alternatively, the buffer layer 32 may be a single crystal germanium having a thickness of! Nm to 50 nm, and most Fortunately, the thickness is about 2 niT ^] 20 nm. In the use of germanium buffer -14-This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 513810 A7 _________B7 5. Description of the invention (12 1 " -— The thickness of the layer can be used about A monomolecular layer of germanium-fault (Ge_sr) or germanium-titanium (Ge-Ti) template layer is used as the gathering site for the subsequent growth of the single crystal synthetic semiconductor material layer. The way to form the oxide layer is to cover the single molecular layer 镙 or Monolayer Ti is used as the aggregation site for the subsequent precipitation of monocrystalline germanium. Monomolecular layer rhenium or monolayer titanium provides the first monomolecular layer of germanium-bondable aggregation site. Σ Example 5 This example also illustrates the structure shown in Figure 2. Useful materials in the structure 40. The substrate material 22, the containing buffer layer 24, the single-crystal synthetic semiconductor material layer%, and the template layer are the same as the corresponding items described in Example 2. In addition, a buffer layer 32 is inserted between the accommodating buffer layer and the layer covering the single crystal synthetic semiconductor material. The buffer layer (further single crystal semiconductor material) may be, for example, a granular layer of InGaAs or InS1S (InA1As) (at first. According to the -item view of this specific embodiment, The buffer layer 32 includes InGaAs, where the indium composition varies from 0 to about 47%. The thickness of the buffer layer is preferably about 10 to 30 nm. The composition of the buffer layer is changed from GaAs to ΐη ^ Α5 to provide a basic single crystal The lattice matching between the oxidizing material and the single crystal synthetic semiconductor material t cap layer. Such a buffer layer is particularly advantageous if the containing buffer layer 24 and the single crystal synthetic semiconductor material layer% lattice mismatch, which is particularly advantageous. Example 6 This example provides The materials used in structure 14 are shown in Figure 3. The substrate material 22, the template layer 30, and the single crystal synthetic semiconductor material layer% may be the same as the corresponding items described in Example i. The non-junction aa layer 36 is composed of the amorphous middle Layer material (for example, as described above, the -15-I paper size is applicable to the CNS) A4 specification (21G X 297 public directors) ------ " " " " " " '" V. Description of the Invention (13 layers and 28 materials) and A non-processed F ma emulsion layer suitably composed of a combination of a buffer layer material Ho (for example, layer 24 material as described above). For example, the amorphous layer 36 may include SiO fish Sr Ba… 2 I- A combination of zTlO3 (where ζ is in the range of 0 to 1), which is combined or mixed in the annealing process Xiangmen $, A'a to >, Dengfen to form an amorphous oxide layer 36. Amorphous The thickness of the layer 36 of the joint m λ varies depending on the application, and can be based on factors such as the desired isolation characteristics of the layer 36, the layers 26 and 26 + conductor material type, etc. According to this specific embodiment 1 jS + L-J terms are not target puppets, layer 36 is approximately 2 nm thick

至大約1 00 nm，最好县^s , A 疋大、力2至1 〇 nm，並且以大約5至6 nm 最佳。層38包括單結晶合成半導體材料，其可在如用來形成容納缓衝層24之材料的單結晶氧化物材料上以蟲晶方式生長。根據本發明一項具體實施例，層38包含與包含層％之材料相同的材料。例如，層26包含，則層％也包含 GaAs。然而，根據本發明其他具體實施例，層“可包含不同於用來形成層—材料。根據本發明-項示範性具體實施例，層38的厚度為大約丨單分子層至大Ki〇〇nm。、。。月重新麥考圖1至3 ,基板22是諸如單結晶石夕基板之類的 f結晶基板。單結晶基板結晶結構的特徵在於晶格常數及曰曰格方向。在類似的方法中，容納緩衝層24也是單結晶材料’亚且單肖晶材#晶格的特徵在⑥晶格常數及晶體方向合納緩衝層與單結晶基板的必須緊密匹配，或者，必須某-晶體方向係對著另一晶體方向旋#，才料成大體上晶格常數匹配。在上下文中，「大體上等於」及「大體To about 100 nm, it is best to have a large A, large 2 to 10 nm, and most preferably about 5 to 6 nm. Layer 38 includes a single crystalline synthetic semiconductor material that can be grown in a worm-like manner on a single crystalline oxide material such as the material used to form the buffer layer 24. According to a particular embodiment of the invention, layer 38 comprises the same material as the material containing layer%. For example, if layer 26 contains, then layer% also contains GaAs. However, according to other specific embodiments of the present invention, the layer "may contain a material different from that used to form the layer-material. According to an exemplary embodiment of the present invention, the thickness of the layer 38 is about 丨 a single molecular layer to a large Kinm … .. Reconsidering Figures 1 to 3, the substrate 22 is an f-crystal substrate such as a single crystal substrate. The crystal structure of a single crystal substrate is characterized by a lattice constant and a lattice direction. In a similar method In the storage buffer layer 24 is also a single crystalline material, and the characteristics of the crystal lattice are in the lattice constant and crystal direction. The buffer layer must closely match the single crystal substrate, or the向 # in the other crystal direction, it is expected that the lattice constants match. In the context, "substantially equal" and "substantially

-16- A7 B7 五、發明説明（14 _己」表不日日格常數間有充足的相似點，而能夠在基礎層上生長高品質結晶層。 θ曰員丁可達成之南結晶品質生長晶體層厚度的關係，作姓^晶與生長晶的晶格常數之間不匹配的函數。曲線42高曰°°貝材料的界限。曲線42右邊的區域代表容易成為多晶體的層。由於a &加产、古。2於日日格匹配，因此能夠在主晶上生長無限厚、貝石石日日層。由於晶格常數不匹配遞增，所以可達二田兩：質結晶層的厚度迅速遞減。例如，作為參考點， ' 印”生長層間的晶格常數不匹配超過大約2%，則無去達成超過大約2〇 _的單結晶磊晶層。、根據本發明-項具體實施Μ，基板22是以(1〇〇)或(111) :、、、方向的單結晶矽晶圓，而容納緩衝層24是勰鋇鈦酸鹽層達成k兩種材料之晶格常數大體上匹配的方式為，將鈦 &風：料晶體方向往相對於矽基板晶圓晶體方向45。旋轉。 :此鈿例中’ ^果厚度夠厚，則非結晶中間層28結構中所 ^含二氧切層係用來降低鈦酸鹽單結晶層應變，因為欽二風單，、Ό日日層應變會導致主矽晶圓與生長鈦酸鹽層的晶格 :數不匹配。結果根據本發明一項具體實施例，可達成高品質、更厚的單結晶層鈦酸鹽層。請重新參考圖1至3，層26是磊晶生長單結晶材料層，並且該結晶材料的特徵在於晶格常數及晶體方向。根據本發明一項具體實施例，層26的曰曰曰格常數不同基板22的晶格常數為了達成咼結晶品質的磊晶生長單結晶層，容納緩衝層必頊具有咼結晶品質。此外，為了達成高結晶品質的層 -17 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐） A7 B7 五、發明説明（15 ) 26，希望主晶（在此情況下，主晶是單結晶容納緩衝層）與生長晶體的晶格常數之間大體上匹配。配合正確選用的材料，由於生長晶體的晶體方向會相對於主晶方向旋轉j所以可達成晶格常數大體上匹配。如果生長晶體是砷化鎵、砷化鋁鎵、鋅亞硒酸鹽或鋅硫亞硒酸鹽，而容納緩衝層是單結晶SrxBai_xTi〇3，則可達成這兩種材料的晶格常數二= 上匹配，其中會將生長層的晶體方向往相對於主單結晶氧化物方向旋轉45。。同樣地，如果主晶材料是鳃或鋇锆酸鹽或鳃或鋇铪或鋇鍚氧化物，而合成半導體層是磷化銦或砷化鎵銦或砷化鋁銦，則可達成晶格常數大體上匹配，其方式是將生長晶體層的方向往相對於主氧化物晶體方向旋轉 45。。在某些情況_，主晶氧化物與生長合成半導體層之間的結晶半導體緩衝層可用來降低生長單結晶合成半導體層的應變，因為應變會導致晶格常數的微幅差異。藉此可達成最佳的生長單結晶合成半導體層結晶品質。下文說明根據本發明一項具體實施例之製造諸如圖丨至3 所示之、、Ό構之半導體結構的方法。方法的開始步驟是提供一種包括矽或鍺的單結晶半導體基板。根據本發明較佳具體貝施例，半導體晶基板是具有（100)方向的矽晶圓。基板最好是以軸線為方向，最多偏離軸線大約0.5。。半導體基板的至/ °卩伤具有裸面，然而基板的其他部份可能圍繞著其：結構，如下文所述。在此上下文中，術語「裸」表示 2清除基板的部份表面，以去除氧化物、致污物或其他異貝材料眾所g知，裸石夕具有高度反應性，並且很容易形本紙張尺歧财目規格(ΊΓ〇_Χ 297公豹 -18- B7 五、發明説明（16 ) 成天然氧化物。術語「裸」&含此類的天然氧化物。還可能故意在半導體基板上生長薄型氧化矽，然而此類的生長虱化物不是根據本發明之方法的必要項。為了磊晶生長單結晶氧化層以覆蓋單結晶基板，必須先去除天然氧化層，以暴露基礎基板的結晶結構。下列的方法最好是藉由分子束磊晶生長（molecular beam epitaxy ; MBE)方法來實現，雖然根據本發明也可使用其他的磊晶生長方法。藉由先在 MBE裝置中熱沈殿薄層的錄、鋇、銷與鋇的組合或其他驗土金屬或鹼土金屬組合，以去除天然氧化物。在使用鎇的情況下，接著將基板加熱到大約750，使鳃與天然矽氧化層產生化學反應。勰係用來分解氧化矽，而留下無氧化矽表面。所產生的表面包括鳃、氧及矽，並呈現整齊的 2x1結構。整齊的2?U結構形成模板，用以有序生長單結晶氧化物的覆蓋層。模板提供必要的化學及物理特性，以集結結晶生長的覆蓋層。根據本發明替代具體實施例，可轉換天然氧化矽並準備基板表面，以生長單結晶氧化層，其方式是在低溫下藉由 MBE在基板表面上沈澱如氧化鋰、氧化鳃鋇或氧化鋇之類的鹼土金屬氧化物，接著將結構加熱到大約75〇。在此溫度下’氧化錯與天然氧化石夕間發生的固態反應導致天然氧化石夕還原，並在朞板表面上留下具有鳃、氧及石夕的整齊 2x1結構。再次’以此方式形成模板，用以接著生長有序單結晶氧化物層。根據本發明一項具體實施例，在去除基板表面上的氧化 -19- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 513810 A7 _«_____ B7 五、發明説明（17 ) 矽後，將基板冷卻到大約2〇〇到8〇〇 γ範圍内的溫度，並且藉由分子束蠢晶生長在模板層上生長鳃鈦酸鹽層。MBE方法kMBE裝置中的開孔活閘（〇pening shuUer)開始，以暴露總、鈦及氧來源。錄與鈦的比率大約是1:1。氧氣分壓最初設定在最小值，以利於以每分鐘大約〇.3到〇 511111的生長速度來生長推測的錯鈦酸鹽。在初步生長鏍鈦酸鹽後，將氧氣分壓遞增到大約最初的最小值。氧氣過壓會導致在基礎基板與生長中之錯鈦酸鹽層之間的界面上生長非結晶氧化石夕。生長氧化石夕層起因於氧氣會通過生長中之錯鈦酸鹽層擴散到位於基礎基板表面上氧氣與矽產生化學反應的表面。認鈦酸鹽生長成為有序單結晶，並且具有相對於整齊2d 結晶結構之基礎基板旋轉45。的結晶方向。否則，勰鈦酸鹽層可能存在應變，這是因為矽基板與生長晶體之間晶格常數微幅不匹配所致，而在非結晶氧化矽中間層可減緩此類的應變。在锶鈦酸鹽生長到所希望的厚度後，接著藉由模板層來覆蓋單結晶鏍鈦酸鹽，以促進後續生長所希望的合成半導體材料磊晶層。就後續生長砷化鎵層而言，覆蓋MBE生長的鏍鈦酸鹽單結晶層的方式為，以i到2層單分子層鈦、^ 到2層單分子層鈦-氧或}到2層單分子層勰_氧來終止生長。在形成此覆蓋層後，接著沈澱砷，以形成丁i-As鍵合、丁卜〇_ As鍵合或Sr-0-As。這些的任一種都可形成適合沈澱及形成砷化鎵單結晶層的摸板。在形成模板後，接著導入鎵，以與砷產生化學反應，並形成砷化鎵。或者，可在覆蓋層上 •20- 本紙張尺度適用中@ g家標準⑴泌）A4規格(21GX 297公董)"" ""------- 513810 A7 B7 五、發明説明（18 ) 沈澱鎵，以形成Sr-0-Ga鍵合，並且接著導入與鎵反應的砷，以形成GaAs。圖5顯示根據本發明所製造之半導體材料的高解析度透射式電子顯微照相（Transmission Electron Micrograph; TEM) 圖。單晶體SrTi〇3容納緩衝層24係在矽基板22上磊晶生長。於此生長製程期間，會形成非結晶介面層28以減緩因晶格不匹配所導致的應力。然後，使用模板層3〇來磊晶生長-16- A7 B7 V. Description of the invention (14 _ 己) indicates that there are sufficient similarities between the daily and daily lattice constants, and high-quality crystal layers can be grown on the base layer. The relationship between the thickness of the crystal layer is a function of the mismatch between the lattice constants of the surname ^ crystal and the growing crystal. The curve 42 is higher than the limit of the °° shell material. The area on the right side of the curve 42 represents the layer that easily becomes polycrystalline. & Production, Paleo. 2 matches the Rigri grid, so it can grow infinitely thick, besparite Rigri layer on the main crystal. As the lattice constant mismatch increases, it can reach Ertian two: the thickness of the crystalline layer Decrease rapidly. For example, as a reference point, the lattice constant mismatch between the "print" growth layers exceeds about 2%, and there is no way to achieve a single crystal epitaxial layer that exceeds about 20 °. The substrate 22 is a single crystal silicon wafer in the (100) or (111): ,,, and directions, and the holding buffer layer 24 is a hafnium barium titanate layer to achieve a lattice constant of the two materials. The way is, the direction of titanium & wind: crystal The silicon substrate wafer crystal direction is 45. Rotation: In this example, if the thickness is thick enough, the dioxin-containing layer in the structure of the amorphous intermediate layer 28 is used to reduce the strain of the titanate single crystal layer because Qin Erfeng single, the next day's layer strain will cause the main silicon wafer and the growing titanate layer lattice: number mismatch. As a result, according to a specific embodiment of the present invention, a high-quality, thicker single crystal can be achieved A layer of titanate. Please refer to FIGS. 1 to 3 again. Layer 26 is an epitaxially grown single crystalline material layer, and the crystalline material is characterized by a lattice constant and a crystal orientation. According to a specific embodiment of the present invention, layer 26 The lattice constant of the substrate 22 is different from the lattice constant of the substrate 22. In order to achieve an epitaxial growth of a single crystal layer of 咼 crystalline quality, the storage buffer layer must have 咼 crystalline quality. In addition, in order to achieve a layer of high crystalline quality -17 The dimensions are applicable to the Chinese National Standard (CNS) A4 specifications (210 X 297 mm) A7 B7 V. Description of the invention (15) 26, I hope that the main crystal (in this case, the main crystal is a single crystal containing the buffer layer) and the growing crystal Lattice constant With the correct selection of materials, the crystal constant of the growing crystal will be rotated relative to the main crystal direction, so the lattice constant can be roughly matched. If the growing crystal is gallium arsenide, aluminum gallium arsenide, zinc selenite Or zinc thioselenite, and the holding buffer layer is a single crystal SrxBai_xTi〇3, the lattice constants of these two materials can be matched, where the crystal direction of the growth layer will be relative to the main single crystal. The oxide direction is rotated 45. Similarly, if the main crystal material is gill or barium zirconate or gill or barium hafnium or barium hafnium oxide, and the synthetic semiconductor layer is indium phosphide or gallium indium arsenide or indium aluminum arsenide Then, the lattice constants can be roughly matched. The method is to rotate the direction of growing the crystal layer by 45 relative to the direction of the main oxide crystal. . In some cases, a crystalline semiconductor buffer layer between the main crystalline oxide and the growing synthetic semiconductor layer can be used to reduce the strain of the growing single crystalline synthetic semiconductor layer because the strain causes a small difference in the lattice constant. Thereby, it is possible to achieve the best crystal quality of the grown single crystal synthetic semiconductor layer. The following describes a method of fabricating a semiconductor structure, such as the one shown in FIGS. 1-3, according to a specific embodiment of the present invention. The method begins by providing a single crystal semiconductor substrate including silicon or germanium. According to a preferred embodiment of the present invention, the semiconductor crystal substrate is a silicon wafer having a (100) direction. The substrate is preferably oriented in the direction of the axis and can be offset from the axis by at most about 0.5. . Semiconductor substrates have bare surfaces up to and including scratches, but other parts of the substrate may surround them: structure, as described below. In this context, the term "bare" means 2 to remove part of the surface of the substrate to remove oxides, contaminants, or other exotic materials. It is well known that bare stones are highly reactive and can easily form paper. Geometries specifications (ΊΓ〇_ × 297Male Leopard-18- B7 V. Description of the invention (16) into natural oxides. The term "bare" & contains such natural oxides. May also be intentionally on semiconductor substrates Thin silicon oxide is grown, but such growth lice are not necessary for the method according to the present invention. In order to epitaxially grow a single crystal oxide layer to cover a single crystal substrate, the natural oxide layer must be removed first to expose the crystal structure of the base substrate The following methods are best achieved by molecular beam epitaxy (MBE) method, although other epitaxial growth methods can also be used according to the present invention. By first heat sinking the thin layer in the MBE device Combination of barium, barium, pins and barium, or other soil test or alkaline earth metal combinations to remove natural oxides. In the case of thorium, the substrate is then heated to about 750, so that Chemical reaction with the natural silicon oxide layer. It is used to decompose silicon oxide and leave a silicon oxide-free surface. The resulting surface includes gills, oxygen, and silicon, and presents a neat 2x1 structure. A neat 2? U structure is formed A template for orderly growing a cover layer of single crystalline oxide. The template provides the necessary chemical and physical properties to gather the cover layer of crystal growth. According to an alternative embodiment of the present invention, the natural silicon oxide can be converted and the substrate surface can be prepared. A single crystal oxide layer is grown by depositing an alkaline earth metal oxide such as lithium oxide, barium oxide, or barium oxide on the surface of the substrate by MBE at a low temperature, and then heating the structure to about 75 °. Here, At the temperature, the solid state reaction between the oxidation oxide and the natural oxidized stone leads to the reduction of the natural oxidized stone and leaves a neat 2x1 structure with gills, oxygen and stone on the surface of the plate. Once again, 'the template is formed in this way, Used to subsequently grow an ordered single crystal oxide layer. According to a specific embodiment of the present invention, the oxidation on the surface of the substrate is removed. National Standard (CNS) A4 specification (210 X 297 mm) 513810 A7 _ «_____ B7 V. Description of the invention (17) After silicon, cool the substrate to a temperature in the range of about 200 to 800 γ, and The gill titanate layer is grown on the template layer by molecular beam stupid growth. The MBE method starts with an opening shuuer in the kMBE device to expose total, titanium, and oxygen sources. The ratio of titanium to titanium is approximately It is 1: 1. The oxygen partial pressure is initially set to a minimum value to facilitate the growth of the inferred titanate at a growth rate of approximately 0.3 to 511 1111 per minute. After the initial growth of the titanate, the oxygen is divided. The pressure increases to about the initial minimum. Oxygen overpressure can cause amorphous oxide stones to grow at the interface between the base substrate and the growing titanate layer. The growth of the oxidized stone layer is due to the diffusion of oxygen through the growing titanate layer to the surface on the base substrate where the oxygen reacts with silicon. It is believed that the titanate grows into ordered single crystals, and has a rotation of the base substrate 45 relative to the neat 2d crystal structure. Crystallization direction. Otherwise, there may be strain in the hafnium titanate layer, which is caused by the constant mismatch of the lattice constant between the silicon substrate and the growing crystal, and the intermediate layer of amorphous silicon oxide can reduce such strain. After the strontium titanate is grown to the desired thickness, the single crystal osmium titanate is then covered with a template layer to promote subsequent growth of the desired epitaxial layer of the synthetic semiconductor material. For the subsequent growth of the gallium arsenide layer, the method of covering the single crystal layer of gadolinium titanate grown by MBE is: i to 2 monomolecular layers of titanium, ^ to 2 monomolecular layers of titanium-oxygen or} to 2 layers The monolayer is dysprosium-oxygen to stop growth. After forming this capping layer, arsenic is then precipitated to form a butadiene-As bond, a butadiene bond or Sr-0-As. Either of these can form a pattern suitable for precipitation and formation of a gallium arsenide single crystal layer. After the template is formed, gallium is then introduced to chemically react with arsenic and form gallium arsenide. Alternatively, it can be on the cover • 20- this paper size is applicable @ g 家标准 ⑴ 密) A4 size (21GX 297 public director) " " " " ------- 513810 A7 B7 V. DESCRIPTION OF THE INVENTION (18) Gallium is precipitated to form an Sr-0-Ga bond, and then arsenic that reacts with gallium is introduced to form GaAs. FIG. 5 shows a high-resolution transmission electron micrograph (TEM) image of a semiconductor material manufactured according to the present invention. The single-crystal SrTi03 buffer layer 24 is epitaxially grown on a silicon substrate 22. During this growth process, an amorphous interface layer 28 is formed to reduce the stress caused by the lattice mismatch. Then, the template layer 30 is used for epitaxial growth.

GaAs合成半導體層26。圖6顯示包含使用容納緩衝層24在矽基板22上生長之 GaAs合成半導體層26之結構的X射線衍射譜。光譜的峰值指示容納緩衝層24及GaAs合成半導體層26都是單晶體並且係以（100)方向為目的。藉由如上文所述的方法並加上額外緩衝層沈澱步驟，即可形成如圖2所示的結構。在沈澱單結晶合成半導體層之前，會先形成覆蓋模板層的緩衝層。如果緩衝層是合成半導體超晶袼，則可在如上文所述的模板上藉由（例如）mbe來沈殿此類的超晶格。女上述的方法，以最後$ 層，然後藉由沈澱鍺，如果用鍺層來取代緩衝層，則會修改GaAs synthesized semiconductor layer 26. Fig. 6 shows an X-ray diffraction spectrum of a structure including a GaAs synthetic semiconductor layer 26 grown on a silicon substrate 22 using a containing buffer layer 24. The peak value of the spectrum indicates that both the storage buffer layer 24 and the GaAs composite semiconductor layer 26 are single crystals and are aimed at the (100) direction. By the method described above and adding an additional buffer layer precipitation step, the structure shown in Fig. 2 can be formed. Before the Shendian single crystal synthetic semiconductor layer, a buffer layer covering the template layer is formed first. If the buffer layer is a synthetic semiconductor supercrystal, a superlattice such as Shen Dian can be deposited on the template as described above by, for example, mbe. Female The above method, with the last $ layer, and then by depositing germanium, if the buffer layer is replaced with a germanium layer, it will be modified

晶氧化物層經過退火製程， A 1犯疋，生長容納緩衝層、物層’以及在容納緩衝層上生。然後，將容納緩衝層及非結使容納緩衝層的結晶結構足以本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公爱) A7 B7 五、發明説明（19 ) — ~-- 從單結晶變更成非結晶，I!由形成非結晶層，使非結晶氧化物層與現在的非結晶容納緩衝層的組合形成單一非纟士晶氧化物層36。接著在層38上生長層26。或者，可接著實= 退火製私以生長層26。、根據此具體實施例的一項觀點，形成層36 板1容納緩衝層 ' 非結晶氧化物層及半導體層速熱退火製程，使用的最高溫度大約7〇〇〇c至大約1〇〇〇 % ，製程時間大約10秒至大約10分鐘。然而，根據本發明，可採用其他適當的退火製程以將容納緩衝層轉換為非結晶層。例如，可使用雷射退火或「傳統」熱退火製程（在適當的環境中）來形成層36。當採用傳統熱退火來形成層36時，於退火製程期間需要過壓一層或一層以上結構成分層3〇，以避免層3 8降級。例如，當層3 8包括GaAs時，退火環境最好包括過壓砷，以減輕層3 8降級。如上文所述，結構34的層38可包括適用於層32或26的任何材料。因此，可採用配合層32或26所說明的沈澱或生長方法來沈澱層3 8。圖7顯示根據圖3所示之本發明具體實施例所製造之半導體材料的南解析度透射式電子顯微照相（丁ransmissi〇n Electron Micrograph ; TEM)圖。根據本具體實施例，單晶體Si:Ti〇3容納緩衝層係在矽基板22上磊晶生長。如上文所述，於此生長製程期間，非結晶介面層形成。接著，在容納緩衝層上面形成GaAs層3 8，並且將容納緩衝層經過退火處理’以形成非結晶氧化物層3 6。 -22- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 513810 A7 __ B7 五、發明説明（2〇) 圖8顯示包含GaAs合成半導體層38及形成於矽基板22上的非結晶氧化物層3 6之結構的X射線衍射譜。光譜的峰值指示GaAs合成半導體層38是單晶體並且係以（100)方向為目的 ’大約4 0至5 〇度的無峰值指示層3 6是非結晶。如上文所述的方法說明一種藉由分子束磊晶生長方法來形成半導體結構的方法，其中該半導體結構包含一矽基板、一覆蓋氧化物層及一單結晶砷化鎵合成半導體層。還可能藉由化學蒸汽化殿積（chemical vapor deposition ; CVD)、金屬有機化學蒸汽殿積（metal organic chemical vapor deposition ; MOCVD)、遷移率增強型磊晶生長（migration enhanced epitaxy ; MEE)、原子層磊晶生長（atomic layer epitaxy，ALE)、物理蒸汽化澱積（physical vapor deposition ;PVD)、化學溶劑澱積（chemical solution deposition ; CSD)、脈衝雷射澱積（pulsed laser deposition ; PLD)等等來貫現此項方法。另外，藉由類似的方法，還可生長其他的單結晶容納緩衝層，諸如，鹼土金屬鈦酸鹽、鹼土金屬錘酸鹽、鹼土金屬铪酸鹽、鹼土金屬钽酸鹽、鹼土金屬釩酸鹽、驗土金屬釕酸鹽、鹼土金屬銳酸鹽、如鹼土金屬鍚基鈣鈦礦（alkaline earth metal tin-based perovskite)之類的氧化 4丐鈦礦、鑭鋁酸鹽、氧化鑭銃及氧化釓。另外，藉由諸如 MBE的類似方法，還可沈澱其他的第III-V及II-VI族單結晶合成半導體層’以覆蓋單結晶氧化物容納緩衝層。合成半導體材料與單結晶氧化物容納緩衝層的每種變化都疋使用適當的模板層，以利於開始生長合成半導體層。 -23- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 五、發明説明（21 例如’如果谷納緩衝層是驗土金屬錯酸鹽，則可藉由薄型锆層來覆蓋氧化物。沈澱鍅之後，接著沈澱要與锆產生化學反應的砷或磷，作為分別沈澱砷化銦鎵、砷化銦鋁或磷化姻的刖導。同樣地’如果單結晶氧化物容納緩衝層是驗土金屬給酸鹽，則可藉由薄型铪層來覆蓋氧化層。沈澱給之後’接著沈澱要與铪產生化學反應的砷或磷，作為分別生長神化銦鎵、砷化銦鋁或磷化銦層的前導。在類似的方法中’可用錯或錄暨氧層來覆蓋錄鈦酸鹽，並’且用鋇或鋇暨氧層來覆蓋鋇鈦酸鹽。沈澱前述各項之後，接著沈殿要與覆蓋材料產生化學反應的砷或磷，以形成用來沈澱合成半導體材料層的模板，其中合成半導體材料層包括砷化銦鎵、砷化銦鋁或磷化銦層。After the crystalline oxide layer is subjected to an annealing process, A 1 undergoes a growth process, and a storage buffer layer and an object layer are grown and grown on the storage buffer layer. Then, the crystalline structure of the containing buffer layer and the non-junction containing buffer layer are sufficient for the paper size to apply the Chinese National Standard (CNS) A4 specification (210X 297 public love) A7 B7 V. Description of the invention (19) — ~-From the single The crystal is changed to amorphous. I! By forming an amorphous layer, a single amorphous oxide layer 36 is formed by a combination of the amorphous oxide layer and the current amorphous storage buffer layer. A layer 26 is then grown on the layer 38. Alternatively, the growth layer 26 may be followed by annealing. According to an aspect of this specific embodiment, the formation layer 36, the plate 1 contains the buffer layer, and the non-crystalline oxide layer and the semiconductor layer are rapidly thermally annealed. The highest temperature used is about 7000c to about 10,000%. The process time is about 10 seconds to about 10 minutes. However, according to the present invention, other appropriate annealing processes may be used to convert the receiving buffer layer into an amorphous layer. For example, layer 36 may be formed using a laser annealing or "traditional" thermal annealing process (in the appropriate environment). When the conventional thermal annealing is used to form the layer 36, it is necessary to overpress one or more structural component layers 30 during the annealing process to avoid the degradation of the layer 38. For example, when layer 38 includes GaAs, the annealing environment preferably includes overvoltage arsenic to mitigate layer 38 degradation. As mentioned above, layer 38 of structure 34 may include any material suitable for layer 32 or 26. Therefore, the precipitation or growth method described for the compound layer 32 or 26 can be used to precipitate the layer 38. FIG. 7 shows a South Resolution Transmission Electron Micrograph (TEM) of a semiconductor material manufactured according to the embodiment of the present invention shown in FIG. 3. FIG. According to this embodiment, a single-crystal Si: Ti03-containing buffer layer is epitaxially grown on a silicon substrate 22. As mentioned above, during this growth process, an amorphous interface layer is formed. Next, a GaAs layer 38 is formed on the receiving buffer layer, and the receiving buffer layer is subjected to an annealing treatment 'to form an amorphous oxide layer 36. -22- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 513810 A7 __ B7 V. Description of the invention (20) FIG. 8 shows a semiconductor layer 38 composed of GaAs and formed on a silicon substrate 22 X-ray diffraction spectrum of the structure of the amorphous oxide layer 36. The peak value of the spectrum indicates that the GaAs synthetic semiconductor layer 38 is single crystal and is aimed at the (100) direction. The peak-free indicating layer 36 of about 40 to 50 degrees is amorphous. The method described above illustrates a method for forming a semiconductor structure by a molecular beam epitaxial growth method, wherein the semiconductor structure includes a silicon substrate, a cover oxide layer, and a single crystal gallium arsenide synthetic semiconductor layer. It is also possible to use chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), migration enhanced epitaxy (MEE), atomic layer Epitaxial growth (atomic layer epitaxy, ALE), physical vapor deposition (PVD), chemical solution deposition (CSD), pulsed laser deposition (PLD), etc. To implement this method. In addition, by a similar method, other single crystal containing buffer layers can be grown, such as alkaline earth metal titanate, alkaline earth metal hammer salt, alkaline earth metal phosphonate, alkaline earth metal tantalate, alkaline earth metal vanadate Earth test metal ruthenates, alkaline earth metal sharps, oxides such as alkaline earth metal perovskite (Alkaline earth metal tin-based perovskite), titanium oxide, lanthanum aluminate, lanthanum oxide, and oxidation Alas. In addition, by a similar method such as MBE, other Group III-V and II-VI single crystal synthetic semiconductor layers can also be precipitated to cover the single crystal oxide containing buffer layer. Each change in the synthetic semiconductor material and the single crystal oxide containing buffer layer uses an appropriate template layer to facilitate the growth of the synthetic semiconductor layer. -23- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X 297 mm) 5. Description of the invention (21 For example, 'If the Gona buffer layer is a soil metal salt, you can use a thin zirconium layer to Cover oxides. After osmium is precipitated, arsenic or phosphorus to be chemically reacted with zirconium is then precipitated as a guide for precipitating indium gallium arsenide, indium aluminum arsenide, or phosphine, respectively. Similarly, if a single crystal oxide holds The buffer layer is a soil metal salt, and the oxide layer can be covered by a thin gadolinium layer. After precipitation, the arsenic or phosphorus to be chemically reacted with the gadolinium is precipitated as the growth of indium gallium and indium aluminum arsenide. Or the precursor of the indium phosphide layer. In a similar method, the titanate can be covered with the wrong or oxygen layer, and the barium titanate can be covered with the barium or barium and oxygen layer. After precipitation of the foregoing Then, Shen Dian wants to chemically react with arsenic or phosphorus to form a template for precipitating a layer of synthetic semiconductor material, wherein the layer of synthetic semiconductor material includes an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer.

圖9半導體結構90的斷面原理圖，其包括單結晶半導體基板層92、覆蓋基板的非結晶氧化物層94、覆蓋非結晶氧化物層的單結晶合成半導體層9 8、源極端子1 〇〇、；；及極端子 104、通道1〇5及具有裝置區域114的CMOS電路112。熟知技藝人士應知道，源極端子1〇〇、汲極端子104、通道1〇5及裝置£域114功能共同形成場效電晶體（FET)。在較佳具體實施例中，非結晶氧化物層94包括前文中配合層3 6所說明的任何材料（如，鹼土金屬氧化物），例如，SrxBabxTiOs其中 X介於0至1之間的範圍内。合成半導體層98最好包括選自由下列材料所組成之群組的材料.GaAs、AlGaAs、InP、 InGaAs、InGaP、ZnSe及ZnSeS。或者，單結晶合成半導體層98可能是以選自由III-V合成物、II-VI合成物及混合II-VI -24 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 裝 η 線發明説明（22 ) 合成物所組成之群組之任何適當的材料所製成。CM0S電路 Η 2可包括控制電路、數位邏輯、數位積體電路或於單結晶半導體基板層92内製造的幾乎任何其他微電子結構。I特定較佳具體實施例中，單結晶半導體基板層92以基板。熟知技藝人士應進一步明白，通道1〇5、源極端子1〇〇及汲極端子1〇4會經過適當建構，以依據裝置區域u4的偏壓，將電流沿著通道105從汲極端子1〇4引導至源極端子ι〇〇(反之亦然）。具體而言，在裝置區域丨14(通常是閘極）的控制下 ’可用線性方式或雙穩（例如，開關）來控制與通道1〇5關聯的現行傳導率限度。熟知技藝人士也還知道，源極端子 100及汲極端子104可包含在單結晶合成半導體層98上模製的金屬圖樣。、、圖10顯不廣泛相似於圖9所示之半導體結構之半導體結構 120的斷面原理圖，用以解說分隔的源極區域1〇6和汲極區域108，其中源極區域和汲極區域是在單結晶合成半導體層 9 8中形成的摻雜雜質區域。圖11半導體結構122的斷面原理圖，其中源極區域1〇6和汲極區域108被建構以配合閘極118來形成FET，其中閘極 118的偏壓控制通道丨〇5的傳導率。若需要，閘極ιΐ8可能形成以作為藉由閘極電介質116而與通道1〇5隔離的金屬電極。閘極118及/或閘極電介質116可能是用照相微影印刷法在單結晶合成半導體層98上模製而成。 …谨、’’貝參考圖n，裝置區域1 14可能被建構以作為第二閘電極，用以配合閘極丨丨8來影響通道丨〇5的傳導率。例如，五、發明説明（23 ) 閉極118可作為源極區域106和及極區域⑽的「前端」間極 ’而閘極114作為源極區域和汲極區域的「後端」間極。以此方式，藉由其中一個偏壓’可將邝丁裝置的門限電壓有气地從第-(例如，較高的電壓值)偏移至第二(例如，較低的電壓值）門限值。或者，藉由電氣連接第一閘極ιι8與第二閑極114 ’就可顯著增加裝置的跨傳導率，例如，以兩等級。 ° 1 ▲在-項具體實施例中’第二閘極114可包含用來接收電壓 k唬之CMOS電路112的摻雜雜質區域。在另一項具體實施例中’第二閘極電極可包含與⑽⑽電路u2關聯的傳導電極並用來接收電壓信號。另外，雖然電路1丨2最好是 CMOS電路，但是電路！ } 2可包括任何想要的微電子結構，其至少部份於單結晶半導體基板層92内製造。圖12顯示半導體結構142的斷面原理圖，其包括大體上如上文所述的各層92、94和98，其包括在基板層92内形成且互相分隔的源極區域1 4 6和汲極區域1 4 8，以及部份在在單結晶合成半導體層98中形成或在其上模製成形的閘電極 144。為了當作FET，閘電極144被適當地配置在大體上對齊源極區域146和汲極區域148的位置。就這一點而言，閘極144、源極區域146和汲極區域148可適當作為是金屬半 1 體％效電晶體（metal semiconductor Held effect transistor ;MESFET)使用。若需要’半導體結構142還可包括源電極143和汲電極 145 ’其位於有利於分別歐姆接觸位於單結晶合成半導體層 -26- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）9 is a schematic cross-sectional view of a semiconductor structure 90, which includes a single crystalline semiconductor substrate layer 92, an amorphous oxide layer 94 covering a substrate, a single crystalline synthetic semiconductor layer 98 covering an amorphous oxide layer, and a source terminal 1. 〇, ;; and the terminal 104, the channel 105, and the CMOS circuit 112 having the device region 114. Those skilled in the art should know that the source terminal 100, the drain terminal 104, the channel 105, and the device 114 function together to form a field effect transistor (FET). In a preferred embodiment, the amorphous oxide layer 94 includes any of the materials (eg, alkaline earth metal oxides) described in the above-mentioned complex layer 36, for example, SrxBabxTiOs where X is in the range of 0 to 1. . The synthetic semiconductor layer 98 preferably includes a material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS. Alternatively, the single crystal synthetic semiconductor layer 98 may be selected from the group consisting of III-V composite, II-VI composite, and mixed II-VI -24. This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) The η line invention description (22) is made of any suitable material in the group of composites. The CMOS circuit Η 2 may include a control circuit, a digital logic, a digital integrated circuit, or almost any other microelectronic structure fabricated in the single crystal semiconductor substrate layer 92. In a specific preferred embodiment, the single crystal semiconductor substrate layer 92 is a substrate. Those skilled in the art should further understand that the channel 105, the source terminal 100, and the drain terminal 104 will be appropriately constructed to route the current from the drain terminal 1 along the channel 105 according to the bias of the device region u4. 〇4 leads to the source terminal ι〇〇 (and vice versa). Specifically, under the control of the device area 14 (usually the gate), the current conductivity limit associated with channel 105 can be controlled in a linear manner or bistable (for example, a switch). It is also known to those skilled in the art that the source terminal 100 and the drain terminal 104 may include a metal pattern molded on the single crystal synthetic semiconductor layer 98. 10 shows a schematic cross-section of a semiconductor structure 120 similar to the semiconductor structure shown in FIG. 9 for explaining the separated source region 106 and the drain region 108, of which the source region and the drain region are separated. The region is a doped impurity region formed in the single crystal synthetic semiconductor layer 98. 11 is a schematic cross-sectional view of a semiconductor structure 122, in which a source region 106 and a drain region 108 are configured to cooperate with a gate 118 to form a FET, wherein the bias of the gate 118 controls the conductivity of the channel 05. If desired, the gate electrode 8 may be formed as a metal electrode isolated from the channel 105 by the gate dielectric 116. The gate 118 and / or the gate dielectric 116 may be molded on the single crystal synthetic semiconductor layer 98 by a photolithographic process. …, “” With reference to FIG. N, the device region 1 14 may be constructed as a second gate electrode to cooperate with the gate electrode 8 to affect the conductivity of the channel 5. For example, V. Description of the Invention (23) The closed electrode 118 can be used as the “front end” electrode between the source region 106 and the electrode region 而, and the gate 114 can be used as the “back end” electrode between the source region and the drain region. In this way, with one of the bias voltages, the threshold voltage of the Ding device can be gasically shifted from the first (for example, a higher voltage value) to the second (for example, a lower voltage value) threshold value. . Alternatively, by electrically connecting the first gate electrode 8 and the second idler electrode 114 ', the transconductance of the device can be significantly increased, for example, at two levels. ° 1 ▲ In the-embodiment, the second gate 114 may include a doped impurity region of the CMOS circuit 112 for receiving the voltage k1. In another embodiment, the 'second gate electrode may include a conductive electrode associated with the rubidium circuit u2 and is used to receive a voltage signal. In addition, although the circuit 1 丨 2 is preferably a CMOS circuit, but the circuit! } 2 may include any desired microelectronic structure, which is fabricated at least partially within the single crystal semiconductor substrate layer 92. FIG. 12 shows a schematic cross-sectional view of a semiconductor structure 142, which includes layers 92, 94, and 98 substantially as described above, which include source regions 146 and drain regions formed within the substrate layer 92 and separated from each other. 148, and a gate electrode 144 partially formed or molded on the single crystal synthetic semiconductor layer 98. To function as a FET, the gate electrode 144 is appropriately arranged at a position substantially aligned with the source region 146 and the drain region 148. In this regard, the gate electrode 144, the source region 146, and the drain region 148 can be suitably used as metal semiconductor Held effect transistor (MESFET). If needed, the 'semiconductor structure 142 may also include a source electrode 143 and a drain electrode 145', which are located to facilitate the ohmic contact and are located in a single crystal synthetic semiconductor layer-26 %)

198中之對應摻雜雜質型源極區域147和及極區域149。臨請：續參考圖12’隔離層94最好包括選自由鹼土金屬鈦酸The corresponding impurity-doped source regions 147 and 149 in 198. Temporary: Continued reference to FIG. 12 'The isolation layer 94 preferably includes a material selected from the group consisting of alkaline earth metal titanic acid.

風、驗土金屬鍅酸趟、給+M 凰屬釦馼鹽、鹼土金屬钽酸鹽、 :土燦了酸鹽、驗土金屬㈣鹽所組成之群組的絕緣體。」寺疋k佳具體實施例中，氧化物層94包括⑽心了叫其中 ;S 1之間的粑圍内。單結晶合成半導體結構最好包 =選自由下列材料所組成之群組的材料：㈣族合成物、此σ III-V私.合成物、n_VUg合成物及混合mi族合成物。在特定較佳具體實施例令，合成半導體層98最好包括選自由下列材料所組成之群組的材料：〇aAs、AiGaAs、Inp ' hGaAs、lnGaP、ZnSe&ZnSeS。一如刖文配合圖3的簡短說明，鹼土金屬氧化物層％可包含错由將單結晶氧化物架加熱處理所形成的非結晶氧化物。或者，層94可包含單結晶容納緩衝層及非結晶介面，如配合圖1至2的說明。圖1 4顯示半導體結構1 2 4的斷面原理圖，其包括單結晶基板92 (例如，石夕）、覆蓋基板92的驗土金屬氧化物層94、介於基板92與隔離層94之間的非結晶氧化物層u〇、覆蓋與隔離層9 4的單結晶合成半導體層9 §、在單結晶合成半導體層 9 8上开y成且互相分隔的源極端子i 〇〇和沒極端子1 〇 4、介於源極端子1〇〇與汲極端子1〇4之間延伸的通道區域126，以及在基板92内形成且通常與通道區域126對齊的閘電極128。在這個組態中’源極端子i00、汲極端子1〇4、通道區域 126和閘電極128係作為是FET使用。 -27- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐） B7 五、發明説明（25 ) P同離層94最好包括選自由鹼土金屬鈦酸鹽、鹼土金屬锆鲅鹽、鹼土金屬铪酸鹽、鹼土金屬鈕酸鹽、鹼土金屬釕酸鹽、驗土金屬銳酸鹽所組成之群組的絕緣體。在特定較佳具體實施例中，隔離層94包括srxBaIXTi03其中x介於 :間的範圍内。請繼續參考圖14，單結晶合成半導體層98 最子〇括遥自由下列材料所組成之群組的材料·· 族合成物、混合IIIeV族合成物、Π-VI族合成物及混合„^1族 '成物在特疋較佳具體實施例中，合成半導體層9 8最好如以砷化鎵為材料所製成，但是可使用由A1GaAs、hp、 InGaAs、InGaP、ZnS_ ZnSeS所組成的任何材料。圖15顯示廣泛相似於圖14所示之半導體結構i24之半導體結構13丨的斷面原理圖，其進一步包括在合成半導體層％上形成或至少部份在其内的第二閘電極1 〇2 ,其中第二閘電極1 CL·有助於覆蓋通.道區域丨26。在這個組態中，依據普遍已知的原理，源電極100、汲電極1〇4、通道區域126和第一閘電極102可一起作為是MESFET使用。或者，源電極 100及包極104、通道區域12ό和第二閘電極1〇2可形成高速電子遷移電晶體（high eiect_ m〇binty transist〇r ; MT)如如文中配合圖11的說明，包含第一閘電極128 和第二閘電極1〇2的半導體結構132也可被建構以作為具有兩個閘極的單一 FET使用，其中可採用一閘極來調變另一閘電極的問限電壓’或者可連接這兩個閘電極以大體上增加電日日體的跨傳導率。圖16顯示廣泛相似於圖14所示之半導體結構124之半導體 -28- 本紙張尺㈣财國a家標準(CNS) M規格(謂χ挪公爱) 513810 A7 ---- B7 五、發明説明~ 〜 --- 結構134的斷面原理圖’用以進一步解說在基板92中形成的邏輯電路’例如，CM〇s電路13〇。半導體…說明與在矽基板92上生長單結晶合成半導體層128關聯的許多優點，其允 5午將合成半導體層98的微電子結構與基板92的微電子結禮整體集成。 ^ 具體而言，圖1 7顯示廣泛相似於圖1 6所示之半導體結構 134之半導體結構136的斷面原理圖，用以進一步解說耦人至電路130的閘電極128，例如透過電氣互接132。以此私路1 3 0可被建構以將預先決定電壓供應給閘極12 $，菸此開啟、關閉或以其他方式綢變介於源極端子1〇〇與汲極端子104之間的電流。在另一項具體實施例中，圖丨8顯示廣泛相似於圖16所示之半導體結構134之半導體結構138的斷面原理圖，用以進一步解說在基板92中形成的摻雜雜質型區域丨4〇，用以有效電氣耦合電路130與閘電極128。依據下列的製程參數，可 ‘成如圖9至1 8所提及的許多結構。首先提供半導體基板92。之後，可在半導體基板内製造電路112 (圖10)、電路130(圖16)或任何其他想要的微電子結構若耑要，在半導體基板92内製造的積體電路可包括用以接收信號（例如’電壓信號）的裝置區域’然後在該裝置區域上採用偏壓通道丨〇 5，這是介於源極1 〇〇和及極1 〇 $之間延伸的通道。之後’磊晶生長一單結晶合成半導體層9 4，以覆蓋該半導體基板。於前述的磊晶生長單結晶層步驟期間，可在單 -29· 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） B7 五、發明説明（27 ) 結晶氧化物層94的7面形成非結晶氧化物H如，類似所示之層⑴的非結晶氧化物層。，然後，可蟲晶生長單結晶合成半導體層98 ’以單結晶氧化物層94,如配合圖1 制·兒月再者，如配合圖3的說明，可將層94曝露於退 =程，使層94結構從單結晶變更成非結晶。然後，可在早結晶合成半導體層98内形成半導體裝置，例如，一個或一個以上源極端子1〇〇 '汲極端子1〇4和通道區域丨〇5(請參閱圖9)。如上文所述，源極100、汲極104和通道105最好作為半導體裝置（例#，FET)，其建構以響應供應給基板92内之裝置區域（例如’圖9的區域丨14)來改變通道的傳導率。如丽文配合圖1-3的簡短說明，前文提及的磊晶生長步驟可藉由任何適當的製程來實施，所使用的製程係選自由 MBE' M〇CVD、MEE及ALE所組成的群組。另外，磊晶生長單結晶合成半導體層的步驟可用下列方法來實施：先生長單結晶半導體材料的種子層以覆蓋單結晶氧化物層，之後’生長單結晶合成半導體裝置層以覆蓋該種子層。另外，可用兩個或兩個以上階段來生長合成半導體，以便在任何兩階段之間執行退火製程，其中退火製程係用來使單結晶層94變成非結晶。於河面的說明書中’已參考特定具體實施例來說明本發明。然而’熟知技藝人士應明白本發明的各種修改並且容易修改’而不會脫離如下文中申請專利範例所提供之本發明 ‘ -30 - 本紙張尺度適用中國國豕標準(CNS) A4規格(210 X 297公憂） 513810 A7 B7 五、發明説明（28 ) 的範疇與精神。因此，說明書暨附圖應視為解說，而不應視為限制’並且所有此類的修改皆屬本發明範疇内。It is an insulator consisting of wind, soil test metal sulphuric acid, and + M phoenix. It belongs to the group consisting of buckle salt, alkaline earth metal tantalate,: earth salt, and metal test salt. In the specific embodiment of the temple, the oxide layer 94 includes a core and a core; S1 is within the boundary. The single crystal synthetic semiconductor structure is preferably composed of a material selected from the group consisting of: a Group III compound, this σ III-V private compound, a n_VUg compound, and a mixed mi group compound. In a specific preferred embodiment, the synthetic semiconductor layer 98 preferably includes a material selected from the group consisting of: oaAs, AiGaAs, Inp'hGaAs, InGaP, ZnSe & ZnSeS. As with the short description in conjunction with Figure 3, the alkaline earth metal oxide layer% may contain an amorphous oxide formed by heat-treating a single crystalline oxide frame. Alternatively, the layer 94 may include a single crystalline accommodating buffer layer and an amorphous interface, as described in conjunction with FIGS. 1-2. FIG. 14 shows a schematic cross-sectional view of a semiconductor structure 124 including a single crystal substrate 92 (for example, Shi Xi), a soil inspection metal oxide layer 94 covering the substrate 92, and a space between the substrate 92 and the isolation layer 94. A non-crystalline oxide layer u0, a single-crystal synthetic semiconductor layer 9 covering and isolating layer 94, §, a source terminal i 00 and a non-terminal separated from each other on the single-crystal synthetic semiconductor layer 98 104, a channel region 126 extending between the source terminal 100 and the drain terminal 104, and a gate electrode 128 formed in the substrate 92 and generally aligned with the channel region 126. In this configuration, the source terminal i00, the drain terminal 104, the channel region 126, and the gate electrode 128 are used as FETs. -27- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) B7 V. Description of the invention (25) The P separation layer 94 preferably includes a salt selected from alkaline earth metal titanate, alkaline earth metal zirconium hafnium salt , Alkaline earth metal phosphonate, alkaline earth metal button salt, alkaline earth metal ruthenate, earth test metal sharp group of insulators. In a particularly preferred embodiment, the isolation layer 94 includes srxBaIXTi03 where x is in a range between:. Please continue to refer to FIG. 14. The single crystal synthetic semiconductor layer 98 includes the following materials: a group of compounds, a group IIIeV compound, a Π-VI compound, and a compound. ^ 1 In the preferred embodiment, the synthetic semiconductor layer 98 is preferably made of gallium arsenide, but any composition composed of A1GaAs, hp, InGaAs, InGaP, ZnS_ZnSeS can be used. FIG. 15 shows a cross-sectional schematic diagram of a semiconductor structure 13 丨 which is broadly similar to the semiconductor structure i24 shown in FIG. 14, which further includes a second gate electrode 1 formed on or at least partially within the synthetic semiconductor layer%. 〇2, where the second gate electrode 1 CL · helps to cover the channel area 26. In this configuration, according to generally known principles, the source electrode 100, the drain electrode 104, the channel area 126, and the first One gate electrode 102 can be used as a MESFET together. Alternatively, the source electrode 100 and the encapsulation electrode 104, the channel region 12 and the second gate electrode 102 can form a high-speed electron transport transistor (high eiect_m0binty transistor; MT). As explained in the text with Figure 11 The semiconductor structure 132 including the first gate electrode 128 and the second gate electrode 102 can also be constructed to be used as a single FET with two gates, where one gate can be used to modulate the problem of the other gate electrode. 'Limit voltage' or these two gate electrodes can be connected to substantially increase the transconductance of the electric sun. Figure 16 shows a semiconductor -28 which is broadly similar to the semiconductor structure 124 shown in Figure 14 Home Standard (CNS) M specification (referred to as χ Norwegian public love) 513810 A7 ---- B7 V. Description of the invention ~ ~ --- Sectional schematic diagram of structure 134 'is used to further explain the logic circuit formed in the substrate 92 'For example, CMOS circuit 13. The semiconductor ... illustrates many of the advantages associated with growing a single crystal synthetic semiconductor layer 128 on a silicon substrate 92, which allows the microelectronic structure of the synthesized semiconductor layer 98 to be microelectronic with the substrate 92 at 5 o'clock. The overall integration is concluded. ^ Specifically, FIG. 17 shows a cross-sectional schematic diagram of a semiconductor structure 136 that is broadly similar to the semiconductor structure 134 shown in FIG. 16 to further explain the gate electrode 128 that couples people to the circuit 130. For example, through electrical interconnection 132. The private circuit 130 can be configured to supply a predetermined voltage to the gate 12 $, which is turned on, off, or otherwise alters the current between the source terminal 100 and the drain terminal 104. In In another specific embodiment, FIG. 8 shows a schematic cross-sectional view of a semiconductor structure 138 that is broadly similar to the semiconductor structure 134 shown in FIG. 16 to further explain the doped impurity-type region formed in the substrate 92. 4 〇, for effectively electrically coupling the circuit 130 and the gate electrode 128. According to the following process parameters, many structures as mentioned in Figs. 9 to 18 can be formed. First, a semiconductor substrate 92 is provided. Thereafter, the circuit 112 (FIG. 10), the circuit 130 (FIG. 16), or any other desired microelectronic structure may be fabricated in the semiconductor substrate. If desired, the integrated circuit fabricated in the semiconductor substrate 92 may include a signal receiving circuit. The device region (eg, a 'voltage signal') then uses a bias channel on the device region, which is a channel extending between the source 100 and the source 10 $. Thereafter, a single crystal synthetic semiconductor layer 94 is epitaxially grown to cover the semiconductor substrate. During the aforementioned epitaxial growth of a single crystal layer step, the Chinese paper standard (CNS) A4 (210 X 297 mm) can be applied at the single -29. B7 V. Description of the invention (27) Crystal oxide layer 94 The amorphous oxide H is formed on the 7 sides of the amorphous oxide layer as shown in FIG. Then, a single crystal synthetic semiconductor layer 98 ′ can be grown by worm crystal. The single crystal oxide layer 94 can be exposed to the retreat process as shown in FIG. 1 and then as described in FIG. 3. The layer 94 structure was changed from a single crystal to an amorphous. Semiconductor devices, such as one or more source terminals 100 'and 104, and channel regions 105, can then be formed within the early-crystallized synthetic semiconductor layer 98 (see Figure 9). As described above, the source 100, the drain 104, and the channel 105 are preferably used as semiconductor devices (e.g., FETs), which are constructed in response to a device area (for example, the area of FIG. 9) provided in the substrate 92. Change the conductivity of the channel. If Liwen cooperates with the brief description of Figures 1-3, the epitaxial growth step mentioned above can be implemented by any suitable process, the process used is selected from the group consisting of MBE 'M0CVD, MEE and ALE group. In addition, the step of epitaxial growth of a single crystal synthetic semiconductor layer can be performed by: growing a seed layer of a single crystal semiconductor material to cover a single crystal oxide layer, and thereafter 'growing a single crystal synthetic semiconductor device layer to cover the seed layer. In addition, a synthetic semiconductor can be grown in two or more stages to perform an annealing process between any two stages, wherein the annealing process is used to make the single crystal layer 94 become amorphous. In the description of the river surface, 'the present invention has been described with reference to specific embodiments. However, 'the person skilled in the art should understand the various modifications of the present invention and can easily modify it' without departing from the present invention provided by the patent application examples below. -30-This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public concerns) 513810 A7 B7 5. The scope and spirit of the invention description (28). Therefore, the description and drawings should be regarded as illustrations and should not be regarded as limitations' and all such modifications are within the scope of the present invention.

裝已說明關於特定具體實施例的優勢、其他優點及問題解決方案。However，the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage，or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims.本文中所使用的術語「包括」、「包含」或其任何其他的變化都是用來涵盍非專有内含項，使得包括元件清單的方法、方法、物品或裝置不僅包括這些元件，而且還包括未明確列出或此類方法、方法、物品或裝置原有的其他元件。 -31 · 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)The advantages, other advantages, and problem solutions of specific embodiments have been described. However, the benefits, advantages, solutions to problems, and any element (s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. As used in this article, the terms "including", "including" or any other variation thereof are used to encompass non-proprietary inclusions, such as methods, methods, articles, or devices that include a list of components These include not only these elements, but also other elements not explicitly listed or such methods, methods, articles, or devices. -31 · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims

申请專利範圍一'種半導體裝置結括：一包含矽的單結板； -鹼土金屬絕緣體’其覆蓋該基板；一非結晶氧化石夕層，其介體之間；土伋鹼土金屬絕緣 -單結晶合成半導體層，以覆蓋該鹼在該單結晶合成半導fh f + A π 离、、、巴、味體， k 體層上形成分隔的源電極和汲電極’並在其之間界定-通道區域H 域。*包極’其形成於該基板中並對齊該通道區如申請專利範圍第1項之結構，該結構進-步包括一第二其形成於該單結晶合成半導體層.上以覆蓋該通逼區域。如申請專利範圍第2項之結構，纟中該源電極、及電極、通逞區域和第二閘電極構成一MESFET。如申請專利範圍第2項之結構，丨中該源電極、及電極、通道區域和第二閘電極構成一 HEMT。如申請專利範圍第〗項之結構，該結構進一步包括一形成於該基板中的CMOS電路。 6. 其中該第一閘電極係耦合其中該第一閘電極包括如申請專利範圍第5項之結構至該CMOS電路。如申請專利範圍第5項之結構..........， 6雜雜貝型區域’其形成於該基板中並轉合至該CM〇s 電路。 -32- 本紙張尺度適用中國國豕標準(CMS) A4規格(21〇 X 297公爱）The scope of the patent application includes a type of semiconductor device including: a single junction plate containing silicon;-an alkaline earth metal insulator covering the substrate; an amorphous stone oxide layer between the mediators; a soil alkaline earth metal insulation-single The semiconductor layer is crystallized to cover the base to form a separated source electrode and a drain electrode on the single crystal synthetic semiconducting fh f + A π ion, ion, bar, odorant, and k body layer, and define a channel between them. Zone H zone. * Wrap pole 'It is formed in the substrate and aligned with the channel area as in the structure of the scope of patent application item 1, the structure further includes a second it is formed on the single crystal synthetic semiconductor layer to cover the general force region. For example, in the structure of the second scope of the patent application, the source electrode, and the electrode, the pass region, and the second gate electrode constitute a MESFET. For example, the structure of the second scope of the patent application, in which the source electrode, and the electrode, the channel region and the second gate electrode constitute a HEMT. For example, the structure of the scope of the patent application, the structure further includes a CMOS circuit formed in the substrate. 6. Wherein the first gate electrode is coupled, wherein the first gate electrode includes the structure as in item 5 of the patent application scope to the CMOS circuit. For example, the structure in the scope of the patent application No. 5 ........., 6 miscellaneous shell type region 'is formed in the substrate and transferred to the CMOS circuit. -32- This paper size applies to China National Standard (CMS) A4 (21〇 X 297 public love)

8.如申σ月專利範圍第5項之結構’纟中該第一閘電極包括一库禹3至该CMOS電路的電連接器。 9·如申請專利範圍第6項之結構，其中該cM〇S電路被建構以選擇性控制一供應至該第一閘電極的偏壓。 1 〇.如T凊專利範圍第丨項之結構，其中該鹼土金屬絕緣體包括選自由鹼土金屬鈦酸鹽、鹼土金屬锆酸鹽、鹼土金屬铪I鹽、鹼土金屬鈕酸鹽、鹼土金屬釕酸鹽及鹼土金屬銳酸鹽所組成之群組的絕緣體。 1 1 ·如申請專利範圍第丨項之結構，其中該單結晶合成半導體層包含一選自由下列所組成之群組的材料：ΠΙ_ν族合成物、混合III-V族合成物、π_νι族合成物及混合⑴％族合成物。 12 ·如申請專利範圍第丨項之結構，其中該單結晶合成半導體層包含一遠自由下列所組成之群組的材料：GaAs、 AlGaAs、InP、InGaAs、InGaP、ZnSe及 ZnSeS。 13.如申請專利範圍第12項之結構，其中該鹼土金屬絕緣體包括SrxBai.xTi〇3 v其、中χ值介於〇到丨範圍内。 14 · 一種半導體裝置結$冓^^括：一單結晶半導體; 一鹼土金屬氧化物，其覆蓋該基板；一單結晶合成半導體層，以覆蓋該驗土金屬氧化物；分隔的源極區域和汲極區域，其形成於該基板中；以及一閘電極，其形成於該單結晶合成半導體層中並且對8. The structure of the fifth item of the patent scope of claim 纟, the first gate electrode includes an electrical connector from Kuyu 3 to the CMOS circuit. 9. The structure of claim 6 in which the cMOS circuit is configured to selectively control a bias voltage supplied to the first gate electrode. 10. The structure according to item 1 of the patent scope of T 凊, wherein the alkaline earth metal insulator is selected from the group consisting of alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal sulfonium I salts, alkaline earth metal button salts, and alkaline earth metal ruthenic acids. A group of insulators composed of salt and alkaline earth metal sharps. 1 1 · The structure according to item 丨 in the scope of patent application, wherein the single crystal synthetic semiconductor layer comprises a material selected from the group consisting of: a III-V composite, a mixed III-V composite, and a π_νι composite And mixed ⑴% family composition. 12. The structure according to item 1 of the scope of patent application, wherein the single crystal synthetic semiconductor layer includes a material far from the following group: GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS. 13. The structure according to item 12 of the scope of the patent application, wherein the alkaline earth metal insulator comprises SrxBai.xTi03 v, where the median χ value is in the range of 0 to 丨. 14. A semiconductor device structure includes: a single crystalline semiconductor; an alkaline earth metal oxide covering the substrate; a single crystalline synthetic semiconductor layer to cover the soil metal oxide; a separated source region and A drain region formed in the substrate; and a gate electrode formed in the single crystal synthetic semiconductor layer and facing the gate electrode.

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•齊該源極區域和汲極區域。 b·=:二利，圍第14項之裝置結構，該結構進-步包括 ^ ; 5亥早結晶合成半導體層中的MESFET。括口：請專利範圍第15項之裝置結構，其中該_FET包其歐姆接觸該單結晶合刀隔的源極區域和汲極區域成半導體層；以及• Align the source and drain regions. b · =: Erli, the device structure around item 14, the structure further includes ^; MESFET in the semiconductor layer is crystallized early. Included: The device structure of item 15 of the patent, wherein the _FET includes a ohmic contact with the source region and the drain region of the single crystal blade to form a semiconductor layer; and

裝 :金屬閘電極，其接觸該單結晶合成半導於该源極區域和汲極區域之間的位置。 17 ·如申請專利範 .貝衣置結構，其中在該單結晶合成+導體層中，該源電極及汲電極分別接觸該摻雜雜質型源極區域和;及#區域。 1如申料利範圍第14項之結構，其中該鹼土金屬絕緣體包括選自由鹼土金屬鈦酸鹽、鹼土金屬錘酸鹽、鹼土金蜀铪馱鹽、鹼土金屬钽酸鹽、鹼土金屬釕酸鹽及鹼土金屬銳酸鹽所組成之群組的絕緣體。 t 19·如申請專利範圍第14項之結構，其中該單結晶合成半導體層包含一選自由了列所組成之群組的材料·· m-v族合成物、混合III-V族合成物、II-VI族合成物及混合⑴… 族合成物。 20·如申請專利範圍第14項之結構，其中該單結晶合成半導體層包含一選自由下列所組成之群組的材料：GaAs、 AlGaAs、InP、InGaAs、InGaP、ZnSe及 ZnSeS。 21 ·如申請專利範圍第20項之結構，其中該鹼土金屬絕緣體 -34- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公^ -----—Device: a metal gate electrode that contacts the single crystal synthetic semiconductor at a position between the source region and the drain region. 17 · As claimed in the patent application structure, wherein in the single crystal synthesis + conductor layer, the source electrode and the drain electrode respectively contact the doped impurity type source region and the # region. 1 The structure of claim 14, wherein the alkaline earth metal insulator is selected from the group consisting of an alkaline earth metal titanate, an alkaline earth metal hammer salt, an alkaline earth golden salt, an alkaline earth metal tantalate, and an alkaline earth metal ruthenate. And alkaline earth metal sharps. t 19 · The structure according to item 14 of the scope of the patent application, wherein the single crystal synthetic semiconductor layer includes a material selected from the group consisting of: · mv group compound, mixed group III-V compound, II- Group VI composites and mixed ⑴ ... Group composites. 20. The structure according to item 14 of the scope of patent application, wherein the single crystal synthetic semiconductor layer comprises a material selected from the group consisting of GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS. 21 · If the structure of the scope of application for patent No. 20, wherein the alkaline earth metal insulator -34- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public ^ ------

包括 SrxBa“xTi〇3，其 ^ 22· ·如申請專利範圍第14¾ 包含一單結晶氧化物。 23·如申請專利範圍第14jj 包含一藉由加熱處化物。 24· —種半導體裝置結’ 一單結晶半導體i • X值介於0到1範圍内。之結構，其中該鹼土金屬氧化物之結構，其中該鹼土金屬氧化物單結晶氧化物所形成的非結晶氧Including SrxBa "xTi〇3, ^ 22 · If the scope of patent application No. 14¾ contains a single crystalline oxide. 23 · If the scope of patent application No. 14jj includes a compound by heating. 24 ·-a semiconductor device junction 'a The single crystal semiconductor i has an X value in the range of 0 to 1. The structure, wherein the structure of the alkaline earth metal oxide, wherein the amorphous oxygen formed by the alkaline earth metal oxide single crystal oxide

括：一非結晶氧化物層，以覆蓋該基板；單結晶合成半導體層，以覆蓋該非結晶氧化物層；一場政電晶體，其具有至少部份於該合成半導體層中形成的一源極、汲極、閘極及通道，該通道具有一電流傳導率；以及 "" CMOS電路，其至少部份形成於該矽基板中，該 CMOS電路包含一裝置區域，其建構以控制該通道的電流傳導率。 25 ·如申請專利範圍第24項之裝置結構，其中該非結晶氧化物層包含一鹼土金屬氧化物。 26 ·如申請專利範圍第25項之裝置結構，其中鹼土金屬氧化物包括SrxBaNxTi〇3，其中X值介於〇到丨範圍内。 2 7 ·如申凊專利範圍第2 6項之裝置結構，其中該合成半導體層包含一選自句下列所組成之群組的材料：GaAs、 AlGaAs、InP、InGaAs、InGaP、ZnSe及 ZnSeS。 2 8 ·如申請專利範圍第24項之裝置結構，其中該合成半導體 -35-Includes: an amorphous oxide layer to cover the substrate; a single crystalline synthetic semiconductor layer to cover the amorphous oxide layer; a field-effect crystal having a source electrode formed at least partially in the synthetic semiconductor layer, Drain, gate, and channel, the channel having a current conductivity; and " " CMOS circuit, which is at least partially formed in the silicon substrate, the CMOS circuit includes a device region, which is constructed to control the channel's Current conductivity. 25. The device structure of claim 24, wherein the amorphous oxide layer comprises an alkaline earth metal oxide. 26. The device structure as claimed in claim 25, wherein the alkaline earth metal oxide includes SrxBaNxTi03, where the X value is in the range of 0 to 丨. 27. The device structure as claimed in item 26 of the patent application, wherein the synthetic semiconductor layer includes a material selected from the group consisting of: GaAs, AlGaAs, InP, InGaAs, InGaP, ZnSe, and ZnSeS. 2 8 · The device structure according to item 24 of the patent application scope, wherein the synthetic semiconductor -35-

本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱）This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)

:包含-選自由下列所組成之群組的材料：m_v族合成、混合III.V族合成物、„_VI族合成物及成物。矢σ 29.如申請專利範圍第24 ^ 、、衣罝結構，其中該CMOS電路包含一數位積體電路。 3〇·如中請專利範圍第24項之裝置結構，丨中該源極和沒極包含形成於該合成半導體層中之分隔的摻雜雜質型區域。 31·如申請專利範圍第30項之裝置結構，Λ中該閘極包含金屬電極，其形成於該源極和汲極之間的合體上。導 32.如申請專利範圍第3Q項之裝置結構，其中該閘極包含一 ^金屬電極，其藉由一閘極電介質與該通道隔離。 33·如中請專利範圍第24項之裝置結構，其中該裝置區域包含一第二閘電極μ 34. 如申請專利範圍第33項之裝置結構，其中該第二閘電極包含用來接收一電壓信號之該CM〇s電路的摻雜雜質區域。 35. 如申請專利範圍第33項之裝置結構，其中該第二問電極包含用來接收一電壓信號之該CM〇s電路的傳導電極。 36·如申請專利範圍第24項之裝置結構，其中該單結晶半導體基板包含一矽基板。 3 7.種製造半導體裝置結構之方法，該方法包括下列步驟： -36- 513810: Contains-a material selected from the group consisting of: m_v group synthesis, mixed III.V group composition, "_VI group composition and product. Vector σ 29. As claimed in the scope of application for patent No. 24 ^, clothing Structure, in which the CMOS circuit includes a digital integrated circuit. 30. The device structure of item 24 in the patent scope, wherein the source electrode and the non-electrode electrode include isolated doped impurities formed in the synthetic semiconductor layer. 31. If the device structure of the scope of patent application No. 30, the gate in Λ contains a metal electrode, which is formed on the combination between the source and the drain. 32. If the scope of patent application is No. 3Q The device structure, wherein the gate electrode includes a metal electrode, which is isolated from the channel by a gate dielectric. 33. The device structure of item 24 in the patent scope, wherein the device region includes a second gate electrode μ 34. The device structure according to item 33 of the patent application, wherein the second gate electrode includes a doped impurity region of the CMOS circuit for receiving a voltage signal. 35. The device according to item 33 of the patent application Structure, which The second interrogating electrode includes a conducting electrode of the CMOS circuit for receiving a voltage signal. 36. The device structure of the 24th aspect of the patent application, wherein the single crystal semiconductor substrate includes a silicon substrate. 37. A method for manufacturing a semiconductor device structure, the method includes the following steps: -36- 513810

提供一半導體基板； .形成一積體電路，其至少部份形成於該半導體基板内，该積體電路包含一建構以接收一信號的裝置區域；石石日日生長一單結晶氧化物層，以覆蓋該半導體基板；於郝日日生長一單結晶氧化物層期間，在該單結晶氧化物層下形成一非結晶氧化物層；磊晶形成一單結晶合成半導體層，以覆蓋該單結晶氧化物層；以及形成一半導體t置，其至少部份形成於該單結晶半導體層中，該半導體裝置建構以改變其傳導率，以響應該裝置區域所接收到的信號。 3 8.如申請專利範圍第37項之方法，其中該半導體基板包含石夕。 3 9·如申請專利範圍第38項之方法，其中形成一單結晶氧化物層的步驟包括生長一氧化矽的步驟。 40·如申請專利範圍第38項之方法，其中該磊晶生長一單結晶氧化物的步驟息括磊晶生長一包含一材料的氧化物，該材料係選自由驗土金屬鈦酸鹽、鹼土金屬錯酸鹽、驗土金屬铪酸鹽、鹼土金屬钽酸鹽、鹼土金屬釕酸鹽及驗土金屬鈮酸鹽所組成的群組。 4 1.如申請專利範圍第40項之方法，其中該磊晶生長一單結晶氧化物的步驟包括磊晶生長Sr^Ba^xTiO;的步驟，其中 X值介於0到1範圍内。 42.如申請專利範圍第40項之方法，其中該磊晶生長一單結 -37- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐）Providing a semiconductor substrate; forming an integrated circuit at least partially formed in the semiconductor substrate, the integrated circuit including a device region constructed to receive a signal; a single crystal oxide layer growing day by day, To cover the semiconductor substrate; during Hao Riri's growth of a single crystalline oxide layer, an amorphous oxide layer was formed under the single crystalline oxide layer; epitaxial formation of a single crystalline synthetic semiconductor layer to cover the single crystal An oxide layer; and forming a semiconductor device, at least partially formed in the single crystalline semiconductor layer, the semiconductor device is constructed to change its conductivity in response to a signal received in the device area. 38. The method of claim 37, wherein the semiconductor substrate comprises Shi Xi. 39. The method of claim 38, wherein the step of forming a single crystalline oxide layer includes a step of growing silicon monoxide. 40. The method of claim 38, wherein the step of epitaxial growth of a single crystalline oxide includes epitaxial growth of an oxide including a material selected from the group consisting of a soil test metal titanate and alkaline earth. A group of metal malate, earth test metal osmate, alkaline earth metal tantalate, alkaline earth metal ruthenate, and earth test niobate. 4 1. The method of claim 40, wherein the step of epitaxial growth of a single crystal oxide includes the step of epitaxial growth of Sr ^ Ba ^ xTiO; wherein the X value is in the range of 0 to 1. 42. The method according to item 40 of the scope of patent application, wherein the epitaxial crystal grows a single knot -37- This paper size applies to China National Standard (CNS) A4 specification (210X 297 mm)

513810 A B c D 六、申請專利範圍晶氧化物的步驟包括藉由選自由隱、M0CVD、MEE 和ALE所組成之群組的方法來生長__氧㈣” ^ 43·如申請專利範圍第3? # ^ ^ 吊項之方法，其中該磊晶生長一單結晶合成半導體層步驟包括下列步驟： "生長-單結晶半導體材料的種子層，以覆蓋該單結晶氧化物層；以及生長一單結晶合成半導體裝置，以覆蓋該種子層。 44. 如申請^利範圍第43項之方法，該方法進一步包括加熱處理該單結晶氧化物層的步驟，用以將該單結晶氧化物層轉換為一額外的非結晶氧化物層。 45. 如中請專利範圍第44項之方法，其中該加熱處理步驟係在生長一種子層步驟之後實施。 6如申1專利範圍第44項之方法，其中該加熱處理步驟係在生長一單結晶合成半導體裝置層步驟之後實施。 47·如申請專利範圍第43項之方法，其中該生長一單結晶合成半導體裝置層的步驟包括生長一材料的步驟，該材料係選自由 GaAs、AlGaAs、InP、inGaAs、InGaP、ZnSe 及ZnSeS所組成的群組。 48.如申請專利範圍第43項之方法，其中該生長一種子層步驟包括磊晶生長一由鍺與一材料的超晶格所組成的材料，其中該超晶格材料係選自：GaASxPi、x(其中χ值介於〇到1範圍内）、InyGai-yP(其中y值介於〇到i範圍内）、 InGaAs、GaAs、AlGaAs、InGaP、AllnP及 AllnP。 49·如申請專利範圍第37項之方法，其中該磊晶生長一單結 -38- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 513810 8 8 8 A B c D 、申請專利範圍晶合成半導體層的步驟包括生長一材料的步驟，該材料係選自由 GaAs、AlGaAs、InP、InGaAs、InGaP、ZnSe 及Z n S e S所組成的群組。 5 0.如申請專利範圍第49項之方法，其中該磊晶生長一單結晶合成層的步驟包括藉由選自由]VIBE、MOCVD、MEE 和ALE所組成之群組的方法來生長一合成半導體層的步驟。 5 1，一種製造半導體裝置之方法’該方法包括下列步驟：提供一具有一表面的單結晶半導體基板；於該基板表面上形成分隔的源極和汲極區域，在亨、'原極和汲極區域之’間界定一第一通道，該通道建構以運載一電流；蠢晶生長一閘極絕緣體，以覆蓋該表面；磊晶生長一合成半導體材料層，以覆蓋該閘極π 體；〜於該合成半導體材料層中形成一閘電極，該帝構以控制通過該通道區域的電流；分域斜齊該材料層通道區以及閘電極於該合成半導體材料層中形成一閘電極中形成第隔源極和汲極區域，該第二分隔源極和汲極區第一分隔源極和汲極區域，並且於該合成半導體中在該第二分隔源極和汲極區域之間界定一第一域，該第二通道區域建構以引導一第二通道電流· 幵> 成一第一閘電極以覆蓋該通道區域’該第建構以控制該第二通道電流。 -39 本紙張尺度適用t S S家_(CNS)八故“獻撕公复） 513810 8 8 8 8 ABC D •、申請專利範圍 5 2.如申請專利範圍第5 0項之方法，其中該第二通道被建構以影響通過該第一通道的電流，以響應供應至該第二分隔源極和沒極區域的電子信號。 53·如申請專利範圍第50項之方法，其中該第一汲極區域被建構以影響通過該第二通道的電流，以響應供應至該第一汲極區域的電子信號。 -40 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）513810 AB c D VI. Patent application step The crystal oxide step includes growing by a method selected from the group consisting of crypto, MOCVD, MEE, and ALE. # ^ ^ The method of hanging items, wherein the step of epitaxial growth of a single crystal synthetic semiconductor layer includes the following steps: " Growth-a seed layer of a single crystal semiconductor material to cover the single crystal oxide layer; and growing a single crystal A semiconductor device is synthesized to cover the seed layer. 44. If the method of claim 43 is applied, the method further includes a step of heat-treating the single crystal oxide layer to convert the single crystal oxide layer into a Additional non-crystalline oxide layer. 45. The method according to item 44 of the patent, wherein the heat treatment step is performed after growing a sub-layer step. 6 The method according to item 44 of claim 1, wherein the The heat treatment step is performed after the step of growing a single crystal synthetic semiconductor device layer. 47. The method of claim 43 in the scope of patent application, wherein the growing a single crystal synthesis The step of the conductor device layer includes a step of growing a material selected from the group consisting of GaAs, AlGaAs, InP, inGaAs, InGaP, ZnSe, and ZnSeS. 48. The method according to item 43 of the patent application, wherein the The step of growing a sub-layer includes epitaxial growth of a material consisting of germanium and a superlattice of a material, wherein the superlattice material is selected from the group consisting of: GaASxPi, x (where χ is in the range of 0 to 1), InyGai-yP (where the value of y is in the range of 0 to i), InGaAs, GaAs, AlGaAs, InGaP, AllnP, and AllnP. 49. The method according to item 37 of the patent application, wherein the epitaxial growth is a single junction -38 -This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 513810 8 8 8 AB c D. The patent application step includes the step of growing a material, which is selected from the group consisting of GaAs , AlGaAs, InP, InGaAs, InGaP, ZnSe, and Z n S e S. 50. The method according to item 49 of the patent application, wherein the step of epitaxial growth of a single crystal composite layer includes by Selected from] VIBE, MOCVD The method of grouping MEE and ALE to grow a synthetic semiconductor layer. 51. A method of manufacturing a semiconductor device. The method includes the following steps: providing a single crystal semiconductor substrate having a surface; A separate source and drain region is formed on the top, and a first channel is defined between Heng, 'primary and drain region', the channel is constructed to carry a current; a stupid crystal grows a gate insulator to cover the surface ; Epitaxial growth of a layer of synthetic semiconductor material to cover the gate π body; ~ forming a gate electrode in the layer of synthetic semiconductor material, the emperor structure to control the current passing through the channel region; diagonally aligning the material layer The channel region and the gate electrode form a gate electrode in the synthetic semiconductor material layer to form a second source and drain region. The second source and drain region separate the source and drain region. A synthetic semiconductor defines a first domain between the second separated source and drain regions, and the second channel region is constructed to guide a second channel current. 幵 & g t; forming a first gate electrode to cover the channel region ’the first structure to control the second channel current. -39 This paper standard is applicable to SS home_ (CNS) eight reasons "offering and tearing public" 513810 8 8 8 8 ABC D • Application for patent scope 5 2. If the method of applying for patent scope item 50, where the first The two channels are configured to affect the current passing through the first channel in response to an electronic signal supplied to the second separated source and non-electrode regions. 53. The method of claim 50 in the patent application scope, wherein the first drain electrode The area is constructed to affect the current passing through the second channel in response to the electronic signal supplied to the first drain area. -40-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)