TW511267B - Wafer package with buffer bump pads - Google Patents

Abstract

A new wafer level package is proposed in this invention. The present invention establishes a double pad interconnect structure to disperse the stress of the bump. The double pad structure includes bump pad, electrode pad and plural conductive columns of the package. The conductive columns are the interconnection between the electrode pad and the bump pad. Around the conductive columns is insulated material. Due to the buffer characteristic of the conductive columns and the insulated material, the stress of the bump can be dispersed and the reliability can be increased. Further, the double pad structure manufacturing are wafer-level processes and the manufacturing cost can be decreased.

Description

MIZb/ 五、發明說明（1) 1.背景說明 近年來由於半導體相關科技的急速提昇，其多元化、可攜 2與輕、薄、微小化的需求，使晶片封裝製程業已脫離了 ，統的技術而朝高功率、高密度、輕、薄與微小化等高精 猎度製程發展。除此之外，電子封裝（Electr〇nicMIZb / V. Description of the invention (1) 1. Background note In recent years, due to the rapid advancement of semiconductor-related technologies, its diversification, portability, and lightness, thinness, and miniaturization have caused the chip packaging process to be separated. Technology is developing towards high-precision hunting processes such as high power, high density, lightness, thinness, and miniaturization. In addition, electronic packaging (Electronic

Packaging )產品尚需保有高可靠度、低製造成本等必要 ，性二於下一世代電子封裝結構中晶片尺寸封裝（csp )、覆晶（Flip Chip)與晶圓級封裝（Wafer Uvel Packaging )扮演著關鍵性之角色。 鲁 電子封裝結構大部份的破壞模式皆導源於低週波之熱應力 與應變疲勞破壞。因電子封裝元件是由數種不同的材料組 合而成，其熱膨脹係數等具有很大的差異性，如SiHc〇n 的膨服係數為3.3ppm/〇C，FR-4 為16 PPm/〇C (x，y Plane)。當不同機械特性的材料接合在一起，因其膨脹係 數（Coefficient of Thermal Expansion，CTE)的不 同，則當受到環境溫度變化時其膨脹或收縮量將有所差 異，熱應力應變於是產生。對於覆晶與晶圓級封裝的電子 封裝結構而言，導電凸塊的熱變形往往是破壞的主因。一 叙傳統的面積陣列覆晶導電凸塊如圖1 a所示，其剖面圖如 圖2b所不，包含有矽基板1〇1、電極1〇2、絕緣保護層 103 ^電凸塊底下的擴散阻隔層1 〇5 (UBM，under bump metallurgy)以及導電凸塊丨〇4等。然而，由於熱膨脹係(Packaging) products still need to maintain high reliability, low manufacturing costs, etc. Second, in the next generation of electronic packaging structure, chip size packaging (csp), flip chip (Flip Chip) and wafer-level packaging (Wafer Uvel Packaging) play Plays a key role. Most of the failure modes of Lu electronic packaging structures are caused by low-frequency thermal stress and strain fatigue failure. Because electronic packaging components are composed of several different materials, their thermal expansion coefficients are very different. For example, the expansion coefficient of SiHcOn is 3.3ppm / 〇C, FR-4 is 16 PPm / 〇C (x, y Plane). When materials with different mechanical properties are joined together, due to different coefficients of thermal expansion (CTE), the amount of expansion or contraction will be different when subjected to changes in ambient temperature, and thermal stress and strain will occur. For flip chip and wafer level packaging electronic packaging structures, thermal deformation of conductive bumps is often the main cause of damage. A typical area array chip-on-chip conductive bump is shown in Figure 1a, and its cross-sectional view is shown in Figure 2b. It includes a silicon substrate 101, an electrode 102, an insulating protection layer 103, and a semiconductor substrate. Diffusion barrier layer 105 (UBM, under bump metallurgy) and conductive bumps 104. However, due to thermal expansion

511267 五、發明說明（2) 數的不匹配，為維持封裝的可靠度，覆晶封裝另外需要填 充底膠（underfill)。但底膠的填充製作方式，將提高 成本與製作時程。如Fujitsu的美國專利5475236，Super CSP(Chip Scale Package)封裝，圖2所示，包含有石夕基板 201、電極2 02、絕緣保護層2〇3、絕緣保護層20 9、填膠 2 04、銅柱205、錫球207、重新佈線導線2〇8。其利用銅柱 205與填膠204作為應力緩衝層，降低因熱膨脹係數不匹配 所產生的熱應力，但成本較高且可靠度改善有限。又如 Mitsubishi的美國專利5656863，如圖3所示，包含矽基 板301、電極302、絕緣保護層3〇3、絕緣保護層3〇9、填膠_ 3 04、内部錫球2〇5、錫球3〇7、重新佈線導線3〇8。其利用 兩階段的錫球連接來增加封裝可靠度。這些型態的封裝方 ^ =的均在降低因熱膨脹係數不匹配所產生的熱應力，以 Ϊ 虞可靠度，但目前為止封裝的可靠度仍然是晶圓級 構裝的一大議題。 2 ·本技藝之摘要說明 本發明提出一 曰®#丄土 V日日圓敬封裝結構，目的在於改善傳統 可靠度的問冑。為達到此目的，本發明於導電 有連接電個的導體柱。*多數個導體柱不僅 二；曰气電子元件承受熱疲勞負載時，因印刷電路板 /、夕曰曰片之㈤熱膨脹係數不E酉己所產t的熱應力容易511267 V. Description of the invention (2) The number does not match. In order to maintain the reliability of the package, the flip-chip package needs an underfill. However, the filling method of the primer will increase the cost and production schedule. For example, US Patent No. 5,475,236 to Fujitsu, Super CSP (Chip Scale Package) package, as shown in Figure 2, contains Shi Xi substrate 201, electrode 202, insulation protection layer 203, insulation protection layer 20 9, adhesive 2 04, Copper pillars 205, solder balls 207, and rewiring wires 208. It uses the copper pillars 205 and the filler 204 as a stress buffer layer to reduce the thermal stress caused by the mismatch of thermal expansion coefficients, but the cost is high and the reliability improvement is limited. Another example is U.S. Patent No. 5,565,863 to Mitsubishi. As shown in FIG. 3, it includes a silicon substrate 301, an electrode 302, an insulating protective layer 30, an insulating protective layer 309, a filler _ 04, an internal solder ball 205, and tin. Ball 307, reroute the wires 308. It uses a two-stage solder ball connection to increase package reliability. These types of packages are reducing thermal stress due to mismatched thermal expansion coefficients in order to reduce reliability, but the reliability of packaging is still a major issue for wafer-level packaging. 2 · Summary description of this technology The present invention proposes a ## 丄 V V-Japanese Yen packaging structure, the purpose is to improve the traditional reliability question. To achieve this object, the present invention is applied to a conductive post having a conductor. * Most conductor posts are not only two; when the electronic components are subjected to thermal fatigue loads, the thermal expansion coefficient of the printed circuit board is not easy because of the thermal expansion coefficient of the printed circuit board.

第6 f 5112676th 511267

的導電凸塊產生熱破壞，造成電子訊號的中 道二Λ杨ί ?中提出的多數個導體柱結構能夠有效的分散 ，的應力，提高封裝的可靠度。本發明的結構 ^ ί f晶片，·多數個導體柱，·導體柱頂端之導電塾片 以及¥電導體凸塊。整個結構不僅能提高封裝的長時 Γ;低ί=:ί作過程均能在晶圓級完成，所樣 本，明之前述與其他目的、特徵、以及優點，將藉由 下文中簽照圖示之較佳實施例之詳細說明而更明確。_ 3 · 本技藝之較佳實施例 圖4可表不本發明之一較佳實施例之細部製作流程剖面 圖’圖4a為一矽基板4〇1含有I/O電極4〇2與絕緣保護層 4〇3。在表面上塗佈另一絕緣保護層4〇4並蝕刻開出接9觸孔 通道408，此絕緣保護層404可為楊氏模數較低之高分子材 料如聚硫亞胺（polyimide)等，如圖化所示。接觸孔通道 408的目的在於可沈積導體柱，以連接電極4〇2與導電凸塊 407之用（圖4d)。而頂端可以再一次擴大蝕刻面積，用 以沈積導電墊片，如圖4c所示之接觸孔通道4〇9。沈積導 體柱4 0 5與導電墊片410的方法可以採用電鍍的方式。因 此，導電墊片41 0的材料若與導體柱相同，則可以一次完 成導體柱405與導電墊片410的沈積，如圖4d所示，然The conductive bumps produced by the thermal damage caused the majority of the conductor pillar structure proposed in the middle of the electronic signal can effectively disperse the stress and improve the reliability of the package. The structure of the present invention is a wafer, a plurality of conductor posts, a conductive cymbal at the top of the conductor post, and an electric conductor bump. The entire structure can not only improve the long-term packaging time; low ί =: ί can be completed at the wafer level, the sample, the aforementioned and other purposes, features, and advantages will be compared by the following chart The detailed description of the preferred embodiment is more clear. _ 3 · The preferred embodiment of this technology. Figure 4 can show a detailed cross-sectional view of the manufacturing process of a preferred embodiment of the present invention. 'Figure 4a is a silicon substrate 400. It contains I / O electrodes 402 and insulation protection. Layer 403. Apply another insulating protective layer 404 on the surface and etch to open the 9-contact hole channel 408. This insulating protective layer 404 can be a polymer material with a low Young's modulus such as polyimide , As shown in the figure. The purpose of the contact hole channel 408 is to deposit a conductive post to connect the electrode 40 to the conductive bump 407 (FIG. 4d). The top can be enlarged again to etch the area to deposit conductive pads, such as the contact hole channel 409 shown in Figure 4c. The method for depositing the conductive pillars 405 and the conductive pads 410 may be electroplating. Therefore, if the material of the conductive pad 410 is the same as that of the conductive post, the deposition of the conductive post 405 and the conductive pad 410 can be completed at one time, as shown in FIG. 4d.

第7頁 511267Page 7 511267

402、405與410可為同材質之導體。圖“表示導體柱4〇5與 導電墊片410的3D圖形，可表示剖面圖無法顯現的完整結 構。導體柱4 05為多數根在導電墊片41〇之下的柱子，連接 導電墊片410與電極402，在圖形中以4根導體柱表示，而 數目可以由封裝的需求而定，其導體柱與墊片形狀可為圓 沁^橢圓或夕邊形柱體。圖4 f表示在表面塗佈第二層絕緣 保護層40 6，材料可以和絕緣保護層4〇4相同。最後是導電 凸塊4 0 7的長成，如圖4 g所示。 本發明的另一種形式如圖5所示。多數個導體柱4〇5亦可以_ 製作在導電凸塊下的擴散阻隔層5(π之上。 本發明的另一種形式如圖6所示。多數個導體柱4〇5可以在 重新佈線之後導線6〇1與絕緣保護層6〇2之上製作。 本發明意欲涵蓋對於熟習此項技藝之人士而言係明顯的各 種修改與相似配置。因此，申請專利範圍之範圍應根據最 廣的给釋’以包容所有此類修改與相似配置。402, 405 and 410 may be conductors of the same material. The figure "shows the 3D graphics of the conductive post 405 and the conductive pad 410, which can show the complete structure that cannot be seen in the cross-section. The conductive post 405 is a majority of the pillars below the conductive pad 410, which is connected to the conductive pad 410 And the electrode 402 is represented by 4 conductor pillars in the figure, and the number can be determined by the requirements of the package. The shape of the conductor pillars and the spacers can be round ellipses or evening pillars. Figure 4f shows on the surface The second layer of insulating protection layer 406 is coated, and the material can be the same as that of the insulating protection layer 404. Finally, the conductive bump 407 is grown, as shown in Fig. 4g. Another form of the present invention is shown in Fig. 5 As shown in the figure, most of the conductive pillars 405 can also be made under the conductive bumps on top of the diffusion barrier layer 5 (π. Another form of the present invention is shown in Figure 6. Most of the conductive pillars 405 can be After rewiring, the wires 601 and the insulating protection layer 602 are made on top. The present invention is intended to cover various modifications and similar configurations that are obvious to those skilled in the art. Therefore, the scope of the scope of patent application should be based on the most Extensive interpretations to accommodate all such modifications and similar matches Home.

第8頁 511267 圖式簡單說明 5. 圖式之簡單說明 圖1 a至1 b為傳統的面積陣列覆晶封裝示意圖。 圖2為Fujitsu的Super CSP的封裝結構示意圖。 圖3為Mitsubishi的CSP的封裝結構示意圖。 圖4a至g為本發明的結構製作流程示意圖。 圖5為本發明之另一種形式示意圖。 圖6為本發明之另一種形式示意圖。 6. 元件符號說明 1 01矽基板 1 0 2電極 103絕緣保護層 104導電凸塊 105導電凸塊底下的擴散阻隔層 2 01基板 2 0 2電極 2 03絕緣保護層 2 0 9絕緣保護層 204填膠 2 05内部錫球 2 0 7銅柱 2 0 8重新佈線導線Page 8 511267 Brief description of the drawings 5. Brief description of the drawings Figures 1a to 1b are schematic diagrams of a conventional area array flip chip package. Figure 2 is a schematic diagram of the package structure of Fujitsu's Super CSP. FIG. 3 is a schematic diagram of a package structure of Mitsubishi's CSP. 4a to g are schematic diagrams of a structure manufacturing process of the present invention. FIG. 5 is a schematic diagram of another form of the present invention. FIG. 6 is a schematic diagram of another form of the present invention. 6. Description of component symbols 1 01 silicon substrate 1 0 2 electrodes 103 insulation protection layer 104 conductive bump 105 diffusion barrier layer under the conductive bump 2 01 substrate 2 0 2 electrode 2 03 insulation protection layer 2 0 9 insulation protection layer 204 Glue 2 05 Internal solder ball 2 0 7 Copper post 2 0 8 Reroute the wires

第9頁 511267 圖式簡單說明 3 0 1基板 3 0 2電極 3 0 3絕緣保護層 3 0 9絕緣保護層 304填膠 3 0 5内部錫球 3 0 7錫球 308重新佈線導線 4 01矽基板 4 0 2電極 403絕緣保護層 404絕緣保護層 405導體柱 4 0 6絕緣保護層 407導電凸塊 408接觸孔通道 409接觸孔通道 410導電墊片 501導電凸塊底下的擴散阻隔層 6 01導線 6 02絕緣保護層Page 9 511267 Brief description of the drawing 3 0 1 Substrate 3 0 2 Electrode 3 0 3 Insulating protective layer 3 0 9 Insulating protective layer 304 Filling 3 0 5 Internal solder ball 3 0 7 Solder ball 308 Rewiring wires 4 01 Silicon substrate 4 0 2 electrode 403 insulation protection layer 404 insulation protection layer 405 conductor post 4 0 6 insulation protection layer 407 conductive bump 408 contact hole channel 409 contact hole channel 410 conductive pad 501 diffusion barrier layer under the conductive bump 6 01 lead 6 02Insulation protective layer

第10頁Page 10

Claims (1)

六 '申請專利範圍 種晶圓級封裝結構，包含 矽晶圓之上； 秒日曰圓’具有電極在前述之 多數個導體柱，安置在前沭恭 分散m力t 1 4 呔之电極之上，作為電信連接與 ，，主可為圓形、橢圓或多邊形枉體。 緩衝應力之 絕緣保護層，用來作為介電層與保護晶圓或 用； 導電凸塊墊片，作為η 4導電凸塊的墊片；以及 導電凸塊，作為連接電路之用。 2 ·如申請專利範圚μ 1 之多數個導體柱，，所述之晶圓級封裝結構’其所述 上。 文置在導電凸塊下之擴散阻隔層UBM之 3 ·如申請專利範圍资 含重新佈線層，而\弟、項所述之晶圓級封裝結構’其更包1 向上述之多數個導體枉安置在重新佈線層 之上°Six types of patent-applied wafer-level package structures, including silicon wafers; the second day, the sun's circle, has electrodes on most of the aforementioned conductive pillars, and is placed on the front of the electrode to disperse m force t 1 4 4 As a telecommunication connection, the main body can be a round, oval or polygonal carcass. An insulating protection layer for buffering stress is used as a dielectric layer and a protective wafer; a conductive bump pad is used as a η 4 conductive bump pad; and a conductive bump is used as a connection circuit. 2. According to a plurality of conductor posts of the patent application 圚 μ 1, the wafer-level package structure is described above. The diffusion barrier layer UBM placed under the conductive bumps 3 · If the scope of the patent application includes a rewiring layer, and the wafer-level packaging structure described in the above paragraph, its package 1 is directed to the majority of the above conductors 枉Placed above the redistribution layer °