TW511252B

TW511252B - Method of fabricating a NROM cell to prevent charging

Info

Publication number: TW511252B
Application number: TW90120137A
Authority: TW
Inventors: Chen-Chin Liu; Jiann-Long Sung
Original assignee: Macronix Int Co Ltd
Priority date: 2001-08-16
Filing date: 2001-08-16
Publication date: 2002-11-21

Abstract

The present invention provides a method of fabricating an NROM cell and preventing charging. An oxide-nitride-oxide (ONO) layer and bit line masks are formed on the ONO layer of the memory array area and an implantation process forms buried bit lines within the substrate. Rows of word lines can then be formed on the ONO layer approximately perpendicular to the buried bit lines. Finally, a spacer is formed on sidewalls of each word line, and a barrier layer and a passivation layer used for preventing the NROM cell being charged during process is respectively formed on the surface of the substrate.

Description

511252 五、發明說明（1) 發明之領域本發明係提供一種氮化物唯讀記憶體的製作方法。背景說明氮化物唯讀記憶體（nitride read only memory， = R0M )是一種用來儲存資料的半導體元件，由複數個記憶單元（memory cell)所組成，其中每一記憶單元皆包含有一 M0S電晶體以及一氮化石夕層。由於氮化石夕層具有高度之緻密性，因此可使經由M0S電晶體隧穿（tunnel ing)進入至氮化石夕層中的熱電子陷於（t r a p )其中，以達到儲存資料之目的。、請參考圖一至圖四，圖一至圖四為一習知製作氮化物唯讀記憶體的方法示意圖。如圖一所示，習知之氮化物唯瀆3己憶體係製作於一石夕基底1 2表面。石夕基底1 2係為一 P型矽基底且包含有一用以儲存電荷的記憶區（mem〇ry array) 以及一進行邏輯電路控制的週邊區（periphery c i ircu i t)。習知方法係先於矽基底1 2表面進行一傳統的氧化-氮化-氧化（oxide-n i tride-oxide，0N0)製程，以形成一由底氧化層（bottom oxide)14、氮化矽層16以及上氧化層（top oxide )1 8所組成的0N0介電層19。然後在0N0介電層1 9表面形成一光阻層2 0，並進行一黃光製程以及蝕刻製511252 V. Description of the Invention (1) Field of the Invention The present invention provides a method for manufacturing a nitride read-only memory. Background: Nitride read only memory (R0M) is a semiconductor device used to store data. It is composed of multiple memory cells, and each memory cell contains a MOS transistor. And a nitrided layer. Since the nitride nitride layer is highly dense, it is possible to trap (t r a) the hot electrons that enter the nitride nitride layer through tunneling of the MOS transistor to achieve the purpose of storing data. Please refer to Figures 1 to 4, which are schematic diagrams of a conventional method for making nitride read-only memory. As shown in Fig. 1, the conventional nitride compound is produced on the surface of a stone evening substrate 1 2. The Shixi substrate 12 is a P-type silicon substrate and includes a memory area (memory array) for storing electric charges and a peripheral area (peripheral c i ircu it) for logic circuit control. A conventional method is to perform a traditional oxide-n i tride-oxide (0N0) process on the surface of the silicon substrate 12 to form a bottom oxide layer 14 and silicon nitride. A 0N0 dielectric layer 19 composed of a layer 16 and a top oxide layer 18. Then, a photoresist layer 20 is formed on the surface of the 0N0 dielectric layer 19, and a yellow light process and an etching process are performed.

第5頁五、發明說明（2) 圖案，用來定義位元線（bit 程，以使光阻層20形成 1 i ne )的位置。如圖二所示，技- &彳t一來利用光阻層20作為遮罩（mask)， =氣=t6 i;;t被光阻層2°覆蓋之上氧化層18 ί上,I i數個摻雜區24，以作為記憶體之位元線，或再：’、、埋*式；及極（b u r i e d d r a i η )。隨後將光阻層2 0完全去除。如圖一所示’利用一熱氧化法（thermal oxidation)· 於位το線2 4上方表面形成一場氧化層2 6，作為各氮化矽層 1 6之間的隔離。最後如圖四所示，再沉積一摻雜多晶矽層 2 8，作為字元線。一，知士化物唯讀記憶體在字元線製作完成後，為避免 = 後續的化學沉積製程或蝕刻製程中受到紫外線照射 :產生電漿損壞，因此會形成一保護層29覆蓋於各字元線 f面，且各字元線之周圍側壁皆形成有一側壁子（spacer; 1 i 五所示。然而由於保護層29與該氮化物唯讀記憶介電層19係直接相接觸，所以後續在化學沉積製 =或蝕刻製程中受到紫外線照射所產生之部份的游離電將會穿過保護層29而進入0N0介電層19中，進而影響 ^氮化物唯讀記憶體之電性表現。Page 5 V. Description of the invention (2) A pattern is used to define a bit line (bit path, so that the photoresist layer 20 forms 1 in ne). As shown in FIG. 2, the technology- & 彳 t uses the photoresist layer 20 as a mask, === t6 i ;; t is covered by the photoresist layer 2 ° on the oxide layer 18, I i several doped regions 24 are used as bit lines of the memory, or further: ',, buried *, and pole (burieddrai η). Subsequently, the photoresist layer 20 is completely removed. As shown in FIG. 1 ', a thermal oxidation method is used to form a field oxide layer 26 on the surface above the position το line 2 4 as an isolation between the silicon nitride layers 16. Finally, as shown in FIG. 4, a doped polycrystalline silicon layer 28 is deposited as a word line. First, after the character line read-only memory is completed, in order to avoid = ultraviolet radiation during the subsequent chemical deposition process or etching process: plasma damage occurs, so a protective layer 29 is formed to cover each character Line f, and a sidewall (spacer; 1 i 5) is formed around the side walls of each character line. However, since the protective layer 29 is in direct contact with the nitride read-only memory dielectric layer 19, The part of the free electricity generated by the chemical deposition process or the etching process by ultraviolet radiation will pass through the protective layer 29 and enter the 0N0 dielectric layer 19, which will affect the electrical performance of the nitride read-only memory.

511252 五、發明說明（3) ---- 發明概述因此’本發明之目的在於提供一種改良的氮化物記憶體（NROM)的製作方法，以避免該氮化物唯讀記憶喝後續製程中受糸外線（U V 1 i gh t )照射或產生電漿損壞一； (plasma damage)° 在本發明之最佳實施例中，是先提供一表面包含有一記憶區以及一週邊區之基底，然後於該基底表面形成一由一底氧化（bottom oxide)層、一氮化石夕層以及一上氧化 (top oxide)層所構成之 0N0(oxide —nitride —〇xide)層。接著於該§己憶區内之該〇 N 〇層表面形成複數條縱向排列之位元線遮罩（bit line mask)，隨後進行一第一離子佈植製程三以於未被該位元線遮罩所覆蓋之該基底中形成複數條埋藏位元線（b u r i e d b i t 1 i n e )。在去除該位元線遮罩之後:於該ΟΝΟ層表面上形成複數條橫向排列並與該複數條埋藏位元線幾近垂直之字元線。最後於該基底表面形成一犧牲層’並對該犧牲層進行一回蝕刻製程，以於各該字元線之周圍側壁形成一側壁子（spacer)，並於該基底表面依序形成一阻絕層以及一保護層。 ^於本發明製作之氮化物唯讀記憶體表面依序形成有阻、、、巴層以及一保護層，因此可以避免該氮化物唯讀記憶511252 V. Description of the invention (3) ---- Summary of the invention Therefore, the purpose of the present invention is to provide an improved method for making a nitride memory (NROM) to avoid the nitride read-only memory and subsequent problems in the subsequent process. Plasma damage is caused by irradiation (UV 1 i gh t); (plasma damage) In a preferred embodiment of the present invention, a substrate including a memory area and a peripheral area on a surface is first provided, and then A 0N0 (oxide-nitride-oxide) layer formed by a bottom oxide layer, a nitride nitride layer, and a top oxide layer is formed on the substrate surface. Next, a plurality of longitudinally arranged bit line masks are formed on the surface of the 0N0 layer in the §memory area, and then a first ion implantation process 3 is performed so as not to affect the bit line. A plurality of buried bit lines are formed in the substrate covered by the mask. After the bit line mask is removed: a plurality of horizontally arranged word lines are formed on the surface of the ONO layer and are approximately perpendicular to the buried bit lines. Finally, a sacrificial layer is formed on the surface of the substrate and an etching process is performed on the sacrificial layer to form a spacer on the sidewalls around the word lines, and a barrier layer is sequentially formed on the substrate surface. And a protective layer. ^ The surface of the nitride read-only memory fabricated in the present invention is sequentially formed with a resistive, a, a, and a protective layer, so that the nitride read-only memory can be avoided.

第7頁 511252 五、發明說明（4) 體於後續製程中受紫外線（U V 1 i gh t )照射或產生電漿損壞 (plasma damage)，同時該阻絕層更可以有效地隔離該保護層與遠氣化物唯謂a己憶體之Ο N 〇介電層，以避免該保護層與該ΟΝΟ介電層直接接觸，因此能進一步抑制該保護層中之游離電子進入該0Ν0介電層而影響該氮化物唯讀記憶體之電性表現。發明之詳細說明Page 7 511252 5. Description of the invention (4) The body is exposed to ultraviolet rays (UV 1 i gh t) in the subsequent process or generates plasma damage. At the same time, the barrier layer can effectively isolate the protective layer from the distance. The gaseous substance is only a 0 N 〇 dielectric layer of a memory, to prevent the protective layer from directly contacting the 0 NO 0 dielectric layer, so it can further inhibit the free electrons in the protective layer from entering the ONO dielectric layer and affect the Electrical performance of nitride read-only memory. Detailed description of the invention

請參考圖六至圖十，圖六至圖十為本發明製作氮化物唯讀記憶體的剖面示意圖。如圖六所示，本發明之氮化物唯讀記憶體係製作於一半導體晶片3 〇之基底3 2表面，且基底3 2表面定義有一記憶區以及一週邊區。在本發明之較佳實鉍例中’基底3 2係為一 Ρ型矽基底。然而本發明並不限定=此’在本發明之其它實施例中，基底32亦可以為一矽覆絕緣（silicon-on-insulator, SOI)基底。為了方便說Please refer to FIGS. 6 to 10, which are schematic cross-sectional views of the nitride read-only memory fabricated by the present invention. As shown in FIG. 6, the nitride read-only memory system of the present invention is fabricated on the surface of the substrate 32 of a semiconductor wafer 30, and the surface of the substrate 32 defines a memory region and a peripheral region. In the preferred embodiment of the present invention, the 'substrate 32' is a P-type silicon substrate. However, the present invention is not limited to this. In other embodiments of the present invention, the substrate 32 may also be a silicon-on-insulator (SOI) substrate. For convenience

=i f明之重點，圖六至圖十只顯示本發明氮化物唯讀記 ΐ声"己憶區之剖面。如圖六所示，首先於基底3 2表面形成 ⑽L度約為150至2 5 0埃（angstrom，又）的0Ν0介電層39， "電層3 9係由一厚度約為5 〇至i 5 〇埃之底氧化層3 4、一 :又約為2 0至1 5 0埃之氮化矽層3 6以及一厚度約為5 〇至1 5 〇埃之上氧化層38所組成。接下來進行一調整週邊區元件啟始電壓（thresh〇ldThe important point of the figure is that Figures 6 to 10 only show the cross-sections of the slang " memory area of the nitride of the present invention. As shown in FIG. 6, first, a 0N dielectric layer 39 having an L degree of about 150 to 250 angstroms (angstrom, again) is formed on the surface of the substrate 32, and the electrical layer 39 is formed by a thickness of about 50 to i 50 Angstrom bottom oxide layer 34, one: a silicon nitride layer 36 of about 20 to 150 Angstroms, and an oxide layer 38 having a thickness of about 50 to 150 Angstroms. The next step is to adjust the starting voltage of components in the peripheral area.

5112S5- 補充五、發明說明（5) volt age)之步驟，首先於記憶區内之〇N〇介電層39表面形成一遮罩（未顯示），並進行一離子佈植製程，以調整未被遮罩所覆蓋之基底32中之摻質濃度，最後去除該遮罩。隨後如圖七所示，於0N0介電層3 9表面形成一光阻層4〇，並進行一黃光製程以及蝕刻製程，使光阻層4〇形成一圖案，用來定義位元線的位置。然後利用光阻層40作為一位元線遮罩，縱向排列於0Ν0介電層39表面。接著進行一離子佈 f製程42’利用砷離子（arsenic，As)或其他Ν型摻質對未層4〇覆蓋之基底32進行摻雜，以於基底32中形成複數個N型摻雜之摻雜i 44，作^己憶體之埋藏式位元線離二ϋ bl七1 lne)。在離子佈植製程42中，一典型的珅 )^ Γ旦為1X, 1〇丨5至以1〇16原子每平方公分㈤产约里約為Μ至SOKeV，較佳為50KeV。接著進行一飢度約為δ〇ο至loocrc之快速火饮底3 2中夕换所 ^ U火製程，以活化植入於基底32中之摻質。、隨後再將光阻層4()完全去除。如圖八所示，再於半導體矽層46，作為字元線。此字元二^表面沉積一摻雜多晶 3〇表面，並與摻雜區44形成—幾^向排列於半導體晶片係’如圖九所示。. 垂直之上下重疊排列關5112S5- Supplement V. Description of the invention (5) volt age). First, a mask (not shown) is formed on the surface of the 0N0 dielectric layer 39 in the memory area, and an ion implantation process is performed to adjust the voltage. The dopant concentration in the substrate 32 covered by the mask is finally removed. Subsequently, as shown in FIG. 7, a photoresist layer 40 is formed on the surface of the 0N0 dielectric layer 39, and a yellow light process and an etching process are performed to form a pattern on the photoresist layer 40 to define a bit line. position. Then, the photoresist layer 40 is used as a one-bit line mask, and is vertically arranged on the surface of the ON0 dielectric layer 39. Next, an ion cloth process 42 ′ is performed to use arsenic (As) or other N-type dopants to dope the substrate 32 not covered by the layer 40 to form a plurality of N-type doped dopants in the substrate 32. Miscellaneous i. 44. It is the buried bit line of ^ Ji Yi body. In the ion implantation process 42, a typical)) is 1X, 10 to 5 to 1016 atoms per square centimeter, and the production yield is about M to SOKeV, preferably 50KeV. Then, a rapid fire process with a hunger degree of about δ〇ο to loocrc is performed. The U fire process is used to activate the dopants implanted in the substrate 32. Then, the photoresist layer 4 () is completely removed. As shown in FIG. 8, the semiconductor silicon layer 46 is used as a word line. A doped polycrystalline 30 surface is deposited on the surface of this character, and is formed with the doped region 44—arranged in a semiconductor wafer system 'as shown in FIG. . Vertically stacked up and down

最後如圖十所示，圖十為、” L ?夫宛於基底32表面形成一由氡；：i:剖線a_a之剖面 (未頌不），並對該犧牲層進行—:物所構成之犧牲層 '飿刻製程’直至基底32 511252 五、發明說明（6) 表面，以於且各該字元線之周圍側壁形成— (spacer) 47。最後於基底32表面依序形成:㈣壁子物所構成之阻絕層48以及一由氮矽化合物田/乳1G σ 5〇。保護層5。係用來避免該氮化物唯讀記二: 後續製程中受紫外線（uv light)照射或產生電壞^ (Plasma damage)，而形成於保護層50與該氮化1"物貝唯^記憶體之間的阻絕層48，則是用來防止保護層5 〇盥氮化胃石夕層 36相接觸，以避免後續在化學沉積製程或蝕刻^程中受到紫外線照射所產生之部份的游離電子穿過保護層5〇而進入 ΟΝΟ介電層39中，進而影響該氮化物唯讀記憶體（NR〇M^ 電性。相較於習知之氮化物唯讀記憶體製作方法，本發明係利用一化學氣相沉積方式形成一阻絕層，以隔離該保護層與該氮化物唯讀記憶體之0N0介電層，由於該保護層可能在後續的化學沉積製程或蝕刻製程中受到紫外線照"射而產生之游離電子，因此該阻絕層可以阻止該保護層内之游離電子進入該0Ν0介電層，達到避免該氮化物唯讀記憶體於製私中被電荷充電的效果，進而提高該氮化物唯讀記憶體之持耐性（endurance)以及可靠度（reliability)。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵蓋範圍。Finally, as shown in Fig. 10, Fig. 10 is, "L? Fuwan formed a yoke on the surface of the substrate 32 :: i: the cross-section of the line a_a (not sung), and the sacrificial layer is made of-: The sacrificial layer 'engraving process' up to the base 32 511252 V. Description of the invention (6) The surface is formed by the side walls around each of the word lines-(spacer) 47. Finally, the surface of the base 32 is sequentially formed: the wall The barrier layer 48 composed of the daughter substance and a nitrogen-silicon compound field / milk 1G σ 50. The protective layer 5. It is used to prevent the nitride. Read only note 2: UV light is irradiated or generated in subsequent processes. Electrical damage (Plasma damage), and the barrier layer 48 formed between the protective layer 50 and the nitride 1 " memory is used to prevent the protective layer 50. nitride gastrolith layer 36 Contact to prevent the part of the free electrons generated by the ultraviolet irradiation during the chemical deposition process or etching process from passing through the protective layer 50 and entering the ONO dielectric layer 39, thereby affecting the nitride read-only memory (NR〇M ^ Electrical properties. Compared with the conventional method of making nitride read-only memory, this The Ming Department used a chemical vapor deposition method to form a barrier layer to isolate the protective layer from the 0N0 dielectric layer of the nitride read-only memory. The protective layer may be exposed to ultraviolet rays during subsequent chemical deposition processes or etching processes. The free electrons generated by the photo ", so the blocking layer can prevent the free electrons in the protective layer from entering the ON0 dielectric layer, to prevent the nitride read-only memory from being charged by the charge in the private system, and then The endurance and reliability of the nitride read-only memory are improved. The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention are It should be covered by the invention patent.

511252 圖式簡單說明圖示之簡單說明圖一至圖五為習知製作一氮化物唯讀記憶體的方法示意圖。圖六至圖十為本發明製作一氮化物唯讀記憶體的方法示意圖。圖示之符號說明 12 矽基底 14 底氧化層 16 氮化矽層 18 上氧化層' 19 ΟΝΟ介電層 20 光阻層 22 離子佈植製程 24 摻雜區 (位元線） 26 場氧化層 27 側壁子 28 摻雜多晶石夕層 (字元線） 29 保護層 30 半導體晶片 32 基底 34 底氧化層 36 氮化矽層 38 上氧化層 39 0Ν0介電層 40 光阻層 (位元絲 ‘遮罩 ) 42 離子佈植製程 44 摻雜區 (位元综 46 摻雜多晶矽層 (字元線） 47 側壁子 48 阻絕層 5 0 保護層511252 Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 5 are schematic diagrams of the conventional method for making a nitride read-only memory. 6 to 10 are schematic diagrams of a method for manufacturing a nitride read-only memory according to the present invention. Explanation of symbols in the figure 12 silicon substrate 14 bottom oxide layer 16 silicon nitride layer 18 upper oxide layer '19 ΝΟ dielectric layer 20 photoresist layer 22 ion implantation process 24 doped region (bit line) 26 field oxide layer 27 Side wall 28 Doped polysilicon layer (word line) 29 Protective layer 30 Semiconductor wafer 32 Substrate 34 Bottom oxide layer 36 Silicon nitride layer 38 Upper oxide layer 39 0N0 dielectric layer 40 Photoresistive layer (bit wire ' Masking) 42 Ion implantation process 44 Doped region (bit synthesis 46 Doped polycrystalline silicon layer (word line) 47 Side wall 48 Barrier layer 5 0 Protective layer

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Claims

511252 六、申請專利範圍 1· 一種用於氮化物唯讀記憶體（nitride read only memory, NR0M)防止電荷充電的製作方法，該方法包含有下列步驟：提供一基底，且該基底表面包含有一記憶區以及一週邊區；於該基底表面形成一由一底氧化（bottom oxide)層、一氮化石夕層以及一上氧化（top oxide)層所構成之 ONO(oxide-nitride-oxide)層；記憶區内之該0N0層表面形成複數條縱向排列之罩（bit line mask); 一第一離子佈植製程，以於未被該位元線遮罩所基底中形成複數條埋藏位元線（buried bit 該位元線遮罩； 0N0層表面上形成複數條線幾近垂直之字元線；、"列並與該複數條基底表面形成一犧牲層，，，直至該基底表面，以於^犧牲層進行一回側壁子（s p a c e r);以及予几線之周圍側基底表面依序形成-随絕層以及—保護層。請專利範圍第1項之方法，盆元線遮罩之前，尚包含古中該方法於形成該有下列步驟· 記憶區内之該0N0層表s犯二、〆鄉· 间形成一遮罩；於該位元線遮進行覆蓋之該 line); 去除於該埋藏位元於該蝕刻製程壁形成一於該 2. 如申複數條位至少於該511252 6. Scope of patent application 1. A manufacturing method for preventing charge charging of nitride read only memory (NR0M), the method includes the following steps: a substrate is provided, and the surface of the substrate contains a memory Area and a peripheral area; an ONO (oxide-nitride-oxide) layer consisting of a bottom oxide layer, a nitride layer and a top oxide layer is formed on the surface of the substrate; memory A plurality of bit line masks are formed on the surface of the 0N0 layer in the area; a first ion implantation process is performed to form a plurality of buried bit lines in the substrate not covered by the bit line. bit The bit line mask; a plurality of lines forming nearly vertical zigzag lines on the surface of the 0N0 layer; " juxtaposed with the surface of the plurality of substrates to form a sacrificial layer, until the surface of the substrate, ^ The sacrificial layer is subjected to a spacer; and the base surface of the surrounding sides of the lines is sequentially formed-with the insulation layer and-the protective layer. Please use the method in the first scope of the patent, before the basin element line is masked, Containing the ancient method, the method has the following steps: forming a mask between the 0N0 layer in the memory area and the village; forming a mask; covering the bit line to cover the line); removing in the burial A bit is formed on the wall of the etching process in the 2. If multiple bits are less than the

511252 六、申請專利範圍進行一第二離子佈植製程，以調整未被該遮罩所覆蓋之該基底中之摻質濃度；以及去除該遮罩。 1 如申請專利範圍第1項之方法，其中該底氧化層厚度係"於5 0至1 5 0埃（a n g s t r 〇 m，A )，該氮化石夕層厚度係介於 2 0至1 5 0埃，而該上氧化層厚度係介於5 0至1 5 0埃。 4 ·如申請專利範圍第1項之方法，其中該位元線遮罩係由光阻所構成。 r • 如申請專利範圍第1項之方法，其中該基底係為一矽底1 或—石夕覆絕緣（silicon-on-insulator，SOI )基底。 g • 如申請專利範圍第1項之方法，其中該犧牲層係由氮矽化合物所構成。避如t請專利範圍第1項之方法.，其中該保護層係用來 (uv ^氮化物唯讀記憶體（NR0M)於一後續製程中受紫外線 1 lght)照射或產生電漿損壞（pi asma damage ) 〇 ί申請專利範圍第7項之方法，其中該保護層係由氮夕化合物所構成。511252 6. Scope of patent application Perform a second ion implantation process to adjust the dopant concentration in the substrate not covered by the mask; and remove the mask. 1 The method according to item 1 of the scope of patent application, wherein the thickness of the bottom oxide layer is between 50 and 150 angstroms (angstrom), and the thickness of the nitrided layer is between 20 and 15 The thickness of the upper oxide layer is between 50 and 150 angstroms. 4 · The method according to item 1 of the patent application range, wherein the bit line mask is composed of a photoresist. r • The method according to item 1 of the patent application scope, wherein the substrate is a silicon substrate 1 or a silicon-on-insulator (SOI) substrate. g • The method according to item 1 of the patent application, wherein the sacrificial layer is composed of a silicon nitride compound. Avoid the method described in item 1 of the patent scope, wherein the protective layer is used to (uv ^ nitride read-only memory (NR0M) in a subsequent process exposed to UV light 1 lght) or to generate plasma damage (pi asma damage) The method of claim 7 in which the protective layer is composed of a nitrogen compound.

第13頁 511252 六、申請專利範圍 9. 如申請專利範圍第1項之方法，其中該阻絕層用來避免該保護層與該氮化矽層接觸導致該氮化物唯讀記憶體於製程中被電荷充電，而影響該氮化物唯讀記憶體（NROM)的電性。 1 0.如申請專利範圍第9項之方法，其中該阻絕層係由矽氧化合物所構成。Page 13 511252 6. Application for Patent Scope 9. The method of the first scope of patent application, wherein the barrier layer is used to avoid the contact between the protective layer and the silicon nitride layer, which may cause the nitride read-only memory to be used in the manufacturing process. The charge charges and affects the electrical properties of the nitride read-only memory (NROM). 10. The method according to item 9 of the patent application, wherein the barrier layer is composed of a silicon oxide compound.

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