507511 經濟部智慧財產局員工消費合作社印製 五、發明説明（ 發明領域：本發明係有關於-種增層電路板之製程 於一種用於製作增層電職之薄核心板，=有關 之形成係利用一其表面覆有導 ：：该核心板 層衣作禮導通盲孔’以提供導電相之連接。 發明背景： 動電====树彻知之趨勢，如行 動以手“月甸、手提錄放影機或個人數位助理 (pe細al d_ assistants)等。這些電子產品之製作因此 需要使用比以前更小、更薄的電路板及電子元件。产著此 縮小化之趨勢，各種不同功能之半導體元件鎮歲在:電路 板上則有朝更高密度之需求。因此，對應用上述更薄且言 佈線密度之多層電路板於電子產品來說，電路板之製程= 設計則將面臨更高之挑戰。 ~ 在電路板製造業界，低成本、高可靠度及高佈線密度 -直是所追求之目標。為達目標，於是發展出_種增= •術（build-up)。所謂的增層技術基本上是指在一核:二表 面上交互堆疊多層絕緣層及導電層，再於絕緣層製作電^ 導通孔（via holes)以提供各導電層間之電性連接:然 而，增層電路板之數目可依實際業界情況之所需堆疊超過 10或20層之多。至今，增層電路板之技術已製造出許多裝 載有各式電子元件之多層電路板應用於各種不同之商業產 品。 (請先閱讀^面之注意事項再填寫本頁) 、11 本紙張尺度適用中國國家標準（CNS ) A4規格（210X2$公釐） 經濟部智慧財產局員工消費合作社印製 A7 s--_---BT^_ 五、發明説明（>) - ^-~— 通常’製造增層電路板需__單、雙面板或多層板 乍為核心基板（core subst論）或簡稱核心板。圖—及圖 二則為習知弱多層電路板之示意圖。請參關—，_择 層多層電路板包含-核心基板朗及兩增層結構1〇2。曰 7亥核‘、基板101包含若干已圖案化之電路層1〇3，以及位於 任兩電路層103間的絕緣層104。一導電通孔105則作為電 路層1〇3間的電性内連接。而該增層結獅2亦包含電路層 106與絕緣層107之多層，然而，增層結構⑽之電路層^ 與，緣層1〇7較核心基板101之電路層1〇3與絕緣層⑽通常 要薄的S。该增層結構1〇2之電路層1〇6間則以導電通孔 i〇uvias) ^乍電性連接。以圖一來說，核心、基板ι〇ι為一 多層電路板（亦即六層），而增層結構1〇2則為上下各 兩層。 、，圖二所示為另一習知增層多層電路板之示意圖，其中 -增層多層電路板200包含-電路板2Q1作為核^基板及 增層結構202。該電路板观包含兩圖案化電路層2〇3及盆 間之絕緣層204。-導電通孔2〇5則作為電路層2〇3間的電 性連接。而該增層結構202亦包含電路層2〇6與絕緣芦 2〇7 ’ _，增層_2()2之電路制6與絕緣層2贿電ς 板201之電路層203與絕緣層2〇備常要薄的多。該增層結 構202之電路層206間則以通孔2〇8 (*)作電性連^二 以圖二來說，電路板201為一多層電路板（亦即兩層）， 而增層結構202在電路板201之上下兩面則各有兩增層，如 此則形成一六層電路板結構。 〇 本紙張尺度適财_家榡 (請先閲諫背面之注意事項再填寫本頁) ΙΦ.507511 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Field of Invention (Field of the Invention: The present invention relates to the process of a type of layered circuit board in a thin core board for the production of layered electrical posts, = related formation It is based on a surface covered with a guide: the core board layer is used as a rite blind hole to provide a conductive phase connection. BACKGROUND OF THE INVENTION: Dynamic electricity ==== Trees fully understand the trend, such as action by hand "Yuedian, Hand-held video recorders or personal digital assistants, etc. The production of these electronic products therefore requires smaller and thinner circuit boards and electronic components than before. With this trend of shrinking, various functions The semiconductor components of this year are: the demand for higher density on circuit boards. Therefore, for the application of the above-mentioned thinner multilayer wiring boards with electronic wiring, the process of circuit board = design will face more High challenges. ~ In the circuit board manufacturing industry, low cost, high reliability, and high wiring density-have always been the goals pursued. In order to achieve the goals, we have developed _ species increase = • build-up. So The so-called layer-increasing technology basically means that one layer of cores: two layers of insulating layers and conductive layers are alternately stacked on the two surfaces, and electrical holes are formed on the insulating layers to provide electrical connections between the conductive layers: however, The number of layered circuit boards can be stacked more than 10 or 20 layers according to the actual industry conditions. So far, the technology of layered circuit boards has produced many multilayer circuit boards loaded with various electronic components and applied to various different Commercial products (please read the precautions before filling in this page), 11 This paper size applies the Chinese National Standard (CNS) A4 specification (210X2 $ mm) Printed by A7 s- -_--- BT ^ _ V. Description of the invention (>)-^-~ — Usually '__ single, double-sided or multi-layer board is the core substrate (core subst theory) or core for short. Board. Figure-and Figure 2 are the schematic diagrams of the conventional weak multi-layer circuit boards. Please refer to the related chapters.-Selecting the multilayer circuit board includes-the core substrate Lang and the two layered structure 102. Said "7 Hai core", substrate 101 includes a number of patterned circuit layers 103, and An insulating layer 104 between any two circuit layers 103. A conductive via 105 serves as an electrical interconnection between circuit layers 103. The layered junction 2 also includes multiple layers of a circuit layer 106 and an insulating layer 107. However, the circuit layer of the build-up structure ^ and the edge layer 107 are generally thinner than the circuit layer 103 and the insulation layer 核心 of the core substrate 101. The circuit layer 10 of the build-up structure 102 Between them are conductive vias (via vias (via vias)) ^ At first, they are electrically connected. As shown in Figure 1, the core and substrate are a multilayer circuit board (that is, six layers), and the build-up structure is 102 There are two layers above and below. Figure 2 shows a schematic diagram of another conventional build-up multilayer circuit board, where the build-up multilayer circuit board 200 includes a circuit board 2Q1 as a core substrate and a build-up structure 202. The circuit board 28 includes two patterned circuit layers 203 and an insulating layer 204 between the basins. -The conductive vias 205 are used as electrical connections between the circuit layers 203. The layer-increasing structure 202 also includes a circuit layer 206 and an insulating layer 207 ′, a circuit layer 6 of the layer _2 () 2 and an insulating layer 2 and a circuit layer 203 and an insulating layer 2 of the board 201. 〇 Preparations are often much thinner. The circuit layers 206 of the build-up structure 202 are electrically connected with through-holes 208 (*). In terms of FIG. 2, the circuit board 201 is a multi-layer circuit board (ie, two layers). The layer structure 202 has two additional layers each on the upper and lower sides of the circuit board 201, thus forming a six-layer circuit board structure. 〇 This paper is suitable for financial use_Home 榡 (Please read the notes on the back of the book before filling out this page) ΙΦ.
、1T f 川7511 經濟部智慧財產局員工消費合作社印製 A7 五、發明説明（)） 為達到更可靠的導通孔設計於多層電路板之製程，圖 二顯不業界常見的三種導通孔製程。圖三A所示為一俗稱 電鍍導通孔（plated through hole，PTH)之示意圖。其中通 孔之開口延伸穿越絕緣層301及覆於其表面之電路層3〇2及 303，而由電鍍金屬304構成之導電層則形成於該導S通孔之 側壁。在電鍍完成後，再填充一導電或不導電填充材3〇5 填滿殘留空隙，以保證導通孔之可靠度。 圖三B所示為另一種通孔形式，即所謂盲孔（blmd via)，其中目孔之開口延伸至絕緣層3⑽内部，但未穿透 電路層307。在電鍍層308沈積之後，填充一導電或不導電 材309於凹陷處，以為後續製程提供適當平坦度。 圖三C所示為第三種通孔形式，其中盲孔之開口延伸 穿越絕緣層31〇，但亦未穿透電路層扣。在通孔填入導電 材313之後，再形成電路層312。 兒 上述三種習知技術皆需填入填充材於通孔之空隙内。 然而在通孔直徑低於〇·〇5腿以下時，其製程將變得難以 實施。因此-般業界在大量製造生產時，上述三種製程必 須於通孔直徑在〇·75 mm以上時實施，使製造的可行性容 易許多。如此情況之了，核心基板便會因通孔之製程技= 限制，而無法達到更高佈線密度之要求。 何 因此，本發明所要揭露解決的問題，即是提供更言 線密度之核心基板，而形成一更薄及更高佈 = 多層電路板。 ·又層 本纸張尺度適用中國國豕標準（CNS ) A4規格（21〇χ^97公酱） (請先閲讀^-面之注意事項再填寫本頁), 1T f Chuan 7511 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the Invention ()) In order to achieve a more reliable process of designing vias in multilayer circuit boards, Figure 2 shows three types of via processes that are not common in the industry. FIG. 3A is a schematic diagram commonly known as a plated through hole (PTH). The opening of the through hole extends through the insulating layer 301 and the circuit layers 302 and 303 covering the surface, and a conductive layer made of a plated metal 304 is formed on the side wall of the through S hole. After the electroplating is completed, a conductive or non-conductive filler material 305 is filled to fill the remaining gaps to ensure the reliability of the vias. Figure 3B shows another form of through-hole, the so-called blind via (blmd via), in which the opening of the eyelet extends to the inside of the insulating layer 3, but does not penetrate the circuit layer 307. After the plating layer 308 is deposited, a conductive or non-conductive material 309 is filled in the recess to provide proper flatness for subsequent processes. Figure 3C shows a third type of through-hole, in which the opening of the blind hole extends through the insulation layer 31, but does not penetrate the circuit layer buckle. After the through hole is filled with the conductive material 313, the circuit layer 312 is formed. All three of the above-mentioned conventional techniques need to be filled in the gaps of the filling materials in the through holes. However, when the diameter of the through hole is less than 0.05 leg, the process becomes difficult to implement. Therefore, when the industry generally mass-produces, the above three processes must be implemented when the diameter of the through hole is more than 0.75 mm, making the manufacturing feasibility much easier. In this case, the core substrate cannot meet the requirements of higher wiring density because of the process technology of the vias. Therefore, the problem to be solved by the present invention is to provide a core substrate with a more linear density, so as to form a thinner and higher-layer multi-layer circuit board. · Layered This paper size is in accordance with China National Standard (CNS) A4 specification (21〇χ ^ 97 公 酱) (Please read the ^ -side precautions before filling this page)
507511 A7 B7 五 經濟部智慧財產局員工消費合作社印製 、發明説明（^) 發明概述： 本毛明的主要目的為提供插田^ γ & 薄核心板之製法，尤其是二=製:::電路板之 線密度之增層多層電路板。__〜板製造缚且高佈 本發明的另一目的為提供—種用於製作增層電路板之 絕二二㈡:核心板製程包含使用附有導電薄層之 、巴、，彖層’且该導電層之預定位置形成開口，其 =絕緣層中之處。再沈積—導電層覆蓋通孔。在 層與導電層圖案化之後，便形成所述之核心基板〜缚 路板目Γ ’本發明係提供一種用於製作増層電 用孕右、二‘法，本發明之較佳實施步驟係包含利 之絕緣層，製作—開口於該絕緣層之預 疋置，也就是後績盲孔形成之處。沈積一導 於所述盲孔開口上形成導通盲孔結構；而在 ^ 2 導電層圖案化之後，即製造出核心板。然後再完成 層結構於該核心板之至少一面上，則可製造出高曰 增層電路板。 非度之 為了使貴審查委員對本發明之目的、特徵及功致 更進-步的瞭解與期，魏合圖式詳加_如後。有 圖式之簡單說明： 圖一係習知技術中增層多層電路板結構之示意圖 圖二係另-習知技術巾增層多層電路板結構之 意 I----*---^---------、玎------^9— (請先W1#.背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ$97公釐） 507511 A7 B7 五、發明説明（f ) 圖三A係習知技術電鍍通孔結構之示意圖。 圖二B係習知技術凹陷處填有填充材之亡 圖。 ㈣孔結構示意 圖二C係習知技術完全填有導電材材之畜 圖。 —孔結構示意 圖四Α係附有凹陷處之盲孔之核心板結構之八土 圖四B係另一形式全填滿之盲孔之核心示意 圖 圖 圖 五A至五F係本發明實施例製作薄核心板製程之示咅 圖六A係本發明實施例利用一薄核心層形成增 之不意圖。 圖六B係本發明另一實施例利用一薄核心層形成.增層電 路板之不意圖。 層電路板 經濟部智慧財產局員工消費合作社印製 圖號說明： 1，10，13 104, 107, 301，306, 310, 403, 503-絕緣層 2, 11-導電薄層 ' 3_開口 4-盲孔開口 5, 6, 7, 8, 307, 405, 505-導電層 14, 103, 106, 203, 206, 302, 303, 307, 312, 313, 401，402, 501， 502_電路層 9, 102, 202•增層結構 本紙張尺度適用中國國家標準（CNS ) A4規格（210Xg97公釐） (請先閱讒背面之注意事項再填寫本頁)507511 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the description of the invention (^) Summary of the invention: The main purpose of this Maoming is to provide cutting methods ^ γ & thin core board manufacturing method, especially the two = system :: : Multilayer circuit boards with increased linear density of circuit boards. __ ~ Board manufacturing and high cloth Another object of the present invention is to provide a kind of second and second board for making layered circuit boards: the core board manufacturing process includes the use of conductive, thin, and thin layers, and An opening is formed at a predetermined position of the conductive layer, which is a place in the insulating layer. Redeposition—the conductive layer covers the via. After the layer and the conductive layer are patterned, the core substrate described above is formed. The present invention provides a method for making the right-layer and two-layer electrical methods. The preferred implementation steps of the present invention are: Contains a good insulating layer, made—open in the pre-set of the insulating layer, which is where the post-blind hole is formed. A conductive layer is formed by depositing on the blind hole opening; and after the conductive layer is patterned, the core board is manufactured. A layer structure is then completed on at least one side of the core board, and a high-layer build-up circuit board can be manufactured. Fei Duzhi In order for your review committee to have a further understanding and expectation of the purpose, features, and functions of the present invention, Wei He plans to add details _ as follows. There are simple explanations of the drawings: Figure 1 is a schematic diagram of the structure of the multilayer circuit board in the conventional technology. Figure 2 is another meaning of the structure of the multilayer circuit board in the conventional technology. I ---- * --- ^- --------, 玎 ------ ^ 9— (please note on the back of W1 #. Before filling out this page) This paper size applies to China National Standard (CNS) Α4 specification (210 × $ 97) (Centi) 507511 A7 B7 V. Description of the Invention (f) Figure 3 is a schematic diagram of the plating through-hole structure of the conventional technology of A series. Figure 2B is a diagram showing the filling material filled with depressions in the conventional technology. Schematic diagram of the countersinking structure. Figure 2 is a picture of the conventional technology completely filled with conductive materials. —Schematic diagram of the hole structure 4A is the eighth soil of the core plate structure with the blind hole in the depression Figure 4B is the schematic diagram of the core of another form of fully filled blind hole Figures 5A to 5F are made according to the embodiment of the present invention The thin core plate manufacturing process is shown in FIG. 6A. This embodiment of the present invention utilizes a thin core layer to form a layer. Fig. 6B shows another embodiment of the present invention, which uses a thin core layer to form a circuit board. Printed circuit board printed by the consumer co-operatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: 1, 10, 13 104, 107, 301, 306, 310, 403, 503-insulating layer 2, 11-conductive thin layer 3_opening 4 -Blind hole openings 5, 6, 7, 8, 307, 405, 505-Conductive layers 14, 103, 106, 203, 206, 302, 303, 307, 312, 313, 401, 402, 501, 502_Circuit layer 9, 102, 202 • Additional structure This paper size is applicable to Chinese National Standard (CNS) A4 specification (210Xg97mm) (Please read the precautions on the back before filling this page)
507511 A7 _____B7___ 五、發明説明（) 101,400, 500-核心基板 100, 200, 60(^ 700-增層多層電路板· 105,205-導通孔（throughhole) 108,208-導孔（via) 201,202-電路板 304-電鍍金屬 305, 309-填充材 313-導電材 404-盲孔 詳細說明： 為了使本發明之目的、特徵及功效，能更進一步的暸 解與認同，茲配合詳細揭露、申請專利範圍及圖式詳加説 明如后。當然，本發明可以多種形式實施之，接下所述僅 是本發明之較佳實施例，而非限制本發明之範圍，只要是 依附在本發明之精神下之實施例，皆屬於本發明之範圍。 本發明係提出-種用於製作增層電路板之薄核心板之 製法，利用該核心板可製作出薄且具高佈線密度之多層電 路板。本發明之圖示僅為簡單說明，並非依實際尺寸描 繪，亦即未反應出多層電路基板中，各層次之實際尺寸與 特色’先予敛明。 本發明之實施例所述之薄核心板係為一具兩導電層之 電路板，該電路板係、有電性導通盲孔之設計。如圖四A所 不為〃型之核％基板400，其為附有盲孔設計之兩層電 氏張尺度適用中國國家標準（___ (讀先閱请背面之注意事項再填寫本頁) 訂 m 經濟部智慧財產局員工消費合作社印製 -i^n DU/：)丄丄 五 、發明説明（， A7 B7 經濟部智慧財產局員工消費合作社印製 路板，其中有兩電路層4Q1、搬分別設在絕緣層403之上 下兩側’且覆蓋有導電層405之言孔4G4作為兩電路層 4〇1 4〇2之電性連接。然而，通孔的凹陷處並未被導電声 4〇5材枓所完全填滿。如圖_所補為另—形式之核心基 板500 ’其亦為附有盲孔設計之兩層電路板，其中有兩電 路層501、502分別設在絕緣層5〇3之上下兩側，盲孔的開 口 504則被導電層5〇5材料所完全填滿。 咬a圖五所示為前述之核心基板4〇〇或500之製程示意圖。 明苓閱圖五A，先提供一有機絕緣層丨，其鍵結有上下兩導 ，薄層2，該絕緣層丨之較佳厚度為⑽卜〇2麵之間，更 佳者為_〜0.06 mm之間。所述之有機絕緣層m由有機 材質、、纖維強化（flber_remf〇rced)有機材質或顆粒強化 (partlde-remf0rced)有基材質等所構成，如環氧樹脂 (epoxy resin )' 聚乙醯胺（p〇iyimide )、雙順丁 稀二酸 酿亞胺/三氮牌（b馳aleimide咖跡5_ )樹脂、氰醋 (cyanate ester )、p〇iybenzocyclobutane 或其玻璃纖維 (glass fiber)之複合材料等。當然，有機絕緣層丨亦可由 多層不同材質所疊合而成。而所述之導電薄層2可為金屬 材質，如金、銀、銅、銘等，或導電性高分子（c〇nductive polymer)等；該導電薄膜2較佳為銅材質，而較佳厚度則 為0.008〜0.015 mm之間。導電薄層2亦可依所需進行化學 或物理蝕刻使之變薄，因較薄之導電層可在一般蝕刻電路 形成技術中，更容易形成緻密電路圖案（fmner ci=mt pattern)。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 公董） (請先閱議背面之注意事項再填寫本頁} i^w.507511 A7 _____B7___ 5. Description of the invention () 101,400, 500-core substrate 100, 200, 60 (^ 700-multilayer circuit board 105,205-throughhole 108,208-via 201,202-circuit board 304- Electroplated metal 305, 309-filling material 313-conductive material 404-blind hole Detailed description: In order to make the purpose, features and effects of the present invention better understand and agree with, we will cooperate with the detailed disclosure, patent application scope and detailed drawings. The explanation is as follows. Of course, the present invention can be implemented in various forms. The following description is only a preferred embodiment of the present invention, rather than limiting the scope of the present invention, as long as it is an embodiment attached to the spirit of the present invention, All belong to the scope of the present invention. The present invention proposes a method for manufacturing a thin core board for a build-up circuit board, and the core board can be used to make a thin and high wiring density multi-layer circuit board. It is only a simple description, and is not drawn according to actual size, that is, the actual size and characteristics of each layer in the multilayer circuit substrate are not reflected. The thin core board system described in the embodiment of the present invention It is a circuit board with two conductive layers. The circuit board is designed with electrically conductive blind holes. As shown in Figure 4A, the core% substrate 400 is not a 〃 type, which is a two-layer electrical circuit with a blind hole design. The Zhang scale is applicable to China's national standards (___ (read first, please read the notes on the back, and then fill out this page) Order m Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs-i ^ n DU / :) , A7 B7 The printed circuit board is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. There are two circuit layers 4Q1, which are located on the upper and lower sides of the insulating layer 403, and are covered with a conductive layer 405. The holes 4G4 are two circuit layers 4 〇1 4〇2 electrical connection. However, the recess of the through hole is not completely filled with conductive sound 405 material. As shown in Figure _ supplemented by another form of core substrate 500 'It is also attached A two-layer circuit board with a blind hole design, of which two circuit layers 501, 502 are respectively located above and below the insulating layer 503, and the opening 504 of the blind hole is completely filled by the conductive layer 505 material. a Figure 5 shows a schematic diagram of the aforementioned core substrate 400 or 500. Mingling read Figure 5A First, an organic insulating layer 丨 is provided, which is bonded with two upper and lower conductors, and a thin layer 2. The preferred thickness of the insulating layer 丨 is between ⑽ 〇2 surface, and more preferably between _ ~ 0.06 mm. The organic insulating layer m is composed of an organic material, a fiber-reinforced (flber_remf〇rced) organic material, or a particle-reinforced (partlde-remf0rced) base material, such as epoxy resin 'polyacetamide (p. iyimide), bismaleic acid / imide / triazine resin (bachialeide 5_) resin, cyanate ester, poiybenzocyclobutane or its glass fiber composite materials. Of course, the organic insulation layer 丨 can also be formed by stacking multiple layers of different materials. The conductive thin layer 2 may be made of a metal material, such as gold, silver, copper, copper, etc., or a conductive polymer (conductive polymer). The conductive thin film 2 is preferably made of copper, and has a preferable thickness. It is between 0.008 and 0.015 mm. The conductive thin layer 2 can also be thinned by chemical or physical etching as required, because a thinner conductive layer can more easily form a dense circuit pattern (fmner ci = mt pattern) in general etching circuit formation technology. This paper size applies to China National Standard (CNS) A4 specification (210X public director) (Please read the precautions on the back before filling out this page} i ^ w.
、1T -—ϋ mama n n 507511 A7 '-------- B7 五、發明説明（g ^ ^~ --~- 接著如圖五B所示’以雷射***磨除〇黯她聰） 或_技術移除部分導電薄層2，在導電薄層2上形成開口 3 ;該開口3之較佳直徑為咖叫G _之間，更佳為_ 〜0.04 mm之間。 接著可以雷射***磨除、化學侧或(細⑷ 蝕刻等技術形成盲孔開口 4於該絕緣層β，如圖五⑽ 示。然而在此情形之下難意的是，若絕緣層k材質為 光顯像性樹脂（_〇1mageabieresm)，則無法藉習知微 衫技術形成g孔開口4，這是因為紫外光（w)會被導電 薄層2所阻擋住（blocked)。在形成盲孔開口4之後，再對 目孔内進行清潔步驟’特別是盲孔内之導電薄層2之表 面，易受殘渣污染，接著亦可對盲孔内及盲孔外之表面進 行物理或化學粗化，以增進黏著性（adhesi〇nproperty)。 沈積一如圖五D及圖五E中之導電層5或圖五F中之導電 層ό ’覆蓋導電薄層2和/或盲孔開口 4内，其可以電鍍 (electroplating)、無電錢（electroless plating)、物理氣 相沈積（PVD)或化學氣相沈積（CVD)等方式形成。其 中銅電鍍（copper plating)應是在本發明實施成本考量下 之較佳選擇。另外，相對於圖五F之導電層6完全填充於盲 孔開口4内’圖五D及圖五E之導電層5則只有填充部分盲孔 開口4而仍具有未填滿之凹陷（recess)。當然，當孔徑小 於0.05 mm時，以電鍍銅將通孔開口完全填滿將較容易達 成，亦是對製作堆疊通孔（stacked vias)較有助益。在以 雷射***磨除（俗稱雷射直接圖案化方法）、化學或電漿 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χψ公釐） (請先閲请背面之注意事項再填寫本頁) 衣· 經濟部智慧財產局員工消費合作社印製 507511 、發明説明（y) 蝕刻技術形成圖幼及圖邱中之電路層7 ( 之電酬 〇二 Γ: 路層7、8之較佳厚度可在麵〜 A ° ΐ 心基板伽、5QQ (分騎於圖四 A、圖四B中）之製作於焉完成。 當然’圖五〇及圖邱之導電層5因只有填充部分盲孔 開口 4而仍具有未填滿之凹陷結構，其中凹陷結構可 在絕緣層1之不同-面上，如圖五〇之結構示意圖，或在同 一面上，如圖五E之結構示意圖所示。 一如圖六A所示’其中增層結構9包含有絕緣層腿導電 層薄1卜其並形成於核^基板上以形成—增層多層電 路触)0,其中，該增層多層電路板_之盲孔凹陷處並埴 有絕緣材質10。 " 同樣的方法，如圖六B中，所述之增層結構12包含有 絕緣層13及電路層Μ ,其並形成於核心基板5〇〇上以形成 另★曰層夕層黾路板7〇〇。然而須注意的是，在電路板7QQ 中所謂的堆疊通孔15 (stacked vias)可提供更高的佈線密 度。更者，所述之增層多層電路板6〇〇、7〇〇可當作為核心 層以形成更多層之疊層。而且，所述之增層技術實施例並 非限定本發明之範圍所在，熟悉此項技藝人士皆知道，任 何增層電路板製程之應用皆屬本發明之範圍。 實施例中所述如圖五D至圖五F之導電層7.、8以雷射爆 破磨除法在導電薄層2上形成開口3或形成導電層7及8，則 可使用9300〜10600 nm波長之遠紅外線雷射光束（far_ 本紙張尺度通用中國國家標準（CNS ) A4規格（210X%7公釐） (請先閱番背面之注意事項再填寫本頁} 衣· -訂· 經濟部智慧財產局員工消費合作社印製 507511、 1T --- ama mama nn 507511 A7 '-------- B7 V. Description of the invention (g ^ ^ ~-~-Then, as shown in Figure 5B), the laser blast is used to remove 〇 Anta Satoshi ) Or _ technology to remove a portion of the conductive thin layer 2 to form an opening 3 in the conductive thin layer 2; the preferred diameter of the opening 3 is between 叫 called G _, and more preferably between _ ~ 0.04 mm. Then, the blind hole opening 4 can be formed in the insulating layer β by laser blasting, chemical side or (fine etching) techniques, as shown in Fig. 5. However, in this case, it is difficult to understand that if the insulating layer k material As a photo-imaging resin (_〇1mageabieresm), it is impossible to form the g-hole opening 4 by the conventional micro-shirt technology, because the ultraviolet light (w) will be blocked by the conductive thin layer 2. In the formation of blindness After the hole opening 4, the cleaning step is performed in the eye hole. Especially the surface of the conductive thin layer 2 in the blind hole is easily contaminated by residues. Then, the surface inside and outside the blind hole can be physically or chemically roughened. To improve adhesion (adhesion properties). Deposit a conductive layer 5 as shown in Figures 5D and 5E or a conductive layer as shown in Figure 5F to cover the conductive thin layer 2 and / or the blind hole opening 4 It can be formed by electroplating, electroless plating, physical vapor deposition (PVD), or chemical vapor deposition (CVD), etc. Copper plating should be under consideration of the implementation cost of the present invention A better choice. In addition, compared to the guidance of Figure 5F The layer 6 is completely filled in the blind hole opening 4. The conductive layer 5 in FIG. 5D and FIG. 5E only fills a part of the blind hole opening 4 and still has an unfilled recess. Of course, when the hole diameter is less than 0.05 mm It is easier to achieve the complete filling of the through-hole openings with electroplated copper, and it is more helpful for making stacked vias. In laser blasting (commonly known as laser direct patterning method), chemical Or the size of this paper is in accordance with Chinese National Standard (CNS) A4 specification (210 × ψmm) (Please read the notes on the back before filling this page) Clothing and Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative 507511, invention description (Y) The etching layer is used to form the circuit layer 7 in the picture and the picture (the electrical charge is 02 Γ: the preferred thickness of the circuit layers 7 and 8 can be on the surface ~ A ° ΐ core substrate gamma, 5QQ (divided in the figure) (4A, 4B) was completed in 焉. Of course, the conductive layer 5 of Figure 50 and Figure Qiu still has an unfilled recessed structure because only the blind hole opening 4 is filled, and the recessed structure can be insulated. The difference of layer 1-as shown in Figure 50 Or on the same side, as shown in the schematic diagram of the structure of Figure 5E. One is shown in Figure 6A, where the build-up structure 9 includes an insulating layer and a thin conductive layer and is formed on the core substrate to form— The layered multilayer circuit is touched) 0, wherein the blind hole recess of the layered multilayer circuit board is not provided with an insulating material 10. " The same method, as shown in FIG. 6B, the layered structure 12 includes The insulating layer 13 and the circuit layer M are formed on the core substrate 500 to form another layer of circuit board 700. It should be noted, however, that so-called stacked vias 15 in the circuit board 7QQ provide higher wiring density. Furthermore, the above-mentioned multi-layer multi-layer circuit boards 600 and 700 can be used as a core layer to form a stack of more layers. Moreover, the described embodiments of the layer-increasing technology do not limit the scope of the present invention. Those skilled in the art will know that any application of the layer-increasing circuit board process is within the scope of the present invention. The conductive layers 7, 8 shown in Figures 5D to 5F described in the example are formed by opening 3 on the conductive thin layer 2 or forming conductive layers 7 and 8 by laser blasting and grinding, and 9300 ~ 10600 nm can be used. Far-infrared laser beam of wavelength (far_ This paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X% 7mm) (Please read the precautions on the back of the fan before filling out this page.) Printed by the Bureau of Property and Staff Consumer Cooperatives 507511
經濟部智慧財產局員工消費合作社印製 mf職i laser beam) ’係如二氧化碟雷射；或355麵或更 低波長之紫外光雷射，係如兩極真空管泵（偏^ 卯寧d)、i態（帽·敝）或準分子雷射（ex_ 總y。然而’如细遠紅外線㈣光束，在圖宰化 層之前，可先進行粗化（麵ghened)，然後再於導電層 7、8 (如為金屬材質）％成一表面氧化層以降低雷射光束 之反射，且同時增加鈴之魏度與轉性。而如使 外光雷射，所述之導電層7、8則不必先形成表面氧化層， 而可直接進行圖案化步驟。在随化之後，導電層7、8可 再進㈣理或化學粗化，並形成—氧化層以增加^著性。 ”上所* ’本發明係揭露一種用於製作增層電路板之 ’專核心板之製法’可提供薄且高佈線密度之勒多層電路 =3”触好可#度°本發·f知技術領耻無 ^之技_露’ 6具_性；本制之技_容可確實 領域之問題4方法原理屬非根據習知技藝而易於 2之H其功雜業已料述’實錢步性；又本發明採 ^軸方法及所需設備本身鋪於本技術綱，亦具產 用性。因此，基於鼓勵發明之目的，專利之惠准 利審查基準之精神，相信#審查委員秉持多年 κ務、、'二馱，亦能認同本案符合專利要件及專利精 種技術並非—般人士所能思及者，此點尚祈貴審 —正考量明11之，盼能早日核准專利，實為感禱。 奋> ν “、： 乂上所述僅為本發明電路板結構與製程之較佳 貫施例，並非__本發明之實施翻，任何熟習該項 A4規格（210x^97公釐） 請 先 閱 讀‘ 背 意 事 項 再 填 寫 本 頁 訂 4 507511 A7 B7 五、發明説明（丨丨） 技藝者在不違背本發明之精神所做之修改，均應屬於本發 明之範圍，因此本發明之保護範圍當以下列所述之申請專 利範圍做為依據。 (請先閱1#.背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X#7公釐）Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, mf laser beam) 'Like a laser diode laser; or UV laser with a wavelength of 355 or lower, such as a bipolar vacuum tube pump (partially ^ 卯 d) , I-state (cap · 敝), or excimer laser (ex_ total y. However, such as a fine far-infrared chirped beam, you can roughen the surface before plotting the layer, and then apply it to the conductive layer 7 8 (if it is made of metal)% into a surface oxide layer to reduce the reflection of the laser beam, and at the same time increase the power and rotation of the bell. If the external light laser is used, the conductive layers 7, 8 are not necessary The surface oxide layer is formed first, and the patterning step can be directly performed. After the photoresist, the conductive layers 7, 8 can be further subjected to mechanical or chemical roughening, and an oxide layer can be formed to increase adhesion. "上 所 * ' The present invention discloses a 'special core board manufacturing method' used to make a layered circuit board, which can provide a thin and high-wiring density Le multi-layer circuit = 3 ″ touch good can be # °° the present technology knows no shame ^ Skills _ Dew '6 characteristics; the skills of this system _ Rongke can be a problem in the field 4 method principle is not based on The skill and miscellaneousness of the know-how and easy 2 have already been described as' real money step; the method of mining the shaft and the required equipment itself are laid out in this technical outline and are also productive. Therefore, based on the purpose of encouraging invention The spirit of the patent review criteria for the benefit of patents, I believe that the #examination committee members have upheld many years of service, and can also agree that this case meets the patent requirements and patented technology is not what ordinary people can think about. Praying for Guidance—We are considering the 11th, and we are looking forward to granting the patent as soon as possible. Fen > ν ",: 乂 The above is only a preferred embodiment of the circuit board structure and manufacturing process of the present invention, not _ _Implementation of the present invention, anyone familiar with the A4 specification (210x ^ 97 mm), please read 'Intentions before filling out this page to order 4 507511 A7 B7 V. Description of the invention (丨 丨) The artist does not violate this The modifications made by the spirit of the invention should all belong to the scope of the present invention, so the protection scope of the present invention should be based on the scope of patent application described below. (Please read the precautions on the back of 1 # before filling this page ) Order the Intellectual Property Bureau of the Ministry of Economic Affairs Co-op work printed in this paper scale applicable Chinese National Standard (CNS) A4 size (210X # 7 mm)