506082 A7 B7 五、發明説明（1 ) 發明領域 (請先閱讀背面之注意事項再填寫本頁) 本發明係關於輕度現場摻雜非晶矽，尤係關於輕度現 場摻雜非晶矽於動態隨機存取記憶體上的應用。 發明背景 互補式金氧半導體（CMOS)電晶體包括一 N通道金氧 半導體場效電晶體(NMOSFET)以及一 P通道場效電晶體 (PMOSFET)，如果形成的CMOS是雙井（twin well)構型 的話，則具有一 N井與一 P井。CMOS具有低耗能、高速 等等的優點，且廣泛應用於各種半導體記憶與邏輯電路 中，如動態隨機讀取記憶體的控制電晶體。 CMOS上由於有NMOSFET以及PM0SFET的電極， 所以一 CMOS具有一 P型摻雜的閘極以及一 N型摻雜的閘 極。N型不純物，如砷、磷等，植入需要形成N型摻雜區 域的部份，相對的，P型不純物，如硼或二氟化硼（boron difluoride)，則植入需要形成P型摻雜區域的部份中。 經濟部智慧財產局員工消費合作社印製 儘管在許多地方可能會有些修改或增減，CMOS仍有 一典型的基本結構。請參考圖1，一基板1〇〇上具有P型 井的的區域101以及N型井的區域102。P型井的區域101 與N型井的區域102之間必須加以隔開。在圖1中係以一 淺溝槽隔離層（shallow trench isolation) 103隔開區域101 與區域102，也有以局部氧化矽（LOCOS，Local Oxidation of Semiconductor)技術加以隔開者。一閘極氧化層104 形成於基板1〇〇上，閘極氧化層104上具有一多晶砂層 4PROMOS/200104TW，90032 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 506082 A7 B7 五、發明説明（1) 105。此多晶矽層105通常係以化學氣相沉積法形成。 (請先閱讀背面之注意事項再填寫本頁) 在多晶矽層105中，位於P型井的區域101上方之區 域植入以N型離子，如磷離子，而N型井區域102上方中 係植入以P型導電離子，如硼離子。植入離子的多晶矽層 105上則具有一導電層110，如矽化鎢層。 此典型的基本結構形成步驟如下。首先，如圖2a所 示，在一基板1〇〇上沉積一閘極氧化層104。此基板100 包括P型井的區域101、N型井的區域102以及將兩區域 101、102隔開的機制，在此爲一淺溝槽隔離層103。接著 如圖2b所示，沉積一多晶矽層105於閘極氧化層104上。 經濟部智慧財產局員工消費合作社印製 如圖2c所示，在植入N型離子107時，.以光阻106 遮蔽部分多晶矽層105，暴露出P型井的區域101上方之 多晶矽層105。如圖2d所示，在植入P型離子109時，則 以光阻108遮蔽多晶矽層105除了區域102之外的其他部 分。當N型與P型離子植入完成後，有時也會對基板100 進行熱處理，活化（activate)植入之離子。於後，如圖 2e所示，再形成一導電層110於多晶矽層105上。離子植 入與導電層110形成的先後次序可以依需要調換。可想見 的是，先完成導電層110再進行植入離子時，必須進行趨 入（drive-in)的步驟，以使離子確實到達多晶矽層105中。 隨著半導體裝置積集度的迅速升高，閘極氧化層104 的厚度也快速的變得較薄。以往較不會發生的硼穿透 (boron penetration )現象已經成爲必須積極面對的課題。 硼離子易於穿透過閘極氧化層104到多晶矽層105中，造 4PROMOS/200104TW, 90032 2 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 506082 A7 B7 五、發明説明（3 ) 成聞極氧化層104的破壞、起始電壓（threshold voltage)的 變化與閘極的空乏（gate depletion)。 此外，一般發現N型離子與P型離子在矽化鎢（常用 的導電層110的材料）中的交互擴散的速率比在多晶矽層 1〇5中要快上許多。在經過後續多道必要之加熱後，會使 多晶矽層105的費米能量(Fermi energy)產生變化並使閘極 空乏。 綜上所述，典型CMOS的基本結構遭遇到兩個主要的 困難。一個是抑制硼離子向下穿透至閘極氧化層，另一個 則是減低N型離子與P型離子之間的橫向擴散。 基於此，本發明中提出一種方法，以同時抑制硼穿透 與摻雜之不純物離子之間的交互擴散。 發明目的與槪述 本發明的一目的在於，提供一種製造半導體裝置的方 法’以同時避免硼穿透以及N型不純物與P型不純物之間 的橫向擴散。 本發明提供一種製造一半導體裝置的方法，半導體裝 置具有一基板、基板上具有屬於第一導電類型的一第一導 電區域以及屬於第二導電類型的一第二導電區域，此方法 包含形成一輕度摻雜（lightly-doped)的非晶矽層於該基 板上的第一步驟；熱處理輕度摻雜之非晶矽層的步驟；形 成一導電層於輕度摻雜之多晶矽層之上的步驟，以及一步 驟，包括植入第一導電類型不純物離子到輕度摻雜的多晶 4PROMOS/200104TW, 90032 3 本紙張尺度適用中國國家標準（CMS ) A4規格（210X297公釐）~ " (請先閱讀背面之注意事項再填寫本頁) V__ 、1T- · 經濟部智慧財產局員工消費合作社印製 506082 A7 B7 五、發明説明（斗） 矽層中，以形成第一導電區域，並且植入第二導電類型不 純物離子到輕度摻雜的多晶矽層中，以形成第二導電區域。 本發明的方法採用之非晶矽層係於現場（in-situ)沉 積時，通入化合物氣體’而輕度摻雜生成。在本發明的一 較佳實施例中，當欲輕度摻雜砷或磷時，所使用的化合物 氣體則爲含有砷或磷的氣體，如氫化砷、氫化磷等等。其 中輕度摻雜的非晶矽層係以屬於第一導電類型的不純物離 子進行摻雜。 圖式之簡單說明 圖1係爲先前技術中典型CMOS結構的示意圖； 圖2a係爲先前技術於基板上形成一閘極氧化層後之 示意圖； 圖2b係爲先前技術於閘極氧化層上再形成一多晶矽 層後之示意圖； 圖2c係爲先前技術植入N型離子到多晶矽層中p型 井區域的示意圖； 圖2 d係爲先則技術植入P型離子到多晶砂層中n型 井區域的示意圖； 圖2e係爲先前技術沉積一矽化鎢層於如圖2d所示之 基板上後之示意圖； 圖_ 3a係爲一基板上沉積一閘極氧化層後之示意圖； 圖3b係爲圖3a中之基板沉積一輕度現場摻雜非晶砂 層後之示意圖； 4PROMOS/200104TW, 90032 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' (請先閱讀背面之注意事項再填寫本頁) - - I -Γ - 、τ 經濟部智慧財產局員工消費合作社印製 506082 A7 B7 五、發明説明（5 ) 圖3c係爲對圖3b中之基板進行熱處理後，輕度現場 摻雜非晶矽層轉變成多晶矽層後之示意圖； (請先閱讀背面之注意事項再填寫本頁) 圖3d係爲沉積一矽化鎢層於如圖3c所示之基板上後 之示意圖； 圖3e係爲植入磷離子到多晶矽層中P型井區域的示意 圖； 圖3f係爲植入硼離子到多晶矽層中N型井區域的示 意圖； 圖3g係爲在導電層上方形成一絕緣保護層的示意 圖；以及 圖4係爲本發明之方法的流程圖。 圖式元件符號說明 先前技術 100基板 101P型井的區域 102N型井的區域 103淺溝槽隔離層 104閘極氧化層 105多晶矽層 106、108 光阻 107 N型離子 109 P型離子 110導電層 本發明 200基板 201P型井的區域 202N型井的區域 203閘極氧化層 經濟部智慧財產局員工消費合作社印製 4PROMOS/200104TW，90032 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 506082 A7 B7 五、發明説明（b ) 204A輕度現場摻雜非晶矽層204P多晶矽層 205淺溝槽隔離層 206導電層 (請先閱讀背面之注意事項再填寫本頁) 207磷離子 206光阻 209硼離子 210光阻 211絕緣保護層 發明之詳細說明 本發明提供一種製造一半導體裝置的方法，此半導體 裝置具有一基板，基板中具有屬於第一導電類型的一第一 導電區域以及屬於第二導電類型的一第二導電區域，基板 上並具有一氧化層。 請參考圖3a，一基板200中具有P型井的區域201與 N型井的區域202,區域201與202以一淺溝渠隔離層205 加以隔開。基板200上具有一閘極氧化層203。 在本發明的一較佳實施例中，首先形成一輕度摻雜 (lightly-doped)的非晶砂層204A於基板200上，如圖 3b所示。在此所謂之輕度摻雜係相對於區域201與202最 後的摻雜濃度而言者。 經濟部智慧財產局員工消費合作社印製 輕度摻雜的非晶矽層204A通常係以化學氣相沉積的 方式形成，在形成過程中現場摻雜的不純物較佳爲N型的 不純物，如磷或砷。接著熱處理輕度摻雜的非晶矽層 204A，使輕度摻雜的非晶砂層204A結晶形成多晶:&夕層 204P，如圖3c所示。經過摻雜再加以熱處理的矽晶，因爲 摻雜的不純物可以幫助矽晶核的形成，可形成更大的晶 4PROMOS/200104TW, 90032 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 506082 A7 B7 五、發明説明（η ) 粒。須注意，此時P型井區域201與N型井區域202上方 皆具有含N型不純物的多晶矽層204P。 然後，沉積一導電層206於多晶矽層204P之上，如 圖3d所示。此導電層206較佳係爲金屬矽化物，如矽化鎢、 矽化鈦、矽化鉬、矽化鉅與矽化鈷，而通常使用矽化鎢作 爲此導電層206的材料。此導電層206可以提昇多晶矽與 鋁之間的歐姆式接觸。這種多晶矽層204P加上矽化鎢導 電層206的組合又可稱爲多晶矽化物金屬（p〇lycide)，此 種組合爲閘極導電層（gate contact)常用者。 接著，如圖3e所示，以光阻208遮住導電層206除了 區域201之外的部份，植入N型不純物離子207到P型井 的區域201上方之多晶矽層204P中，並以光阻210遮蔽 除了區域202之外的部份，植入P型不純物離子209到N 型井的區域202上方之多晶矽層204P中，如圖3f所示。 承前面所述，由於輕度摻雜的非晶矽層204A中已經含有 不純物離子，此時植入的不純物離子的濃度必須有所調 整。舉例來說，如果之前輕度摻雜的非晶矽層204A中係 摻雜N型不純物，則植入的N型不純物離子的濃度就必須 比預定濃度低，以使得植入N型不純物離子207後的濃度 約等於預定的濃度，而植入之P型不純物離子的濃度實質 上則不受輕度摻雜之N型不純物影響。於本發明的最佳實 施例中，輕度摻雜較佳是最後摻雜濃度的十分之一到二分 之一。輕度摻雜之砷或磷的濃度較佳爲lE14/cm2到 lE15/cm2，而P型井的區域201上方之多晶矽層2CMP中 4PROMOS/200104TW, 90032 7 ^氏張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) ' (請先閱讀背面之注意事項再填寫本頁) - 1- I = -Φ. 經濟部智慧財產局員工消費合作社印製 506082 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（δ ) 的砷或磷的植入的濃度則爲6E15/cm2，而N型井的區域 2〇2上方之多晶矽層204P中硼的濃度則爲lE15/cm2到 2E15/cm2 〇 由於P型井之區域201與N型井之區域202之上方的 多晶矽層2〇4P中都含有N型不純物離子，可有效降低摻 雜離子的交互擴散。此外N型不純物離子與P型不純物離 子共處於N型井的區域202之上方的多晶矽層204P中， 也具有抑制硼穿透的作用。 具有較大晶粒的多晶矽層204P，因爲晶粒間的晶界 (grain boundary)減少，硼離子向下擴散到閘極氧化層 203的路徑相對減少，可有效抑制橫向（n型不純物離子 與P型不純物離子之間）與縱向（硼穿透到閘極氧化層203 ) 的擴散。此外，因爲多晶矽層204P中擴散的路徑變少，N 型與P型的不純物離子不容易擴散到導電層206中。先前 技術的文獻中即指出，大部份N型不純物離子與P型不純 物離子之間的橫向擴散係在導電層（通常爲矽化鎢層）發 生’所以當本發明的方法抑制不純物離子擴散到導電層 206中時，其實已經間接防止了 N型不純物離子與p型不 純物離子之間的橫向擴散。 本發明的方法可進一步包含形成一絕緣保護層211於 導電層上的步驟，以保護導電層206，如圖3g所示。 本發明於形成輕度摻雜的非晶矽層204A時，先進行 一次摻雜，再於離子植入時進行另一次摻雜，如果以摻雜 的角度觀之，本發明的方法可謂爲一種兩步摻雜的方法。 4PROMOS/200104TW, 90032 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (讀先閲4背面之注意事項再填寫本頁} —ϋ ....... . 、τ 506082 A7 B7 五、發明説明（（5)) (請先閲讀背面之注意事項再填寫本頁) 於本發明的一較佳實施例中，輕度摻雜的非晶矽層204A 係於沉積時摻雜以砷離子或磷離子，再進行熱處理。爲了 有效使晶粒成長變大，熱處理通常都以回火的方式進行。 與硼離子相較，磷或砷離子的擴散速度較慢，不會於熱處 理時縱向向下擴散至閘極氧化層中，而造成起始電壓的不 穩定。待於完成導電層後，再進行第二次摻雜，也就是離 子植入的動作。 於前一較佳實施例中，係先形成導電層後再進行離子 植入的動作。因爲較淺處之導電層中亦有少量離子，可以 減緩多晶矽層中離子的向上擴散。如果先進行離子植入再 形成導電層，原本多晶矽層中已達到預定濃度的離子可能 會於後大量擴散到導電層中，進而加速兩種離子的交互擴 散。然而，如果事先考量到這些因素並加以控制，於本發 明的另一實施例中，亦可先進行離子植入然後再形成導電 層。 經濟部智慧財產局員工消費合作社印製 綜觀以上，本發明提供一種製造一半導體裝置的方 法，此半導體裝置具有一基板，基板上具有屬於第一導電 類型的一第一導電區域以及屬於第二導電類型的一第二導 電區域。請參考圖4，本發明首先於步驟401中形成一輕 度摻雜的非晶矽層於基板上。即如圖3b所示，沉積一非晶 石夕層204A於閘極氧化層203上。接著，於步驟402中， 熱處理輕度摻雜的非晶矽層。即如圖3c所示，使非晶矽層 204A結晶成長爲多晶矽層204P。再於步驟403中，形成 一導電層於輕度摻雜的多晶矽層之上。即如圖3d所示，沉 4PROMOS/200104TW, 90032 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 506082 A7 _B7_五、發明説明（\〇) 積一導電層206’例如矽化鎢，於多晶矽層204P上。並且， 於步驟4〇4中’植入一第一導電類型不純物離子到輕度摻 雜的多晶矽層中，以形成第一導電區域，並且植入一第二 導電類型不純物離子到輕度摻雜的多晶矽層中，以形成第 二導電區域。即如圖3e到圖3f所示，以光阻208與210 部份遮蔽導電層206，以植入N型不純物離子207與P型 不純物離子209到預定的位置中。本發明的方法也可以進 一步於步驟405中，形成一絕緣保護層於導電層上。即如 圖3g所不’沉積一絕緣層211於導電層206上。 承前所述，本發明之步驟403與404係爲可調換順序 者。 熟悉本項技術者應該淸楚了解，本發明可以在不脫離 本發明的精神與範圍下，以許多其他特定形式加以實施。 因此，現在提供的實施例應該被當作說明性的，而不是限 制性的，此發明不受文中所給細節的侷限，而可以於隨附 申請專利範圍的範圍內作均等的變化與修改。 (請先閲讀背面之注意事項再填寫本頁) 訂' · 經濟部智慧財產局員工消費合作社印製 4PROMOS/200104TW, 90032 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）506082 A7 B7 V. Description of the invention (1) Field of invention (please read the notes on the back before filling this page) The present invention is about lightly doped amorphous silicon in situ, especially about lightly doped amorphous silicon in situ. Applications on dynamic random access memory. BACKGROUND OF THE INVENTION Complementary metal-oxide-semiconductor (CMOS) transistors include an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) and a P-channel field-effect transistor (PMOSFET). If the CMOS formed is a twin-well structure In the case of the type, there are one N well and one P well. CMOS has the advantages of low power consumption, high speed, etc., and is widely used in various semiconductor memories and logic circuits, such as control transistors for dynamic random read memory. Because CMOS has electrodes of NMOSFET and PMOSFET, a CMOS has a P-type doped gate and an N-type doped gate. For N-type impurities, such as arsenic, phosphorus, etc., implantation requires the formation of N-type doped regions. In contrast, for P-type impurities, such as boron or boron difluoride, implantation requires the formation of P-type impurities. Part of the miscellaneous area. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Although there may be some modifications or additions in many places, CMOS still has a typical basic structure. Please refer to FIG. 1, a region 101 having a P-type well and a region 102 of an N-type well on a substrate 100. The area 101 of the P-well and the area 102 of the N-well must be separated. In FIG. 1, a shallow trench isolation layer (shallow trench isolation) 103 is used to separate the region 101 and the region 102. There is also a method using a local silicon oxide (LOCOS) technology to separate the region 101 from the region 102. A gate oxide layer 104 is formed on the substrate 100. The gate oxide layer 104 has a polycrystalline sand layer 4PROMOS / 200104TW, 90032 1 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 506082 A7 B7 V. Description of Invention (1) 105. The polycrystalline silicon layer 105 is usually formed by a chemical vapor deposition method. (Please read the precautions on the back before filling this page) In the polycrystalline silicon layer 105, the area above the area 101 of the P-type well is implanted with N-type ions, such as phosphorus ions, and the area above the N-type well area 102 is implanted. Into P-type conductive ions, such as boron ions. The ion-implanted polycrystalline silicon layer 105 has a conductive layer 110, such as a tungsten silicide layer. The typical basic structure formation steps are as follows. First, as shown in FIG. 2a, a gate oxide layer 104 is deposited on a substrate 100. The substrate 100 includes a region 101 of a P-type well, a region 102 of an N-type well, and a mechanism for separating the two regions 101 and 102. Here, it is a shallow trench isolation layer 103. As shown in FIG. 2 b, a polycrystalline silicon layer 105 is deposited on the gate oxide layer 104. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. As shown in FIG. 2c, when the N-type ion 107 is implanted, a portion of the polycrystalline silicon layer 105 is shielded with a photoresist 106, exposing the polycrystalline silicon layer 105 above the region 101 of the P-well. As shown in FIG. 2d, when the P-type ion 109 is implanted, the photoresist 108 is used to shield other parts of the polycrystalline silicon layer 105 except the region 102. After the N-type and P-type ion implantation is completed, the substrate 100 may also be heat-treated to activate the implanted ions. Thereafter, as shown in FIG. 2e, a conductive layer 110 is further formed on the polycrystalline silicon layer 105. The order of the ion implantation and the formation of the conductive layer 110 can be changed as needed. It is conceivable that when the conductive layer 110 is completed before implanting ions, a drive-in step must be performed so that the ions can actually reach the polycrystalline silicon layer 105. As the degree of semiconductor device accumulation rapidly increases, the thickness of the gate oxide layer 104 also rapidly becomes thinner. In the past, the phenomenon of boron penetration, which is less likely to occur, has become an issue that must be actively faced. Boron ions easily penetrate through the gate oxide layer 104 to the polycrystalline silicon layer 105, making 4PROMOS / 200104TW, 90032 2 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) 506082 A7 B7 V. Description of the invention (3) The destruction of the oxide layer 104, the change of the threshold voltage, and the gate depletion. In addition, it is generally found that the rate of interdiffusion of N-type ions and P-type ions in tungsten silicide (commonly used as the material of the conductive layer 110) is much faster than that in the polycrystalline silicon layer 105. After subsequent necessary heating, the Fermi energy of the polycrystalline silicon layer 105 will be changed and the gate will become empty. To sum up, the basic structure of a typical CMOS encounters two main difficulties. One is to inhibit the boron ions from penetrating downward to the gate oxide layer, and the other is to reduce the lateral diffusion between N-type and P-type ions. Based on this, a method is proposed in the present invention to simultaneously suppress the interdiffusion between boron penetration and doped impurity ions. OBJECTS AND DESCRIPTIONS OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device 'to simultaneously avoid boron penetration and lateral diffusion between N-type impurities and P-type impurities. The invention provides a method for manufacturing a semiconductor device. The semiconductor device has a substrate having a first conductive region of a first conductivity type and a second conductive region of a second conductivity type on the substrate. The method includes forming a light The first step of a lightly-doped amorphous silicon layer on the substrate; the step of heat-treating the lightly-doped amorphous silicon layer; forming a conductive layer on the lightly-doped polycrystalline silicon layer Step, and a step, including implanting the impurity of the first conductivity type into the lightly doped polycrystalline 4PROMOS / 200104TW, 90032 3 This paper size is applicable to China National Standard (CMS) A4 specification (210X297 mm) ~ " ( Please read the notes on the back before filling in this page) V__, 1T- · Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 506082 A7 B7 V. Description of the invention (bucket) In the silicon layer to form the first conductive area, and Impurities of the second conductivity type are implanted into the lightly doped polycrystalline silicon layer to form a second conductive region. When the amorphous silicon layer used in the method of the present invention is deposited in-situ, a compound gas is introduced into the amorphous silicon layer and lightly doped. In a preferred embodiment of the present invention, when lightly doped with arsenic or phosphorus, the compound gas used is a gas containing arsenic or phosphorus, such as arsenic hydride, phosphorus hydride, or the like. The lightly doped amorphous silicon layer is doped with impurities of the first conductivity type. Brief description of the drawings FIG. 1 is a schematic diagram of a typical CMOS structure in the prior art; FIG. 2a is a schematic diagram of a gate oxide layer formed on a substrate in the prior art; FIG. 2b is a diagram of the prior art on the gate oxide layer. Schematic diagram after forming a polycrystalline silicon layer; Figure 2c is a schematic diagram of implanting N-type ions into the p-type well region in the polycrystalline silicon layer in the prior art; Figure 2d is a prior art technique of implanting P-type ions into the n-type in the polycrystalline sand layer Schematic diagram of well area; Figure 2e is a schematic diagram of a tungsten silicide layer deposited on the substrate shown in Figure 2d in the prior art; Figure _3a is a schematic diagram of a gate oxide layer deposited on a substrate; Figure 3b is It is a schematic diagram after depositing a lightly doped amorphous sand layer on the substrate in Fig. 3a; 4PROMOS / 200104TW, 90032 4 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) '(Please read the back Please note this page, please fill in this page)--I -Γ-τ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 506082 A7 B7 V. Description of the invention (5) Figure 3c shows the heat treatment of the substrate in Figure 3b. Degree scene Schematic diagram of hetero-amorphous silicon layer converted into polycrystalline silicon layer; (Please read the precautions on the back before filling this page) Figure 3d is a schematic diagram after depositing a tungsten silicide layer on the substrate as shown in Figure 3c; Figure 3e Is a schematic diagram of implanting phosphorus ions into the P-type well region in the polycrystalline silicon layer; FIG. 3f is a schematic diagram of implanting boron ions into the N-type well region in the polycrystalline silicon layer; Schematic; and Figure 4 is a flowchart of the method of the present invention. Graphical element symbols explain the prior art 100 substrate 101P region 102N region 103 shallow trench isolation layer 104 gate oxide layer 105 polycrystalline silicon layer 106, 108 photoresist 107 N type ions 109 P type ions 110 conductive layer Invented 200 substrate 201P well area 202N well area 203 Gate oxide layer Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4PROMOS / 200104TW, 90032 5 This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ) 506082 A7 B7 V. Description of the invention (b) 204A Mild on-site doped amorphous silicon layer 204P polycrystalline silicon layer 205 Shallow trench isolation layer 206 conductive layer (Please read the precautions on the back before filling this page) 207 Phosphorous ion 206 Photoresistor 209 Boron ion 210 Photoresistor 211 Insulating protective layer Detailed description of the invention The present invention provides a method for manufacturing a semiconductor device having a substrate, the substrate having a first conductive region of a first conductivity type and A second conductive region of the second conductivity type has an oxide layer on the substrate. Referring to FIG. 3a, a region 201 having a P-type well and a region 202 of an N-type well in a substrate 200 are separated by a shallow trench isolation layer 205. The substrate 200 has a gate oxide layer 203. In a preferred embodiment of the present invention, a lightly-doped amorphous sand layer 204A is first formed on the substrate 200, as shown in FIG. 3b. The so-called light doping is relative to the final doping concentration of the regions 201 and 202. The lightly doped amorphous silicon layer 204A printed by the employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is usually formed by chemical vapor deposition. In the process of formation, the impurities doped on site are preferably N-type impurities, such as phosphorus. Or arsenic. The lightly doped amorphous silicon layer 204A is then heat-treated to crystallize the lightly doped amorphous sand layer 204A to form a polycrystalline: & evening layer 204P, as shown in FIG. 3c. Silicon crystals that have been doped and then heat-treated, because the doped impurities can help the formation of silicon nuclei, which can form larger crystals 4PROMOS / 200104TW, 90032 6 This paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X297) (Centi) 506082 A7 B7 5. Description of the invention (η) grains. It should be noted that, at this time, a polycrystalline silicon layer 204P containing an N-type impurity is provided above the P-type well region 201 and the N-type well region 202. Then, a conductive layer 206 is deposited on the polycrystalline silicon layer 204P, as shown in FIG. 3d. The conductive layer 206 is preferably a metal silicide, such as tungsten silicide, titanium silicide, molybdenum silicide, silicide giant, and cobalt silicide, and tungsten silicide is usually used as the material of the conductive layer 206. The conductive layer 206 can improve the ohmic contact between polycrystalline silicon and aluminum. The combination of the polycrystalline silicon layer 204P and the tungsten silicide conductive layer 206 can also be referred to as polycrystalline silicon (polysilide), and this combination is commonly used for gate contact. Next, as shown in FIG. 3e, a portion of the conductive layer 206 other than the region 201 is covered with a photoresist 208, and an N-type impurity ion 207 is implanted into the polycrystalline silicon layer 204P above the region 201 of the P-type well, and light is applied. The resist 210 shields the part other than the region 202 and implants the P-type impurity 209 into the polycrystalline silicon layer 204P above the region 202 of the N-type well, as shown in FIG. 3f. As mentioned above, since the impurity impurity ions are already contained in the lightly doped amorphous silicon layer 204A, the concentration of the implanted impurity ions must be adjusted at this time. For example, if the lightly doped amorphous silicon layer 204A was doped with an N-type impurity, the concentration of the implanted N-type impurity ions must be lower than the predetermined concentration, so that the N-type impurity 207 is implanted 207 The subsequent concentration is approximately equal to the predetermined concentration, and the concentration of the implanted P-type impurity is substantially unaffected by the lightly doped N-type impurity. In a preferred embodiment of the present invention, the light doping is preferably one-tenth to one-half of the final doping concentration. The concentration of lightly doped arsenic or phosphorous is preferably 1E14 / cm2 to 1E15 / cm2, and the polycrystalline silicon layer 2CMP in the region 201 of the P-type well is 4PROMOS / 200104TW, 90032 7 ^ Zhang scale applicable to Chinese national standards (CNS ) A4 size (210X297mm) '(Please read the notes on the back before filling out this page)-1- I = -Φ. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 506082 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Preparation A7 B7 V. Description of the invention (δ) The implantation concentration of arsenic or phosphorus is 6E15 / cm2, and the concentration of boron in the polycrystalline silicon layer 204P above the area 202 of the N-type well is 1E15 / cm2 to 2E15 Since the polycrystalline silicon layer 204P above the region 201 of the P-type well and the region 202 of the N-type well contains N-type impurity ions, it can effectively reduce the interdiffusion of doped ions. In addition, the polycrystalline silicon layer 204P in which the N-type impurity ions and the P-type impurity ions are located above the region 202 of the N-type well also has a function of suppressing the penetration of boron. Polycrystalline silicon layer 204P with larger grains, because the grain boundaries between grains are reduced, the path for boron ions to diffuse down to the gate oxide layer 203 is relatively reduced, which can effectively suppress lateral (n-type impurity ions and P Diffusion between the type impurities and the vertical direction (boron penetrates into the gate oxide layer 203). In addition, because there are fewer diffusion paths in the polycrystalline silicon layer 204P, impurity ions of the N-type and P-type are not easily diffused into the conductive layer 206. It is pointed out in the literature of the prior art that the lateral diffusion between most of the N-type impurity ions and the P-type impurity ions occurs in the conductive layer (usually a tungsten silicide layer). Therefore, when the method of the present invention suppresses the diffusion of the impurity ions into the conductive layer, In the layer 206, the lateral diffusion between the N-type impurity ions and the p-type impurity ions has been indirectly prevented. The method of the present invention may further include the step of forming an insulating protection layer 211 on the conductive layer to protect the conductive layer 206, as shown in FIG. 3g. When the lightly doped amorphous silicon layer 204A is formed in the present invention, first doping is performed, and then another doping is performed during ion implantation. If viewed from the perspective of doping, the method of the present invention can be described as a kind of Two-step doping method. 4PROMOS / 200104TW, 90032 8 This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) (read the precautions on the back of 4 before filling this page} —ϋ ........, Τ 506082 A7 B7 V. Description of the invention ((5)) (Please read the notes on the back before filling this page) In a preferred embodiment of the present invention, the lightly doped amorphous silicon layer 204A is doped during deposition Doped with arsenic ions or phosphorus ions, and then heat treatment. In order to effectively increase the grain growth, heat treatment is usually performed by tempering. Compared with boron ions, the diffusion rate of phosphorus or arsenic ions is slower than that of boron ions. During heat treatment, it diffuses down into the gate oxide layer vertically, causing instability of the initial voltage. After the conductive layer is completed, the second doping, which is the action of ion implantation, is better than the previous one. In the embodiment, the conductive layer is formed first, and then the ion implantation is performed. Because there are also a small amount of ions in the shallower conductive layer, the upward diffusion of ions in the polycrystalline silicon layer can be slowed down. If the ion implantation is performed first, the conductive layer is formed. Layer, originally in the polycrystalline silicon layer Ions that reach a predetermined concentration may diffuse into the conductive layer in a large amount later, thereby accelerating the interdiffusion of the two ions. However, if these factors are considered and controlled in advance, in another embodiment of the present invention, Ion implantation is then performed to form a conductive layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the present invention provides a method for manufacturing a semiconductor device having a substrate having a substrate of a first conductivity type. A first conductive region and a second conductive region belonging to the second conductivity type. Please refer to FIG. 4. In the present invention, a lightly doped amorphous silicon layer is first formed on a substrate in step 401, as shown in FIG. 3b. As shown, an amorphous stone layer 204A is deposited on the gate oxide layer 203. Next, in step 402, a lightly doped amorphous silicon layer is heat-treated. That is, as shown in FIG. 3c, the amorphous silicon layer 204A is crystallized. Grow into a polycrystalline silicon layer 204P. Then in step 403, a conductive layer is formed on the lightly doped polycrystalline silicon layer. That is, as shown in FIG. 3D, Shen 4 PROMOS / 200104TW, 90032 9 The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 506082 A7 _B7_ V. Description of the invention (\ 〇) A conductive layer 206 'such as tungsten silicide is deposited on the polycrystalline silicon layer 204P. And, in step 4 4 'implant a impurity of a first conductivity type into a lightly doped polycrystalline silicon layer to form a first conductive region, and implant a impurity of a second conductivity type into a lightly doped polycrystalline silicon layer to A second conductive region is formed, that is, as shown in FIG. 3e to FIG. 3f, the conductive layer 206 is partially shielded with photoresist 208 and 210 to implant N-type impurity 207 and P-type impurity 209 into predetermined positions. The method of the present invention can also be further performed in step 405 to form an insulating protection layer on the conductive layer. That is, as shown in FIG. 3g, an insulating layer 211 is deposited on the conductive layer 206. According to the foregoing description, steps 403 and 404 of the present invention are interchangeable sequences. Those skilled in the art should understand that the present invention can be implemented in many other specific forms without departing from the spirit and scope of the invention. Therefore, the embodiments provided now should be regarded as illustrative rather than restrictive. This invention is not limited by the details given in the text, but can be changed and modified equally within the scope of the accompanying patent application. (Please read the notes on the back before filling out this page) Order '· Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4PROMOS / 200104TW, 90032 10 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)