TW506051B

TW506051B - Method for forming gate dielectric material layer in silicon nitride ROM

Info

Publication number: TW506051B
Application number: TW89125961A
Authority: TW
Inventors: Guo-Hua Jang
Original assignee: Macronix Int Co Ltd
Priority date: 2000-12-06
Filing date: 2000-12-06
Publication date: 2002-10-11

Abstract

The present invention relates to a method for increasing the coupling ratio of a gate dielectric material and increasing the reliability of a silicon nitride ROM-type flash memory device by forming a zirconium oxide layer with a high dielectric constant on a substrate. The invented method at least comprises: providing a substrate; using a reactive magnetically-controlled sputtering method to form a zirconium oxide layer on the substrate; forming a silicon nitride layer on the zirconium oxide layer; forming a silicon oxide layer on the top layer, thereby forming an ONO (oxide-nitride-oxide) layer. The high coupling ratio using zirconium oxide as a gate dielectric material can reduce the control gate voltage while better controlling the on/off capability of a gate and the time-dependent dielectric breakdown properties of the gate.

Description

506051506051

5-1發明領域：卜本發明係有關於一種利用氧化锆取代傳統的氧化矽在氮化砍唯讀記憶體晶胞中形成閘介電層的方法，特別是關於一種增加閘介電層耦合率的方法。疋 5-2發明背景：二根據第一圖，係說明一種典型的習知技藝氮化矽，憶體晶胞。此晶胞包含一底材丨〇〇，一氧化矽—氮化項氧化矽（0N0，oxide-nitride —〇xide)結構，在結構中，一，，矽層122在兩個氧化矽層12〇及124之間形成，然後一多晶矽層150以低壓化學氣相沉積（LpcvD，L〇w C^enncal Vapor Dep〇siti〇n)法在氧化矽-氮化矽—氧化曰的頂α卩形成。接著，以广蝕刻步驟依序蝕刻多晶矽層 5〇以及氧化矽—氮作/秒—氧化矽層以形成一閘極。接著曰，，閘=的侧壁形成間隙壁126及128。再則，在底材ι〇〇植入一源極1 0 1與一汲極丨〇 2。 h a ί於可程式記憶體（EPR〇M)，記憶體結構中包含一閘 ^ X及汲極1 0 2。在閘極的最底層為一氧化矽層1 2 0 ，^化矽層120的厚度薄到允許F〇wler —N〇rdheim穿隧（以可，nneHng，可縮寫成FN穿隧）發生。所匕联氐層的氧化矽層1 2 0 w且氧化矽層1 2 0可視為隧 5060515-1 Field of the Invention: The present invention relates to a method for forming a gate dielectric layer in a read-only memory cell using zirconia instead of traditional silicon oxide, and particularly to a method for increasing the coupling of the gate dielectric layer. Rate method.疋 5-2 Background of the Invention: According to the first figure, it illustrates a typical conventional technique of silicon nitride, recalling the unit cell. This unit cell includes a substrate, a silicon oxide-nitride oxide silicon oxide (ONO) structure. In the structure, a silicon layer 122 is on two silicon oxide layers 12. A polycrystalline silicon layer 150 is formed between silicon oxide and silicon nitride-oxidized silicon by a low-pressure chemical vapor deposition (LpcvD, Low Carbon Vapor DepOsiti) method. Then, the polycrystalline silicon layer 50 and the silicon oxide-nitrogen as / second-silicon oxide layer are sequentially etched in a wide etching step to form a gate. Then, the side walls of the gates form the partition walls 126 and 128. Furthermore, a source electrode 101 and a drain electrode 02 are implanted in the substrate ιOO. h a is in Programmable Memory (EPROM). The memory structure includes a gate ^ X and a drain electrode 102. At the bottom of the gate is a silicon oxide layer 120. The thickness of the silicon oxide layer 120 is thin enough to allow Fowler-Nordheim tunneling (could, nneHng, abbreviated as FN tunneling) to occur. The silicon oxide layer 1 2 0 w and the silicon oxide layer 1 2 0 can be regarded as a tunnel 506051.

氧化層（tunneling oxide layer)。在寫入模式時將問極接地而高電壓接至没極102。在抹除程式時，高電壓接至閘極，汲極1〇2則是接地。〆门根據熱電子射入（HEI，hot electrc)n injectiQn)， $最底層的氧化矽層120很薄時，一些熱電子會滲透過底層的氧化矽層120，而電子則是聚集在氮化矽層122中。在習知技藝中，氮化矽層122所收到的電荷極1 〇2的區域。干τ隹罪迎戍在傳統形成閘介電層的方法是利用熱氧化法在底材 U上形成。氧化矽12〇的介電常數為3 8至3 9莫耳每立方一、且熱氧化法的溫度很高。此外，閘介電層的耦合率 2 ^ ’對閘介電層而言，若對閘極/汲極導入一高電壓以厣^程^式化晶胞超過一百次以上的情況下，隧道式氧化 ς 很容易有崩潰的情形發生，且漏電流會增加，而隧 ^式氧化層1 2 〇的可靠性會降低。 3發明目的及概述：根據本發明電介層的方法，，係提供在氮化式唯讀記憶體中形成一閘其中以一氧化鍅層取代傳統隧道式氧化層Oxide layer (tuning oxide layer). In the write mode, the question pole is grounded and the high voltage is connected to the pole 102. When erasing the program, the high voltage is connected to the gate, and the drain 102 is grounded. According to the hot electron injection (HEI, hot electrc) n injectiQn), when the bottommost silicon oxide layer 120 is thin, some hot electrons will penetrate the bottom silicon oxide layer 120, and the electrons are concentrated in the nitride. In the silicon layer 122. In the conventional art, the region of the charge electrode 102 received by the silicon nitride layer 122 is. The traditional method for forming a gate dielectric layer is to form it on the substrate U by a thermal oxidation method. The dielectric constant of silicon oxide 12 is 38 to 39 mol per cubic meter, and the temperature of the thermal oxidation method is high. In addition, the coupling rate of the gate dielectric layer is 2 ^ 'For the gate dielectric layer, if a high voltage is introduced to the gate / drain to transform the cell more than a hundred times, the tunnel It is easy for the oxide oxide to collapse, and the leakage current will increase, and the reliability of the tunnel oxide layer 12 will decrease. 3 Purpose and summary of the invention: According to the dielectric layer method of the present invention, it is provided to form a gate in a nitride read-only memory, wherein a hafnium oxide layer is used to replace the traditional tunnel oxide layer.

第5頁月曰一修正 i 號 8Q1 舛 Qq_ 五、發明說明（3) 本發明的目的县、濺鑛沉積的溫度低於傳形成氧化錯層，而熱預算。、、勺冋，皿熱乳化法，使得可以降低本發明的再—日ώΑ θ丄的閘介電層。、底材上形成高耦合率和低漏電本毛明的次-目的是在底材上形成—古人a 化1口層，此氧化鍅層可以降低押制電爆以^電吊數的氧度以顯示較低的次臨限電壓以及有良好的門2電荷增益本發明的又-目的’可以增加閘介電層的c性。體元件的可靠性。了也了歼快閃型記憶主要：亡Γ目的’在一實施例中，對於本發明最王罟的刀疋在氮化矽唯讀記情知乃敢極的結構包含在一底材〜^中形成一閘W電層。閘 s户兮# 底材上形成一氧化鍅層，以及一所仆切層在该虱化錯層與一氧化矽#之門拉朴各虱化矽形成一多晶矽声以及/夕曰1間。接者，在氧化矽層上依序蝕刻夕s 1 Μ 夕曰曰矽層上定義一光阻層。再者，形成閘極！利，氮切層以及氧化錯層成-源極與：汲極。先的離子植入的方法在底材内形 5-4發明詳細說明第6頁 506051 ----案號89125961 _年月日條正五、發明說明（幻 " " " ' '^ 本發明的一些實施例會詳細描述如下。然而，除了 ▲、, 細描述外，本發明還可以廣泛地在其他的實施例施彳^，坪本發明的範圍不受限定，其以之後的專利範圍為準。丁且參考第二圖，為一直流式濺鍍系統。一反應室2 θ 〇内主要是由一個放置金屬靶材21〇的陰電極，一個擺放曰底材1 0的晶座3 〇〇 (可以接地），以及一擋板2 2 0所構成。持電漿及濺鍍所須要的氣體由反應室另一端的氣體供應器 240提供，並且由另一端通往提供反應室2〇〇真空度的幫; (pump) 280。電漿運作所須要的能量，則由一組直流電源供應器2 5 0所提供。其中’接地遮板（g r 0 u n d ,、 shield)230A、230B、230C及230D位於晶座300及金屬靶材 2 1 0兩侧。為了使電漿裏帶正電荷的離子能對金屬靶2 1 〇的表面進行錢擊，放置金屬靶210的電極將與直流電源2 5〇相接。因為金屬的濺鍍對不純物的容忍度不高，尤其是氧氣及水氣，所以在進行金屬的濺鍍之前，通常將反應室2〇〇的壓力藉著冷凍幫浦（Cryopump) 270，將這些對金屬有強氧化能力的氣體抽離。並且稱這個執行濺鍍前所須要的低壓為基準壓力（Base Pressure)，通常在10-6甚至於10_7托爾以下。當反應室200已達到基準壓力之後，接下來通入反應氣體，準備進行金屬的濺鍍。在執行濺鍍之前，金屬靶Page 5 Month: A correction i No. 8Q1 舛 Qq_ V. Description of the invention (3) The target county of the present invention, the temperature of sputter deposits is lower than the temperature of the formation of oxidation faults, and the thermal budget. The method of thermal emulsification of 冋, 冋, and 皿 makes it possible to reduce the gate dielectric layer of the present invention. 2. The substrate has a high coupling rate and low leakage. The purpose is to form on the substrate. The ancients formed a mouth layer. This hafnium oxide layer can reduce the oxygen content of the electric explosion and the number of electric charges. In order to show a lower secondary threshold voltage and a good gate 2 charge gain, another purpose of the present invention is to increase the c property of the gate dielectric layer. Body component reliability. The flash memory mainly annihilates the purpose of the flash: in one embodiment, the structure of the most ingenious blade of the present invention is read in silicon nitride, and the structure is extremely contained in a substrate ~ ^ A gate W electrical layer is formed. A gate oxide layer was formed on the substrate of the gate s 户兮 #, and a servant layer formed a polycrystalline silicon sound at the lice-forming fault layer and the gate of the silicon oxide # Lapu. Then, a photoresist layer is defined on the silicon oxide layer in order to etch s 1 μm. Moreover, the gate is formed! Conveniently, the nitrogen-cut layer and the oxidized layer are formed into a source and a drain. The previous method of ion implantation in the substrate is described in detail in the 5-4 invention. Page 6 506051 ---- Case No. 89125961 _ Year, Month, and Day Article 5. Description of the Invention (Magic " " " '' ^ Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely applied in other embodiments, the scope of the present invention is not limited, and the scope of the following patents For reference, please refer to the second figure, which is a direct-flow sputtering system. A reaction chamber 2 θ 〇 is mainly composed of a cathode electrode placing a metal target 21 〇, and a crystal base 10 3 00 (can be grounded), and a baffle 2 220. The gas required for holding the plasma and sputtering is provided by the gas supplier 240 at the other end of the reaction chamber, and the other end leads to the reaction chamber 2 〇〇 The degree of vacuum; (pump) 280. The energy required for the operation of the plasma is provided by a group of DC power supplies 250. Among them 'ground shields (gr 0 und, shield) 230A, 230B , 230C and 230D are located on both sides of the crystal base 300 and the metal target 210. In order to make electricity The positively charged ions in the slurry can hit the surface of the metal target 210, and the electrode on which the metal target 210 is placed will be connected to the DC power supply 250. Because the sputtering of metal does not have a high tolerance for impurities, especially It is oxygen and water gas, so before the metal sputtering, the pressure of the reaction chamber 200 is usually used to cryopump (Cryopump) 270 to extract these gases that have strong oxidation ability to the metal. The low pressure required before performing sputtering is the base pressure, which is usually 10-6 or even 10-7 Torr. After the reaction chamber 200 has reached the base pressure, the next step is to pass in the reaction gas to prepare for metal sputtering. Plating. Metal target before performing sputtering

進沉積\膜由此已經遭到污染，為了避免讓這些不純物帶定的岑塑，、=，並且防止合金金屬在濺鍍初期時的成份不 210iJ^a#，在金屬濺鍍的初期，通常以檔板22〇將金屬靶 S i晶片1〇隔開’使得滅鑛初期的沉積被擔在播板 Μ矣而不，會直接到底材晶片1 〇的表面。等到金屬靶2 1 0 於。j： f件穩定之後’才移開擔板220，以進行金屬的沉貝。/、中，接地遮板（gr〇Und shield)23〇A、及230D位於晶座3〇〇及金屬乾材21〇兩侧。The deposition and film have been contaminated. In order to avoid these impurities from forming certain plastics, and =, and to prevent the composition of the alloy metal at the initial stage of sputtering, it is not 210iJ ^ a #. The baffle plate 22 separates the metal target Si wafer 10 ′, so that the deposition at the initial stage of demineralization is carried on the seeding plate M0, and it will directly be on the surface of the substrate wafer 10. Wait until the metal target 2 1 0. j: The fender 220 is removed after the f pieces have stabilized to allow the metal to sink. /, In the ground shield (grOUnd shield) 23A and 230D are located on both sides of the wafer base 300 and the dry metal 21o.

在本勒明的方法中係以誥（；2丨1«(：〇]1丨11111)做為金屬犯21〇 ’在錯的金屬靶21 〇上以直流電源供應器2 5 〇提供大約丨〇〇 ^400瓦特的功率使得鍅金屬靶21〇產生離子化，並且反應至1〇〇内的總壓為4〇毫托爾。在反應室2〇〇中以氬氣做為惰 ^氣體，再通入氧氣使得氧氣與鍅離子而在底材丨〇上形成氧化錯層2 Q，其中氧化鍅層2 〇的介電常數約為2 5，所形成，厚度大約在20至70埃之間，溫度約在250至450 °C之間，壓力約為20至70毫托爾。氧化鍅層20在底材1〇上形成之後 ’將底材10移出反應室2〇〇，利用回火處理氧化鍅層20，其中處理的時間為2〇至50秒之間，而處理溫度在650至 1 〇 0 0 C之間以及總壓力為4 〇毫托爾。回火處理的目的是為了要降低氧化锆層2 0的介面陷入電荷的濃度以及可以降低傳統的氧化矽層1 2 0漏電流的問題，同時氧化錘層2 0可以考于到較佳的時依性介電崩潰特性。然而，其他的錢鍍方法如，反應性磁控濺鍍也可以應用在本發明中。In Ben Lemming's method, 诰 (; 2 丨 1 «(: 〇] 1 丨 11111) is used as the metal culprit 21〇 'on the wrong metal target 21 〇 and a DC power supply 2 5 〇 provides approximately 丨The power of 0.0000 watts makes the rhenium metal target 21 to ionize, and the reaction reaches a total pressure of 40 mTorr within 1000. Argon is used as the inert gas in the reaction chamber 2000, Oxygen is passed in to make oxygen and krypton ions form an oxide layer 2 Q on the substrate 丨. The dielectric constant of the yttrium oxide layer 20 is about 25, and the thickness is about 20 to 70 angstroms. , The temperature is about 250 to 450 ° C, and the pressure is about 20 to 70 mTorr. After the hafnium oxide layer 20 is formed on the substrate 10, the substrate 10 is removed from the reaction chamber 200 and tempered. The hafnium oxide layer 20, wherein the treatment time is between 20 and 50 seconds, and the treatment temperature is between 650 and 1000 C, and the total pressure is 40 mTorr. The purpose of the tempering treatment is to reduce The interface of the zirconia layer 20 sinks into the concentration of charge and can reduce the leakage current problem of the conventional silicon oxide layer 120. At the same time, the hammer oxide layer 20 can In consideration of better time-dependent dielectric breakdown characteristics, however, other money plating methods such as reactive magnetron sputtering can also be used in the present invention.

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^ 根據第二圖，係在氧化锆層2 0上形成一氮化矽層2 2。氮化矽層22是用來取代傳統的浮置閘（n〇ating Gate)，以做為儲存電荷所用。一般而言氮化矽層22依其功能分別以低壓化學氣相沉積（LPCVD，L〇w Pressure Chemical^ According to the second figure, a silicon nitride layer 22 is formed on the zirconia layer 20. The silicon nitride layer 22 is used to replace a conventional floating gate for storing electric charges. Generally speaking, the silicon nitride layer 22 is respectively formed by low pressure chemical vapor deposition (LPCVD, Low Pressure Chemical

Vapor Deposition)或是電漿促進化學氣相沉積（pECVD， Plasma Enhanced Chemical Vapor Dep〇siti〇n)法在氧化鍅層20上形成。而低壓化學氣相沉積方法，操作溫度太高約為650至800 t：之間，因此在保護層的應用上，氮化矽層 22都是以電漿促進化學沉積的方式來形成，其中形成的溫度約在250至400 C之間，而沉積的厚度約為2〇至ι8〇埃之間。一般而言，形成氮化矽22的反應材料有矽甲烷（ Silane，即SiH4)以及四氧乙基矽（TE〇s，Tetra —Ethyl —(Vapor Deposition) or plasma-enhanced chemical vapor deposition (pECVD) method is formed on the hafnium oxide layer 20. However, the low-pressure chemical vapor deposition method has an operating temperature that is too high between about 650 and 800 t: Therefore, in the application of the protective layer, the silicon nitride layer 22 is formed by a plasma-promoted chemical deposition method, in which The temperature is about 250 to 400 C, and the thickness of the deposition is about 20 to ι80 Angstroms. Generally speaking, the reaction materials for forming the silicon nitride 22 include silane (SiH4) and tetraoxyethyl silicon (TEOs, Tetra —Ethyl —

Oi^tho-Siljcate )分別與氧（〇2)以及氧化氮（N2〇)反應之後形成。接著，再利用化學氣相沉積（CVD，Chemical Vap〇r Deposition)法在一氮化矽層22上形成一氧化矽層24。矽層然後，以低壓化學沉積（LPCVD，L〇w Pressure Chemical Vapor Deposition)在氧化層24形成一多曰e 5 0，其中多晶矽層5 0是藉著矽甲烷經加熱後解離（ Decompose)的方式，在氧化矽層24上形成所須的多晶矽層 5〇。。般而a ，形成多晶矽層5 〇時，溫度大多控制在6 〇〇至650 °C之間，而反應壓力約在數百毫托爾左右，多晶矽層50形成的厚度約為80 0至2〇〇〇埃之間。接著，圖像轉移光阻層在多晶矽層50上且圖像轉移圖案為一閘極，接著，利用一光阻遮罩依序I虫刻多晶矽層50，氧化矽層24，氮化Oi ^ tho-Siljcate) is formed after reacting with oxygen (02) and nitrogen oxide (N2O), respectively. Next, a chemical vapor deposition (CVD) method is used to form a silicon oxide layer 24 on the silicon nitride layer 22. The silicon layer is then formed by low pressure chemical deposition (LPCVD, Low Pressure Chemical Vapor Deposition) on the oxide layer 24 to form e 50, where the polycrystalline silicon layer 50 is decomposes by heating with silicon methyl chloride. A desired polycrystalline silicon layer 50 is formed on the silicon oxide layer 24. . Generally, when the polycrystalline silicon layer 50 is formed, the temperature is mostly controlled between 600 and 650 ° C, and the reaction pressure is about several hundred mTorr. The thickness of the polycrystalline silicon layer 50 is about 80 to 20. 〇〇Angels. Next, the image transfer photoresist layer is on the polycrystalline silicon layer 50 and the image transfer pattern is a gate. Then, a photoresist mask is used to sequentially etch the polycrystalline silicon layer 50, the silicon oxide layer 24, and nitride.

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矽層22以及氧化錯層20而形成一閘極結構，接著再將光層移除。 ' 、參考第四圖，在底材1〇上藉由離子植入輕摻雜汲極區 r 以及14 (Light-Doped Drain，LDD)。接著，一均句覆蓋矽層沉積在底材與閘極結構上。此晶片覆蓋在均|覆氧化夕層疋且利用非等向性|虫刻（a n i s 〇 t Γ 〇 p i C a 1 etching)在閘極結構的侧邊形成間隙壁。因為此非等向性 = 要蝕刻沉積氧化石夕的厚度，氧化石夕層在閘極結The silicon layer 22 and the oxide layer 20 are oxidized to form a gate structure, and then the optical layer is removed. With reference to the fourth figure, lightly doped drain regions r and 14 (Light-Doped Drain, LDD) are implanted on the substrate 10 by ion implantation. Next, a uniform layer of silicon is deposited on the substrate and gate structure. This wafer is covered with an oxide layer, and a gap is formed on the side of the gate structure by using anisotropic | insect etching (an n s 〇 t Γ 〇 p i C a 1 etching). Because this anisotropy = the thickness of the oxide oxide layer to be etched, the oxide oxide layer is at the gate junction

猛旱度大於其他的部份，但在此蝕刻步驟並不會將你a、石9去除。因此，間隙壁26以及28在閘極結構的側邊然後，及28做為一及汲極1 2。礙或是高固深的離子。根據第五圖，利用所有的閘極結構與間隙壁2 6 遮罩，利用離子植入的方式以形成源極區1 1以，，子植人為一重摻雜（Heavy Doping)以及 I =解度砷可以離子化以實行濃度更高以及更此離子植入的濃度約為1〇15每平方公分。在這一由於氧化锆傳統的以熱低了熱預算因而降低以可以降低晶較層氧〇及胞佳是化另提的實以法外昇缺施濺形 j 例鍍成由電密中’以氧化錘做為隧道式的方式形成，其形成的溫間氧化層的溫度。因此，於氧化鍅的高介電常數，荷増益。再者，高耦合率加閘介電層的完氧化度遠大幅控制的氧整性層。低於的降電壓化鍅，因了陷The degree of drought is greater than other parts, but this etching step will not remove you a, stone 9. Therefore, the spacers 26 and 28 are on the side of the gate structure, and 28 and 28 serve as one and the drain 12. Or high solids and deep ions. According to the fifth figure, all gate structures and spacers 2 6 masks are used, and ion source implantation is used to form the source regions 1 1 to 1. The seeds are heavily doped and I = resolution. Arsenic can be ionized to perform higher concentrations and the ion implantation concentration is about 1015 cm 2. In this traditional zirconia, the thermal budget is lowered due to the lower heat budget, which can reduce the crystal layer oxygen and the cell strength. In addition to the actual method, it is applied in the form of a sputter shape. The oxide hammer is formed in a tunnel manner, and the temperature of the inter-temperature oxide layer formed by the hammer is used. Therefore, the high dielectric constant of hafnium oxide is beneficial. Furthermore, the high coupling rate plus the complete oxidation of the gated dielectric layer greatly controls the oxygen integrity layer. The voltage drop below is reduced due to the trap

第10頁 506051 _案號89125961_年月曰修正_ 五、發明說明（8) 而增加了快閃記憶體的可靠性。以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍内。Page 10 506051 _Case No. 89125961_ Year Month Revision _5. Description of the invention (8) The reliability of flash memory has been increased. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

第11頁 506051 _案號89125961_年月日__ 圖式簡單說明第一圖為一半導體晶片的截面圖，以說明在傳統的氮化矽唯讀記憶體中形成閘介電層傳統示意圖；第二圖為一表示用於形成閘介電層方法的一裝置示意圖；第三圖為根據本發明之一半導體晶片的截面圖，以說明在底材上形成閘介電層的步驟示意圖；第四圖為根據本發明之一半導體晶片的截面圖，以說明根據本發明以形成間隙壁的步驟示意圖；第五圖為根據本發明在氮化矽唯讀記憶體中形成一閘介電層之示意圖。主要部分之代表符號： 10 底材 11 源極 12 汲極 13 N井 14 N井 20 氧化锆層 22 氧化矽層 24 氮化碎層 26 間隙壁Page 11 506051 _Case No. 89125961_ 年月日 __ Brief description of the drawings The first diagram is a cross-sectional view of a semiconductor wafer to illustrate the traditional schematic diagram of forming a gate dielectric layer in a conventional silicon nitride read-only memory; The second figure is a schematic diagram showing a device for forming a gate dielectric layer method; the third figure is a cross-sectional view of a semiconductor wafer according to the present invention to explain the steps of forming a gate dielectric layer on a substrate; The fourth figure is a cross-sectional view of a semiconductor wafer according to one of the present invention to illustrate the steps for forming a spacer according to the present invention; the fifth figure is a view of forming a gate dielectric layer in a silicon nitride read-only memory according to the present invention. schematic diagram. Representative symbols of the main parts: 10 substrate 11 source 12 drain 13 N well 14 N well 20 zirconia layer 22 silicon oxide layer 24 nitrided layer 26 gap wall

506051 修正案號 89125961 圖式簡單說明 2 8 間隙壁 5 0多晶矽層 1 0 0 底材 1 0 1 源極 1 0 2 汲極 103 N 井 104 N 井 1 2 0 氧化矽層 1 2 2 氮化矽層 124 氧化矽層 1 2 6 間隙壁 1 2 8 間隙壁 2 0 0 反應室 210 金屬靶 2 2 0擋板 2 3 0 A接地遮板 2 3 0 B接地遮板 2 3 0 C接地遮板 2 3 0 D接地遮板 240 氣體供應源 2 5 0 直流電供應源 2 6 0 隔離閥 270 冷凍幫浦 2 8 0機械式幫浦 2 9 0 接地線506051 Amendment number 89125961 Brief description of the drawing 2 8 Spacer wall 5 0 Polycrystalline silicon layer 1 0 0 Substrate 1 0 1 Source 1 0 2 Drain 103 N Well 104 N Well 1 2 0 Silicon oxide layer 1 2 2 Silicon nitride Layer 124 Silicon oxide layer 1 2 6 Gap wall 1 2 8 Gap wall 2 0 0 Reaction chamber 210 Metal target 2 2 0 Baffle 2 3 0 A ground shield 2 3 0 B ground shield 2 3 0 C ground shield 2 3 0 D ground shield 240 Gas supply source 2 5 0 DC power supply source 2 6 0 Isolation valve 270 Freezing pump 2 8 0 Mechanical pump 2 9 0 Ground wire

第13頁 506051 案號89125961_年月日修正圖式簡單說明 3 0 0晶片支座參參第14頁Page 13 506051 Case No. 89125961_Year Month and Day Amendment Brief description of the drawing 3 0 0 Wafer support See page 14

Claims

六six

修正 ^:種在一氮化矽唯讀記憶體中形成-閘介電層的方法，该方法至少包含： "电增扪刀汰申請專利範圍提供^一底材；以及在該底材上利用濺鍍法形成一氧化錯層做A形成兮新化石夕唯讀記憶體中的該間介電層日U為H衾亂中形志兮P爿八φ麻 ^ ^ 在邊虱化矽唯讀記憶體 8〇0它之間。八中形成忒虱化錘的溫度約在2 0 0至其中上述氧化锆層係利成。其中上述在該底材上形更包含以一回火步驟處Amendment ^: A method for forming a gate dielectric layer in a silicon nitride read-only memory, the method at least includes: " A substrate provided by the patent application scope of electrical increase; and a substrate on the substrate; A sputtering layer is used to form a monolayer of oxide. A is formed. The dielectric layer in the read memory is U. The shape of U is H. The shape of P is φ. Hemp ^^ ^ On the edge of the silicon wafer. Read memory 8000 between it. The temperature for forming the tick hammer in Bazhong is about 200 to 200 ° C. The above zirconia layer system is beneficial. The above-mentioned shape on the substrate further includes a tempering step.

2·如申請專利範圍第1項之方法，用反應性磁控濺鍍法在該底材上形 3·、如^申請專利範圍第1項之方法，成的氧化錯層厚度約為20至70埃。 4·如申請專利範圍第丨項之方法，理該氧化锆層。 6 ·如申凊專利範圍第4 氣體環境為惰性氣體。項之方法，其中上述之回火處理的2. If the method according to item 1 of the scope of patent application is applied, use reactive magnetron sputtering to form the substrate on the substrate 3. If the method according to item 1 of the scope of patent application, the thickness of the oxidized layer is about 20 to 70 Angstroms. 4. According to the method in the scope of patent application, the zirconia layer is treated. 6 · The gas environment is the inert gas as described in the 4th patent application. Item method, wherein the tempering

種在氮化石夕唯讀記憶體中形成一閘介電層的方法Method for forming a gate dielectric layer in nitride nitride read-only memory

第15頁 506051 案號 89125961 年月日六、申請專利範圍該方法至少包含：提供一底材；在該底材上利用濺鑛法形成一氧化锆層做為形成該^ 化石夕唯讀記憶體中的該閘介電層’在該氮化矽唯讀記^ 中形成該閘介電層；以及 ' °〜對該氧化锆層進行一回火處理步驟。 8·如申請專利範圍第7項之方法，其中上述氧化锆層係利用反應性磁控減:鍍法在該底材上形成。 9 ·如申請專利範圍第7項之方法，其中上述形成該氧化錯層的溫度約2 0 0至8 0 0 °C之間。 I 0 ·如申請專利範圍第7項之方法，其中上述在該底材上形成的氧化錯層厚度約為20至70埃。 II ·如申請專利範圍第7項之方法，其中上述之回火的步驟溫度約6 5 0至1 0 0 0 °C之間，時間約為2 0至5 0秒之間。 1 2 ·如申請專利範圍第7項之方法，其中上述之回火處理的氣體環境為惰性氣體。 1 3 ·如申請專利範圍第7項之方法，其中上述回火處理時的環境是選自於由氬氣，氮氣以及氧化氮所組成的族群之Page 15 506051 Case No. 89125961 6. The scope of the patent application The method at least includes: providing a substrate; forming a zirconia layer on the substrate by a sputtering method to form the ^ fossil evening read-only memory The gate dielectric layer in the 'forms the gate dielectric layer in the silicon nitride read-only note; and' ° ~ a tempering step is performed on the zirconia layer. 8. The method according to item 7 of the scope of patent application, wherein the zirconia layer is formed on the substrate by a reactive magnetron subtraction: plating method. 9. The method according to item 7 of the scope of patent application, wherein the temperature at which the oxide layer is formed is between about 200 and 800 ° C. I 0 · The method according to item 7 of the scope of patent application, wherein the thickness of the oxide layer formed on the substrate is about 20 to 70 angstroms. II. The method according to item 7 of the patent application range, wherein the tempering step is performed at a temperature of about 6500 to 100 ° C and a time of about 20 to 50 seconds. 1 2 · The method according to item 7 of the scope of patent application, wherein the gas environment of the above-mentioned tempering treatment is an inert gas. 1 3 · The method according to item 7 of the scope of patent application, wherein the environment during the tempering treatment is selected from the group consisting of argon, nitrogen and nitrogen oxide.

lili

第16頁 506051 8912RQR1 修正曰六、申請專利範圍中〇 14·—種在形成氮化矽唯綠#卜立_ 士 &七、也 X 、么石包含· ％項g己憶體中的方法，該方法至少提供一底材； $:，材上以濺鍍法形成—氧化锆層；對该氧化錯層進行一回火步驟；在該氧化錯層上形成—氮化矽声. 在該氮化矽層上形成—氧化矽；· 在該氧化矽層上形成—多晶矽；：在該多晶矽層上形成_光阻，^ j * 、、極圖案，以形成一光阻遮罩；该光阻係定義成一閘利用該光阻做為遮罩以蝕刻兮夕曰，該氮化矽層以及該氧化錯層以形：：矽層，言亥氧化矽層移除該光阻層； ^ —閘極；在閘極的側壁上形成間隙壁；以及在该底材内，該閘極的兩侧形 — 源極以及一汲極。 15·如申請專利範圍第1 4項之方法，其用反應性磁控濺鍍法在該底材上形成了上述氣化鍅層利 16·如申請專利範圍第1 4項之方法，其中锆層的溫度約在2 0 0至8 0 0 °C之間。 ’、上述形成該氧化第17頁 506051 _案號89125961_年月日_魅_ 六、申請專利範圍 17. 如申請專利範圍第1 4項之方法，其中上述該氧化銼層在底材上形成的厚度約在2 0至7 0埃之間。 18. 如申請專利範圍第1 4項之方法，其中上述回火處理該氧化锆層的溫度約在6 5 0至1 0 0 0 °C之間以及該回火的時間約2 0至5 0秒之間。Page 16 506051 8912RQR1 Amendment VI. In the scope of patent application 〇14 · —A method of forming silicon nitride only green # 卜立 _ 士 & VII, also X, Mo Shi contains ·% item g memory The method provides at least one substrate; $ :, a zirconia layer is formed on the material by sputtering; a tempering step is performed on the oxidized oxide layer; and a silicon nitride sound is formed on the oxidized oxide layer. In the Forming a silicon oxide layer on the silicon nitride layer; forming a polycrystalline silicon layer on the silicon oxide layer; forming a photoresistor pattern on the polycrystalline silicon layer to form a photoresist mask; the light The resistance system is defined as a gate that uses the photoresist as a mask to etch. The silicon nitride layer and the oxide layer are shaped as :: silicon layer, and the silicon oxide layer removes the photoresist layer; ^ — A gate electrode; forming a gap wall on a side wall of the gate electrode; and in the substrate, both sides of the gate electrode-a source electrode and a drain electrode. 15. The method according to item 14 of the patent application, which uses the reactive magnetron sputtering method to form the above-mentioned gaseous rhenium layer on the substrate. 16. The method according to item 14 in the patent application, wherein zirconium The temperature of the layer is between 2000 and 800 ° C. '、 The above-mentioned formation of the oxidation page 17 506051 _ case number 89125961 _ month_day_ charm _ 6. Application for patent scope 17. The method of applying for the scope of patent application No. 14 wherein the above-mentioned oxide file layer is formed on the substrate The thickness is between 20 and 70 Angstroms. 18. The method according to item 14 of the scope of patent application, wherein the temperature of the above-mentioned tempering treatment of the zirconia layer is about 6 50 to 100 ° C and the time of the tempering is about 20 to 50. Between seconds.

19. 如申請專利範圍第1 4項之方法，其中上述回火處理時的環境是選自於由氬氣，氮氣以及氧化氮所組成的族群之中〇19. The method according to item 14 of the scope of patent application, wherein the environment during the tempering treatment is selected from the group consisting of argon, nitrogen and nitrogen oxides.

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