TW504701B

TW504701B - Method and circuit for performing critical erasing test onto flash memory device

Info

Publication number: TW504701B
Application number: TW90108698A
Authority: TW
Inventors: Yu-De Chr; Ching-Huang Wang; Jeng-Shiung Guo
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2001-04-11
Filing date: 2001-04-11
Publication date: 2002-10-01

Abstract

A kind of voltage adjustment circuit capable of being used for performing critical erasing test onto the flash memory device is disclosed in the present invention. The voltage adjustment circuit at least contains plural transistors, in which the drain is connected to the gate for each transistor, and the source is connected in series with the drain of the next transistor such that a voltage drop is generated by the serially connected plural transistors, and the required operation voltage of the flash memory device is then generated. A bypass loop circuit is provided in the invention for conducting the bypass voltage drop function onto part of the transistors so as to decrease the output voltage of the voltage adjustment circuit for the required test voltage when executing the critical erasing test. Thus, by adjusting the number of transistors undergone with the bypass voltage drop, the effects of controlling the difference value between the output voltage and the test voltage can be obtained.

Description

504701 五、發明說明（i) 發明領域：本發明與一種積體電路中快閃記憶體之可靠性測試有關有關，特別是一種用來對快閃記憶體進行臨界抹除測試 (marginal erase test)之方法與相關電路設計，以提昇判定快閃記憶體使用壽命的能力與可靠性。發明.背景：一般而言，在積體電路的相關設計中，往往會定義相當數里的圮憶體元件，以增加電子元件儲存資料的能力。典型的記憶元件，如動態存取記憶體（DRAM)或靜態存取記憶體（SRAM)等等揮發性記憶體，由於在當電源關閉時，所儲存之資料將完全消失，因此對於某些需要在電源切斷 J，仍可留存輸入資料的裝置、系統而言，便需使用非揮發性的記憶體疋件。例如，唯讀記憶體（R〇M)、可程式唯 1記憶體（PR0M)、可抹除可程式唯讀記憶體（EpR〇M)、電二m可程式唯讀記憶體(EEP_)、與快閃記憶體保留給等…記憶體元件’皆可在電源中斷後仍長時間504701 V. Description of the invention (i) Field of the invention: The present invention relates to the reliability test of flash memory in an integrated circuit, in particular to a marginal erase test for flash memory. Method and related circuit design to improve the ability and reliability of judging the life of flash memory. Background of the Invention: Generally speaking, in the related design of integrated circuit, a memory device of a considerable number is often defined to increase the electronic device's ability to store data. Typical memory components, such as volatile memory, such as dynamic access memory (DRAM) or static access memory (SRAM), will be completely disappeared when the power is turned off, so for some needs For devices and systems that can still store input data when the power is turned off J, non-volatile memory files are required. For example, read-only memory (ROM), programmable only memory (PR0M), erasable programmable ROM (EpROM), programmable ROM (EEP_), And flash memory reserved ... memory components' can be long after power interruption

保留輸入的資料。 j U 中，：ί第一圖’該圖顯示快閃記憶體之相關電路。其 * 對快閃記憶體元件1 Q > 、 ) 而進灯程式化（programming)或 m μ ^ 〒i(J而吕，可回應由電壓調節電路2〇所叙供的操作電壓（v ) , uKeep the entered information. In j U, the first picture is a picture showing the relevant circuits of the flash memory. Its * is programmed to the flash memory element 1 Q >,) or m μ ^ 〒i (J and Lu), which can respond to the operating voltage (v) provided by the voltage adjustment circuit 20 , u

504701 五、發明說明（2) 移除化（erasing)程序，並決定是否留存資料於快閃記憶體元件10中。至於電壓調節電路2〇則分別連接於電荷昇壓電路（charge pump)30 與電流鏡（current mirror)40。其中，藉著使用電荷昇壓電路3〇 ,可將由電源供應器輸入约 3至5 JL特的供應電壓，提高至快閃記憶體元件1〇所需的電壓位準（約10至15伏特）。並且，由於電荷昇壓電路3〇輸出的電壓往往偏高而容易造成單元胞干擾（disturb Qn cell)或元件應力（stress 〇n device)等問題，是以籍著電壓調節電路20來調整電荷昇壓電路3〇的輸出電壓，"可使其穩定的維持在所需的操作電壓值。此外，籍著連接於電❿ 壓調節電路2〇之電流鏡4〇 ,可提供電壓調節電路2〇進行電壓調節所需之操作電流。典型的電壓調節電路20，如第一圖中所顯示，是由彼此串接的二極體22與η個NM0S電晶體（Mi、M2 “·Μη)所構成。其中，對每一個NM0S電晶體而言，其汲極皆與閘極相連’而產生類似二極體元件的操作效能。並且，由於電壓調節電路2 0的尾端為接地狀態（gr〇und)，是以由電荷昇壓電路30輸出的電壓，在經過電壓調節電路2〇的調整後，會產生與整串電壓調節電路2〇壓降相等的操作電壓Vne。亦_ 即’輸入快閃記憶體元件10的操作電壓Vne，會相等於二極體22的崩潰電壓Vbd加上η個籠⑽電晶體的啟始電壓、。如此一來，藉著使用電壓調節電路20，便可提供此快閃記憶體元件ίο進行程式化/移除化程序所需的操作電壓Vne °。㈣504701 V. Description of the invention (2) The erasing process and decide whether to retain the data in the flash memory element 10 or not. The voltage regulating circuit 20 is connected to a charge pump circuit 30 and a current mirror 40, respectively. Among them, by using the charge boost circuit 30, it is possible to increase the supply voltage of about 3 to 5 JL from the power supply to the voltage level required by the flash memory element 10 (about 10 to 15 volts). ). In addition, since the voltage output from the charge booster circuit 30 is often high, it is easy to cause problems such as disturbance Qn cells or stress on the device, so the charge is adjusted by the voltage adjustment circuit 20 The output voltage of the booster circuit 30 can be stably maintained at the required operating voltage value. In addition, the current mirror 40, which is connected to the voltage regulation circuit 20, can provide the operating current required by the voltage regulation circuit 20 for voltage regulation. A typical voltage regulating circuit 20, as shown in the first figure, is composed of a diode 22 and n nMOS transistors (Mi, M2 "· Mη) connected in series to each other. Among them, for each NMOS transistor In other words, their drains are connected to the gates', which results in similar operating performance of a diode element. Moreover, since the tail end of the voltage regulation circuit 20 is in a grounded state, the voltage is boosted by the charge. The voltage output from the circuit 30 is adjusted by the voltage adjustment circuit 20 to generate an operation voltage Vne equal to the voltage drop of the entire string of voltage adjustment circuits 20. That is, 'the input operation voltage Vne of the flash memory element 10 , Will be equal to the breakdown voltage Vbd of the diode 22 plus the starting voltage of the n caged transistors. In this way, by using the voltage adjustment circuit 20, this flash memory element can be provided for programming Operating voltage Vne ° required for the chemical removal / removal procedure. ㈣

504701 五、發明說明（3) 值得注遂氧化層在陷獲（trap) 除程序的最第二圖，其最小抹除電時，.祇需要可是隨著反需.要約12. 3 且，當其反才能有效的意的是，對反覆進行抹效應而造成小電壓往往中顯示了快壓之關係。約11_· 3伏特覆使用的次伏特的電壓覆使用至1 0 進行抹除。於快閃記憶體元件而言，其間的穿除/程式化的程序中’會由於電子接合面產生缺陷，是以允許進行抹會隨著元件反覆使用而上昇^參照閃記憶體元件反覆抹除次數與所^ 當此快閃記憶體元件剛開始使用的操作電壓，即可進行抹除程序。數增加，當其使用約5萬次時，便，才能有效的進行抹除動作。並萬次時，更需要約14伏特的高壓，電路2=提所需的最小抹除電壓超過電壓調節 I法Μ墙# '、的刼作電壓Vne後，快閃記憶體元件1 0便士，JL接你發π田…、，對於所製作的快閃記憶體元件而 s，其操作電壓Vne舍鉍；μ也令愛Vne會較疋件實際所需的最小抹除電壓同’以產生一段電壓差且，為了判斷此快閃纪時^此70件可反覆的使用。並格需求，在製作出快件10的使用壽命是否符合規低的測試電壓Vme來閃體元件10後，可藉著利用一較 eFase tes1;>。士 70件進行臨界抹除測試（marginal 請參照第三圖 ’此圖顯示了目前業界進行臨界抹除測504701 V. Description of the invention (3) Worth to note is the second picture of the trap removal process, the minimum erasing of electricity, it only needs to follow the reverse demand. It is about 12.3 and when The opposite is effective meaning is that fast voltage is often shown in the small voltage caused by repeated wiping effect. Approx. 11_ · 3 Volts Sub-Voltage Used Subsequent to 1 0 for erasing. For flash memory components, during the erasing / programming process, 'there will be defects due to the electronic joint surface, so it is allowed to erase as the component is used repeatedly. Refer to flash memory components repeatedly erased. Number of times and operating voltage When the flash memory element has just been used, the erasing process can be performed. The number increases. When it is used about 50,000 times, it can be effectively wiped. When 10,000 times, a high voltage of about 14 volts is needed. Circuit 2 = The minimum erasing voltage required exceeds the voltage adjustment I wall #, the operating voltage Vne of the flash memory device, and the flash memory element 10 pence. JL will send you π field ... For the flash memory device, the operating voltage Vne is bismuth; μ also makes love Vne the same as the minimum erasing voltage required by the file to generate a segment Voltage difference, and in order to determine the flash time, these 70 pieces can be used repeatedly. It is required that after the flash element 10 is manufactured to determine whether the service life of the shipment 10 meets the low test voltage Vme, the eFase tes1; > can be used. 70 pieces were tested for critical erasure (marginal please refer to the third picture ’)

504701504701

其中玉、發明說明（4) 試之裝置。 52，而產生閃記憶體之於所製作的規格的要求境因素，每當的差異，因此，當使時，並無法規袼需求。一固定晶片54 晶片54 ，但實一個晶而如第用較低精確的可經由、且較進行臨 m3 a ，際上受片54所四圖所且固定判斷出外接的低的測界抹除僅管其制於製具有的示，呈的測試這些晶同壓裝置50與串接的電試電壓Vme，來對具有快測試。值得注意的是，對在相關製程中皆符合相關程參數的漂移與可能的環操作電壓Vne仍會產生相現出高斯狀的曲線分佈。電壓Vme來進行抹除測試片54的使用壽命是否符合參照片而言，皆可成功說，其臨界區段B) 界測試，持較長的時，使所的估計出 j 丄例如對實際操作電壓為VneuVne2的晶便用/固疋且較低的測試電壓Vme對其進行測試，的^行抹除動作。但就操作電壓為Vnel的晶片來界區段A顯然會較操作電壓為Vne2的晶片（具有臨 2的=。換句話說，僅管此兩種晶片皆可通過臨但在，際使用時，具有臨界區段Β的晶片將可維使用壽命。是以，如果能在進行臨界移除測試 f的晶片皆滿足相同的臨界區段，則當可進一步這些晶片的使用壽命。發明目的及概述：本發明之目的為提供一種可直接利用電壓調節電路來Among them, jade, invention description (4) test device. 52, and the requirements of the produced flash memory due to the specifications of the environment, whenever there is a difference, so when using, it is not possible to regulate the demand. A fixed chip 54 and a chip 54, but a solid crystal can be passed with a lower accuracy, and is more prone to pass the m3a, and it is fixed by the four maps of the film 54 and it is fixed to determine the external low boundary of the erase. Regardless of the indications made by the manufacturer, the test is performed by testing the crystal same-pressure device 50 and the electrical test voltage Vme connected in series. It is worth noting that the drift and the possible loop operating voltage Vne, which all meet the relevant process parameters in the relevant process, will still produce a Gaussian-like curve distribution. The voltage Vme is used to determine whether the service life of the test strip 54 is consistent with the reference photos. It can be successfully said that the critical section B) of the boundary test. When it is longer, the estimated j 丄 is, for example, for actual operation. The crystal with a voltage of VneuVne2 is tested with a low test voltage Vme, and the erase operation is performed. But for the wafer with operating voltage Vnel, it is clear that sector A will be better than the wafer with operating voltage Vne2 (with Pro = 2. In other words, only these two kinds of wafers can pass through Pro, but when in use, Wafers with critical section B will maintain their service life. Therefore, if the wafers that can be subjected to the critical removal test f meet the same critical section, the service life of these wafers can be further improved. Purpose and summary of the invention: The object of the present invention is to provide a voltage regulation circuit which can directly use

^U4/U1^ U4 / U1

五、發明說明（5) 產生進行臨界抹除測試所需測試電壓之設計與電路。本發明之又一目的為提供一種可隨著積體電路輸出電々不同，而產生相對應臨界抹除測試電壓之電壓調節電路，以便進一步提昇所製作晶片的可靠度。本發明元件進行臨壓電路，可件所需操作回應於電荷調整，而產調節電路包汲極與閘極接’使複數所需的測試晶體的頭、導通時，可低電壓調節所需的測試路，以提供揭露了一種可利用電界抹除測試之晶片。將電源供應的輸入電電壓之位準。另外，昇壓電^，可對電荷生快閃記憶體元件所含複數個NMOS電晶體相連’而源極則與下個NMOS電晶體以串連電壓，可提供一旁通尾兩端，可以切換開對部份NMOS電晶體產電路的輸出電壓，以電壓。此外，一電流電壓調節電路進行操壓調節電路對快此晶片至少包含壓，提昇至快閃亦包括了電壓調昇壓電路輸出的需的操作電壓。 ’且每一個NMOS 一個NMOS電晶體方式產生壓降。迴路，連接於部關加以控制，當生旁通降壓之效作為進行臨界抹鏡，耦合於電壓作所需之操作電閃記憶體了電荷昇記憶體元節電路，電壓進行其中電壓電晶體之之淡極串為了產生份NMOS電旁通迴路果，而降除測試時調節電流0 發明詳細說明：5. Description of the invention (5) Design and circuit for generating test voltage required for critical erasure test. Another object of the present invention is to provide a voltage adjustment circuit that can generate a corresponding critical erasure test voltage as the output circuit of the integrated circuit is different, so as to further improve the reliability of the fabricated wafer. The element of the invention performs a voltage-receiving circuit, and the required operation can be responded to the charge adjustment, and the production adjustment circuit includes a drain connected to a gate, so that a plurality of test crystal heads required for low voltage adjustment can be adjusted when conducting Test circuit to provide a chip that can be used for electrical erasure testing. Level the input voltage of the power supply. In addition, the boost voltage ^ can be connected to a plurality of NMOS transistors included in the charge generation flash memory element, and the source is connected to the next NMOS transistor in series voltage, which can provide a bypass tail at both ends, which can be switched Turn on the output voltage of some NMOS transistor to the voltage. In addition, a current and voltage adjustment circuit performs the operation of the voltage adjustment circuit. The chip contains at least voltage, and the promotion to fast flashing also includes the required operating voltage output by the voltage adjustment boost circuit. ’And one NMOS transistor per NMOS generates a voltage drop. The circuit is connected to the gate for control. When the effect of bypass voltage reduction is used as a critical wiper, the flash memory is coupled to the voltage operation required. The electric charge rises the memory element circuit. The voltage is performed by the voltage transistor. In order to generate the NMOS electrical bypass circuit, the light pole string reduces the adjustment current during the test. 0 Detailed description of the invention:

504701 五、發明說明（6) 請參照第五圖，此圖顯示了本發明所提供用來對晶片 100進行臨界抹除測試之相關設計。其中，如同上述在此晶片100中包括了一電壓調節電路120，用來產生操作電壓 Vne ’以提供快閃記憶體元件130進行程式化 (programming)或移除化（erasing)程序。此電壓調節電路 120分別連接於電荷昇壓電路（charge p{imp)14〇與電流鏡 Ceui*i*ent mirror)l5〇。其中，電荷昇壓電路14〇可將電源輸入的供應電壓·，提昇至快閃記憶體元件1 3 〇進行操作所需的電壓位準。至於，電流鏡150則可用來提供電壓調節電路120所需的操作電流，以維持電壓調節電路120的運作狀態。至於電壓調節電路12〇則可用來調整電荷昇壓電路丨4〇輸出的電壓，使其維持在較穩定的操作電壓Vne ,以提供快閃記憶體元件130操作之用。如同第五圖所示，本發明所提供的電壓調節電路120，亦包括了彼此串接的二^體 122與η個NM0S電晶體（Μ1、Μ2···Μη)所構成。其中二極體 122的負端分別連接至電荷昇壓電路14〇與快閃記憶體元件 130，而正端則與串接於隨〇s電晶體们之汲極。對每一 NM0S電晶體而言，其进搞磁叙關你知、盡 . -長及極白與閘極相連，而產生類似二極體疋件的操作效能，至於其源極部份則會與下一個㈣〇s 晶體的汲極相連，而形成串接的結構。值得注意的，在本發明中為了產生臨界抹除測試之功504701 V. Description of the invention (6) Please refer to the fifth figure, which shows the related design for critical erasure test of the wafer 100 provided by the present invention. Among them, as mentioned above, the chip 100 includes a voltage adjustment circuit 120 for generating an operating voltage Vne ′ to provide a flash memory element 130 for programming or erasing procedures. The voltage adjusting circuit 120 is connected to a charge boosting circuit (charge p {imp) 14o and a current mirror Ceui * i * ent mirror 1550, respectively. Among them, the charge boost circuit 14 can raise the supply voltage of the power input to the voltage level required for the flash memory element 130 to operate. As for the current mirror 150, the operating current required by the voltage regulating circuit 120 can be provided to maintain the operating state of the voltage regulating circuit 120. As for the voltage adjustment circuit 120, it can be used to adjust the output voltage of the charge boost circuit 4o to maintain it at a relatively stable operating voltage Vne, so as to provide the operation of the flash memory element 130. As shown in the fifth figure, the voltage regulating circuit 120 provided by the present invention also includes a diode 122 and n NMOS transistors (M1, M2 ... Mn) connected in series to each other. The negative terminal of the diode 122 is connected to the charge boost circuit 14 and the flash memory element 130, respectively, and the positive terminal is connected in series to the drain of the 0s transistors. For each NM0S transistor, you need to know and understand the magnetic description. -The long and extremely white is connected to the gate, which results in the operation efficiency of a diode-like component. As for the source part, Connected to the drain of the next ㈣0s crystal to form a tandem structure. It is worth noting that in order to generate a critical erasure test in the present invention,

第9頁五、發明說明（7) _一" 能’可在位於整串元件尾端之部份歷〇§電晶體上，製作旁通迴路124。其中此旁通迴路124上並具有切換開關126，备切換開關126接通時，經由旁通降壓的效果，可降低電㈣節電糊的輸出電壓Vnee反之，當二了關= 斷時_，f]電壓調節電路12〇的輪出電壓Vne會恢復原來的位準。如此一來’藉著控制切換開關126便可有效的調整Vne 的大小。並且，由於對每一個題〇s電晶體（jn至Mn)而言，其啟始電壓值大·約為〇·4~0·5伏特。因此，藉著決定旁通迴路124所含括的電晶體數量，便可精準的控制輸出電壓 Vne降低的幅度。例如，當操作者欲調整輸出電壓Vne，使其降低约1伏特時，可在彼此串接的腿〇s電晶體與心鬌其兩端形成旁通迴路124。如此，當所生產的晶片1 〇〇需要進行臨界抹除測試時’.便可接通旁通迴路124，而使電壓調節電路12〇的輸出電壓Vne降低至預定的位準，以作為測試電壓Vme使用。此時，對每一個晶片1 〇〇來說，儘管受制於製程條件與環境的差異，其Vne會呈現高斯曲線的分佈，但由於可藉著旁通迴路124來控制壓降的大小，是以對所有的晶片1〇()而言’其輸出電壓Vne與測試電壓vme的壓差將會維持在定 f丨值。請參照第六圖，其中顯示出在進行臨界抹除測試時，晶片100的測試電壓Vme會呈現與輸出電壓Vne相同形狀的高斯分佈。並且，對操作電壓為Vnel的晶片來說，其測試出來的臨界區段C會與操作電壓為Vne2晶片的臨界區段1)相 U / 丄五、發明說明（8) 等0如此一來，對通過臨界臨展F，比知* m t〖列试的晶片100而言，由於其臨界£段皆相等，因此其使災用I命亦會較為平均。使用具有湘„當抹除測試以並不需生所需的本發明的實際操作晶片進行利於元件 ί發明的#法來對生產的晶片進行臨界抹除測試的優點。例如，在本發明中由於用來進行臨界之電壓Vme疋來自晶片中的電壓調節電路，是要像傳統技術中一樣，使用額外的高壓裝置來產電壓。其次’相較於傳統的測試技術而言，由於方法與電路設計，可以固定測試電壓Vme與晶片電壓Vne的差距，是以在對製程參數有所變化的、】试時將可使相關的耐受能力趨於一致，而俾可靠度的测試與提昇。本發明雖以一較佳實例闡明如上，然其並非用以限定本發明精神與發明實體，僅止於此一實施例爾。因此，在 =脫離本發明之精神與範圍内所作之修改，均應包含在下述之申請專利範圍内。Page 9 V. Explanation of the invention (7) _ 一 " Can 'can make the bypass circuit 124 on the transistor located at the tail end of the whole string of components. The bypass circuit 124 has a changeover switch 126. When the backup changeover switch 126 is turned on, the output voltage Vnee of the power-saving paste can be reduced by the effect of bypassing the voltage drop. When the second switch is off = the switch is off_, f] The wheel-out voltage Vne of the voltage adjustment circuit 12 will restore the original level. In this way, by controlling the switch 126, the size of Vne can be effectively adjusted. In addition, since each of the 0s transistors (jn to Mn) has a large initial voltage value of about 0.4 to 0.5 volts. Therefore, by determining the number of transistors included in the bypass circuit 124, it is possible to accurately control the reduction of the output voltage Vne. For example, when the operator wants to adjust the output voltage Vne to reduce it by about 1 volt, a bypass circuit 124 may be formed between the leg 0s transistor connected in series with each other and the heart end. In this way, when a critical erasure test is performed on the produced wafer 100, the bypass circuit 124 can be turned on, and the output voltage Vne of the voltage adjustment circuit 120 can be reduced to a predetermined level as the test voltage. Vme is used. At this time, for each wafer 100, although subject to differences in process conditions and environment, its Vne will show a Gaussian curve distribution, but because the size of the voltage drop can be controlled by the bypass circuit 124, For all the chips 10 (), the voltage difference between the output voltage Vne and the test voltage vme will be maintained at a constant f 丨 value. Please refer to the sixth figure, which shows that when the critical erasure test is performed, the test voltage Vme of the chip 100 will have a Gaussian distribution with the same shape as the output voltage Vne. And, for a wafer with an operating voltage of Vnel, the critical section C tested will be the critical section 1 of the wafer with an operating voltage of Vne2. 1) U / / 5, Invention Description (8), etc. For the critical 100 wafers that passed the critical trial F, compared to * mt, the critical £ segments are all equal, so the disaster I life will be more average. The advantage of using the #method with the practical method of the present invention that does not require the actual operation of the wafer to perform the critical # erase method for critically erasing the produced wafer is, for example, in the present invention, because The voltage Vme used to carry out the threshold comes from the voltage regulating circuit in the chip, which is to use the extra high-voltage device to generate voltage like in traditional technology. Secondly, compared to traditional testing technology, due to the method and circuit design The gap between the test voltage Vme and the chip voltage Vne can be fixed, so that when the process parameters are changed, the relevant tolerance can be made uniform during the test, and the reliability can be tested and improved. Although the invention is illustrated as above with a preferred example, it is not intended to limit the spirit and the inventive substance of the invention, but only to this embodiment. Therefore, all modifications made within the spirit and scope of the invention should be changed. It is included in the scope of patent application described below.

第11頁 504701 圖式簡單說明藉由以下詳細之描述結合所附圖示，將可輕易的上述内容及此項發明之諸多優點，其中·· 第一圖作具身、快閃 f-* tsj 一—|B^| 次數舆所需第三圖除測試時所第四圖製程參數影佈；第五圖體電路晶片第六圖測試電壓將除測試之可為電路架構圖，顯示根據目前半導體技術記憶體之積體電路； 1 為實驗數據圖，顯示快閃記憶體元件反覆抹除最小抹除電壓之關係； “ 為f路架構圖，顯示根據目前業界進額外增加之裝置；琢為實驗數據圖，顯示製作的積體電路晶片由於響，而使其操作電壓呈現出如高斯狀的曲線分為電路架構圖，顯示了本發明所楹 m ^ ^ κ it ^ ^ ^ 73所钕供用來對積遘仃臨界抹除測忒之相關配置·及 ί實驗數據圖，顯示使用本發明電路所提供的 2應南斯狀分佈的操作電壓，而増加臨界抹Page 504701 Brief description of the drawings By combining the following detailed description with the attached drawings, the above content and the many advantages of this invention can be easily made. Among them, the first picture is a body, flashing f- * tsj I— | B ^ | The third picture is required to show the process parameters of the fourth picture except for the test; the fifth picture is the circuit chip and the sixth picture is the test voltage. Integrated circuit of technical memory; 1 is an experimental data diagram showing the relationship between the minimum erasing voltage of the flash memory device repeatedly erased; "is a diagram of the f road structure showing an additional device added according to the current industry; it is considered an experiment The data graph shows that the fabricated integrated circuit chip has a Gaussian-shaped curve due to the response, and is divided into circuit architecture diagrams, showing the 钕 m ^ ^ κ it ^ ^ ^ 73 neodymium for use in the present invention. The relevant configuration of the critical erasure test and the experimental data diagrams show that the operating voltage of the 2 Yingesian distribution provided by the circuit of the present invention is used, and the critical erasure is added.

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Claims

六、申請專利範圍專利申請範圍： 1. 一種可用來對快閃記情於_ i 之電壓調節電路，該電 /體70件進行臨界抹除測試體，其中每一個該電1 電路至少包含複數個電晶下'個該電晶體之没：串接' 源極則與麗，其中可Ϊ供記憶體元件所需的操作電壓之功能，而；該電壓3部份該電晶體進行旁通降進仃臨界抹除測試時所需的測試電^出電壓祕以作為路之2頭端如專利範圍第1項之電路，其中該電壓調節電 4^之頭端了耦接於電荷異饜該電荷昇壓雷敗趴^ 電（Ρ·Ρ) ^以便對壓。订幵屋電路輸出的電壓進行調整，而產生該操作電 3.-如申睛專利範圍第2項之電路，其中該電壓調節電之該頭端可耦接於快閃記憶體元件，而提供該快閃記憮體疋件進行輕式化/移除化程序之操作電壓。似 4·如申請專利範圍第2項之電路，其中上述電壓調節電路更包括一個二極體元件，該二極體元件之負端連接至該電荷昇壓電路，而正端則與該複數個NMOS電晶體串接。 5·如申請專利範圍第2項之電路，其中該電壓調節電6. Scope of patent application Scope of patent application: 1. A voltage adjustment circuit that can be used to remember flash memory, i.e., 70 pieces of electricity / body are subjected to a critical erasure test body, each of which contains at least a plurality of electricity 1 circuits Under the transistor, 'the transistor is not connected in series' and the source is connected to the LED, which can provide the function of the operating voltage required by the memory element, and 3 parts of the voltage are bypassed into the transistor.仃 The test voltage required in the critical erasure test is used as the circuit of the 2 terminal of the circuit, such as the circuit in the first item of the patent scope, wherein the terminal of the voltage regulating circuit 4 ^ is coupled to the charge and the charge is different. Boost the voltage ^ ^ electric (P · P) ^ in order to counter pressure. The voltage of the output of the squatter circuit is adjusted to generate the operating power. 3. The circuit of item 2 in the patent scope of Shenyan, in which the head end of the voltage regulating power can be coupled to a flash memory element and provided. Operating voltage of the flash memory body file for lightening / removing process. Like 4. The circuit of item 2 in the scope of patent application, wherein the voltage regulating circuit further includes a diode element, the negative terminal of the diode element is connected to the charge boost circuit, and the positive terminal is connected to the complex number NMOS transistors are connected in series. 5. The circuit according to item 2 of the patent application, wherein the voltage regulating circuit

第13頁 504701 六、申請專利範圍路之尾端，可與一電流鏡（current mirror)相連’並由該電流鏡提供該電壓調節電路操作電流。 6.如申請專利範圍第1項之電路，其中上述複數個電晶體是油NM0S電晶體所構成。 7.如申請專利範圍第6項之電路，其中吁籍著決定該旁通迴路產生旁-通效應的該電晶體數量，而決定該測試電壓與該操作電壓之差值。 I 8· —種可利用電壓調節電路對快閃記憶體元件進行臨界抹除測試之積體電路，該積體電路至少包含：電荷昇壓電路，可將電源供應的輸入電壓，提昇至快閃記憶體元件所需操作電壓之位準； ^電壓調節電路，回應於該電荷昇壓電路，可對該電荷昇壓電路輸出的電壓進行調整，而產生該快閃記憶體元件的操作電壓’其中該電麼調節電路包含複數個腿⑽電每—個該麵S電晶體之汲極與閘極相連，而源極 ;以秦電晶體之汲極串接，使該複數個瞧電 5曰鱧以串連方式產生壓降； I 旁通迴路’連接於部份該麵s電晶體的頭，以切換開關加以控制，當該旁通份NM0S電晶體產生旁诵隆厭♦从i 等通時，可對該部 Φ ^ tr 旁通降壓效果，而降低該電壓調節雷路的輸出電壓，以作為推弁电缓调即電為進订臨界抹除測試時所需的測試電Page 13 504701 6. Scope of patent application The tail end of the road can be connected with a current mirror 'and the current mirror provides the operating current of the voltage adjustment circuit. 6. The circuit according to item 1 of the scope of patent application, wherein the plurality of transistors are composed of oil NMOS transistors. 7. The circuit of item 6 in the scope of patent application, wherein the book is called to determine the number of the transistors that have a bypass-pass effect in the bypass circuit, and to determine the difference between the test voltage and the operating voltage. I 8 · —Integrated circuit capable of performing critical erasure test on flash memory elements using a voltage regulation circuit. The integrated circuit includes at least: a charge boost circuit that can increase the input voltage of the power supply to fast The level of the operating voltage required by the flash memory element; ^ the voltage adjustment circuit, in response to the charge boost circuit, can adjust the voltage output by the charge boost circuit to generate the operation of the flash memory element The voltage 'wherein the electric regulation circuit includes a plurality of legs. Each-the drain of the S transistor on the face is connected to the gate and the source; the drain of the Qin transistor is connected in series to make the plurality of On the 5th, 鳢 generates a voltage drop in series; I bypass circuit is connected to the head of a part of the transistor on the surface, and is controlled by a switch. When the bypass part NM0S transistor generates a paranoid dysfunction ♦ From i When isostatic, it can bypass the voltage reduction effect of Φ ^ tr and reduce the voltage to regulate the output voltage of the mine circuit.

作節電路以提供該電壓調節電路電路如申凊專利範圍第8項之電路，其中上述電壓調節該電孓個二極體元件，該二極體元件之負端連接至可垄電路’而正端則與該複數個NMOS電晶體串接。元件：乂：請專利範圍第9項之電路’ λ中上述二極體記憶體=並連接至該快閃記憶體元件，而提供該快閃進行程式化/移除化程序之操作電壓。該旁U迴ί I請專利範圍第8項之電路，λ中可藉著決定碾迴路所涵括該 NM0S電晶疋式電遷與該操作電壓之差值。而…測As a section circuit to provide the voltage adjustment circuit circuit such as the circuit in item 8 of the patent application, wherein the above voltage adjustment adjusts the electric diode element, and the negative terminal of the diode element is connected to the ridgeable circuit. The terminal is connected in series with the plurality of NMOS transistors. Component: 乂: Please use the circuit of item 9 in the patent scope λ. The above-mentioned diode memory = and connect to the flash memory component, and provide the flash with the operating voltage for the programming / removal process. The circuit of item 8 in the patent scope of this patent can be determined by lapping the difference between the NM0S transistor and the operating voltage included in the circuit. And ...

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