TW498491B - Method for improving fence issue by the photoresist back-etching in the damascene processing - Google Patents
Method for improving fence issue by the photoresist back-etching in the damascene processing Download PDFInfo
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498491 五、發明說明(1) 5 - 1發明領域: 本發明係有關於一種半導體元件的製造方法,特別是 有關於一種在金屬鑲嵌製程中藉由光阻回蝕以改善柵攔問 題的方法。 5-2發明背景: 近年來在半導體元件的需求因大量的使用電子零件而 快速的增加。特別是電腦快速的普及及增加了半導體元件 的需求。由於需要數百或是數千電晶體組成很複雜的積體 電路製造在單一半導體晶片上,為了增加積體電路内電子 元件密度,必須將元件的尺寸縮小,且保持元件原來所擁 有的特性,所以元件尺寸的縮小及提供一簡化的製造方法 是重要的。 第一 A圖,提供具有銅金屬層101的半導體矽底材100 。接著,蓋帽層1 0 2沈積在半導體底材1 0 0的表面上與銅金 屬層1 0 1的頂表面上。於蓋帽層1 0 2上再沈積上一層第一低 k值介電層1 0 4,此第一介電層1 0 4以化學氣相沈積的方式 形成。蝕刻終止層1 0 6,材料至少包含氮化矽,沈積在第 一介電層1 0 4的表面上。於钱刻終止層1 0 6上再沈積上一層 第二低k值介電層1 0 8。接著,以具有一開口之第一光阻層498491 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for improving the barrier problem by photoresist etchback in a damascene process. 5-2 Background of the Invention: In recent years, the demand for semiconductor components has increased rapidly due to the large number of electronic components used. In particular, the rapid popularity of computers has increased the demand for semiconductor components. Since hundreds or thousands of transistors are required to make a complex integrated circuit manufactured on a single semiconductor wafer, in order to increase the density of electronic components in the integrated circuit, the size of the component must be reduced and the original characteristics of the component must be maintained. Therefore, it is important to reduce the size of the components and provide a simplified manufacturing method. First A diagram, a semiconductor silicon substrate 100 having a copper metal layer 101 is provided. Next, a cap layer 102 is deposited on the surface of the semiconductor substrate 100 and the top surface of the copper metal layer 101. A first low-k dielectric layer 104 is deposited on the cap layer 102, and the first dielectric layer 104 is formed by chemical vapor deposition. The etch stop layer 106 is made of at least silicon nitride and is deposited on the surface of the first dielectric layer 104. A second low-k dielectric layer 108 is deposited on the money-cut stop layer 106. Then, a first photoresist layer having an opening is used.
第4頁 498491 五、發明說明(2) 為罩幕,經由此開口蝕刻第二低k值介電層1 0 8,蝕刻終止 層1 0 6與第一介電層1 0 4且蝕刻終止於蓋帽層1 0 2上,以形 成一介層洞1 0。接著,利用氧氣電漿法去除第一光阻層( 此未標示於圖上)。覆蓋第二光阻層1 1 0於第二低k值介電 層1 0 8上與介層洞1 0内,且第二光阻層1 1 0於第二介電層上 具有一溝渠圖案開口 1 5,在介層洞1 0内之第二光阻層1 1 0 為不平坦表面。 第一 B圖,以第二光阻層1 1 0為罩幕,蝕刻第二低k值 介電層1 0 8且終止於I虫刻終止層1 0 6上,由於介層洞1 0内之 第二光阻層1 1 0與第二低k值介電層1 0 8具有不同之蝕刻選 擇比,所以介於第二低k值介電層1 0 8與第二光阻層1 1 0之 間,造成側壁殘留之聚合物1 1 1,即所謂的柵攔(f e n c e i ssue)問題。 第一 C圖,蝕刻介層洞1 0内之第二光阻層1 1 0,以曝出 部分之蓋帽層1 0 2,介於第二低k值介電層1 0 8與第二光阻 層1 1 0之間之聚合物1 1 1仍存在,將會影響後續製程。 基於上述金屬鑲嵌技術的缺點,極欲尋求一種在金屬 鑲嵌製程中藉由光阻回蝕以改善柵欄問題的方法。 5 - 3發明目的及概述:Page 4 498491 V. Description of the invention (2) is a mask, through which the second low-k dielectric layer 108 is etched, the etch stop layer 10 6 and the first dielectric layer 104 are etched and the etching is terminated at The cap layer 102 is formed to form a via hole 10. Then, the first photoresist layer is removed by an oxygen plasma method (this is not shown in the figure). Covering the second photoresist layer 1 10 on the second low-k dielectric layer 108 and the dielectric hole 10, and the second photoresist layer 1 10 has a trench pattern on the second dielectric layer The opening 15, and the second photoresist layer 1 1 0 in the via hole 10 is an uneven surface. In the first diagram B, the second photoresist layer 1 10 is used as a mask, and the second low-k dielectric layer 108 is etched and terminated on the I-etched stop layer 1 06. The second photoresist layer 1 1 0 and the second low-k value dielectric layer 1 8 have different etching selection ratios, so they are between the second low-k value dielectric layer 1 0 8 and the second photoresist layer 1 1 Between 0, causing the residual polymer 1 1 1 on the sidewall, the so-called fencei ssue problem. In the first C diagram, the second photoresist layer 1 1 0 in the via hole 10 is etched to expose a part of the cap layer 10 2 between the second low-k dielectric layer 108 and the second light. The polymer 1 1 1 between the resistance layers 1 10 still exists, which will affect subsequent processes. Based on the shortcomings of the above-mentioned metal damascene technology, it is extremely desirable to seek a method to improve the fence problem by photoresist etchback in the metal damascene process. 5-3 Invention Purpose and Overview:
第5頁 498491 五、發明說明(3) 鑒於上述之發明背景中,傳統的半導體元件製程所產 生的諸多缺點,在本發明中提供一種在金屬鑲嵌製程中藉 由光阻回蝕以改善柵欄問題的方法,用以蝕刻方式控制光 阻層高度,使得光阻層低於氮化矽層,再藉由輕微蝕刻殘 留介層洞側壁之光阻,有效預防栅欄問題(fence i s sue) 本發明之主要目的係提供一種在金屬鑲嵌製程中藉由 光阻回蝕以改善柵攔問題的方法,用以解決了金屬鑲嵌結 構中柵欄問題(f e n c e i s s u e)。 根據上述之目的,本發明揭露形成一種在金屬鑲嵌製 程中藉由光阻回蝕以改善柵欄問題的方法。首先,提供一 底材,在底材上具有第一介電層,其中第一介電層上具有 蝕刻終止層,且蝕刻終止層上具有一第二介電層。接著, 形成介層洞在第二介電層,蝕刻終止層與第一介電層内, 以暴露出底材。然後,填入一光阻於介層洞内與第二介電 層上,其中光阻具有一溝渠圖案開口 ,且溝渠圖案開口位 於介層洞上方,其中光阻藉由一#刻步驟使得高度低於# 刻終止層,再藉由輕微蝕刻去除介層洞側壁的光阻。再者 ,形成一溝渠在第二介電層内,最後,移除光阻。 本發明之目的及諸多優點藉由以下較佳具體實施例之 ·Page 5 498491 V. Description of the invention (3) In view of the above-mentioned background of the invention, the traditional semiconductor device manufacturing process has many disadvantages, in the present invention provides a metal damascene process by photoresist etchback to improve the fence problem Method for controlling the height of the photoresist layer by means of etching so that the photoresist layer is lower than the silicon nitride layer, and then lightly etching the photoresist on the sidewall of the residual via layer to effectively prevent fence is sue. The main purpose is to provide a method to improve the barrier problem by photoresist etchback in the metal damascene process to solve the fence issue in the metal damascene structure. According to the above purpose, the present invention discloses a method for improving a fence problem by photoresist etchback in a damascene process. First, a substrate is provided with a first dielectric layer on the substrate, wherein the first dielectric layer has an etch stop layer and the etch stop layer has a second dielectric layer. Next, a dielectric hole is formed in the second dielectric layer, and the etching stopper layer and the first dielectric layer are formed to expose the substrate. Then, a photoresist is filled in the dielectric hole and on the second dielectric layer, wherein the photoresist has a trench pattern opening, and the trench pattern opening is located above the dielectric hole. The photoresist is made to have a height by a #etching step. Below the # etch stop layer, the photoresist on the sidewall of the via hole is removed by light etching. Furthermore, a trench is formed in the second dielectric layer, and finally, the photoresist is removed. The object of the present invention and its many advantages are provided by the following preferred embodiments:
第6頁 498491 五、發明說明(4) 詳細說明,並參照所附圖式,將趨於明瞭。 5 - 4較佳具體實施例之詳細說明: 本發明的半導體設計可被廣泛地應用到許多半導體設 計中,並且可利用許多不同的半導體材料製作,當本發明 以一較佳實施例來說明本發明方法時,習知此領域的人士 應有的認知是許多的步驟可以改變,材料及雜質也可替換 ,這些一般的替換無疑地亦不脫離本發明的精神及範疇。 其次,本發明用示意圖詳細描述如下,在詳述本發明 實施例時,表示半導體結構的剖面圖在半導體製程中會不 依一般比例作局部放大以利說明,然不應以此作為有限定 的認知。此外,在實際的製作中,應包含長度、寬度及深 度的三維空間尺寸。 第二A圖至第二F圖為本發明一最佳實施例,關於一種 在金屬鑲嵌製程中藉由光阻回蝕以改善柵欄問題的方法之 截面剖視圖。 參照二A圖顯示,提供具有傳導性層2 0 1的半導體底材 200。此傳導性層201至少包含一金屬且最好為銅金屬或任 何具傳導性材質例如摻雜矽。半導體底材2 0 0至少包含矽Page 6 498491 V. Description of the invention (4) Detailed description, with reference to the attached drawings, will become clearer. 5-4 Detailed description of the preferred embodiments: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention is described in a preferred embodiment, When inventing the method, those who are familiar with this field should recognize that many steps can be changed, and materials and impurities can be replaced. These general replacements undoubtedly do not depart from the spirit and scope of the present invention. Secondly, the present invention is described in detail with a schematic diagram as follows. In the detailed description of the embodiments of the present invention, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process to facilitate the description, but it should not be used as a limited recognition. . In addition, the actual production should include three-dimensional space dimensions of length, width and depth. FIGS. 2A to 2F are cross-sectional views of a preferred embodiment of the present invention, which relates to a method for improving a fence problem by photoresist etchback in a metal damascene process. Referring to FIG. 2A, it is shown that a semiconductor substrate 200 having a conductive layer 201 is provided. The conductive layer 201 contains at least one metal, preferably copper metal or any conductive material such as doped silicon. Semiconductor substrate 2 0 0 contains at least silicon
第7頁 498491 五、發明說明(5) 。接著,蓋帽層2 0 2,材料至少包含氮化矽,其介電常數 大約為7 . 0,沈積在半導體底材2 0 0的表面上與傳導性層 2 0 1的頂表面上。此蓋帽層2 0 2沈積的厚度約為2 0 0至1 0 0 0 埃於蓋帽層20 2上再沈積上一層第一介電層204,此第一介 電層2 0 4以適當的物料形成,例如低介電常數矽(S i LK ; FSG):這些物料因其介電常數大約小於4,故被認為是低 介電常數物料。此第一介電層』0 4沈積的厚度約為2 0 0 0至 4 0 0 0埃。此第一介電層2 0 4以化學氣相沈積的方式形成。 蝕刻終止層2 0 6,材料至少包含氮化矽,沈積在第一介電 層2 0 4的表面上。此#刻終止層2 0 6沈積的厚度約為2 0 0至 1 0 0 0埃。於蝕刻終止層2 0 6上再沈積上一層第二介電層2 0 8 ,此第二介電層2 0 8以適當的物料形成,例如低介電常數 矽(SiLK ; FSG);這些物料因其介電常數大約小於4,故 被認為是低介電常數物料。此第二低k值介電層2 0 8沈積的 厚度約為2 0 0 0至4 0 0 0埃。此第二介電層2 0 8以化學氣相沈 積的方式形成。於第二低k值介電層2 0 8上利用傳統的曝光 與顯影技術形成第一光阻層2 1 0,其中此第一光阻層2 1 0具 有一開口。 參照二B圖,以具有一開口之第一光阻層2 1 0為罩幕, 經由此開口#刻第二低k值介電層2 0 8,餘刻終止層2 0 6與 第一介電層2 0 4且钱刻終止於蓋帽層2 0 2上’以形成一介層 洞2 0。接著,利用氧氣電漿法去除第一光阻層2 0 6。Page 7 498491 V. Description of the invention (5). Next, the capping layer 202, which contains at least silicon nitride, has a dielectric constant of about 7.0 and is deposited on the surface of the semiconductor substrate 200 and the top surface of the conductive layer 201. The cap layer 2 0 2 is deposited to a thickness of about 200 to 1 0 0 0 angstroms, and a first dielectric layer 204 is deposited on the cap layer 20 2. The first dielectric layer 2 0 4 is made of a suitable material. Formation, such as low dielectric constant silicon (Si LK; FSG): These materials are considered low dielectric constant materials because their dielectric constant is less than about 4. The thickness of the first dielectric layer ′ 0 4 is approximately 20,000 to 4,000 angstroms. The first dielectric layer 204 is formed by a chemical vapor deposition method. The etch stop layer 206 is made of at least silicon nitride and is deposited on the surface of the first dielectric layer 206. At this moment, the stop layer 206 is deposited to a thickness of about 200 to 100 angstroms. A second dielectric layer 208 is deposited on the etch stop layer 206. The second dielectric layer 208 is formed of a suitable material, such as low dielectric constant silicon (SiLK; FSG); these materials Because its dielectric constant is less than about 4, it is considered a low dielectric constant material. This second low-k dielectric layer 208 is deposited to a thickness of about 2000 to 400 angstroms. This second dielectric layer 208 is formed by chemical vapor deposition. A first photoresist layer 2 1 0 is formed on the second low-k dielectric layer 2 08 using conventional exposure and development techniques, wherein the first photo resist layer 2 1 0 has an opening. Referring to FIG. 2B, the first photoresist layer 2 1 0 having an opening is used as a mask, and the second low-k dielectric layer 2 0 8 is etched through the opening #, and the stop layer 2 06 and the first dielectric The electrical layer 204 is terminated on the cap layer 202 to form a via hole 20. Then, the first photoresist layer 206 is removed by an oxygen plasma method.
498491 五、發明說明(6) 參照二C圖,形成第二光阻層2 1 2於第二介電層上與介 層洞20内,其中第二光阻層21 2於第二介電層上具有第一 溝渠圖案開口 3 0,且第一溝渠圖案開口 3 0位於介層洞2 0之 上方,其中在介層洞2 0内之第二光阻層2 1 2為不平坦表面 。接著,以時間控制,回蝕介層洞2 0内之第二光阻層2 1 2 直到位於蝕刻終止層之下,大約位於蝕刻終止層約為1 0 0 0 〜1 δ 0 0埃之間。 參照二D圖,再以Ν2/02電漿輕微蝕刻lOO-SOOWaH/SO1 15 0mT/,殘留於介層洞20内之側壁之第二光阻層212。因 使用低選擇比之N 2/0 #虫刻氣體介於該第二低k值介電層2 0 8 與第二光阻層2 1 2之間可減少側壁殘留之一聚合物。 參照二E圖,以具有第一溝渠圖案開口 3 0之第二光阻 層2 1 2為罩幕,經由此第一溝渠圖案開口 3 0蝕刻第二低k值 介電層2 0 8且終止於蝕刻終止層2 0 6上,其中第二低k值介 電層2 0 8具有第二溝渠圖案開口 40。使用具有CF4/CHF咸 N 2H辰應式離子蝕刻法,以蝕刻第二低k值介電層2 0 8且終 止於蝕刻終止層2 0 6上。參照二F圖,利用氧氣電漿法去除 第二光阻層2 1 2。接著,以N 2/ 0 2電漿蝕刻介層洞内2 0之第 二光阻層2 1 2,以曝出部分之蓋帽層2 0 2。 根據以上所述,本發明乃提供一種在金屬鑲嵌製程中 藉由光阻回#以改善柵攔問題(f e n c e i s s u e)的方法。由498491 V. Description of the invention (6) Referring to the second C diagram, a second photoresist layer 2 1 2 is formed on the second dielectric layer and in the dielectric hole 20, wherein the second photoresist layer 21 2 is on the second dielectric layer There is a first trench pattern opening 30 on the top, and the first trench pattern opening 30 is located above the via hole 20, wherein the second photoresist layer 2 12 in the via hole 20 is an uneven surface. Next, under time control, the second photoresist layer 2 1 2 in the via hole 20 is etched back until it is under the etch stop layer, which is approximately between the etch stop layer about 1 0 0 0 to 1 δ 0 0 angstrom . Referring to FIG. 2D, the second photoresist layer 212 on the sidewall of the via hole 20 is further etched with 100-SOOWaH / SO1 150mT / using N2 / 02 plasma. Because of the use of a low selection ratio of N 2/0 # insect etch gas between the second low-k dielectric layer 2 0 8 and the second photoresist layer 2 1 2, a polymer remaining on the sidewall can be reduced. Referring to FIG. 2E, the second photoresist layer 2 1 2 with the first trench pattern opening 30 is used as a mask, and the second low-k dielectric layer 2 8 is etched and terminated through the first trench pattern opening 30. On the etch stop layer 206, the second low-k dielectric layer 208 has a second trench pattern opening 40. A CF4 / CHF salt N 2H Chenying ion etching method is used to etch the second low-k dielectric layer 208 and terminate on the etch stop layer 206. Referring to FIG. 2F, the second photoresist layer 2 1 2 is removed by an oxygen plasma method. Next, the second photoresist layer 2 1 2 in the via hole is etched with N 2/0 2 plasma to expose a part of the cap layer 2 2. According to the above, the present invention provides a method for improving the blocking problem (f e n c e i s s s u e) by photoresisting back # in a metal damascene process. by
498491 五、發明說明(7) 於先以N 2/0 2電漿蝕刻介層洞2 0内之第二光阻層2 1 2直到位 於蝕刻終止層2 0 6之下,將不會造成因回蝕第二低k值介電 層2 0 8時,由於介層洞2 0内之第二光阻層2 1 2與第二低k值 介電層2 0 8具有不同之選擇比,造成在介層洞20内之第二 光阻層2 1 2側壁會有殘留聚合物,因而預防了柵攔問題( fence issue) °498491 V. Description of the invention (7) Prior to etching the second photoresist layer 2 1 2 in the via hole 20 with N 2/0 2 plasma until it is below the etching stop layer 2 06, there will be no cause When the second low-k value dielectric layer 208 is etched back, the second photoresist layer 2 1 2 in the dielectric hole 20 and the second low-k value dielectric layer 2 0 8 have different selection ratios, resulting in There will be residual polymer on the side wall of the second photoresist layer 2 1 2 in the via hole 20, thereby preventing fence issues.
以上所述僅為本發明之實施例而已,並非用以限定本 發明之申請專利範圍;凡其它未脫離本發明所揭示之精神 下所完成之等效改變或修飾,均應包含在下述之申請專利 範圍内。The above are only examples of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following applications Within the scope of the patent.
第10頁 498491 圖式簡單說明 本發明之上述目的與優點,將以下列的實施例以及圖 示,做詳細說明如下,其中: 第一 A圖至第一 C圖係為習知的金屬鑲嵌結構之截面剖 視圖, 第一 A圖所顯示的是在具有金屬層之内金屬介電層上 依序沈積蓋帽層,第一介電層,蝕刻終止層,第二低k值 介電層、在第二介電層上形成具有溝渠圖案之第二光阻層 與填入第二光阻層之介層洞之後的晶圓剖面圖; 第一 B圖所顯示的是蝕刻第二低k值介電層於蝕刻終止 層上,由於第二低k值介電層與第二光阻層蝕刻選擇比的 不同造成側壁殘留聚合物之後的晶圓剖面圖; 第一 C圖所顯示的是蝕刻介層洞内之光阻使曝露出部 分蓋帽層,側壁殘留聚合物仍存在之後的晶圓剖面圖。 第二A圖至第二F圖顯示的是依據本發明的方法,製作 電晶體中的金屬鑲嵌(Dual Damascene)之一連串製程。 關於一種在金屬鑲嵌製程中藉由光阻回蝕以改善柵欄問題 的方法之截面剖視圖; 第二A圖所顯示的是在具有金屬層之内金屬介電層上Page 498491 The drawings briefly explain the above-mentioned objects and advantages of the present invention. The following embodiments and diagrams will be used to make detailed descriptions as follows, wherein: Figures A through C are conventional metal mosaic structures. Sectional cross-sectional view. The first diagram A shows a cap layer, a first dielectric layer, an etch stop layer, a second low-k dielectric layer, Cross-sectional view of the wafer after the second photoresist layer with a trench pattern is formed on the two dielectric layers and the via hole filled in the second photoresist layer; Figure B shows the second low-k dielectric. Layer on the etch stop layer, the cross-sectional view of the wafer after the residual polymer on the sidewall due to the difference in the etching selection ratio between the second low-k dielectric layer and the second photoresist layer; the first C picture shows the etched dielectric layer The photoresist inside the hole exposes part of the capping layer, and the cross-sectional view of the wafer after the residual polymer on the sidewall still exists. Figures 2A to 2F show a series of processes for making metal damascene in a transistor according to the method of the present invention. A cross-sectional view of a method for improving the problem of a fence by photoresist etchback in a metal damascene process; FIG. 2A shows a metal dielectric layer having a metal layer
498491 圖式簡單說明 依序沈積蓋帽層、第一介電層、银刻終止層、第二低k值 介電層與具有開口圖案之第一光阻層之後的晶圓剖面圖; 第二B圖所顯示的是在蓋帽層上定義出介層洞之後的 晶圓剖面圖; 第二C圖所顯示的依據本發明步驟,在第二低k值介電 層上形成具有溝渠圖案之第二光阻層與填入第二光阻層之 介層洞之後的晶圓剖面圖,其中部分第二光阻層殘留在介 層洞側壁上; 第二D圖所顯示的依據本發明步驟,蝕刻介層洞内之 第二光阻層使其高度低於蝕刻止層終之後的晶圓剖面圖; 第二E圖所顯示的是蝕刻第二低k值介電層於蝕刻終止 層上,其中第二低k值介電層具有一溝渠圖案開口之後的 晶圓剖面圖; 第二F圖所顯示的是蝕刻介層洞内之光阻使曝露出部 分蓋帽層之後的晶圓剖面圖。 主要部分之代表符號: 1 0、2 0 介層洞 15 溝渠圖案開口498491 The diagram briefly illustrates the cross-sectional view of the wafer after the cap layer, the first dielectric layer, the silver etch stop layer, the second low-k dielectric layer, and the first photoresist layer with an opening pattern are sequentially deposited. Second B The figure shows a cross-sectional view of the wafer after a via hole has been defined on the cap layer. The second figure C shows the formation of a second trench pattern on the second low-k dielectric layer according to the steps of the present invention. A cross-sectional view of the wafer after the photoresist layer and the via hole filled with the second photoresist layer, in which a portion of the second photoresist layer remains on the sidewall of the via hole; the second D picture shows etching according to the steps of the present invention. The second photoresist layer in the via hole has a height lower than the cross-sectional view of the wafer after the etch stop layer is finished. The second E picture shows the etching of the second low-k dielectric layer on the etch stop layer, where The second low-k dielectric layer has a cross-sectional view of the wafer after a trench pattern opening. FIG. F shows the cross-sectional view of the wafer after the photoresist in the via hole is etched to expose a portion of the cap layer. Representative symbols of the main parts: 1 0, 2 0 interlayer holes 15 trench pattern openings
498491 圖式簡單說明 30 40 100、 200 101 > 201 102、 202 104、 204 106、 206 108、 208 111 210 110、 212 第一溝渠圖案開口 第二溝渠圖案開口 半導體底材 金屬層 蓋帽層 第一介電層 I虫刻終止層 第二低k值介電層 聚合物 第一光阻層 第二光阻層498491 Brief description of drawings 30 40 100, 200 101 > 201 102, 202 104, 204 106, 206 108, 208 111 210 110, 212 First trench pattern opening Second trench pattern opening Semiconductor substrate metal layer cap layer first Dielectric layer I etch stop layer second low-k dielectric polymer first photoresist layer second photoresist layer
第13頁Page 13
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TW90110458A TW498491B (en) | 2001-05-02 | 2001-05-02 | Method for improving fence issue by the photoresist back-etching in the damascene processing |
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