TW498275B

TW498275B - Processor unit

Info

Publication number: TW498275B
Application number: TW089109959A
Authority: TW
Inventors: Kenji Ohmori
Original assignee: Toshiba Corp
Priority date: 1999-05-24
Filing date: 2000-05-23
Publication date: 2002-08-11
Also published as: KR100382018B1; KR20010014964A

Abstract

The present invention discloses a processor unit consisting of a main processor (1) and a coprocessor (20). The main processor (1) comprises a decoder (7) to decode instructions, a register (8) to store data and output data of the addresses stored in the decoded instructions, a first memory (12) for data memory, and an arithmetic-logic unit (10) to, in accordance with the decoding instructions, use data output from the register for the required operations before storing the operation results into either the register or the first memory. The coprocessor (20) comprises a control register (21) to store control signal values, three address generators (23, 24, 27), three memories (25, 26, 28) corresponding to the three address generators, and a main controller (22) to, in accordance with the control signal values stored in the control register, transmit instruction signals to the address generators for generating addresses before outputting data of the addresses stored in the address generators from the memories to the arithmetic-logic unit of the main processor for the required operations. Thus, not only high speed processing can be accomplished but also the overall required space can be reduced as much as possible at the same time.

Description

498275 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（1 ) 本發明係關於具備有R I S C ( Reduced Instruction Set Computer )部及協同處理器部之處理裝置。 :一般如果要以R I S C進行例如語音處理之疊入之單純環路處理，則記憶器之位址生成或環路之判定也必須使用 R I S C 之 ALU ( ArithmeticandLogicUnit)來進行，因此上述處理花費很多時間。爲了消除這種問題，以往是考慮一種將 R I S C 部與 D、S P ( Digital Signal Processor)部合在一起之架構之處理器裝置。第7圖表示此傳統之處理器裝置之架構。此傳統之處理器裝置具備有R I S C部1.及D S P部6 0。 R I S C部1備有，命令記億器3、命令讀入部4、暫存器5、命令解碼部6、暫存器9、ALU1 0、暫存器1 1、記憶器1 2。命令解碼部6具有解碼器7、及萬用暫存器8。而DSP部60則備有，暫存器61、命令解碼部 62、記億器 65i、6 52、653及ALU67。命令解碼部6 2具有解碼器6 3及位址生成器6 4:、6 42、 6 4 3。再者，記憶器6 5 i ( i = 1、2、3、）係對應位址生成器6 4 i所配設。儲存在R I S C部1之命令記憶器3之命令係由命令讀入部4讀進。而若此讀進之命令是要在R I s <^部1處理之命令，則送至暫存器5，是要在D S P部6 0處理之命令，則送至暫存器6 1。送至暫存器5之命令由解碼器7加以解碼。被解碼之 -------：---·----霞 (請先閱A背面之注意事項寫本頁) ^1 ·ϋ ·1 an »^50^ fl 1_1 tmt ϋ eet tmmr ϋ . 線本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -4- 498275 A7 B7 五、發明說明（2) 命令之位址部分送至萬用暫存器8。於是取出對應上述位址部分內之位址之萬用暫存器8之位址所記憶之資料，而送給暫存器9。同時，上述解碼之命令之位址部分以外之部分，例如作業碼由解碼器7送至ALU 1 〇，使用送給上述暫存器 9之資料進行算術運算或邏輯運算。此運算結果經由暫存器1 1記憶在記憶器1 2後，送出到萬用暫存器8內或直接送出到萬用暫存器8，儲存在萬用暫存器8之一定之位址。另一方面，送至D S P部6 0之暫存器6 1之命令則由解碼器6 3加以解碼。而依據此解碼之命令，從3個位址生成器6 、6 42、6 43中之兩個位址生成器分別生成位址，而由對應之記憶器輸出資料。使用此等資料，由A L U 6 7進行對應從上述解碼器6 3送來之解碼之命令之運算。而此運算結果則儲存在上述記憶器6 5 i、 6 5 2、6 5 3中之至少一個記憶器。如此，在傳統之處理器裝置，DSP部60係使用位址生成器6 4\、6 4 2、6 4 3生成記憶器之位址，因此不必以ALU運算，較之無DSP部僅有RISC部者，可以作高速處理。惟，這種傳統之處理器裝置，因爲採RISC部1與 D S P部6 0之雙方均有ALU之架構，因此有整体之面積很大之問題。同時另有，在RISC部1與DSP部 6 0間進行程式控制，或記憶在記憶器之資料之授受動作 (請先閱讀背面之注意事項 --- 本頁) 訂---------線一經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -5 - 498275 經濟部智慧財產局員工消費合作社印製 A7 _ B7_五、發明說明（3 ) 變複雜之問題。本發明係考慮上述情事而完成者，以提供可作高速處理：，同時整体之佔用面積可以儘量縮小之處理器裝置。本發明之處理器裝置，其特徵在於，具備有主處理器部及協同處理器部，該主處理器部包含有：將取進之命令加以解碼之解碼器；儲存有資料，可將儲存於上述經解碼之命令所含之位址之資料輸出之暫存器部；記憶有資料之第1記憶器；以及，依據上述被解碼之命令，使用由上述暫存器部輸出之資料進行運算，將運算結果儲存於上述暫存器部或上述第 1記憶器之運算部；該協同處理器部包含有：依照上述經解碼之命令儲存，從上述暫存器部送來之控制信號之値之控制用暫存器；生成位址之位址生成部；對應上述位址生成部配設之記憶部；以及，依據上述儲存在控制暫存器之控制信號値，將指令信號送給上述位址生成部，使其生成位址，將儲存在此生成之位址之資料從上述記憶部輸出，將此輸出之資料送至上述主處理器部之運算部，令其進行運算之主控制器。再者，上述主處理器部之上述運算部具有多數運算元件，上述多數運算元件由上述協同處理器部之主控制器加以串聯連接較佳。再者，也可以採，上述主處理器部係R I s C部，上述主控制器係依據由上述解碼器送來之起動信號開始動作，之架構。閱讀· 背面之注· 意事項498275 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (1) The present invention relates to a processing device having a Reduced Instruction Set Computer (R I S C) unit and a coprocessor unit. : Generally, if you want to use R I S C to perform simple pure loop processing such as voice processing, the address generation of the memory or the determination of the loop must also be performed using A LU (Arithmetic and Logic Unit) of R I S C, so the above processing takes a lot of time. In order to eliminate such a problem, in the past, a processor device having a structure in which an R I S C part and a D and SP (Digital Signal Processor) part are considered is considered. Figure 7 shows the architecture of this conventional processor device. This conventional processor device includes an R I S C section 1. and a D S P section 60. The R I S C unit 1 includes a command register 3, a command reading unit 4, a register 5, a command decoding unit 6, a register 9, ALU1 0, a register 1 1, and a memory 12. The command decoding unit 6 includes a decoder 7 and a universal register 8. The DSP section 60 includes a temporary register 61, a command decoding section 62, a billion register 65i, 65, 653, and ALU67. The command decoder 6 2 includes a decoder 6 3 and an address generator 6 4 :, 6 42 and 6 4 3. Furthermore, the memory 6 5 i (i = 1, 2, 3,) is provided corresponding to the address generator 6 4 i. The commands stored in the command memory 3 of the RIS C section 1 are read by the command reading section 4. And if this read command is a command to be processed in R I s < ^ Section 1, it is sent to register 5 and a command to be processed in DS SP 60 is sent to register 61. The command sent to the register 5 is decoded by the decoder 7. Decoded -------: ----------- Xia (please read the notes on the back of A first to write this page) ^ 1 · ϋ · 1 an »^ 50 ^ fl 1_1 tmt ϋ eet tmmr ϋ. The size of the paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) -4- 498275 A7 B7 V. Description of the invention (2) The address part of the order is sent to the universal register 8. Then, the data stored in the address of the universal register 8 corresponding to the address in the above address portion is taken out and sent to the register 9. At the same time, the part other than the address part of the decoded command, for example, the operation code is sent from the decoder 7 to the ALU 10, and the data sent to the register 9 is used for arithmetic or logical operations. This calculation result is stored in the memory 12 through the register 1 1 and then sent to the universal register 8 or directly to the universal register 8 and stored in a certain address of the universal register 8 . On the other hand, the command sent to the register 61 of the DS unit 60 is decoded by the decoder 63. According to this decoded command, addresses are generated from two of the three address generators 6, 6, 42 and 6 43 respectively, and the corresponding memory outputs data. Using this data, A L U 6 7 performs an operation corresponding to the decoding command sent from the decoder 63 described above. The calculation result is stored in at least one of the memories 6 5 i, 6 5 2 and 6 5 3. In this way, in the traditional processor device, the DSP section 60 uses the address generator 6 4 \, 6 4 2, 6 4 3 to generate the address of the memory, so it is not necessary to use ALU to calculate, compared to the RISC without the DSP section. Can be used for high-speed processing. However, this conventional processor device has an ALU architecture because both the RISC section 1 and the DS section 60 have an ALU structure, so there is a problem of a large overall area. At the same time, program control is performed between RISC section 1 and DSP section 60, or the teaching and receiving operations of the data stored in the memory (please read the precautions on the back --- this page) Order ------- --Line 1 Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed to the Chinese National Standard (CNS) A4 (210 X 297 mm) -5-498275 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 _V. Description of the invention (3) The problem becomes complicated. The present invention has been completed in consideration of the above circumstances, so as to provide a processor device capable of high-speed processing: and at the same time, the overall occupied area can be minimized. The processor device of the present invention is characterized by including a main processor section and a co-processor section. The main processor section includes: a decoder that decodes the fetched command; and stores data that can be stored in A register unit for outputting data of an address contained in the decoded command; a first memory storing the data; and performing operations using the data output by the register unit according to the decoded command, The operation result is stored in the above-mentioned register unit or the operation unit of the first memory; the coprocessor unit includes: one of the control signals sent from the above-mentioned register unit and stored in accordance with the decoded command; Control register; address generating unit for generating an address; a memory unit corresponding to the above address generating unit; and sending a command signal to the address in accordance with the above-mentioned control signal 储存 stored in the control register The generating unit causes it to generate an address, and outputs the data stored in the generated address from the memory unit, and sends the output data to the computing unit of the main processor unit to perform The main controller of the operation. Furthermore, it is preferable that the operation unit of the main processor unit includes a plurality of operation elements, and the plurality of operation elements are preferably connected in series by a main controller of the coprocessor unit. Furthermore, it is also possible to adopt a structure in which the main processor unit is a R I s C unit, and the main controller is based on a start signal sent from the decoder. Reading · Notes · Notes on the back

Η 頁I I I I I I訂本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -6- 498275 A7 B7____ 五、發明說明（4) 再者，也可以採，上述位址生成器具有第1及第2之位址生成器，上述記憶部具有分別對應上述第1及第2位址:生成器之第2及第3之記憶器，之架構。再者，也可以採，上述指令信號包含S E T信號、增分信號、及加減法信號，上述第1及第2之位址生成器分別具備有，保持現在之位址之位址暫存器，及應上述 S E T信號及加減法信號之値，從保持在上述位址暫存器之位址與增分信號之値，運算下一個位址信號之位址運算器，之架構。再者，也可以採，上述位址運算器在上述S ET信號之値爲^ 1」時，輸出上述增分信號作爲下一位址信號，上述S E T信號之値爲「〇」時，依上述加減法信號之値，以現在之位址與增分信號之和或差作爲下一位址信號，之架構。再者，也可以採，上述主控制器具備有：暫存器；依據定時信號在上暫存器保持之値加1再令暫存器保持之計數器；將表示上述控制暫存器保持之輸入資料之長度之控制信號DATA LENGTH，與上述暫存器所保持之値，依據上述定時信號加以比較之比較器；依據上述比較器之比較結果及上述第2位址生成器所輸出之下一位址信號之値，遷移狀態，向上述第1及第2位址生成器輸出上述S ET信號、增分信號、及加減法信號，同時向上述主處理器之運算部送出控制信號之狀態遷移電路，之架構。再者，也可以採，上述狀態遷移電路具有：復置狀態本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項 — — — — — 訂·！-線· 本頁) 經濟部智慧財產局員工消費合作社印製 498275 A7 B7 五、發明說明（5 ) ;接收起動信號，設定上述第1及第2位址生成器之初期位址之起動狀態；在設定上述初期位址後’向上述運算部送出控制信號同時依序設定上述第1及第2位址生成器之位址，令上述運算部進行計算，返覆此計算’直到上述第 2位址生成器之下一位址信號等於一定値之計算狀態；以及，上述計算狀態結束後，依據上述比較器之比較結果’ 檢查計算是否已結束，未完成時則回到上述起動狀態’已完成時回到上述復置狀態之完成檢查狀態，之架構。再者，也可以採，上述運算部具備有積和運算器’之架構。 * 再者，也可以採，上述協同處理器部進一步備有’可依據上述主控制器之指令信號生成位址之第3位址生成器，及將上述運算部輸出之運算結果儲存在此第3位址生成器所輸出之位址之第4記憶器，之架構。再者，也可以採，進一步備有，可以授受上述主處理部之記憶器及上述協同處理器部之記憶器部之資料之 D Μ A控制裝置。同時，本創作之處理器裝置，其特徵在於，具備有主處理器部及協同處理器部，該主處理器部包含有：將取進之命令加以解碼之解碼器；依據上述解碼之命令，使用輸入之資料進行運算之運算部；該協同處理器部包含有：依據依照上述經解碼之命令送來之控制信號之値，將資料送至上述主處理器部之運算部，令其進行運算之主控制器。第1圖係表示本創作處理器裝置之第1實施形態之架本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事 — II 寫本頁)III Page IIIIII The size of the paper is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) -6-498275 A7 B7____ 5. Description of the invention (4) Furthermore, it can also be adopted. The above address generator has the The first and second address generators, the memory unit has a structure corresponding to the first and second addresses: the second and third memories of the generator, respectively. Furthermore, it is also possible to adopt that the above-mentioned instruction signal includes a SET signal, an increment signal, and an addition and subtraction signal, and the above-mentioned first and second address generators are respectively provided with an address register holding the current address, According to the structure of the above set signal and the addition and subtraction signals, the address calculator that calculates the next address signal from the address of the address register and the incremental signal held in the above address register. Furthermore, it can also be adopted that the address calculator outputs the incremental signal as the next address signal when 値 of the S ET signal is ^ 1 ”, and when 値 of the SET signal is“ 0 ”, according to the above The structure of the addition and subtraction signals is based on the sum or difference between the current address and the incremental signal as the next address signal. Furthermore, it can also be adopted that the above main controller is provided with: a register; a counter which is incremented by 1 in the upper register holding according to the timing signal and then the register is held; an input indicating the above-mentioned control register holding The control signal DATA LENGTH of the length of the data is compared with that held by the above-mentioned register, and is compared according to the above-mentioned timing signal; based on the comparison result of the above-mentioned comparator and the next bit output by the above-mentioned second address generator A state transition circuit that outputs the S ET signal, the incremental signal, and the addition and subtraction signals to the first and second address generators, and sends a control signal to the arithmetic unit of the main processor. , The architecture. In addition, the above state transition circuit can also be adopted. The state of the paper is reset. The paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). (Please read the precautions on the back first. — — — — — Order · ！ -Line · this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498275 A7 B7 V. Description of the invention (5); Receive the start signal and set the start status of the initial address of the first and second address generator ; After setting the initial address, 'send a control signal to the calculation unit and set the addresses of the first and second address generators sequentially, so that the calculation unit performs calculations, and repeats this calculation' until the second The calculation status of a bit address signal below the address generator is equal to a certain value; and, after the above calculation status ends, according to the comparison result of the above comparator, check whether the calculation has ended, and if it is not completed, return to the above-mentioned starting status. Upon completion, return to the completion check state of the above reset state, the structure. Furthermore, it is also possible to adopt a configuration in which the above-mentioned arithmetic unit is provided with a product sum operator '. * Furthermore, it can also be adopted that the co-processor section further includes a third address generator that can generate an address based on the instruction signal of the main controller, and store the operation result output by the operation section in this section. The structure of the 4th memory of the address output by the 3 address generator. Furthermore, it is also possible to further provide a DM A control device that can transmit and receive data from the memory of the main processing unit and the memory unit of the coprocessor unit. At the same time, the processor device of this creation is characterized by including a main processor section and a co-processor section. The main processor section includes: a decoder that decodes the fetched command; based on the decoded command, A computing unit that performs calculations using input data; the coprocessor unit includes: sending data to the computing unit of the main processor unit according to the control signal sent in accordance with the decoded command described above, and performing the calculation Master controller. Figure 1 shows the frame of the first embodiment of the creative processor device. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back first-II to write this page)

«ϋ 1 .1 I 經濟部智慧財產局員工消費合作社印製 498275 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（6 ) 構之方塊圖。此實施形態之處理器裝置具備有R I s C部 1，協同處理器部 2 0，及 DMA ( Direct Memory Access )·’控制電路3 0。 R I S C部1具備有命令記憶器3、命令讀入部4、暫存器5、命令解碼部6、暫存器9、ALU1 〇、暫存器1 1及記憶器1 2。命令解碼部6具備有解碼器7及萬用暫存器8。而協同處理器部2 0則具備有，控制用暫存器2 1、主控制器2 2、位址生成器2 3、2 4、記憶器2 5、 2 6、位址生成器2 7及記憶器2 8。儲存在r I S C部1之命令記憶器3之命令由命令讀入部4讀進，經由暫存器5送到解碼器7。送到解碼器7 之命令由解碼器7加以解碼。而此經解碼之命令若是應由 R I S C部1處理者，此解碼之命令之位址部分被送到萬用暫存器8。上述解碼之命令之位址部分被送到萬用暫存器8後，記憶在對應上述位址部分內之位址之萬用暫存器8之位址之資料被取出，送到暫存器9。上述解碼之命令之位址部分以外之部分則，例如由解碼器7將作業碼送到ALU 1 0，使用送給上述暫存器9 之資料進行算術運算或邏輯運算。此運算結果經由暫存器 1 1記憶在記憶器1 2後，送出到萬用暫存器8內或直接送出到萬用暫存器8，儲存在萬用暫存器8之一定之位址 (請先閱讀背面之注意事項< • 裝--- 寫本頁)«Ϋ 1.1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 498275 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) Block diagram. The processor device of this embodiment includes an R I s C section 1, a coprocessor section 20, and a DMA (Direct Memory Access) · 'control circuit 30. The R I S C unit 1 includes a command memory 3, a command reading unit 4, a register 5, a command decoding unit 6, a register 9, ALU1 0, a register 11 and a memory 12. The command decoder 6 includes a decoder 7 and a universal register 8. The coprocessor section 20 is provided with a control register 2 1, a main controller 2 2, an address generator 2 3, 2 4, a memory 2 5, 2 6, an address generator 2 7 and Memory 2 8. The command stored in the command memory 3 of the r I S C section 1 is read by the command reading section 4 and sent to the decoder 7 through the register 5. The command sent to the decoder 7 is decoded by the decoder 7. If the decoded command should be processed by the R I S C section 1, the address portion of the decoded command is sent to the universal register 8. After the address part of the decoded command is sent to the universal register 8, the data of the address stored in the universal register 8 corresponding to the address in the address part is taken out and sent to the temporary register. 9. For the part other than the address part of the decoded command, for example, the decoder 7 sends the operation code to ALU 1 0, and uses the data sent to the register 9 to perform arithmetic or logical operations. This calculation result is stored in the memory 12 through the register 1 1 and then sent to the universal register 8 or directly to the universal register 8 and stored in a certain address of the universal register 8 (Please read the precautions on the back < • Install --- write this page)

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ϋ n mmmmm I 線本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） f 7 2 8 9, 經濟部智慧財產局員工消費合作社印製 A7 _ B7__五、發明說明（7 ) 另一方面，上述經解碼之命令若是應由協同處理器部 2 0處理者.，則由解碼器7向協同處理器部2 0之控制用暫存器2 1送出定置信號，從萬用暫存器8向控制用暫存器2 1送出各種控制値而加以定置。在控制用暫、存器2 1 定置各種控制値後，從解碼器7向主控制器2 2送出起動信號。於是，主控制器2 2便依據定置在控制用暫存器 2 1之控制値，向位址生成器2 3、24、2 7送出指令信號，由位址生成器2 3、24、27產生位址。於是從位址生成器2 3、2 4生成各種位址，分別由記憶器2 5 、2 6讀出記憶在此等位址之資料，送至A L U 1 0。同時由主控制器2 2向ALU 10送出指令信號，依據從上述記憶器2 5、2 6讀出之資料進行運算。而此運算結果則依據主控制器2 2之指令信號，儲存在由位址生成器 2 7生成之記憶器2 8之位址。此等記憶器2 5、2 6、2 8與R I S C部1之記憶器1 2係由DMA控制裝置3 0授受其資料。在本實施形態，協同處理器部2 0內之記憶器之位址係由位址生成器所生成，因此，以協同處理器部2 0處理單純之返覆命令，則有高速處理之可能，同時，因運算是由RISC部1之ALU10來運算，因此可以獲得與 R I S C部1所作者同等之運算精確度。同時， ALU10是由RISC部1與協同處理器部20共用，因此可以縮小整体之佔有面積。而在協同處理器部2 0內之不必使用A LU 10之命本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) -10- (請先閱讀背面之注意事項 .— 本頁)ϋ n mmmmm I-line paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) f 7 2 8 9, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7__ V. Description of the invention (7 ) On the other hand, if the decoded command is to be processed by the coprocessor unit 20, the decoder 7 sends a set signal to the control register 21 of the coprocessor unit 20 to send a set signal from the universal The register 8 sends various control signals to the control register 21 and sets them. After the various control registers are set in the control temporary register 2 1, a start signal is sent from the decoder 7 to the main controller 2 2. Therefore, the main controller 2 2 sends the instruction signal to the address generator 2 3, 24, 27 according to the control set in the control register 21, and is generated by the address generator 2 3, 24, 27. Address. Therefore, various addresses are generated from the address generators 2 3 and 2 4, and the data stored at these addresses are read out by the memories 2 5 and 2 6 and sent to A L U 1 0. At the same time, the main controller 22 sends a command signal to the ALU 10, and performs calculations based on the data read from the above-mentioned memories 25, 26. The operation result is stored in the address of the memory 28 generated by the address generator 27 according to the instruction signal of the main controller 22. These memories 25, 26, 28 and the memory 1 2 of the R I S C section 1 are given their data by the DMA control device 30. In this embodiment, the address of the memory in the coprocessor section 20 is generated by the address generator. Therefore, if the coprocessor section 20 processes a simple reply command, it may be processed at high speed. At the same time, since the calculation is performed by the ALU10 of the RISC section 1, the same calculation accuracy as that of the author of the RISC section 1 can be obtained. At the same time, the ALU 10 is shared by the RISC unit 1 and the coprocessor unit 20, so that the overall occupied area can be reduced. And in the co-processor department 20, it is not necessary to use A LU 10. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -10- (Please read the precautions on the back first.-This page)

! I I — I 訂·！ I I I I i 498275 A7 B7 五、發明說明（8) 令之處理，則可以與R I S C部1之其他處理同時並行進行。 ;同時，RISC部1之記憶器12與協同處理器部 2 0之記憶器2 5、2 6、2 8之間之資料係經由D Μ A 控制裝置3 0轉送，因此其架構會較傳統之處理器裝置簡單。其次，第2圖係表示本發明處理器裝置之第2實施形態之架構之方塊圖。此第2實施形態之處理器裝置係將第 1實施形態之處理器裝置之R I S C部1之A L U 1 0改用運算部10A，同時以協同處理器部2 0 A取代協同處理器部2 0之架構者，例如使用在語音處理用疊入相關處理。再者，在第2圖，R I SC部1僅表示運算部1 0A ，其他要素予省略。運算部1 0A具備有積和運算器（以下簡稱MAC ( Multiply and Accumulate ) ) 1 0 a、移位電路 1 〇 b 及圓化電路1 0 c。協同處理器部2 0A係在第1實施形態之協同處理器部 20 附加暫存器 31、32、33、34、35、36 、3 7之架構。暫存器3 1、3 2設在主控制器2 2與位址生成器27之間，暫存器33、3 4設在主控制器22 與移位電路1 0 b之間，暫存器3 5設在記億器2 5與 MAC 1 〇 a之間，暫存器3 6設在記憶器2 6與 MAC 1 〇 a之間，暫存器37設在MAC 1 〇 a與移位電路1 0 b之間。本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------—— ΙΓ 裝 (請先閱t#-背面之，注意事項t寫本頁) ----訂----- 經濟部智慧財產局員工消費合作社印製 498275 第89109959號專利申請案中文說明書修正頁民國90年1〇 f! I I — I order! I I I I i 498275 A7 B7 V. Description of the invention (8) The processing of the order can be performed concurrently with other processing of the R I S C section 1. At the same time, the data between the memory 12 of the RISC part 1 and the memory 25, 26, 28 of the coprocessor part 20 are transferred through the D M A control device 30, so its structure will be more traditional The processor device is simple. Next, Fig. 2 is a block diagram showing the structure of the second embodiment of the processor device of the present invention. The processor device of the second embodiment is to replace the ALU 10 of the RISC section 1 of the processor device of the first embodiment with the arithmetic section 10A, and replace the coprocessor section 2 0 with the coprocessor section 2 A. Architects, for example, use overlay processing for speech processing. Note that in FIG. 2, the R I SC section 1 only indicates the arithmetic section 10A, and other elements are omitted. The computing unit 10A includes a product sum calculator (hereinafter referred to as MAC (Multiply and Accumulate)) 1 0a, a shift circuit 1 0b, and a rounding circuit 10c. The coprocessor section 20A is a structure in which a register 31, 32, 33, 34, 35, 36, 37 is added to the coprocessor section 20 of the first embodiment. Registers 3 1, 3 2 are provided between the main controller 22 and the address generator 27, and registers 33, 3 4 are provided between the main controller 22 and the shift circuit 1 0 b. 3 5 is located between the memory register 25 and the MAC 1 〇a, the temporary register 36 is located between the memory 26 and the MAC 1 〇a, and the temporary register 37 is located between the MAC 1 〇a and the shift circuit Between 1 0 b. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) ---------- ΙΓ installed (please read t # -back side first, note this page to write this page) ---- Order ----- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 498275 Patent Application No. 89109959 Amendment of the Chinese Manual of the Republic of China 10f

正修五、發明説明（9) (請先閲讀背面之注意事項再填寫本頁) 控制用暫存器2 1用以記憶5個輸入控制信號ROUND ENABLE， RSHIFT ENABLE， SHIFT LENGTH ^ DATA LENGTH，CONTR及1個輸出控制信號B U S Y 。控芾!1信號 C〇N T R用在相關函數運算處理及疊入運算處理之選擇，控制信號DATA LENGTH用以設定輸入資料之長度，控制信號SHIFT LENGTH用以設定積和後之移位長度。而控制信號RSHIFT ENABLE用以向右側移位，控制信號ROUND ENABLE用以設定運算處理之最後要不要圓形化處理。而控制信號B U S Y則用以表示協同處理器部2 0 A是否在執行中。再者，上述5個輸入控制信號係由萬用暫存器8，定置信號則由解碼器7送至控制用暫存器2 1。訂本實施形態之處理器裝置所使用之位址生成器2 3、 ¾ 2 4、2 7分別具有第3圖所示之架構。亦即，各位址生成器具備有位址暫存器4 1，選擇器4 2，加減法器4 3 ，可依據由主控制器2 2送來之增分信號，S E T信號及加減法信號，生成下一位址。位址暫存器4 1儲存有現在之位址。經濟部智慧財產局員工消費合作社印製其次說明位址生成器之動作。S E T信號之値爲「1 」時，由選擇器4 2選擇增分信號而送至加減法器4 3，增分信號則直接由加減法器4 3輸出，成爲下一位址信號。另一方面，S E T信號之値爲「〇」時，由選擇器4 2 選擇儲存在位址暫存器4 1之現在位址及增分信號而送至加減法器4 3。這時，若加減法信號之値爲「0」時，力口上現在之位址及增分信號之値，此加算結果由加減法器本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -12 498275 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（10) 4 3作爲下一位址信號輸出。另一方面，若加減法信號之値爲「1」時，則在加減法器4 3運算現在之位址與增分信·號之差，此加算結果由加減法器4 3作爲下一位址信號輸出。位址暫存器4 1則在接到此下一位址信號時更新位址。而本實施形態所使用之處理器裝置之主控制器2 2具有第4圖所示之架構。亦即，主控制器2 2具備有計數器 5 1、暫存器52、比較器53及狀態遷移電路54。其次說明此第4圖所示之主控制器2 2之動作。首先，例如第1圖所示，由R I S C部1之解碼器7將起動信號送給狀態遷移電路5 4時，儲存在控制用暫存器2 1之控制信號値則被取進，狀態遷移電路5 4從復置狀態移至起動狀態。這時從狀態遷移電路5 4輸出値「1」之 BUSY信號。於是，爲了設定記憶器25、26之初期位址，從狀態遷移電路5 4將値「1」之S E T信號，成爲各記憶器2 5、2 6之初期位址之增分信號送至位址生成器23、24，從位址生成器23、24分別輸出成爲各初期位址之下一位址信號。再者，設定記憶器2 8之初期位址用之SET信號及增分信號係介由暫存器31、 3 2送至位址生成器2 7。這是爲了要以所希望之定時生成位址之故。如此在位址生成器2 3、2 4，設定初期位址後狀態遷移電路5 4便從起動狀態移至計算狀態。而由狀態遷移電路5 4向運算部1 0A送出控制信號。這時，收容於設 <請先閱讀背面之注意·Correction 5. Description of the invention (9) (Please read the notes on the back before filling this page) Control register 2 1 is used to memorize 5 input control signals ROUND ENABLE, RSHIFT ENABLE, SHIFT LENGTH ^ DATA LENGTH, CONTR and 1 output control signal BUSY. The control signal 1 is used for the selection of correlation function calculation processing and overlap calculation processing. The control signal DATA LENGTH is used to set the length of the input data, and the control signal SHIFT LENGTH is used to set the shift length of the product sum. The control signal RSHIFT ENABLE is used to shift to the right, and the control signal ROUND ENABLE is used to set whether or not rounding is performed at the end of the calculation process. The control signal B U S Y is used to indicate whether the coprocessor section 20 A is being executed. Furthermore, the above five input control signals are sent from the universal register 8 and the set signals are sent from the decoder 7 to the control register 21. The address generators 2 3, ¾ 2 4, and 2 7 used in the processor device of this embodiment have the architecture shown in FIG. 3, respectively. That is, each address generator is provided with an address register 4 1, a selector 4 2, and an adder-subtractor 4 3, which can be based on the increment signal, the SET signal, and the addition and subtraction signals sent from the main controller 2 2. Generate the next address. The address register 41 stores the current address. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, the operation of the address generator will be explained. When the S E T signal is "1", the selector 4 2 selects the incremental signal and sends it to the adder-subtractor 43. The incremental signal is directly output by the adder-subtractor 43 and becomes the next address signal. On the other hand, when the E of the S E T signal is "0", the selector 4 2 selects the current address stored in the address register 41 1 and the increment signal, and sends it to the adder-subtractor 43. At this time, if the signal of the addition and subtraction signal is "0", the current address and the signal of the incremental signal on the force mouth. The result of the addition is calculated by the Chinese paper standard (CNS) A4 (210X297 mm). ) -12 498275 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of Invention (10) 4 3 is output as the next address signal. On the other hand, if the 値 of the addition and subtraction signal is "1", the difference between the current address and the incremental signal · number is calculated by the addition and subtraction device 4 3, and the addition result is obtained by the addition and subtraction device 4 3 as the next bit. Address signal output. The address register 41 updates the address when receiving this next address signal. The main controller 22 of the processor device used in this embodiment has a structure shown in FIG. That is, the main controller 22 includes a counter 51, a register 52, a comparator 53, and a state transition circuit 54. Next, the operation of the main controller 22 shown in FIG. 4 will be described. First, for example, as shown in FIG. 1, when the decoder 7 of the RISC unit 1 sends the start signal to the state transition circuit 54, the control signal stored in the control register 21 is taken in, and the state transition circuit 5 4 Move from reset to start. At this time, the "SY" BUSY signal is output from the state transition circuit 54. Then, in order to set the initial addresses of the memories 25 and 26, the state transition circuit 54 sends the SET signal of "1" to the incremental points of the initial addresses of the memories 25 and 26 to the addresses. The generators 23 and 24 respectively output an address signal below each initial address from the address generators 23 and 24. Furthermore, the SET signal and the incremental signal for the initial address of the setting memory 28 are sent to the address generator 27 through the registers 31 and 32. This is to generate addresses at the desired timing. In this way, in the address generators 2 3 and 2 4, the state transition circuit 5 4 moves from the starting state to the calculating state after the initial address is set. The state transition circuit 54 sends a control signal to the arithmetic unit 10A. At this time, contained in the device < Please read the note on the back first ·

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I ϋ ϋ ϋ ϋ 1 ϋ I I I 線一本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 498275 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（11) 定在位址生成器23、24之記憶器25、26之各初期位址之資料分別送至暫存器3 5、3 6。將控制信號送至運··算部1 0A後MAC 1 0 a便運算儲存在暫存器3 5、 3 6之資料之積（積和）。另一方面，狀態遷移電路5 4在其內部有儲存設定成一定値之値之暫存器（未圖示），從位址生成器2 4送來之下一位址信號不等於上述一定値時，向位址生成器2 3 、2 4送出値「0」之SET信號，同時分別送出加減法信號及增分信號，令位址增減。於是，儲存於此增減之位址之資料從記憶器2 5、2 6分別送至暫存器3 5、3 6 ，藉MAC 1 〇 a運算上述資料之積。而在MAC 1 〇 a 運算此積與以前求得之積和之和。追種積和運算一直進行到從位址生成器2 4送到狀態遷移電路5 4之下一位址信號等於上述一定値爲止。從位址生成器2 4送來之下一位址信號變成上述一定値以下時，狀態遷移電路5 4便從計算狀態移至完成檢查狀態，而向比較器5 3送出定時信號’同時也將定時信號送給計數器51。於是，比較器5 3便比較儲存在暫存器 5 2之値，與從控制暫存器2 1送來之値DATA LENGTH，將比較結果送出到狀態遷移電路5 4 °若向計數器5 1送來定時信號，計數器便輸出儲存在暫存器5 2之値加1之値，而儲存在暫存器5 2。儲存在暫存器5 2之値是在値DATA LENGTH以下時，狀態遷移電路5 4回到起動狀態’而返覆上述程序。這時 ------ΓΓ丨裝 (請先閱t#'背面6注意事寫本頁) • ϋ ϋ l__i I II I 訂-!! t 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） -14 - 經濟部智慧財產局員工消費合作社印製 498275 A7 ___B7_____ 五、發明說明（12) ，狀態遷移電路5 4將控制信號送至M A C 1 〇 a，指令將運算之積和經由暫存器3 7、移位電路1 0 b、圓化電路1 0 c送至記憶器2 8 ’同時進行將上述積和儲存在記憶器2 8用之位址設定’將上述積和儲存在記憶器2 8。再者，在位址生成器2 4初期設定之位址一般與上一次不同。而儲存暫存器5 2之値較値DATA LENGTH爲大時，狀態遷移電路5 4成爲復置狀態’暫存器5 2之値被復置成零，同時輸出値「0」之B U S Y信號。茲以運算疊入時爲例子說明本實施形態之處理裝置之動作。 . N+ 1個資料a〇....... aN，與N+ 1個資料b〇， ......bN之疊入Yj ( j = 0....... N)由下式表不之。〔式1〕 3 Υ. -Σ a-* b.. ……（1) 3 i:0 1 ” 運算這些疊入Y j ( j = 〇....... N)時’首先從 R I S C部1之解碼器7向控制暫存器2 1送出設定運算疊入之控制信號C Ο N T R及設定資料長度之控制信號 DATA LENGTH等。例如，命令CON TR之値爲「〇」時運算疊入，「1」時運算相關函數。而DATA LENGTH之値則設定爲「N」。I ϋ ϋ ϋ ϋ 1 ϋ Line III A paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 498275 A7 B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The data of each initial address in the memories 25 and 26 of the address generators 23 and 24 are sent to the temporary registers 3 5 and 36, respectively. After sending the control signal to the operation department 1 0A, the MAC 1 0 a calculates the product (product sum) of the data stored in the temporary registers 3 5 and 36. On the other hand, the state transition circuit 54 has an internal register (not shown) that stores a certain setting, and the next bit signal sent from the address generator 2 4 is not equal to the above predetermined value. At this time, the SET signal of "0" is sent to the address generators 2 3 and 24, and the addition and subtraction signals and the increment signal are respectively sent to increase or decrease the address. Therefore, the data stored at the increased and decreased addresses are sent from the memory 25, 26 to the temporary registers 3 5, 36, respectively, and the product of the above data is calculated by the MAC 10a. At MAC 1 oa, the sum of this product and the sum of the previous ones is calculated. The product summing operation is continued until the address signal from the address generator 24 to the state transition circuit 54 is equal to the above-mentioned certain threshold. When the next bit address signal sent from the address generator 2 4 becomes the above-mentioned fixed value or lower, the state transition circuit 5 4 moves from the calculation state to the completion check state, and sends a timing signal to the comparator 5 3 at the same time. The timing signal is sent to the counter 51. Thus, the comparator 5 3 compares the data stored in the register 5 2 with the data DATA LENGTH sent from the control register 2 1 and sends the comparison result to the state transition circuit 5 4 ° If it sends to the counter 5 1 When a timing signal is received, the counter outputs the value stored in register 5 2 plus 1 and stored in register 5 2. When one of the values stored in the register 5 2 is less than or equal to “DATA LENGTH”, the state transition circuit 54 returns to the starting state and returns to the above procedure. At this time ------ ΓΓ 丨 installed (please read t # 'back 6 notes to write this page first) • ϋ ϋ l__i I II I order-!! t This paper size applies Chinese National Standard (CNS) A4 specifications ( (210 x 297 mm) -14-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498275 A7 ___B7_____ 5. Description of the Invention (12), the state transition circuit 5 4 sends the control signal to MAC 1 〇a, which instructs the product of the operation And send to memory 2 8 through register 3 7, shift circuit 1 0 b, rounding circuit 1 0 c 'to set the address for storing the above product in memory 2 8 at the same time' Stored in memory 2 8. In addition, the address initially set in the address generator 24 is generally different from the last time. When the value of the storage register 5 2 is larger than that of the DATA LENGTH, the state transition circuit 54 is reset. The register 5 2 is reset to zero, and at the same time, a B U S Y signal of "0" is output. The operation of the processing device according to this embodiment will be described by taking an example of the calculation overlap. . N + 1 data a〇 ....... aN, and N + 1 data b〇, ... bN overlap Yj (j = 0 ....... N) from the following The style is different. [Equation 1] 3 Υ. -Σ a- * b .. …… (1) 3 i: 0 1 ”When calculating these superimposed Y j (j = 〇 ....... N), first from RISC The decoder 7 of the part 1 sends the control signal C 0 NTR for setting the calculation overlap to the control register 2 1 and the data signal DATA LENGTH for the setting data length. For example, when the command CON TR is "0", the operation overlaps , "1" calculates related functions. The DATA LENGTH is set to "N".

在此狀態下，若由解碼器7送出起動信號後’則由主控制器2 2之狀態遷移電路5 4輸出値「1」之B U S Y I!訂！ ί 線秦 (請先閱讀背面之注意事項4HP寫本頁) 寫太本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -15 - 498275 A7 B7__ 五、發明說明（13) 信號，同時，爲了設定記憶器2 5、2 6之初期位址，向位址生成電路23、24送出値「1」之SET信號與値「0」之增分信號。藉此由位址生成電路2 3、24輸出値「0」之下一位址信號，由對應之記憶器2 5、2 6將分別儲存在「0」之位址之資料a。· b 〇送給暫存器3 5 、3 6 0 在從位址生成電路2 4接受下一位址信號前，從狀態遷移電路5 4將控制信號送至運算部1 0 A之 m MAClOa，由MAClOa運算儲存在暫存器35、 36之資料3〇，13。之積3。.13()(積和）。另一方面，狀態遷移電路5 4在未圖示之暫存器儲存有値爲「0」之一定値，而比較此値與從位址生成器2 4 送來之下一位址信號。這時，因下一位址信號之値與上述一定値相同，因此由狀態遷移電路5 4經由暫存器3 3將控制信號送給M A C 1 〇 a，M A C 1 〇 a所運算之積和 γ 〇 ( = a ο · b 〇 )則經由暫存器3 7、移位電路1 0 b，圓化電路1 0 c送給記憶器2 8。這時，由狀態遷移電路 5 4初期設定在位址生成電路2 7之値「0」之下一位址信號輸出到記億器2 8。藉此’在記億器2 8之位址^ 0 」處儲存上述積和Y。（參照第5圖）。因從位址生成器2 4送來之下一位址信號之値與上述一定値相同，狀態遷移電路5 4由計算狀態移行至完成檢查狀態。這時，儲存在第4圖所示主控制器2 2之暫存器 5 2之値爲「〇」，因此，被比較器5 3判定爲較信號 (請先閲讀背面之注意事項寫本頁) • I — I — I — I 訂·！！！ *^ i 經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -16 - 7 2 8 49 經濟部智慧財產局員工消費合作社印製 A7 _ B7 五、發明說明（14 ) DATA LENGTH之値爲小，狀態遷移電路5 4移行至起動狀態。於是，主控制器2 2之計數器便進行在儲存於暫存器 5 2之値加1之運算，將運算結果儲存在暫存器5 2。又因狀態遷移電路5 4移行至起動狀態，由狀態遷移電路5 4將位址生成器2 3、2 4之初期位址分別設定成「0」，「1」。於是，儲存在記憶器25之位址「0」之資料a 〇被送至暫存器3 5，同時，記憶器2 6之儲存在位址「1」之資料b i被送至暫存器3 6。.接著，狀態遷移電路5 4移行至計算狀態，由狀態遷移電路5 4將控制信號送給MAClOa ，運算積ao.bi。這時因從位址生成器2 4送來之下一位址信號之値爲「1」，因而由狀態遷移電路5 4輸出，可使從位址生成器2 3輸出之下一位址信號之値增加「1」，同時從位址生成器2 4輸出之下一位址信號之値減少「1」之S E T信號、增分信號，力口減法信號。於是，儲存在記憶器2 5之位址「1」之資料 a i被儲存至暫存器35，同時，記憶器26之儲存在位址「0」之資料bQ被儲存至暫存器3 6。接著，從狀態遷移電路5 4向M A C 1 0 a送出控制信號’在MAC 1 0 a運算積ai.bo ’冋時運算此積ai •b〇與先前運算之積和a〇.bi之積和（=a〇.bi+ a 1 · b 〇 ) 〇而狀態遷移電路5 4則因從位址生成器2 4送來之下一位址信號之値等於一定値「〇」，因此由狀態遷移電路 5 4將控制信號送給M A C 1 0 a ’經由暫存器3 7、移本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -17 - -------訂-------線) (請先閱讀背面之注意事項@寫本頁) j 之處所（參照第5圖 498275 A7 ____B7_— —___ 五、發明說明（15) 位電路l〇b，圓化電路l〇c，將運算之積和Yl (二 a 〇 · b ! + a ! . b。）送給記憶器2 8。這時因狀態遷移電路54介由暫存器33、34控制位址生成器27 ’由位址生成器2 7輸出値「1」之下一位址信號，上述積和 Y 1則儲存在記憶器2 8之位址而因從位址生成器2 4送來之下一位址信號之値與上述一定値相等，狀態遷移電路5 4由計算狀態移行至完成檢查狀態。這時儲存在第4圖所示主控制器2 2之暫存器 5 2之値爲「1」，此値被比較器5 3判定爲較信號 DATA LENGTH之値「N」爲小。因此狀態遷移電路5 4移行至起動狀態，而如上述依序求出疊入Y 2....... Yn，分別儲存在各記憶器2 8之位址「2」，···…「N」之處所。再者，運算Yj ( j = 0....... N)時，初期設定在位址生成器2 3、2 4之位址分別爲「0」，「j」。再者’在進行上述疊入運算之前’預先藉]：)!^^控制裝置在記憶器2 5儲存資料a 〇....... a n ,在記憶器2 6 (請先閱讀背面之注意事項 — 寫本頁) !1 訂·！儲存資料b b 經濟部智慧財產局員工消費合作社印製In this state, if the start signal is sent by the decoder 7 ', the state transition circuit 5 4 of the main controller 2 2 outputs 値 "1" of B U S Y I! Order! ί Line Qin (Please read the precautions on the back of this page to write this page) The size of the paper used for writing is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -15-498275 A7 B7__ V. Description of the Invention At the same time, in order to set the initial address of the memory 25, 26, the address generation circuit 23, 24 sends a SET signal of "1" and an incremental signal of "0". By this, the address generating circuit 2 3, 24 outputs the address signal under 値 "0", and the corresponding memory 2 5 and 26 will store the data a at the address "0", respectively. · B 〇 send to the register 3 5, 3 6 0 before receiving the next address signal from the address generation circuit 24, from the state transition circuit 54 to send the control signal to the arithmetic unit 10 A m MAClOa, The data stored in the registers 35, 36 are calculated by MAC10Aa 30, 13. The product 3. .13 () (product sum). On the other hand, the state transition circuit 54 stores a certain bit "0" in a register (not shown), and compares this bit with the next bit address signal sent from the address generator 24. At this time, since the 値 of the next address signal is the same as the above-mentioned fixed 状态, the state transition circuit 54 sends the control signal to the MAC 1 〇a through the register 33, and the product sum γ 〇 calculated by the MAC 1 〇a. (= a ο · b 〇) is sent to the memory 28 via the temporary register 37, the shift circuit 10b, and the rounding circuit 10c. At this time, the state transition circuit 54 initially sets an address signal below "0" of the address generation circuit 27 to the billion register 28. In this way, the above product sum Y is stored at the address ^ 0 ″ of the billion register 28. (Refer to Figure 5). Since the signal of the next bit signal sent from the address generator 24 is the same as the above-mentioned certain signal, the state transition circuit 54 moves from the calculation state to the completion check state. At this time, 値 stored in the register 5 2 of the main controller 2 2 shown in FIG. 4 is “0”, so it is judged as a signal by the comparator 5 3 (please read the precautions on the back to write this page) • I — I — I — I Order! !! !! * ^ i Printed on the paper by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) -16-7 2 8 49 _ B7 V. Description of the invention (14) The size of DATA LENGTH is small, and the state transition circuit 54 moves to the starting state. Then, the counter of the main controller 22 performs an operation of adding 1 to the register 5 2 to store the operation result in the register 5 2. Because the state transition circuit 54 moves to the starting state, the initial addresses of the address generators 2 3 and 24 are set to "0" and "1" by the state transition circuit 54. Then, the data a 0 stored at the address “0” stored in the memory 25 is sent to the register 3 5, and the data bi stored at the address “1” of the memory 26 is sent to the register 3 6. Then, the state transition circuit 54 moves to the calculation state, and the state transition circuit 54 sends the control signal to MAC10a, and calculates the product ao.bi. At this time, since one of the next address signals sent from the address generator 2 4 is "1", the state transition circuit 5 4 outputs, which enables the output of the next address signal from the address generator 2 3 to be output.値 Increase “1”, and output the address signal of the next bit from the address generator 24. 値 Decrease the SET signal and the incremental signal of “1”, and force the subtraction signal. Then, the data a i stored at the address "1" stored in the memory 25 is stored in the register 35, and at the same time, the data bQ stored in the memory 26 at the address "0" is stored in the register 36. Next, a control signal is sent from the state transition circuit 54 to the MAC 1 0 a 'to calculate the product ai.bo at the time of the MAC 1 0 a operation ai.bo' 和 The product ai • b〇 and the product of the previous operation sum a0.bi (= A〇.bi + a 1 · b 〇) 〇 The state transition circuit 54 is sent from the address generator 24 to the next bit signal 値 equal to a certain 値 "〇", so the state transition circuit 5 4 Send the control signal to the MAC 1 0 a 'Via the temporary register 3 7. The size of the paper is adapted to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -17-------- Order ------- line) (Please read the precautions on the back @write this page) j Places (refer to Figure 5 498275 A7 ____B7_ — —___ V. Description of the invention (15) Bit circuit 10b, round The circuit 10c sends the product sum Yl (two a 0 · b! + A!. B.) To the memory 28. At this time, the state transition circuit 54 controls the address through the temporary registers 33 and 34. The generator 27 'is output by the address generator 2 7 値 "1", and the above product Y 1 is stored in the address of the memory 2 8 because it is sent from the address generator 2 4 Concurrence of the next address signal The above must be equal, and the state transition circuit 54 moves from the calculation state to the completed check state. At this time, the register 5 2 stored in the main controller 2 2 shown in FIG. 4 is “1”, which is compared by the comparator. 5 3 is judged to be smaller than "N" of the signal DATA LENGTH. Therefore, the state transition circuit 5 4 moves to the starting state, and as described above, the overlapped Y 2 ....... Yn are obtained in order and stored in Each memory 28 has an address "2", ..... "N". In addition, when calculating Yj (j = 0 ......... N), the address generator 2 is initially set. The addresses of 3, 2 and 4 are "0" and "j". Furthermore, 'before borrowing' before performing the above-mentioned overlay operation, 'pre-borrow] :)! ^^ The control device stores data a in memory 2 5 a ... .... an, in the memory 2 6 (Please read the precautions on the back-write this page)! 1 Order ·! Stored data b b Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

如以上所說明求出Y 0 Ν 其次，也可以同樣求出相關函數，茲簡單說明如τ 相關函數Z; ( j = 〇....... N)以下式表示之。〔式2〕Finding Y 0 Ν as described above Secondly, the correlation function can also be obtained in the same way, and it will be briefly explained as τ correlation function Z; (j = 〇 ....... N) The following formula is used to express it. [Formula 2]

Z N Σ 1=3 1-3 ······ (2) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱Ί 經濟部智慧財產局員工消費合作社印製 498275 A7 _ B7___ _ 五、發明說明（16) 運算這些相關函數Z; ( j = 〇，……N )時，首先從 R I S C部1之解碼器7向控制暫存器2 1送出設定，値「1」之信號C〇N T R及値N之信號DATA LENGTH。以此狀態由解碼器7送出起動信號，使主控制器2 2 動作以運算相關函數Z ^ ( j = 〇，……N )。此項動作與運算疊入時基本上是相同，但有下列幾點不一樣。 (a )儲存在狀態遷移電路5 4內之未圖示之暫存器之一定値爲「N」。 (b )求出相關函數Ζ』時，設定在位址生成器2 3、 2 4、2 7之位址分別爲「0」’ 「j」，「j」，而由狀態遷移電路5 4驅動控制，使任一位址生成器其位址均只增加^ 1」。如此求得之相關函數Z ^ ( j二〇，……N )在記憶器 2 8之位址爲「j」時被儲存下來（參照第6圖）。表1表示，使用本實施形態之處理裝置進行，包含有疊入運算與求出相關函數之運算之G7 2 3、1( I TU-T ( International Telecommunication Union-Telecommunication Standard Sector )(國際電氣通信連合一電氣通信標準化部門））之語音編碼運算法之高速率編· 處理時，與僅使用R I S C處理時之比較。本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -19- -1— 訂-!-線{ (請先閱讀背面之注意事項Λϋ寫本頁) _ 498275 A7 ___B7 五、發明説明（丨b-l) 〔表1〕函數名硬體命令呼叫次數相當於1命令之步驟 mips 値僅用 RISC 本發明僅用 RISC 本發明適應碼冊探索疊入 14 26661 2000 12.32 0.92 固定碼冊探索疊入 64 24743 2000 52.26 4.22 自己相關 8 24155 2000 6.38 0.53 互相相關 8 25326 2000 6.59 0.53 計 77.64 6.20 (b) 僅用RISC 本發明編碼器 133.3mips 61.9mips 解碼器 6.1 mips 計 1 39.4mips 68.0mips ------S---r---- (請先閲讀背面之注意事項本頁) 訂 it 經濟部智慧財產局員工消費合作社印製在此，步驟數之合計係每一碼框之値，一個碼框係本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）一丨9 一 I〜 498275 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明說明（17) 2 7 m s e c 〇從上述表1可以看出，若使用本實施形態之處理裝置，：則可以使運算量爲6 8 · 0 m i p s ( million instruction per second )，較之僅用R I S C時之運算量 1 39 · 4mi p s，可以大幅度減少。而這個時候之本實施形態之處理裝置之面積則僅較R I S C時增加數K閘而已。在本實施形態之處理裝置，協同處理部在動作時， R I S C部1無法使用協同處理部在使用之運算器（例如第2圖之MAClOa、移位電路、圓化電路）。但是關於使用協同處理部未在使用之運算器（未圖示，但例如加法器、比較器）之命令，R I S C部1將進行平常之動作，而在要使用協同處理部在使用之運算器之命令到達時， R I S C部1便停止動作，而在協同處理部完成處理時由 R I SC部1再度開始動作，便可以由R I SC部1與處理部並聯處理。同時，在傳統之處理裝置，RI SC部1之 ALU 1 0係如第8圖所示，將輸入之兩個輸入信號 INI、IN2，依據指令信號，經選擇電路102送給選擇之運算器，例如MAC104a、加法器l〇4b，移位電路104c、圓化電路104d內之一個運算器，將運算結果經由選擇電路1 〇 6輸出，需要時可以將上述輸出當輸入信號INI、IN2內之一個，再度輸入。對此，本實施形態係如第2圖所示，A L U 1 〇 A內之運算 (請先閱讀背面之注意事 — i 項寫本頁 ϋ 1 I ϋ 1 ϋ^OJ· ϋ —i 1 ϋ ϋ ·1 ί 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 20^ 498275 A7 B7 五、發明說明（18) 器，例如MAClOa、移位電路l〇b，圓化電路 1 0 c係由協同處理部2 0A串聯連接在一起。因此，較之:傳統者，可以進行高速處理。同時，在上述實施形態，運算器M A C係僅設在主處理器側，但對應處理之運算，在R I S C部之運算器不夠用時，可如第9圖所示，在協同處理部側準備。第9圖所示之協同處理部2 0B，係在第2圖所示協同處理部 2 0A配設MAC 3 8及加法器3 9之架構。MAC 3 8 係依據儲存在暫存器3 5、3 6之値進行積和運算，將運算結果送到加法器3 9。而加法器3 9則將M A C 1 0 a 之輸出與MA C 3 8之輸出相加，將加算結果送到暫存器 3 7。再者，在上述實施形態係以疊入運算處理及相關函數之運算處理爲例子進行說明，但改變主控制器之功能，同時改變R I S C部1之運算器1 〇之功能，便可以進行慮波處理或 F E T ( Fast Fourier Transformation )等之信號處理。如以上所述，依據本發明時，不僅可以高速處理，又可以儘可能地縮小整体之佔用面積。圖式之簡單說明第1圖係表示本發明處理器裝置之第1實施形態之架構之方塊圖。第2圖係表示本發明處理器裝置之第2實施形態之架本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項本頁) 經濟部智慧財產局員工消費合作社印製 -21 - 498275 A7 B7 五、發明說明（19) 構之方塊圖。第3圖係表示本發明處理器裝置之位址生成器之架構之:方塊圖。第4圖係表示本發明處理器裝置之主控制器之架構之方塊圖。第5圖係表示疊入運算之資料之儲存模式圖。第6圖係表示求出相關函數之運算之資料之儲存模式圖。第7圖係表示傳統之處理器裝置之架構之方塊圖。第8圖係表示傳統之處理器裝置之A L U之架構之方塊圖。第9圖係表示本發明處理器裝置之其他實施形態之架構之方塊圖。主要元件對照表 (請先閱讀背面之注意事*31^:寫本頁) 經濟部智慧財產局員工消費合作社印製ZN Σ 1 = 3 1-3 ······ (2) This paper size applies to China National Standard (CNS) A4 (210 X 297 Public Love) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 498275 A7 _ B7___ _ V. Explanation of the invention (16) When calculating these correlation functions Z; (j = 〇, ... N), first send the setting from the decoder 7 of the RISC unit 1 to the control register 21, and the signal of "1" The signal DATA LENGTH of C〇NTR and 値 N. In this state, the decoder 7 sends a start signal to make the main controller 2 2 operate to calculate the correlation function Z ^ (j = 〇, ... N). This action and operation The overlap is basically the same, but the following points are different. (A) The non-illustrated register stored in the state transition circuit 54 must be "N". (B) Find the correlation function "Z", the addresses set in the address generators 2, 3, 2, 4, and 7 are "0", "j", and "j", and are driven and controlled by the state transition circuit 5 4 to make any address The address of the generator is only increased by ^ 1 ". The correlation function Z ^ (j20, ... N) thus obtained is stored when the address of memory 28 is" j " (Refer to Figure 6.) Table 1 shows that G7 2 3, 1 (I TU-T (International Telecommunication Union-Telecommunication) Standard Sector (International Electrical and Telecommunications Unified Electrical and Telecommunications Standardization Sector)) The comparison between the high-speed coding and processing of the speech coding algorithm and the processing using only RISC. This paper standard applies the Chinese National Standard (CNS) A4 specification 210 X 297 mm) -19- -1— order-!-Line {(Please read the precautions on the back to write this page) _ 498275 A7 ___B7 V. Description of the invention (丨 bl) [Table 1] Function name is hard The number of body command calls is equivalent to 1 step of the mips. 値 Only RISC is used. The present invention is only used for RISC. The present invention adapts to the codebook exploration overlay 14 26661 2000 12.32 0.92 Fixed codebook exploration overlay 64 24743 2000 52.26 4.22 Self-relevant 8 24155 2000 6.38 0.53 cross-correlation 8 25326 2000 6.59 0.53 count 77.64 6.20 (b) only RISC encoder of the present invention 133.3mips 61.9mips decoder 6.1 mips count 1 3 9.4mips 68.0mips ------ S --- r ---- (Please read the notes on the back page first) Order it Printed here by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economy, the total number of steps is One frame of each code frame is the size of the paper applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1 丨 9 1 ~ 498275 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation (17) 2 7 msec 〇 As can be seen from Table 1 above, if the processing device of this embodiment is used, the calculation amount can be 6 8 · 0 mips (million instruction per second), compared with when only RISC is used. The amount of calculation is 1 39 · 4mi ps, which can be greatly reduced. At this time, the area of the processing device of this embodiment is only increased by several K gates compared with the time of R I S C. In the processing device of this embodiment, when the cooperative processing unit is operating, the RIS C unit 1 cannot use the arithmetic unit used by the cooperative processing unit (for example, MAC10a, shift circuit, and rounding circuit in FIG. 2). However, regarding the order of using an arithmetic unit (not shown, but such as an adder, a comparator) which is not being used by the cooperative processing unit, the RISC unit 1 will perform ordinary operations, and will use an arithmetic unit which is used by the cooperative processing unit When the command arrives, the RISC unit 1 stops the operation, and when the cooperative processing unit completes the processing, the RI SC unit 1 starts the operation again, and the RI SC unit 1 and the processing unit can process in parallel. At the same time, in the conventional processing device, ALU 1 0 of RI SC section 1 sends the two input signals INI, IN2 as shown in FIG. 8 to the selected arithmetic unit via the selection circuit 102 according to the instruction signal. For example, one of the arithmetic units in the MAC 104a, the adder 104b, the shift circuit 104c, and the rounding circuit 104d outputs the operation result through the selection circuit 106, and when necessary, the above output can be used as one of the input signals INI and IN2. And enter again. In this regard, as shown in Figure 2, this embodiment is based on the calculations in ALU 1 〇A (please read the note on the back-item i to write this page ϋ 1 I ϋ 1 ϋ ^ OJ · ϋ —i 1 ϋ ϋ · 1 ί The paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 20 ^ 498275 A7 B7 V. Description of the invention (18) Device, such as MAC10A, shift circuit 10b, round circuit 1 0 c is connected in series by the cooperative processing unit 2 0A. Therefore, compared with the traditional one, high-speed processing can be performed. At the same time, in the above embodiment, the arithmetic unit MAC is set only on the main processor side, but the corresponding processing is For calculation, when the arithmetic unit of the RISC unit is not enough, it can be prepared on the cooperative processing unit side as shown in Figure 9. The cooperative processing unit 2 0B shown in Figure 9 is the cooperative processing unit 2 shown in Figure 2. 0A is equipped with the architecture of MAC 3 8 and adder 39. MAC 3 8 performs the product and sum operation according to the 暂 stored in the temporary registers 3 5 and 36, and sends the operation result to the adder 3 9 and the adder 3 9 adds the output of MAC 1 0 a and the output of MA C 3 8 and sends the result of the addition to the temporary register 3 7. Furthermore, above The implementation form is described by taking an example of superimposition arithmetic processing and arithmetic processing of related functions. However, if the function of the main controller is changed and the function of the arithmetic unit 1 of the RISC unit 1 is changed at the same time, wave filtering processing or FET (Fast Fourier Transformation, etc. As described above, according to the present invention, not only high-speed processing, but also the overall occupied area can be reduced as much as possible. Brief Description of the Drawings The first diagram shows the processor device of the present invention. The block diagram of the structure of the first embodiment. The second diagram shows the frame of the second embodiment of the processor device of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read first Note on the back page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -21-498275 A7 B7 V. Block diagram of the structure of the invention (19) Figure 3 shows the address generator of the processor device of the present invention Architecture: Block diagram. Figure 4 is a block diagram showing the architecture of the main controller of the processor device of the present invention. Figure 5 is a data showing the superposition operation. Storage mode diagram. Figure 6 shows the storage mode diagram of the data for calculating the correlation function. Figure 7 is a block diagram showing the architecture of a conventional processor device. Figure 8 shows the ALU of a conventional processor device. Block diagram of the architecture. Figure 9 is a block diagram showing the architecture of another embodiment of the processor device of the present invention. Comparison table of main components (please read the notes on the back first * 31 ^: Write this page) Intellectual Property of the Ministry of Economic Affairs Printed by Bureau Consumers Cooperative

1 R I S C 部 3 命令記憶器 4 命令讀入部 5 暫存器 6 命令解碼部 7 解碼器 8 萬用暫存器 9 暫存器 10 A L U 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 498275 A7 B7 五、發明說明（2Q) 11 暫存器 1 0 A 運算部 1 0 a Μ A C 1 0 b 移位電路 1 0 c 圓化電路 1 1 暫存器 1 2 記憶器 2 0 協同處理器部 2 1 控制用暫存器 2 2 主控制器 2 3 、 2 4 2 7 位址生成器 2 5 、 2 6 > 2 8 記憶器 (請先閱|**背面之\注意事 I I 裝·· I 寫本頁) 經濟部智慧財產局員工消費合作社印製 3 0 D Μ A 控制裝置 4 1 位址暫存器 4 2 暫存器 4 3 加減法器 5 1 計數器 5 2 暫存器 5 3 比較器 5 4 狀態 Μ 移電路 6 0 D S Ρ 部 — II 訂·！！！本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -23^1 RISC section 3 Command memory 4 Command read section 5 Register 6 Command decoding section 7 Decoder 8 Universal register 9 Register 10 ALU This paper standard applies to China National Standard (CNS) A4 specification (210 X 297mm) 498275 A7 B7 V. Description of the invention (2Q) 11 Register 1 0 A Operation unit 1 a a Μ AC 1 0 b Shift circuit 1 0 c Rounding circuit 1 1 Register 1 2 Memory 2 0 Coprocessor section 2 1 Control register 2 2 Main controller 2 3, 2 4 2 7 Address generator 2 5, 2 6 > 2 8 Memory (please read first | note on the back of ** (I write this page I write this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economy 3 0 D Μ A Control device 4 1 Address register 4 2 Register 4 3 Adder-subtractor 5 1 Counter 5 2 Register 5 3 Comparator 5 4 State M Shift Circuit 6 0 DS P Part — II Order! !! !! This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -23 ^

Claims

498275498275

A8 B8 C8 D8 々、申請專利範圍附件1 : 第89 109959號專利申請案 (請先閱讀背面之注意事項再填寫本頁) 中文申請專利範圍修正本民國91年5月修正 1 . 一種處理器裝置，其特徵在於，具備有主處理器部及協同處理器部，該主處理器部包含有：將取進之命令加以解碼之解碼器；儲存有資料，可將儲存在上述經解碼之命令所含之位址之資料輸出之暫存器部；記憶有資料之第1記憶器；以及，依據上述經解碼之命令，使用由上述暫存器部輸出之資料進行運算，將運算結果儲存於上述暫存器部或上述第 1記憶器之運算部；經濟部智慧財產局員工消費合作社印製該協同處理器部包含有：依照上述經解碼之命令’儲存從上述暫存器部送來之控制信號之値之控制用暫存器；生成位址之位址生成部；對應上述位址生成部配設之記憶部；以及，依據上述儲存在控制暫存器之控制信號値，將指令信號送給上述位址生成部，使其生成位址，將儲存在· 此生成之位址之資料從上述記憶部輸出，將此輸出之資料送至上述主處理器部之運算部，令其進行運算之主控制器〇 * 2 ·如申請專利範圍第1項之處理器裝置，其特徵在於，上述主處理器部之上述運算部具有多數運算元件，上述多數運算元件由上述協同處理器部之主控制器加以串聯連接。本g尺度適用中關家標準（CNS ) A4^ ( 21GX297公釐) I 一 498275 Α8 Β8 C8 D8 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 3 .如申請專利範圍第1項或第2項之處理器裝置，其特徵在於，上述主處理器部係R I S C部，上述主控制器係依據由上述解碼器送來之起動信號開始動作。 4 .如申請專利範圍第1項或第2項之處理器裝置，其特徵在於，上述位址生成器具有第1及第2之位址生成器，上述記憶部具有分別對應上述第1及第2位址生成器之第2及第3之記憶器。 5 .如申請專利範圍第4項之處理器裝置，其特徵在於，上述指令信號包含S E T信號、增分信號、及加減法信號，上述第1及第2之位址生成器分別具備有，保持現在之位址之位址暫存器，及應上述S E T信號及加減法信號之値，從保持在上述位址暫存器之位址與增分信號之値，運算下一個位址信號之位址運算器。 6 .如申請專利範圍第5項之處理器裝置，其特徵在經濟部智慧財產局員工消費合作社印製於，上述位址運算器在上述S E T信號之値爲「1」時，輸出上述增分信號作爲下一位址信號，上述S E T信號之値爲「0」時，依上述加減法信號之値，以現在之位址與增分信號之和或差作爲下一位址信號。 . 7 .如申請專利範圍第5項之處理器裝置，其特徵在於，上述主控制器具備有：暫存器；依據定時信號在上暫存器保持之値加1再令暫存器保持之計數器；將表示上述控制暫存器保持之輸入資料之長度之控制信號data 本^張尺度適用中國國家標準（CNS ) A4規格（210X297公釐1 ' 498275 A8 B8 C8 D8 々、申請專利範圍 LENGTH，與上述暫存器所保持之値，依據上述定時信號力口以比較之比較器；依據上述比較器之比較結果及上述第2 位址生成器所輸出之下一位址信號之値，遷移狀態，向上述第1及第2位址生成器輸出上述S E T信號、增分信號、及加減信號，同時向上述主處理器之運算部送出控制信號之狀態遷移電路。 8 .如申請專利範圍第7項之處理器裝置，其特徵在於，上述狀態遷移電路具有：復置狀態；接收起動信號，設定上述第1及第2位址生成器之初期位址之起動狀態；在設定上述初期位址後，送出上述運算部控制信號同時依序設定上述第1及第2位址生成器之位址，令上述運算器進行計算，返覆此計算，直到上述第2位址生成器之下一位址信號等於一定値之計算狀態；以及，上述計算狀態結束後，依據上述比較器之比較結果，檢查計算是否已結束，未完成時則回到上述起動狀態，已完成時回到上述復置狀態之完成檢查狀態。 9 .如申請專利範圍第7項之處理器裝置，其特徵在· 於，上述運算部具備有積和運算器。 1 〇 .如申請專利範圍第4項之處理器裝置，其特徵在於，上述協同處理器部進一步備有，可依據上述主控制器之指令信號生成位址之第3位址生成器，及將上述運算部輸出之運算結果儲存在此第3位址生成器所輸出之位址之第4記憶器。 1 1 .如申請專利範圍第1項或第2項之處理器裝置本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 1 -----裝-- (請先閱讀背面之注意事項再填寫本頁) 訂經濟部智慧財產局員工消費合作社印製 498275 A8 B8 C8 D8 六、申請專利範圍，其特徵在於，進一步備有，可以授受上述主處理部之記憶器及上述協同處理器部之記憶器部之資料之D Μ A控制 (請先閱讀背面之注意事項再填寫本頁) 裝置。 1 2 · —種處理器裝置，其特徵在於，具備有主處理器部及協同處理器部，該主處理器部具有：將取進之命令加以解碼之解碼器 :及依據上述解碼器解碼之命令，使用輸入之資料進行運算之運算部；該協同處理器部具有：依照上述解碼器解碼之命令之控制信號，將該協同處理器部使用之資料送至上述主處理器部之運算部之同時，使用該資料於上述運算部進行運算控制之主控制器。 1 3 .如申請專利範圍第1 2項之處理器裝置’其特徵在於，上述主處理器部之上述運算部具有多數運算元件，上述多數運算元件由上述協同處理器部之主控制器串聯連接。經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）A8 B8 C8 D8 々, Patent Application Scope Annex 1: Patent Application No. 89 109959 (please read the notes on the back before filling out this page) Chinese Patent Application Scope Amendment May 1991 Amendment 1. A processor device , Characterized in that it is provided with a main processor section and a co-processor section, the main processor section includes: a decoder that decodes the fetched command; and stores data that can be stored in the above-mentioned decoded command station. The register unit of the data output of the included address; the first memory that stores the data; and, according to the decoded command described above, the data output by the register unit is used for calculation, and the calculation result is stored in the above The register unit or the calculation unit of the above-mentioned first memory; the co-processor unit printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes: According to the above-mentioned decoded command, the control sent from the register unit is stored A register for controlling the signal; an address generating section for generating an address; a memory section corresponding to the above address generating section; and stored in accordance with the above The control signal of the temporary register is generated, and the instruction signal is sent to the above-mentioned address generation section, so that it generates an address, and the data stored in the generated address is output from the above-mentioned memory section, and the output data is sent to The computing unit of the main processor unit, which is the main controller for performing calculations. * 2. For the processor device of the first patent application scope, the computing unit of the main processor unit has a plurality of computing elements. The above-mentioned most computing elements are connected in series by the main controller of the co-processor section. This g standard applies to the Zhongguanjia Standard (CNS) A4 ^ (21GX297 mm) I 498275 Α8 Β8 C8 D8 VI. Scope of patent application (please read the precautions on the back before filling this page) 3. The processor device according to item 1 or item 2, characterized in that the main processor unit is a RISC unit, and the main controller starts operation based on a start signal sent from the decoder. 4. The processor device according to item 1 or item 2 of the patent application scope, characterized in that the above-mentioned address generator has the first and second address generators, and the memory unit has a correspondence to the above-mentioned first and second addresses, respectively. 2nd and 3rd memory of 2 address generator. 5. The processor device according to item 4 of the scope of patent application, wherein the instruction signal includes a SET signal, an increment signal, and an addition and subtraction signal, and the above-mentioned first and second address generators are respectively provided and maintained. The address register of the current address, and the one corresponding to the above SET signal and the addition and subtraction signal, calculate the bit of the next address signal from the address of the address register and the incremental signal held in the above address register. Address calculator. 6. The processor device according to item 5 of the scope of patent application, which is printed on the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the above address calculator outputs the above added points when one of the above SET signals is "1". The signal is used as the next address signal. When the 値 of the above SET signal is "0", the sum or difference between the current address and the incremental signal is used as the next digit signal according to the 値 of the above addition and subtraction signals. 7. The processor device according to item 5 of the scope of patent application, characterized in that the above main controller is provided with: a register; an increase of one held in the upper register according to the timing signal and then the register is held Counter; the control signal data indicating the length of the input data held by the above-mentioned control register. This standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm 1 '498275 A8 B8 C8 D8) 申请, the scope of patent application LENGTH, Comparing with the one held by the above-mentioned register, the comparator based on the timing signal to compare; based on the comparison result of the comparator and the next bit address signal output by the second address generator, the migration state A state transition circuit that outputs the SET signal, the increment signal, and the addition and subtraction signals to the first and second address generators, and sends a control signal to the arithmetic unit of the main processor at the same time. The processor device of the item is characterized in that the state transition circuit has a reset state, receives an activation signal, and sets an initial bit of the first and second address generators. After the initial address is set, the control signal of the calculation unit is sent out, and the addresses of the first and second address generators are sequentially set, so that the calculation is performed by the calculation unit, and the calculation is repeated until the above. After the calculation status of the second address generator is equal to a certain calculation state, and after the calculation state ends, check whether the calculation has been completed according to the comparison result of the comparator, and return to the starting state when it is not completed. When completed, it will return to the completion check state of the above reset state. 9. If the processor device of the scope of application for patent No. 7 is characterized in that the above-mentioned arithmetic unit is provided with a product and arithmetic unit. 1 〇. If applied The processor device according to item 4 of the patent is characterized in that the co-processor section further includes a third address generator that can generate an address according to the instruction signal of the main controller, and a third address generator that outputs the operation section. The result of the operation is stored in the fourth memory of the address output by this third address generator. 1 1. Such as the processor device of the first or second item of the scope of patent application Zhang scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) 1 ----- install-(Please read the precautions on the back before filling this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives 498275 A8 B8 C8 D8 6. The scope of patent application is characterized by further including D Μ A control that can be controlled by the data of the memory of the main processing unit and the memory unit of the co-processor unit above (please read the first Please fill in this page again for details). 1 2-A processor device, which is characterized by including a main processor section and a co-processor section, and the main processor section has: decoding and decoding the fetched command And a computing unit that uses the input data to perform operations based on the commands decoded by the decoder; the coprocessor unit has: according to the control signal of the decoder decoded command, the data used by the coprocessor unit is sent to At the same time as the arithmetic unit of the main processor unit, the main controller that uses the data to perform arithmetic control in the arithmetic unit. 13. The processor device according to item 12 of the patent application scope is characterized in that the operation unit of the main processor unit has a plurality of operation elements, and the plurality of operation elements are connected in series by the main controller of the coprocessor unit. . Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210X297 mm)