494619 A7 --- -_____ 五、發明説明（丨） 【本發明之領域】 本發明係有關驅動電路之技術領域，尤指一種可切換 電壓追隨器及使用該可切換電壓追隨器乏橋式驅動電路裝 置。 【本發明之背景】 第8 A圖及第8 B圖係分別顯示一種習知的波寬調變 (Pulse Width Modulation，PWM )橋式驅動器 (bridge driver)及其驅動波形，其藉由數位波寬調變 後的上波寬調變訊號（PWM-UP )與下波寬調變訊號 (P W Μ - D O W N )來驅動叉叉連接的輸出電體μ p 1、 Μ Ν 1、Μ Ρ 2及Μ Ν 2以驅動味]μ八8 1，並藉由啼j ρ八8 1的低 通濾波（low pass filtering )來轉換出音頻而輸出。這 種橋式驅動放大器構造簡單，且可以在低壓工作下輸出夠 大音量’但其在電壓源V D D高低變化時，輸出音量變化 相當大；且當電壓源VDD為高時，輸出電流大，而容易 在積體電路内部造成過大的暫態雜訊，引發積體電路工作 失誤，譬如誤觸發電源啓動之重置（p〇Wer on reset)等 等；此外，若電晶體MP1、MN1、MP2及MN2在佈局上 有不對稱，或因製程漂移而使（MP 1，MN 1 )的導通電 阻與（MP2，MN2 )的導通電阻不相等，則會引發非對 稱的失眞。 第9圖則顯示一種用於語音處理Ic以推動喇队的橋式 放大器（bridge amplifier)，其中語音數位處理電路輸 本纸張尺度適财關家標準（CNS ) A4規格（210X29/公慶) (請先閱讀背面之注意事項v -裝-- 、11 經濟部智慧財產局員工消費合作社印製 494619 Λ7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 出的資料（bo〜bio)先經由數位類比轉換器91 (digital to analog converter，DAC )轉成類比信號，再藉由單 端至差動轉換器 92 ( single ended t〇 differentU1 output converter)將信號轉成正極性信號¥1與負極性 信號V2，以分別推動兩個作為驅動器之AB類放大器”及 9 4，再由兩個驅動器輸出音頻驅動信號並推動喇叭9 $。 岫述之橋式驅動放大器所用的單端至差動轉換器9 2與 AB類放大器93及94的構造如第！ 〇圖所示；其優點是可以 單端推動喇队或接成橋式驅動喇p八以獲得四倍輸出功率， 然因單端至差動轉換器92會產生偏移（〇ffset)，而兩組 AB類放大器93及94内的運算放大器〇pu及opb會產生直 流偏移（dc offset )，此直流偏移以直流成份加在喇队 9 5上，會引發額外靜態電流消耗，造成橋式輸出 (SPK+，SPK-)的直流偏移過大之缺失。 此外’前述橋式驅動放大器之Ab放大器93及94的電 晶體MN 1、MP 1的靜態偏壓電流與喇队電阻之乘積必須 大於橋式輸出（SPK+，SPK-)的直流偏移，否則就會產 生父叉（cross-over)失眞，而一旦產生交叉失眞就需藉 由偏壓控制電路96之回授來抑制（參考美國專利 U S P 4，9 6 3，8 3 7號專利案），但由於偏壓控制電路9 6乃係 k供局部負回授，反而會使得Ab類放大器的開迴路增益 (open l〇op gain )降到只有1〇〜2〇倍，因此，其回授 I將不足以有效抑制交叉失眞，第丨丨圖便顯示輸入橋式驅 動放大裔之波形VIN與橋式輸出（spk+，SPK-)之波形 _ _ 本紙張尺度剌中國國家標準（CNS)A4規格（2i〇— 297公釐） --------------裝--- (請先閱讀背面之注意事^^^寫本頁) 訂- -丨線· A7 五、發明說明（今） X . SPK-)，其顯不橋式輸出波形（v V )具有明顯之交叉4 t招多士 K sp SPK' 驅動-踗奋古 《具見象。有鑑於此，前述習知之橋式 力％路貫有予以改進之必要。 人爰因於此，本於積極發明之精神，亟思一種可 壓、心ΐ述問題之「可切換電壓追隨器及使用該可切換電 之橋式驅動電路裝置」，幾經 驗終至完成 此項新穎進步之發明。 【本發明之概述】 本t月〈目的係在提供一可切換電壓追隨器及使用該 i刀換電壓追隨器之橋式驅動電路裝置，俾以有效解決習 知技術中之諸項缺失。 依據本發明《一特色，所提出之可切換電壓追隨器主 要包括：一輸出電晶體對，具有一 pM〇s電晶體與一 N山MOj電晶體，該兩電晶體之没極相連以作為―驅動輸出 I ’第、第一及第三切換器，該第二切換器之第一輸入 2連接電壓源，其輸出端連接該PM〇S(f晶體之閘極，該 f三切換器之第二輸人端連接系統低電位，其輸出端連接 孩NMOS電晶體之閘極；以及，_運算放大器，其正輸入 端係作^回授端並連接至該驅動輸出端，其負輸入端係連 接至該第一切換器之輸出端，其輸出端則連接至該第二切 換器之第二輸入端及第三切換器之第一輸入端；其中，每 一切換器均由一極性端所控制，以當該極性端輸入之數位 邏輯信號為第一狀態時，每一切換器之輸出端係切換連接 (請先閱讀背面之注意事寫本頁) -丨裝 . •線· 經濟部智慧財產局員工消費合作社印製 494619 經濟部智慧財產局員工消費合作社印製 Λ7 _ B7五、發明說明（斗） 至其第一輸入端，而當該極性端所輸入之數位邏輯信號為 第二狀態時，每一切換器之輸出端係切換連接至其第二輸 入端0 依據本發明之另一特色，所提出之橋式驅動電路裝置 主要包括第一及第二可切換電壓追隨器，每一可切換電壓 追隨器包括：一輸出電晶體對，具有一PMOS電晶體與一 NM 0 S電晶體，該兩電晶體之汲極相連以作為一驅動輸出 端；第一、第二及第三切換器，該第二切換器之第一輸入 端連接電壓源，其輸出端連接該PMOS電晶體之閘極，該 第三切換器之第二輸入端連接系統低電位，其輸出端連接 該NMOS電晶體之閘極，該第一切換器之第一及第二輸入 端係分別作為低態輸入端及高態輸入端，其中，每一切換 器均由一極性端所控制，以當該極性端輸入之數位邏輯信 號為第一狀態時，每一切換器之輸出端係切換連接至其第 一輸入端，而當該極性端所輸入之數位邏輯信號為第二狀 態時，每一切換器之輸出端係切換連接至其第二輸入端； 以及，一運算放大器，其正輸入端係作為回授端並連接至 該驅動輸出端，其負輸入端係連接至該第一切換器之輸出 端，其輸出端則連接至該第二切換器之第二輸入端及第三 切換器之第一輸入端；其中，該第一及第二可切換電壓追 隨器之低態輸入端係相連以作為低電位輸入端，兩者之高 態輸入端則相連以作為高電位輸入端，而兩者之極性端分 別作為極性切換端，以供輸入反相之極性切換邏輯信號。 _2_ 本紙張尺度適用中國國家標準（CNS)A4規格（2】〇χ 297公釐） (請先閱讀背面之注意事 寫本頁) ;裝 .線· Λ7 B7 五、發明說明（f ) 由於本發明設計新穎， 進功效，故依法申請專利。“疋供產業上利用，且確有增 為使貴審查委貢能 . ，及其目的，兹附以二 瞭解本發明之結構、特徵 后·· 、圖式及較佳具體實施例之詳細說明如 經濟部智慧財產局員Η消費合作社印製 【圖式簡單説明】 發明之橋式驅動電路裝置之功能方塊圖。 係本發明之可切換電壓追隨器之電路圖。 ..係本發明之橋式驅動電路裝置之—種電路組態。 -.係本發明《橋式驅動電路裝置之另一種電 態。 、，5八圖·係依據本發明之pwM驅動器的電路圖。 第® ·係第5 A圖之P W Μ驅動器的驅動波形圖。第6圖·係依據本發明之語音驅動器。第7圖：係第6圖之語音驅動器的驅動波形圖。罘8Α圖：#為一 #習知之波寬調變橋式驅冑器的電路 圖。 第8Β圖：係第8八圖之波寬調變橋式驅動器$ 圖。 第9圖·係為一種用於語音處理丨c以推動喇叭 器之電路圖。 第10圖··係為第9圖之橋式放大器之詳細電路結構圖。 之驅動波形 的橋式放大 (請先間讀背面之注意事 環寫本頁) 裝 · 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 494619 A7494619 A7 --- -_____ V. Description of the invention (丨) [Field of the invention] The present invention relates to the technical field of drive circuits, especially a switchable voltage follower and a bridgeless drive using the switchable voltage follower Circuit device. [Background of the present invention] Figures 8A and 8B show a conventional bridge driver (Pulse Width Modulation, PWM) and its driving waveform, respectively. After the wide modulation, the up-wave wide-modulation signal (PWM-UP) and the down-wave wide-modulation signal (PW Μ-DOWN) are used to drive the output electrical bodies μ p 1, Μ Ν 1, Μ Ρ 2 and MN 2 drives the taste] μ8 8 1 and converts the audio by low-pass filtering to output it. This bridge-type drive amplifier has a simple structure and can output a sufficient volume under low voltage operation. However, when the voltage source VDD changes, the output volume changes considerably; and when the voltage source VDD is high, the output current is large, and It is easy to cause excessive transient noise inside the integrated circuit and cause the integrated circuit to work incorrectly, such as accidentally triggering a power-on reset (p0Wer on reset), etc. In addition, if the transistors MP1, MN1, MP2 and MN2 has asymmetry in the layout, or the on-resistance of (MP 1, MN 1) is not equal to the on-resistance of (MP2, MN2) due to process drift, which will cause asymmetrical loss. Figure 9 shows a bridge amplifier used for speech processing Ic to promote the team, in which the digital processing circuit of the speech input paper standard CNS A4 specification (210X29 / Gongqing) (Please read the precautions on the back v-install--, 11 Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 494619 Λ7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy ~ Bio) first converts to an analog signal through a digital to analog converter (DAC) 91, and then converts the signal to a positive polarity signal through a single ended to differential U1 output converter 92 ¥ 1 and negative polarity signal V2 to drive two Class AB amplifiers as drivers "and 9 4 respectively, and then the two drivers output audio drive signals and drive the speakers 9 $. Single-ended for the bridge driver amplifier The structure of the differential converter 9 2 and the class AB amplifiers 93 and 94 is shown in Fig. ○; its advantage is that it can push the team single-ended or drive the bridge to obtain four times the output power. However, the single-ended-to-differential converter 92 will generate an offset (0ffset), and the two operational amplifiers in the two class AB amplifiers 93 and 94 will generate a DC offset (dc offset). This DC offset Shifting the DC component and adding it to the Raiders 95 will cause extra static current consumption, causing the lack of excessive DC offset of the bridge output (SPK +, SPK-). In addition, 'Ab amplifiers 93 and 94 of the aforementioned bridge drive amplifier The product of the static bias current of the transistor MN1 and MP1 and the resistance of the resistor must be greater than the DC offset of the bridge output (SPK +, SPK-), otherwise a cross-over loss will occur, and Once crosstalk occurs, it needs to be suppressed by the feedback of the bias control circuit 96 (refer to USP 4,9 6 3,8 3 7), but because the bias control circuit 96 is provided by k Local negative feedback will actually reduce the open loop gain of the class AB amplifier to only 10 ~ 20 times. Therefore, its feedback I will not be sufficient to effectively suppress cross-talk. The figure shows the waveform of the input bridge driver amplifier VIN and bridge output (spk +, SPK-) Waveform _ _ This paper size 纸张 Chinese National Standard (CNS) A4 specification (2i0-297mm) -------------- install --- (Please read the notes on the back first ^^^ Write this page) Order--丨 line · A7 V. Description of the invention (today) X. SPK-), its apparent bridge output waveform (v V) has a clear cross 4 t stroke Toast K sp SPK 'Drive-Fen Gu "Visual. In view of this, it is necessary to improve the bridge force of the aforementioned knowledge. Because of this, based on the spirit of positive invention, I think about a “switchable voltage follower and a bridge-type driving circuit device using the switchable electricity” that can be described in a compressible and heart-to-heart manner. A novel and progressive invention. [Summary of the Invention] This month "the purpose is to provide a switchable voltage follower and a bridge-type driving circuit device using the i-knife-change voltage follower, in order to effectively solve the problems in the conventional technology. According to a feature of the present invention, the proposed switchable voltage follower mainly includes: an output transistor pair, which has a pM0s transistor and an N-type MOj transistor, and the two electrodes of the two transistors are connected as- The driving output I ', the first and the third switchers, the first input 2 of the second switcher is connected to a voltage source, and the output end thereof is connected to the gate of the PMOS (f crystal, the first of the three switches of f) The two input terminals are connected to the low potential of the system, and its output terminal is connected to the gate of the NMOS transistor; and, _ op amp, its positive input terminal is used as the feedback terminal and connected to the drive output terminal, and its negative input terminal is Connected to the output of the first switch, and its output is connected to the second input of the second switch and the first input of the third switch; wherein each switch is connected by a polarity terminal Control, when the digital logic signal input from the polarity terminal is the first state, the output terminal of each switch is switched (please read the note on the back first to write this page)-installation. • Wiring · Ministry of Economy Wisdom Printed by the Property Cooperative's Consumer Cooperatives 494619 Printed by the Intellectual Property Bureau employee consumer cooperative Λ7 _ B7 V. Description of the invention (bucket) to its first input terminal, and when the digital logic signal input by the polarity terminal is in the second state, the output terminal of each switch Is connected to its second input terminal 0 According to another feature of the present invention, the proposed bridge driving circuit device mainly includes first and second switchable voltage followers, and each switchable voltage follower includes: an output The transistor pair has a PMOS transistor and an NM 0 S transistor, and the drains of the two transistors are connected as a driving output terminal; the first, second, and third switches are the first and second switches. An input terminal is connected to the voltage source, an output terminal is connected to the gate of the PMOS transistor, a second input terminal of the third switch is connected to the system low potential, and an output terminal is connected to the gate of the NMOS transistor, the first switch The first and second input terminals of the device are respectively used as a low-state input terminal and a high-state input terminal. Among them, each switch is controlled by a polarity terminal, and when a digital logic signal input from the polarity terminal is in a first state, Time The output of each switch is connected to its first input, and when the digital logic signal input from the polarity terminal is in the second state, the output of each switch is connected to its second input. And an operational amplifier whose positive input is used as a feedback terminal and connected to the drive output, its negative input is connected to the output of the first switch, and its output is connected to the second The second input terminal of the switcher and the first input terminal of the third switcher; wherein the low-state input terminals of the first and second switchable voltage followers are connected as low-voltage input terminals, and the high state of the two is The input terminal is connected as a high-potential input terminal, and the polar terminals of the two are respectively used as polarity switching terminals for inputting the polarity switching logic signal of the opposite phase. _2_ This paper standard is applicable to China National Standard (CNS) A4 specification (2) 〇χ 297 mm) (Please read the note on the back to write this page first); Installation. Line · Λ7 B7 V. Invention Description (f) As the invention is novel in design and effective, it is required to apply for a patent according to law. "It is for industrial use, and it has indeed been added to enable your review committee to contribute. And its purpose is attached to the detailed description of the structure, features, drawings, and preferred embodiments of the present invention. For example, printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and a consumer cooperative [Brief description of the diagram] The functional block diagram of the bridge drive circuit device of the invention. It is the circuit diagram of the switchable voltage follower of the present invention .. It is the bridge drive of the present invention. Circuit device-a kind of circuit configuration.-. This invention is "another electrical state of the bridge driving circuit device." Figure 5 is a circuit diagram of a pwM driver according to the present invention. Figure 5 · Figure 5A The driving waveform diagram of the PW M driver. Figure 6 is a voice driver according to the present invention. Figure 7 is the driving waveform diagram of the voice driver of Figure 6. Figure 8A: # 为 一 # 习 知 之 波 调 调Circuit diagram of the variable-bridge driver. Figure 8B: Figure 8 shows the wave-width-modulated bridge driver of Figure 8 and Figure 8. Figure 9 is a circuit diagram for voice processing and driving the speaker. Figure 10 ... is the bridge amplifier of Figure 9 Detailed circuit structure diagram. Bridge-type amplification of driving waveforms (please read the notes on the back first to write this page) Installation · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm 494619 A7)
經濟部智慧財產局員工消費合作社印製 【圖號説明】 (1 1 )( 1 2 )可切換電壓追隨器 (1 3 ) ( 8 1 ) ( 9 5 )喇口八 (2 1 )〜（2 3 )切換器 ( 2 1 1 ) ( 22 1 ) ( 23 1 )第一輸入端 ( 2 1 2 ) ( 222 ) ( 232 )第二輸入端 ( 2 1 3 ) ( 223 ) ( 23 3 )輸出端 (24)運算放大器 （25)輸出電晶體對 (6 0 )數位整流電路 (6 1 )( 9 1 )數位至類比轉換器 (6 2 ) ( 6 3 )反相邏輯閘（6 4 )互斥或邏輯閘 (92)單端至差動轉換器（ 93 ) ( 94 ) AB類放大器 (9 6 )偏壓控制電路 【較佳具體實施例之詳細説明】 第1圖顯示本發明之橋式驅動電路裝置之一較佳實施 例，其係由兩個可切換電壓追隨器u&12 (switehabie voltage follower)所構成，其中之每一個可切換電壓追 隨器11或12之電路結構則如第2圖所示，主要係由一運算 放大态24、三個切換器21〜23及一輸出電晶體對25所構 成，其中，輸出電晶體對25係以PM〇s電晶體⑷與 本紙張尺度適用中ϋ國家標準（CNS)A4規格⑵G χ 297 & ) 494619 經濟部智慧財產局員工消費合作社印製 Λ7 I--~—--——_ 五、發明說明（7) NMOS電晶體M2分別作為輸出元件，而電晶體m#m2 之;及極相連以作為可切換電壓追隨器之驅域出端〇υτ。 珂述之切換器2 1〜23係較佳地為2對丨切換器 (MUX)，其係由—極性端ΡΝ所控制，以當該極性端ΡΝ 所輸入之數位邏輯信號為〇時，切換器2卜23之輸出端 213、223或233係切換連接至其第—輸入端211、221或 231，而當該極性端PN所輸人之數位邏輯信號為丨時，切 換态21〜23之輸出端213、223或233係切換連接至其第二 輸入端212、222或232。 4述運算放大器24係為一全軌對軌（fulljraii-t〇-r a 11 )之差動放大詻，其正輸入端係作為回授端並連接至 該驅動輸出端out，其負輸入端係連接至切換器21之輸 出端213以將輸入信號放大，而其輸出端則連接至切換器 22之第二輸入端222及切換器23之第一輸入端231 ;切換 器22之第一輸入端221連接電壓源VDD，其輸出端223連 接電晶體Μ 1之閘極；切換器2 3之第二輸入端2 3 2連接系 統低電位V S S，其輸出端2 3 3連接電晶體Μ 2之閘極；切換 器2 1之第一及第二輸入端2丨丨及2丨2則分別作為可切換電 壓追隨器之低態輸入端INL及高態輸入端ΙΝΗ。Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [Illustration of drawing number] (1 1) (1 2) Switchable voltage follower (1 3) (8 1) (9 5) Lakou eight (2 1) ~ (2 3) Switcher (2 1 1) (22 1) (23 1) First input terminal (2 1 2) (222) (232) Second input terminal (2 1 3) (223) (23 3) output terminal (24) Operational amplifier (25) Output transistor pair (6 0) Digital rectifier circuit (6 1) (9 1) Digital to analog converter (6 2) (6 3) Inverting logic gate (6 4) Mutual exclusion OR logic gate (92) single-ended-to-differential converter (93) (94) class AB amplifier (9 6) bias control circuit [detailed description of a preferred embodiment] FIG. 1 shows a bridge drive of the present invention A preferred embodiment of the circuit device is composed of two switchable voltage followers u & 12 (switehabie voltage follower), and the circuit structure of each switchable voltage follower 11 or 12 is as shown in FIG. 2 As shown, it is mainly composed of an operational amplifier state 24, three switches 21 to 23, and an output transistor pair 25. Among them, the output transistor pair 25 is a PM0s transistor ⑷ and the paper size Printed with the Chinese National Standard (CNS) A4 Specification ⑵G χ 297 &) 494619 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Λ7 I-- ~ ---------- 5. Description of the invention (7) NMOS transistor M2 respectively As an output element, the transistor m # m2; and the poles are connected to serve as the driving domain output terminal of the switchable voltage follower. Keshuo switch 2 1 ~ 23 is preferably 2 pairs 丨 MUX, which is controlled by-polarity terminal PN to switch when the digital logic signal input to the polarity terminal PN is 0. The output terminals 213, 223, or 233 of device 2 and 23 are switched to be connected to its first input terminal 211, 221, or 231, and when the digital logic signal inputted by the polarity terminal PN is 丨, the switching state 21 ~ 23 is switched. The output terminal 213, 223 or 233 is switched to its second input terminal 212, 222 or 232. The operation amplifier 24 described above is a full-rail-to-rail (fulljraii-to-ra 11) differential amplifier. Its positive input terminal is used as a feedback terminal and connected to the drive output terminal out. Its negative input terminal is Connected to the output terminal 213 of the switch 21 to amplify the input signal, and its output terminal is connected to the second input terminal 222 of the switch 22 and the first input terminal 231 of the switch 23; the first input terminal of the switch 22 221 is connected to the voltage source VDD, and its output terminal 223 is connected to the gate of transistor M 1; the second input terminal 2 of switch 2 3 is connected to the system low potential VSS, and its output terminal 2 3 3 is connected to the gate of transistor M 2 The first and second input terminals 2 丨 丨 and 2 丨 2 of the switch 21 are used as the low-state input terminal INL and the high-state input terminal INN of the switchable voltage follower, respectively.
以前述可切換電壓追隨器1 1及1 2之電路結構，當 ΡΝ=1時，該運算放大器24的負輸入端連結到inH，輸出 | 則連結到電晶體Μ 1的閘極，而電晶經體Μ 1的汲極則連結 到運算放大器2 4的回授端，故可構成一上拉（p u 11 u ρ ) 電壓追隨器，而在此同時，電晶體M2的閘極被連到ν S S 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297 ) ---With the aforementioned circuit structure of the switchable voltage followers 11 and 12, when PN = 1, the negative input terminal of the operational amplifier 24 is connected to inH, and the output | is connected to the gate of transistor M1, and the transistor The drain of the warp body M 1 is connected to the feedback terminal of the operational amplifier 24, so it can constitute a pull-up (pu 11 u ρ) voltage follower, and at the same time, the gate of the transistor M2 is connected to ν SS This paper size applies to China National Standard (CNS) A4 (21〇x 297) ---
裝--- (請先閱讀背面之注意事寫本頁) · -線· 494619 經濟部智慧財產局員工消費合作杜印製 Λ7 --------— B7____ 五、發明說明（5 ) 而關閉。而當ΡΝ = 0時，該運算放大器24的輸入連結到 INL，輸出則連結到電晶體M2的閘極，電晶體m2的汲極 則連結到運算放大器24的回授端，而係構成一下拉（puU down )電壓追隨器，在此同時，電晶體]^1的閘極被連結 到VDD而關閉。由是可知，藉由以極性端pN用來控制三 個切換咨2 1〜2 3 ’便可將此可切換電壓追隨器丨丨及丨2切 換成所需要的組態。 而當組合成第1圖之橋式驅動電路裝置時，該可切換 包壓追隨咨1 1及1 2之低態輸入端INl係共同連接至一低電 位輸入端VIL ’而兩者之高態輸入端INH則共同連接至一 冋電位輸入端VIH，另該可切換電壓追隨器丨丨及丨2之極 性邮PN則分別以第一極性切換端pNS w丨及第二極性切換 緬PNSW2所表示，因此，配合極性切換邏輯信&pNSWi 與PNSW2的控制，當pNswl = 1、pNSW2 = 〇時，可切 換電壓追隨器1 1及1 2之電路組態便如第3圖所示，其分別 k供上拉及下拉之功能以驅動喇叭丨3 ;反之，當pN s w ^ 一 〇、PNSW2 = 1時，可切換電壓追隨器丨丨及12之電路組 悲便如第4圖所示，其分別提供下拉及上拉之功能以驅動 喇队13，據此，即可獲致橋式推挽（push_pun )驅動功 ° 前述利用可切換電壓追隨器丨丨及丨2所構成的橋式驅 動器本身就可以當作是pWM驅動器，如第5A圖及第5B圖 所分別顯示之電路圖及驅動波形圖，其中，橋式驅動器 之可切換電壓追隨器丨丨及丨2的高態輸入端INH係共同連 本紙張尺度適用中國國家標準_(CNS)A4規格（21〇 X 297 釐)-------- ---------------農--- (請先閱讀背面之注意事寫本頁) ·- --線· 4^4619 Λ7 五、發明說明（？） 接·軼问電位的上限參考電壓VRT，其低態輸入端ινή則 共同連接一較低電位的下限參考電壓VRB，而可切換電壓 追隨器11及12之極性端PN係分別用以輸入上波寬調變訊 號（PWM-UP)與下波寬調變訊號（pwM_D〇WN)， J如圖所示，加在喇队丨3負載上的即為一峰値對辛値 (Peak to peak)等於2* (VRT_VRB)的 pwM 訊號。 此種P W Μ驅動器有以下之優點： (1 )電壓追隨器的頻寬高達丨ΜΗζ，可以推動ρ WM 信號。 經濟部智慧財產局員工消費合作社印製 (2)當VDD電壓約高於VRT + VRB + 〇4V以上，輸 出到喇叭負載上電壓為恆定的峰値對峰値等於2* (vrt_ VRB)，而非2*VDD，故可維持穩定的音量輸出，因 此，對於在以電池作為供電的應用中，音量之輸出不會受 到電池新舊之影響。 (3 )由於正、負極性輸出電流的不對稱偏差將來自 兩個運算放大器之間的直流偏移（dc 〇 —"除以 (vrt-vrb )，其中，此直流偏移値小於3〇mv，而 vrt-vrB>2.0V^，因此，偏差値小於15%，但傳統 ^PWM驅動器的正、負極性輸出電流不對稱偏差値則常 尚達5〜10%，因此本發明之pWM驅動器所引發的直流電 泥耗損與失眞都會比傳統的P WM驅動器小很多。 、第6圖係為一以前述利用可切換電壓追隨器1 1及1 2所 構成的橋式驅動器、一數位至類比轉換器61 YDAC)及 -數位整流電路6。所構成之N位元語音驅動器“udio --------------裝--- (請先閱讀背面之注意事寫本頁) · -1線. -n I n - ^長尺度適用中國國家標準（C&S)A4規格⑵Q χ 297送爱'------- 、發明說明（π) driver)(於本實施例中 動^ N—丨〇)，如圖所示，橋式驅 勒為尤兩個可切換的電壓 心u 狹追^态"及12的INL端都連接於 數仏至類比轉換器6丨的下限 ， 颅 參考黾位VRB ’而可切換電 认 场則共同接到數位至類比轉換器 6 1的輸出端。 _孩可切換電壓追隨器η之極性端pn係由輸人之10位 ::音資料的最高位元（msb) Μ〇所控制，其波形如第 、、回B—所7F ’而另-可切換電壓追隨器i 2之極性端則由 孩最高位元b10透過一反相邏輯閘62所控制。 該數位整流電路60係包含有一反相邏輯問63及九個 立2或（exclusive OR)邏輯閘64，俾提供輸入數位語 音資料bl〜bl0之絕對値運算，以輸出數位資料之絕對 値，其中，該最高位元bl0係透過一反相邏輯閘63接到九 個互斥或邏輯閘64，以便分別與輸入之10位元語音資料 的其餘位兀bl〜b 9分別進行互斥或運算後再輸入該數位至 類比轉換器6 1，而可將輸入的語音資料以中點電位 (1 000000000 )為參考點作絕對値運算，使經數位至類 比轉換為6 1轉換的電壓都是正極性，如第7圖a所示，而 可以驅動可切換電壓追隨器n&122INH端，故在spK + 端與SPK-端之波形便如第7圖(：及1)所示，而驅動喇叭之 仏號（VSPK + -VSPK·)即為第7圖E所示之波形。 以前述之語音驅動器可獲致以下之優點： )只需用（N -1 )位元之數位至類比轉換器即可 得到N位元之解析度。 五、發明說明（II ) (2)不需要單端至差動轉換器。 (3 )整個橋式驅動器只用兩個運算放大哭。 -偏二輸出的直流偏移來自兩個運算放大器之間的直 直將比傳統的N位元語音驅動器的直流偏 移^很夕，因此所引發的直流電流耗損會比較小。 ⑴因為使用Β類電壓賴器，故無直流偏壓之產 =上所陳，本發明無論就目的、手段及功效，在在均 顯不其迴異於W知技術之特徵，為驅動電路裝置之咬計上 的-大哭破，懇請貴審查委員明察，早曰賜准專利，俾 最惠社會’實感德便。惟應注意的是，上述諸多實施例僅 係為了便於説明而舉例而已，本發明所主張之權利範圍自 應以申請專利範圍所述為準，而非僅限於上述實施例。Equipment --- (Please read the note on the back first to write this page) · -line · 494619 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs DU7 ------------ B7____ V. Description of the invention (5) And closed. When PN = 0, the input of the operational amplifier 24 is connected to INL, the output is connected to the gate of transistor M2, and the drain of transistor m2 is connected to the feedback terminal of the operational amplifier 24. (PuU down) The voltage follower, at the same time, the gate of the transistor is connected to VDD and closed. It can be seen that by using the polar terminal pN to control the three switching devices 2 1 to 2 3 ′, this switchable voltage follower 丨 丨 and 丨 2 can be switched to the required configuration. When the bridge-type driving circuit device of FIG. 1 is combined, the switchable pack voltage following the low-state input terminals IN1 and 1 2 are connected to a low-potential input terminal VIL ′ and the high state of the two. The input terminal INH is connected to a potential input terminal VIH in common, and the switchable voltage followers 丨 丨 and 丨 2 of the polar post PN are represented by the first polarity switch pNS w 丨 and the second polarity switch PNSW2, respectively. Therefore, with the control of the polarity switching logic signals & pNSWi and PNSW2, when pNswl = 1, pNSW2 = 〇, the circuit configuration of the switchable voltage followers 1 1 and 12 is shown in Figure 3, which are respectively k provides pull-up and pull-down functions to drive the speaker 丨 3; conversely, when pN sw ^ 10 and PNSW2 = 1, the circuit group of the switchable voltage follower 丨 and 12 is shown in Figure 4, which Provide pull-down and pull-up functions to drive the squad 13, respectively. Based on this, you can get the bridge push_pun driving power. The aforementioned bridge driver using the switchable voltage follower 丨 丨 and 丨 2 is itself Can be used as a pWM driver, as shown in Figures 5A and 5B Circuit diagram and driving waveform diagram. Among them, the switchable voltage follower of the bridge driver 丨 丨 and 丨 2 high-state input terminals INH are connected in common. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297%). ) -------- --------------- Farm --- (Please read the note on the back to write this page first) · --- line · 4 ^ 4619 Λ7 V. Description of the invention (?) Connected to the upper limit reference voltage VRT of the potential, the low-state input terminal ιν is connected to a lower potential lower limit reference voltage VRB, and the polar terminals PN of the voltage followers 11 and 12 can be switched It is used to input the up-wave wide modulation signal (PWM-UP) and the down-wave wide modulation signal (pwM_D0WN) respectively. J is shown in the figure, and a peak is added to the load of the Rabat 丨 3. Pe (Peak to peak) is equal to a pwM signal of 2 * (VRT_VRB). This P W Μ driver has the following advantages: (1) The bandwidth of the voltage follower is as high as ΜΗζ, which can drive the ρ WM signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (2) When the VDD voltage is higher than VRT + VRB + 〇4V, the peak voltage of the output to the speaker load is constant, and the peak value is equal to 2 * (vrt_ VRB), and It is not 2 * VDD, so it can maintain stable volume output. Therefore, for applications using batteries as the power supply, the volume output will not be affected by the old and new batteries. (3) Due to the asymmetric deviation of the positive and negative output currents, the DC offset between the two operational amplifiers (dc 0— " divided by (vrt-vrb), where the DC offset 値 is less than 3 mv, and vrt-vrB > 2.0V ^, therefore, the deviation 値 is less than 15%, but the positive and negative output current asymmetry deviation 传统 of traditional ^ PWM driver is often still 5 ~ 10%, so the pWM driver of the present invention The induced loss and loss of DC mud will be much smaller than the traditional P WM driver. Figure 6 is a bridge driver composed of the aforementioned switchable voltage followers 1 1 and 12, a digital to analog Converter 61 YDAC) and-digital rectifier circuit 6. The N-bit voice driver "udio -------------- install --- (Please read the note on the back first to write this page) · -1 line. -N I n- ^ The long scale applies the Chinese National Standard (C & S) A4 specification ⑵Q χ 297 to send love '-------, invention description (π) driver) (moves in this embodiment ^ N- 丨 〇), such as As shown in the figure, the bridge drive is composed of two switchable voltage cores u and the INL terminal of 12 are connected to the lower limit of the digital to analog converter 6 and the cranial reference position VRB '. The switchable electric field is commonly connected to the output of the digital-to-analog converter 61 1. The polarity terminal pn of the switchable voltage follower η is input by the 10th bit :: the highest bit of the audio data (msb) Controlled by Μ0, its waveform is like the first, the second, the second and the last. The polarity of the switchable voltage follower i 2 is controlled by the highest bit b10 through an inverting logic gate 62. The digital rectifier The circuit 60 includes an inverting logic 63 and nine exclusive OR logic gates 64, which provide the absolute operation of the input digital voice data bl ~ bl0 to output the absolute value of the digital data. Among them, The highest bit bl0 is connected to nine mutually exclusive or logic gates 64 through an inverting logic gate 63, so as to perform mutually exclusive OR operations with the remaining bits bl ~ b 9 of the input 10-bit voice data respectively. Input this digit to the analog converter 61, and the input voice data can be used for absolute unitary operation with the midpoint potential (1 000000000) as the reference point, so that the digital to analog conversion to 61 1 conversion voltage is positive, such as As shown in Fig. 7a, the n & 122INH terminal of the switchable voltage follower can be driven, so the waveforms at the spK + terminal and SPK- terminal are as shown in Fig. 7 (: and 1), and the horn of the driver is driven. (VSPK + -VSPK ·) is the waveform shown in Figure 7E. With the aforementioned voice driver, the following advantages can be obtained:) Just use the (N -1) bit digital to analog converter to get N Bit resolution. V. Description of the invention (II) (2) No single-ended-to-differential converter is needed. (3) The entire bridge driver only uses two operations to amplify the cry. The straightness between the two op amps will be offset from the DC of a traditional N-bit voice driver. Therefore, the DC current loss caused will be relatively small. ⑴Because of the use of Class B voltage relays, the production of no DC bias is as described above. The present invention is no different in terms of purpose, means and efficacy. Knowing the characteristics of the technology, we are crying on the bit meter of the driving circuit device. I urge your reviewing committee to make a clear observation and grant a quasi-patent as early as possible to benefit the society's real sense. However, it should be noted that many of the above implementations The examples are merely examples for the convenience of description. The scope of the claimed rights of the present invention should be based on the scope of the patent application, rather than being limited to the above embodiments.