TW494554B - Multi-chip stacking packaging method and the structure thereof - Google Patents
Multi-chip stacking packaging method and the structure thereof Download PDFInfo
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- TW494554B TW494554B TW090117304A TW90117304A TW494554B TW 494554 B TW494554 B TW 494554B TW 090117304 A TW090117304 A TW 090117304A TW 90117304 A TW90117304 A TW 90117304A TW 494554 B TW494554 B TW 494554B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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Abstract
Description
A7 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明( 本發明係關於一種多a 指-種可有效提昇產品製:车隹了方法及其結構,尤 片堆疊料方法及其結構料^ ’㈣產業湘性之多晶 目:已知多晶片堆疊封裝方法,概如 :A7 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (This invention relates to a multi-finger-type product that can effectively improve the product system: the method and structure of the car, the method of stacking tablets and its structure Material ^ 'Industrial Hunan Polycrystalline: Known multi-chip stacked packaging methods, such as:
圖所不者以及附件一公主 +系弟一 Λ 一 C 封裝」發明專利宰所揭干二三九二四-號「晶片的堆疊 之習知多晶片堆最封/方中本案第三Α〜三C圖所示 晶片,取第一晶^計’其係將晶圓切割成複數 )之a Η ρ Γ 7曰6 〇)以其背面黏設於導線架(7 〇 )正:上=久41)—側面,以金屬線將第一晶片(6 0 的各銲墊與導線架(7〇)之内引腳(川連 =、:人:取第二晶片(61)以其背面黏設於導線架( 之曰曰片座(7 1 )另側面,以金屬線將第二晶片( Q、、正面^的1各銲墊與導線架(70)之内引腳(7 )連接,續以—次雙側封膠方式將勝 導線架(7Q)兩側之第-、二晶片(6〇) (6lf外 側,而構成-多晶片堆疊型態之半導體元件結構。 至於附件一揭不之晶片堆疊封裝結構設計概包括二種 實施例,其一者,如附件一第二圖所示,其係使用一内引 腳500呈向下彎折狀之導線架51〇,將銲墊位於中間之第 一晶片310以正面朝下之方式黏著於導線架51〇之内引腳 500上,次以第一組銲線370a連接於第一晶片31〇各銲墊 與導線架510對應之内引腳500間,再將銲墊位於中間之 第一晶片320背面黏著第一晶片310背面上,次以第二組 銲線370b連接於第二晶片320各銲墊與導線架51〇對鹿之 本紙張尺度適用中國國家標準(C,NS)A4規格(210 X 297公釐)What is not shown in the picture and the annex I. The princess + the sibling one Λ-C package "invention patent slaughter reveals the number 2392-" the stacking of wafers. The multi-chip stack is the most sealed / the third one in the case. The wafer shown in Figure C is taken from the first crystal. It is a wafer that is cut into a plurality of) a 之 ρ Γ 7 〇 6) with its backside adhered to the lead frame (7 〇) positive: upper = long 41 ) —Side side, the inner chip of the first chip (60 each pad and lead frame (70)) (metal link = ,: person: take the second chip (61) on the back with metal wires attached to the wire On the other side of the bracket (7 1), metal pads are used to connect the second wafer (Q ,, 1 on the front surface 1 with the pads (7) within the lead frame (70), continued with- The sub-double-side sealing method combines the first and second wafers (60) (6lf) on both sides of the lead frame (7Q) to form a -multi-chip stacking type semiconductor element structure. As for the wafer stacking that can not be uncovered in attachment one The package structure design generally includes two embodiments, one of which, as shown in the second figure of Annex I, uses a lead frame 51 in which the inner pin 500 is bent downward, and the pad is located in the middle. The first chip 310 is adhered to the inner lead 500 of the lead frame 51 in a face-down manner, and is connected to the first chip 31 with a first set of bonding wires 370a. Each pad of the lead chip 510 corresponds to the inner lead of the lead frame 510. Between 500 feet, the back of the first wafer 320 with the solder pads in the middle is adhered to the back of the first wafer 310, and then a second set of bonding wires 370b are connected to each pad 320 and the lead frame of the second wafer 320. Paper size applies to China National Standard (C, NS) A4 (210 X 297 mm)
--------訂---------線»· (請先閱讀背面之注意事項再填寫本頁) 494554 A7-------- Order --------- Line »· (Please read the precautions on the back before filling this page) 494554 A7
(請先閱讀背面之注意事項再填寫本頁) r--------訂---------線»· 五、 發明說明(3 ) 2合力’且對内部堆疊之第―、二晶片及元件本身易產生 龜4、破裂之情事。 ^易產生相鄰金屬線接觸短路而形成廢品:前揭各 :多晶片堆疊封裝結構’係採晶片黏著於導線架,以金屬 :―連,第一 :¾片銲墊與内引腳間之後,再翻轉導線架,將 弟7—曰曰片黏著其上,並以金屬線連接其銲墊與内引腳間,(Please read the precautions on the back before filling this page) r -------- Order --------- line »· 5. Description of the invention (3) 2 Heli 'and the internal stacking The first and second wafers and components themselves are prone to turtles and cracks. ^ It is easy to produce shorts due to short-circuits between adjacent metal wires: front uncovered: multi-chip stacked package structure 'is used to adhere the chip to the lead frame, with metal:-connected, first: ¾ between the pad and the inner lead , And then flip the lead frame, stick the 7-Yue piece on it, and connect the solder pad to the inner pin with a metal wire,
Si整體之封膠程序,其中’因金屬線線徑細微,且相 f金屬線間之間隙小,故—側晶片金屬線連接引腳後欲進 丁 ^側面黏aa及金屬線連接的翻轉過程中,易使金屬線偏 ”相4金屬線接觸而發生短路,導致完成封裝的 凡件形成廢品。 因此,有鐘於目前已知多晶片堆疊封裝設計,尚益法 對元件中各組成構件間之接合力不佳及金屬線易偏位接觸 而短路之問題等,提供有效的解決方案,於是本發明人們 計一種「多晶片堆疊封裝方法及其結構」,並期 I舍明⑤計充分解決上述接合力不佳及金屬線易短路之 問題、’進1昇產品良率,為本發明之主要目的。 為達成前揭目的,本發明所提出之多晶片堆疊封裝方 =結構設計,其係利用不設晶片座且單侧黏附膜片之 ^春木提供第一晶片自導線架一側黏著於膜片上或内引 :下if 一晶片與導線架電性連接後’進行導線架單側封 ^ /、一人’再去除膜片,將第二晶片自導線架另側黏著於 第一晶片背面或膠體上,第二晶片與導線架電性連接後, 再進行導線架另側之單側封膠,而成型一多晶片堆疊封裝 5 本紙張尺度適用中國國家標準(CNS)A4 ii^· 297公釐) 五 、發明說明(¥ ) ,半導體元件,藉此設計,以降低製造時元件之熱應力, 提高其接合力以避免龜裂、破裂等情事,同時藉兩次對各 別晶片封膠之設計,避免製程中因元件翻轉造成金屬線接 觸短路之問題,以提昇其產品良率。 為使貴審查委員能進一步瞭解本發明具體之設計及 其他目的’茲附以圖式詳細說明如后: (一) 圖式部份: 第一 A〜D圖··係本發明之封裝流程示意圖。 第二圖:係本發明另—實施例封m件之剖面示意圖。 第三K目m多晶片堆疊料結構之封裝流程示意 圖。 (二) 圖號部份: (10)導線架 (1 2)黏性膜片 (1 4)第二側面 (2 0)第一晶片 (3 0)第一谬體 (4 0 )第二晶片 (50)第二膠體 (6 0 )第一晶片 (7 0 )導線架 (7 2 )引腳 (8 0 )膠體 (三)附件部份: 請 閱 讀 背 面 之 注 意 事 Μ 再 填 寫 本 頁 I I I I I 訂 (1 1 )引腳 (1 3 )第一側面 (1 5 )缺空區間 (21)金屬線 (41)金屬線 (61(71 第二晶 晶片座 片 線 I 6本紙張尺度適1+ 五、發明說明(t) 、公告第四三九二四 利案公告影本。 號「 晶片的堆疊封裝」發明4 有關本發明多晶片堆疊封 ,其第一種實施例,請參閱第〜法概有兩種具體實施你 將晶圓切割成複數晶片; D圖所不,係包括·· 提供僅具有複數引腳( 導線架(1〇)之第一侧面(,導線架(1〇),該 2),且相對之内引腳(二黏:有黏性膜片(1 間(1 5) · 4开^成谷置晶片的缺空區 ηΓ一晶片(2〇)自導線架(10)第二侧面(1 4)黏設於黏性膜片(12)上,相對於内 間之料區間(15)處,如第_Αβ^; 以金屬線連接於第一晶片(20)各銲墊與其對應的 引腳(1 1 )間; 對導線架(1 0 )黏設第一晶片(1 3 )之第二側面 (1 4)進行單側封膠,膠體(3 〇)將第一晶片(2 〇 )包覆於内,如第一Β圖所示; .去除導線架(10)之膜片(12); 將第二晶片(4 0 )自導線架(1 〇 )第一側面(工 3 )絕緣黏設於第一晶片(2 〇 )背面,如第一 c圖所示 於第二晶片(4 0 )各銲墊與其對應的引腳(1 1 ) 間以金屬線連接; . 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請 先 閱 讀 背 S 之 注 意 畜 Μ 經濟部智慧財產局員工消費合作社印製The overall sealing process of Si, where 'because the metal wire has a small wire diameter and the gap between the f wires is small, the side chip metal wire is connected to the pin, and the side is bonded to the aa and the metal wire connection is reversed. In the process, the metal wires are likely to be biased and the metal wires are in contact with each other and short-circuited, causing the completed package to become scrap. Therefore, there is a known multi-chip stacked package design in the past. The poor bonding force and the problem of the metal wire's susceptible to off-center contact and short circuit provide effective solutions. The present inventors devised a "multi-chip stacked packaging method and structure", and hoped to fully solve the above problems. The problem of poor bonding force and easy short-circuit of metal wires, and the yield of 1 liter product are the main objects of the present invention. In order to achieve the purpose of the previous disclosure, the multi-chip stacked package design structure proposed by the present invention uses ^ spring wood without a chip holder and a single-sided adhesive film to provide a first chip adhered to the film from the lead frame side. Or internal lead: the next if a chip is electrically connected to the lead frame, 'single-sided sealing of the lead frame ^, one person', then remove the diaphragm, and adhere the second chip from the other side of the lead frame to the back of the first chip or the gel After the second chip is electrically connected to the lead frame, the other side of the lead frame is sealed on one side, and a multi-chip stacked package is formed. This paper size is applicable to China National Standard (CNS) A4 ii ^ · 297 mm) Fifth, the invention description (¥), the semiconductor element, by this design, to reduce the thermal stress of the element during manufacturing, improve its bonding force to avoid cracks, cracks, etc., at the same time by twice the design of the sealing of each wafer, Avoid the problem of metal wire contact short circuit due to component flipping during the process to improve its product yield. In order to enable your review committee to further understand the specific design and other purposes of the present invention, a detailed description is attached as follows: (I) Schematic part: The first A to D diagrams are schematic diagrams of the packaging process of the present invention. . FIG. 2 is a schematic cross-sectional view of an m-seal piece according to another embodiment of the present invention. The schematic diagram of the packaging process of the third K-mem multi-wafer stack structure. (2) Part of drawing number: (10) Lead frame (1 2) Adhesive diaphragm (1 4) Second side (2 0) First wafer (30) First absent body (4 0) Second wafer (50) The second gel (60) The first chip (70) The lead frame (72) The pins (80) The gel (III) Attachment part: Please read the notes on the back, and then fill in this page IIIII Order (1 1) Leads (1 3) The first side (1 5) The gap (21) The metal wire (41) The metal wire (61 (71 The second wafer holder sheet line I 6 This paper is suitable for 1+ five 、 Explanation of the invention (t), Announcement of the Announcement No. 439,924 Interest Case No. "Chip Stack Package" Invention 4 For the first embodiment of the multi-chip stack package of the present invention, please refer to the first method. In two specific implementations, you cut the wafer into multiple wafers. What D does not include includes providing the first side of the leadframe (10) with only multiple pins (the leadframe (1〇), the 2 ), And the inner pins (two sticky: there are adhesive membranes (1 space (1 5) · 4 openings ^ vacant area of the valley chip ηΓ a wafer (20) from the lead frame (10)) Two sides (1 4) are attached to the adhesive membrane ( 12), relative to the inner material section (15), such as _Αβ ^; connected by metal wires between each pad of the first chip (20) and its corresponding pin (1 1); to the lead frame (1) The second side surface (14) of the first wafer (1 3) is adhered for single-sided sealing, and the colloid (30) covers the first wafer (20), as shown in the first B picture. As shown in the figure;. Remove the diaphragm (12) of the lead frame (10); the second chip (40) is insulated from the first side (work 3) of the lead frame (10) and is bonded to the first chip (2) On the back, as shown in the first c figure, each pad of the second wafer (40) is connected with a corresponding wire (1 1) by a metal wire;. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Please read the note of S first printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
494554 A7494554 A7
對導線架(10)黏設有第二晶片(4Q)之第一彻 面(1 3 )進行單側封膠,膠體(5 〇)將第二晶片(’ 0 )包覆於内,如第一!)圖所示;以及 曰曰 裁切成形,元成多晶片堆疊封裝之半導體元件。 .前述晶圓切割成複數晶片前,可先於晶圓背面施 磨,以減少晶片厚度; 前述於導線架(10)具第一晶片(2〇)之第二側 面(1 4 )夕Η則封膠|,可施以型體續直之步驟,以 曲度,以利於後續第二晶4 ( 4 〇 )之黏著及第二 前述黏附於導線架(1 〇 )側面之黏性膜片(i 2 ) 可使用聚乙醯胺膠膜; .前述於膠體( 3 0 ) ( 5 0 )封固於導線架(1〇) 之後,相對於裁切成形之前,可對外露於膠體(3 〇 )( 5 0)外側的引腳(χ丄)進行電鍍處理。 經由前述封裝方法所製成之半導體元件結構,請參 第一 D圖所示,其包括: 一導線架(1 〇 ),其僅具有複數引腳(丄丄),相 對應之内引腳(1 1 )間形成缺空區間(1 5 ); 第一晶片(2 〇),其正面具有複數銲墊,且設於 專線架(1 0 )相對於缺空區間(丄5 )_側,其正面上 各銲墊藉金屬、線(2 1 )與導線架(工〇 )對應之引腳( 1 1 )構成電性連接; 第一膠體(3 〇 ),係相對導線架(1 〇.)具第一 8 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱一The first cross-section (1 3) of the lead frame (10) with the second chip (4Q) is sealed on one side, and the second chip ('0) is covered by the gel (50), as shown in the first One! ) As shown in the figure; Before the wafer is cut into a plurality of wafers, grinding may be performed on the back of the wafer to reduce the thickness of the wafer; the lead frame (10) is provided with the second side (1 4) of the first wafer (2) of the wafer; Sealing plastic | can be used to continue the straightening step of the body, with curvature to facilitate subsequent adhesion of the second crystal 4 (4 〇) and the second aforementioned adhesive film (i) adhered to the side of the lead frame (10) 2) Polyethylenimide film can be used. After the gel (30) (50) is fixed to the lead frame (10), it can be exposed to the gel (3 〇) before cutting and forming. ) (50) The outer pins (χ 丄) are plated. The semiconductor device structure manufactured by the aforementioned packaging method is shown in the first D diagram, and includes: a lead frame (10), which has only a plurality of pins (丄 丄), and corresponding inner pins ( 1 1) forms a gap (1 5); the first chip (20) has a plurality of pads on the front side, and is provided on the special wire frame (1 0) relative to the gap (区间 5) _ side, which Each pad on the front side is electrically connected by a lead (1 1) corresponding to metal, wire (2 1) and lead frame (work 0); the first gel (3 〇) is opposite to the lead frame (1 〇.) With the first 8 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 public love one
--------訂------ (請先閱讀背面之注意事項再填寫本頁) _· 線 ^^54 A7 B7 五、 發明說明( 經 濟 部 智 慧 財 產 局 員 社 印 製 曰曰片(2 0 )之側面以單側封膠方式包覆於第一晶片(2 0 )周圍、正面以及連接於銲墊與導線架(丄〇 )引腳( 1 1 )間之金屬線(2 1 ); 一第二晶片(40),其正面具有複數銲墊,且設於 導線架(1 0 )相對於缺空區間(丄5 )㈣,其背面與 第-晶片(20)f面相對黏接’正面上各銲墊藉金屬線 (4 D與導線架(1Q)對應之弓丨腳(11)構成電性 連接;以及 S -第二膠體(5 0) ’係相對導線架(1〇)具第二 晶片(4 0 )之側面以單側封膠方式包覆於第二晶片、" 〇 )外側及連接其銲墊與導線架(丄Q )引腳(丄丄)間 之金屬線(41) ’而構成_多晶片堆疊封裝之半導體元 件結構; -前述第-晶片(20)、第二晶片(4〇)可為大小 相等^等之型體,又可為功能相同或功能不同之晶片 前述第二晶片(4()) f面係以絕緣黏膠或黏膜黏接 於第一晶片(2 0 )背面; 前述第一膠體(3〇)及箆-政贼 氧樹脂; ㈡及第—膠體(50)包含有環 月)述導線木(1 〇 )伸出膠體外側的外引腳(1 1 ) 可雙面鍍設銀、錦、免、金或其他導電性佳之金屬物Ϊ , 本發:多晶片堆疊封裝方法之第二種實施例,其 您………I· 例相同,差異處在於··導線 導線 訂 線 架之内引腳呈側向彎折狀 而第一晶片在晶片在下 9 本紙張尺度適用1關家標準(CNS^^^⑵Q χ 297公^ 494554-------- Order ------ (Please read the notes on the back before filling this page) _ · Thread ^^ 54 A7 B7 V. Description of the invention (printed by the member of the Intellectual Property Bureau of the Ministry of Economic Affairs) The side of the piece (20) is covered with a single-sided sealant around the first chip (20), the front surface, and the metal wire (1 1) connected between the pad and the lead frame (丄 〇) pins (1 1). 2 1); a second wafer (40), which has a plurality of pads on its front surface, and is disposed on the lead frame (1 0) relative to the gap (区间 5), and its back surface is on the f-side of the first wafer (20) The relative bonding pads on the front face are electrically connected by metal wires (4 D corresponding to the lead frame (1Q) and the legs (11); and S-the second gel (50)) is the opposite lead frame ( 1〇) The side of the second chip (40) is covered with a single-side sealant on the second chip, " 〇) outside and connected between the pad and the lead frame (丄 Q) pins (丄 丄). Metal wire (41) 'and constitute a semiconductor element structure of a multi-chip stacked package;-The aforementioned-(20) and second (40) wafers can be of the same size, and can have the same function Wafers with different functions The aforementioned second wafer (4 ()) f surface is adhered to the back of the first wafer (20) with an insulating adhesive or a mucous membrane; the aforementioned first colloid (30) and osmium-thief oxygen resin; ㈡ And the first-the colloid (50) contains the lead wire (10), the outer pin (1 1) protruding from the outside of the colloid can be plated on both sides with silver, brocade, free, gold or other highly conductive metals物 Ϊ, This issue: The second embodiment of the multi-chip stacked packaging method, where you ... …… I · The example is the same, the difference is that the inner leads of the wire lead frame are bent sideways and the first One wafer under the wafer 9 paper standards are applicable to 1 home standard (CNS ^^^ ⑵Q χ 297 公 ^ 494554
經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 架在上之型態(LEAD 0N CHIP,Loc),其係包括: 將晶圓切割成複數晶片; 提供僅具有複㈣腳之導線架,該導線架之第一偏 上黏附有黏性膜片,内弓丨聯達日繁 行鬥μ腳朝弟二側面外側側向彎折,益 導線架間呈高低差; / 將第-晶片以晶片在下之方式黏設於導線架凸出第二 娜面之内引腳底面; 以金屬線連接於第-晶片各銲塾與其對應的引腳間; ,對導線架黏設有第-晶片之第二側面進行單侧封膠, 將弟一晶片包覆於内; 去除導線架第一側面上之黏性膜片,· 將第二晶片自導線架第一側面黏設於膠體上; 以金屬線連接於第u各料與其對 金屬線連接; | 1 π w #對導線架黏設第二晶片之第—側面進行單側封膠,將 第二晶片包覆於内;以及 、 裁切成形,完成多晶片堆疊封裝之半導體元件。 前述晶圓切割成複數晶片前,可先施以晶圓背面研磨 ,,以減少晶圓厚度; 前述於導線架具第一晶片之第二側面外側封膠後,可 施以型體校正之步驟,使其減少型體翹曲狀,以利後續 二晶片之黏著及第二次封膠; 只 前述膜片可為聚乙醯胺膠膜; 前述於膠體封固於導線架之後 相對於裁切成形 本紙張尺度適用中國國家標準(CJMS)A4規格(210 X 297公釐)The LEAD 0N CHIP (Loc) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs includes: cutting the wafer into a plurality of wafers; providing a lead frame with only complex feet, and the lead frame The first upper part is adhered with an adhesive membrane, and the inner bow 丨 Lianda Rifan Traveling Feet μ is bent laterally to the outside of the two sides of the younger brother, and there is a height difference between the lead frames; It is set on the bottom surface of the inner lead protruding from the second surface of the lead frame; it is connected between each welding pad of the first chip and its corresponding pin with a metal wire; The side sealant covers the first chip inside; removes the adhesive film on the first side of the lead frame, and glues the second chip to the gel from the first side of the lead frame; connects to the u through a metal wire Each material is connected to its pair of metal wires; | 1 π w # One side of the second wafer is bonded to the lead frame to seal the second wafer inside, and the second wafer is covered inside; Semiconductor devices in stacked packages. Before the wafer is cut into a plurality of wafers, the backside of the wafer may be ground first to reduce the thickness of the wafer. After the aforementioned sealing is performed on the outer side of the second side of the first wafer of the lead frame, a shape correction step may be performed. To reduce the warpage of the body to facilitate the adhesion of the next two wafers and the second sealing; only the aforementioned film can be a polyethylene film; the foregoing is relatively cut after the gel is fixed to the lead frame The size of the formed paper is applicable to China National Standard (CJMS) A4 (210 X 297 mm)
- (請先閱讀背面之注咅?事項再填寫本頁) --------訂---------線 A. 494554-(Please read the note on the back? Matters before filling out this page) -------- Order --------- line A. 494554
,可對外露於膠體外側的引腳進行電錢處理。 經由前述封裝方法所製成之半導體元件結構,如第二 圖所示,係包括 一導線架(1 〇),其僅具有複數引腳(丄丄),其 内引腳(1 1 )形成朝下彎折狀,與導線帛(丄0)間呈 南低差, 一第一晶片(20),其正面中間位置設有複數銲墊 ,且以正面黏設於導線架(丄〇 )内引聊(丄丄)底面, 正面上各銲墊藉金屬線(2 1 )與對應之引腳⑴)構 成電性連接; 一第一膠體(3 0 ),係相對導線架(丄〇 )具第一 晶片(2 0 )之側面以單側封膠方式包覆於第一晶片(2 0 )外側; 一第二晶片(40),其正面上設有複數銲墊,背面 黏設於導線架(1 〇 )上相對内引腳(i丄)中間位置之 第-膠體(30)上,正面上各鲜塾藉金屬線(41)與 導線架(1 0 )對應之引腳構成電性連接;以及 • 一第二膠體(5 0 ),係相對導線架(丄〇 )具第二 晶片(4 0 )之側面以單側封膠方式包覆於第二晶片(4 0 )外側,而構成一多晶片堆疊封裝之半導體元件結構。 前述第二晶片(4 〇 )背面係以絕緣黏膠或黏膜其黏 接於第一膠體(3 0 )上; 前述第一晶片(2 0 )、第二晶片(4 〇 )可為大小 相等或不等之型體,又可為功能相同或功能不同之晶片; π 本紙張尺度刺+關家標準(CNS)A4規格(21〇\ 297公爱了 (請先閱讀背面之注意事項再填寫本頁) - -------1--------- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 494554 五、發明說明(产) 刖述連接於第一晶片(2 0 )銲墊與導線架(1 〇 ) 内引腳(1 1 )間之金屬、線,以及連接於第二晶片(4 〇 )鲜塾與導線架(1 〇 )内引腳(1 1 )間之金屬線() 為金線; 前述第一膠體(3〇)及第二膠體(5〇)包含有環 氧樹脂; 前述導線架(10)伸出膠體(3〇) (5〇)外側 的外引腳(1 1 )可雙面鑛設銀、鎳、把、金或其他導電 性佳之金屬物。 經由前述封裝方法及結構設計,於製程中當可產生以 下之優點: 1、 降低熱應力、提高接合力··本發明可令晶片不直 接黏著於導線架上或減少晶片直接黏著於導線架,而能有 效改善封膠時,因各組成構件熱膨脹係數不同,所導致彼 此熱脹冷縮比例差異之問題,藉以降低元件内部的熱應力 ,進而提高各構件間接合力,改善元件龜裂、破裂之情事 ’以k幵產品良率。 2、 避免相鄰金屬線接觸短路而形成廢品··本發明係 於導線架一側黏著晶片及金屬線連接後,即進行該側之封 膠,之後,再進行導線架另側黏著晶片、金屬線連接及封 膠,因此,藉由二次單側封膠之方法設計,可避免習用一 次封膠製程中.、,半成品於翻轉時導致金屬線偏位與相鄰金 屬線接觸而發生短路之問題,以提昇該多晶片堆疊封裝結 構之產品良率。 12, Can be exposed to the outside of the colloidal pins for electricity treatment. As shown in the second figure, the semiconductor device structure manufactured by the foregoing packaging method includes a lead frame (10), which has only a plurality of pins (丄 丄), and the inner pins (1 1) are formed toward It is bent down and has a low difference with the wire 帛 (丄 0). A first chip (20) is provided with a plurality of pads at the middle position on the front side and is adhered to the inner side of the lead frame (丄 〇) with the front side. The bottom surface of the chat (丄 丄), each pad on the front side is electrically connected with the corresponding pin (⑴) by a metal wire (2 1); a first gel (30), which is opposite to the lead frame (丄 〇); The side of a wafer (20) is covered with a single-side sealant on the outside of the first wafer (20); a second wafer (40) is provided with a plurality of solder pads on the front side, and the backside is adhered to a lead frame ( 1 〇) on the first colloid (30) at the middle position relative to the inner pin (i 丄), each of the fresh pimple on the front side is electrically connected by the metal wire (41) and the lead corresponding to the lead frame (1 0); And • a second colloid (50), which is covered with a second chip (40) on the side of the lead frame (丄 〇) by a single-side encapsulation on the second crystal (40) outside and the semiconductor elements constituting the structure of more than one chip stack package. The back of the second wafer (40) is adhered to the first gel (30) with an insulating adhesive or a mucous membrane; the first wafer (20) and the second wafer (40) may be equal in size or Different types, can also be the same or different functions of the chip; π paper size thorn + family standard (CNS) A4 specifications (21〇 \ 297 public love (please read the precautions on the back before filling in this (Page)-------- 1 --------- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 494554 V. Invention Description (Production) Description Metals and wires connected between the first wafer (20) pads and the leads (1 1) in the lead frame (10), and connected to the second wafer (40) and the lead frame (10) The metal wire () between the inner pins (1 1) is a gold wire; the aforementioned first gel body (30) and the second gel body (50) contain epoxy resin; the aforementioned lead frame (10) extends out of the gel body (3) 〇) (50) The outer pins (1 1) on the outside can be silver, nickel, handle, gold or other conductive metal objects on both sides. Through the aforementioned packaging method and structure In the manufacturing process, the following advantages can be produced: 1. Reduce thermal stress and improve bonding force. The invention can make the chip not directly adhere to the lead frame or reduce the chip directly adhere to the lead frame, which can effectively improve the sealant. At the same time, due to the different thermal expansion coefficients of the various components, the thermal expansion and contraction ratios of the components are different. This reduces the internal thermal stress of the components, thereby increasing the bonding force between the components, and improving the cracking and cracking of the components. Yield rate 2. To avoid the formation of scraps due to short-circuiting of adjacent metal wires ... The present invention is to adhere the chip on one side of the lead frame and connect the metal wire, then perform the sealing on that side, and then adhere the other side of the lead frame. Chips, metal wires are connected and sealed. Therefore, the design of the two-sided single-side sealing method can avoid the habit of using a single sealing process. When the semi-finished product is turned over, the metal wires are offset and contact the adjacent metal wires. The short-circuit problem occurred to improve the product yield of the multi-chip stacked package structure. 12
--------^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(qMS)A4規格(210 X 297公爱) 494554 A7 五、發明說明_ 綜上所述,本發明創新之多晶片堆疊 設計,確能提佴_ 曰 *凌方法及結潜 鞏利用性之/、車 式夕曰曰片堆疊封裝設計更具』 之兔明’因此’本發明符合發明專利之要件,| 依法具文提出申請。 --------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 13 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公芨-------- ^ --------- (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (qMS) A4 (210 X 297 public love) 494554 A7 V. INTRODUCTION OF THE INVENTION _ In summary, the innovative multi-chip stack design of the present invention can indeed improve the design of the _ * method and the use of the potential latent / / car-type chip stack package design is more "Zhutu Ming 'therefore" this invention complies with the requirements of the invention patent, | filed an application in accordance with the law. -------- Order --------- Line (Please read the notes on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 This paper size applies to Chinese national standards (CNS) A4 size (210 X 297 male)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7105869B2 (en) | 2004-10-29 | 2006-09-12 | Macronix International Co., Ltd. | Multi-chip package |
TWI399845B (en) * | 2009-09-24 | 2013-06-21 | Powertech Technology Inc | Multi-chip stacked device without loop height and its manufacturing method |
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2001
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7105869B2 (en) | 2004-10-29 | 2006-09-12 | Macronix International Co., Ltd. | Multi-chip package |
TWI399845B (en) * | 2009-09-24 | 2013-06-21 | Powertech Technology Inc | Multi-chip stacked device without loop height and its manufacturing method |
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