TW494505B

TW494505B - Manufacture method of chip package body

Info

Publication number: TW494505B
Application number: TW090112857A
Authority: TW
Inventors: Pei-Ting Tsai
Original assignee: Pei-Ting Tsai
Priority date: 2001-05-29
Filing date: 2001-05-29
Publication date: 2002-07-11

Abstract

This invention provides a manufacture method of chip package body. Several layers of conductive interconnects are formed sequentially on a silicon substrate having many active devices, in which an elastic body is formed on the surface of the last layer of conductive interconnect before the last metallization process and a plural number of vertical conductors protruding out of the elastic body are formed on the outer surface of the elastic body. The inventive method can shrink the package dimension to the minimum chip scale and result in good heat dissipation effectiveness and electrical properties without using any leadframe or package substrate and lead.

Description

五、發明說明（1) 發明領域：本發明係有關—種 _ 別是關於-種具有封裝路封裝結構之製造方法，特法。寸之晶片尺寸封裝的製造方發明背隨上元件以上的方式，線間的方式一於矽基材質而且直接月多脹係使I C故會在晶緊點著製程的而今係採或封裝後之晶景·· 著積體電路中元件隹、，之内連線的需长且:又的增加，為了配合矽基板金屬化設計逐漸成為許多半導』；通訊，因此兩層隔離材料，：;:：丄係採用介電層來作為金屬連層-層將二氧：=n電層的製作通常為利用沉積板上以構成—曰 1 2 )或推有雜質的s i 〇2堆疊呈-脆硬之心;片』Μ ’使晶片並會因叫之將晶片焊於印刷+、在日日片之烊墊上長上錫球同’容易造成晶片或錫：二二;3之門而力習知為… ’但由於封膠價格昂貴且加工性不J 言^將會增加生產成本而減少獲利。夕、 :::f穎的構裝技術及材料被開發出’因此現 Z冓衣技術先將晶片安裝在導線架（Lead Frame) 土反上，再利用弓丨線或凸塊形成電連接，以使封裝片可利用焊球或引腳而安裝在PCB上，❻此種封裝V. Description of the invention (1) Field of the invention: The present invention relates to a kind of _ especially a manufacturing method and a special method with a packaging structure. The inventor of the chip-size package invented the method of following the above components. The method of inter-wires is made of silicon-based materials and the direct expansion of the IC makes the IC process at the point where the crystal is tight. Jingjing ... The length of the interconnections between the components 积 and 着 in the integrated circuit needs to be long: and increased, in order to cooperate with the metallization design of the silicon substrate, it has gradually become many semiconductors "; communication, so two layers of insulation materials,:; :: 丄 series uses a dielectric layer as the metal connecting layer-layer will be the two oxygen: = n electrical layer is usually produced by using a deposition board to constitute-say 1 2) or push si 〇2 stack with impurities-brittle The hard heart; the chip "M" makes the chip and will be soldered to the print +, and the solder ball is grown on the pad of the Japanese and Japanese film. It is easy to cause the chip or tin: 22; 3 door It is known as ... 'But because the sealant is expensive and the processability is low, it will increase the production cost and reduce the profit. In the evening, ::: fying's mounting technology and materials were developed. Therefore, the Z-coating technology first mounts the chip on the soil of the lead frame, and then uses bows or bumps to form electrical connections. So that the package can be mounted on the PCB using solder balls or pins.

第4頁 494505 五、發明說明（2) 將受限於導線架、封裝基板、引線的存在，使得縮小封裝尺寸的發展受到相當多的限制，而無法真正縮至最小；且在紅外線回流（I R r e f 1 〇 w )或可靠性測試時，並容易因引線太長，而易產生引線損壞之情形，進而影響該封裝裝置之電器特性。因此，本發明係在提出一種晶片封裝體的製作方法，製作出一種無使用導線架或封裝基板之晶片封裝體，以解決習知封裝裝置的缺失。Page 4 494505 V. Description of the invention (2) It will be limited by the existence of lead frames, packaging substrates, and leads, which will make the development of reducing the size of the package limited by many restrictions, and cannot be reduced to a minimum. ref 1 〇) or reliability test, and it is easy to cause lead damage because the lead is too long, and then affect the electrical characteristics of the packaging device. Therefore, the present invention proposes a method for manufacturing a chip package, and a chip package without a lead frame or a packaging substrate is manufactured to solve the lack of conventional packaging devices.

發明目的與概述：本發明之主要目的係運用現有之製造生產設備，而在無使用任何導線架或封裝基板與引線的情形下，提出一種晶片封裝體的製造方法，以確實將封裝尺寸縮至最小的晶片般尺寸，且具有良好的散熱效果與電性。本發明之另一目的係提出一種製程簡單的晶片封裝體製造方法，以避免耗費不必要之材料而有效縮減製程時間，進而提高晶片封裝體的製造產量。OBJECTS AND SUMMARY OF THE INVENTION: The main purpose of the present invention is to use the existing manufacturing equipment, and propose a method for manufacturing a chip package without using any lead frame or packaging substrate and leads, so as to reduce the package size to The smallest chip-like size with good heat dissipation and electrical properties. Another object of the present invention is to provide a method for manufacturing a chip package with a simple process, so as to avoid unnecessary consumption of materials and effectively reduce the process time, thereby increasing the manufacturing yield of the chip package.

根據本發明5在一配置有許多主動元件之石夕基板上措由金屬化製程依序形成數層導體連線，其中並於進行至最後一道金屬化製程之前，先在導體連線的最外一層表面沉積一彈性體，再於彈性體表面形成複數個凸出之垂直導體，並另安裝複數個焊接導體於彈性體之外表面且分別對應至每一凸出之垂直導體，以形成電連接。底下藉由具體實施例配合所附的圖式詳加說明，當更According to the present invention, a plurality of layers of conductor connections are sequentially formed by a metallization process on a stone substrate with a plurality of active components. Among them, before the last metallization process, the outermost conductor connection is first formed. An elastic body is deposited on one surface, and a plurality of protruding vertical conductors are formed on the surface of the elastomer, and a plurality of soldered conductors are additionally installed on the outer surface of the elastomer and corresponding to each protruding vertical conductor to form an electrical connection. . Detailed descriptions are provided below with specific embodiments and accompanying drawings.

第5頁 494505 五、發明說明（3) 容易瞭解本發明之目的、技術内容、特點及其所達成之功效。圖號說明： 10晶片封裝體 12矽基板 1 4 主動元件 1 6 導體連線 2 0垂直導體 2 2彈性體 2 4焊接導體 3 0容置槽 32 焊墊詳細說明：本發明之主要特點係在I C製作階段之最後一道金屬化製程之前，先製造一層彈性體，再將最後一層之導體連線製作於該彈性體表面，使其在彈性體之表面凸設有複數個垂直導體，以作為對外之接點。一晶片封裝體1 0之製造方法，包括下列步驟：先提供一石夕基板12，如第一a圖所示，其上配置有許多主動元件1 4 ;且在主動元件1 4上並藉由金屬化製程依序形成許多層之導體連線16，如第一b圖所示，且每層導體連線16之間係利用垂直導體2 0相互連接，使每一該主動元件1 4藉由該導體連線1 6與外界通訊；並於進行最後一道金屬化製程前，如第一 c圖所示，先於已設置之導體連線1 6的最外一層表面沉積一彈性體22，其通常係由耐高溫之矽橡膠所構成，且厚度為介於1微米至2 0 0微米之間，而較佳者為5微Page 5 494505 V. Description of the invention (3) It is easy to understand the purpose, technical content, features and functions of the present invention. Description of drawing number: 10 chip package 12 silicon substrate 1 4 active component 1 6 conductor connection 2 0 vertical conductor 2 2 elastomer 2 4 solder conductor 3 0 receiving slot 32 solder pad Detailed description: The main features of the present invention are in Before the final metallization process in the IC manufacturing stage, a layer of elastomer is manufactured, and then the conductors of the last layer are made on the surface of the elastomer, so that a plurality of vertical conductors are convex on the surface of the elastomer as external Its contact. A method for manufacturing a chip package 10 includes the following steps: firstly, a stone substrate 12 is provided, as shown in FIG. 1a, a plurality of active elements 1 4 are arranged thereon; and on the active element 14 and metal The chemical process sequentially forms a plurality of layers of conductor connections 16, as shown in the first b figure, and each layer of conductor connections 16 is connected to each other by vertical conductors 20, so that each of the active components 14 is connected by the The conductor connection 16 communicates with the outside world; and before the last metallization process is performed, as shown in the first figure c, an elastomer 22 is deposited on the outermost surface of the conductor connection 16 that has been set, which is usually It is made of high temperature resistant silicone rubber, and the thickness is between 1 micrometer and 200 micrometers, preferably 5 micrometers.

494505 五、發明說明（4) 米至2 0微米；再於彈性體2 2表面以金屬化製程形成複數個凸出彈性體2 2外表面之垂直導體2 0，如第一 d圖所示，以作為該晶片封裝體1 0之外接點；之後並可再於彈性體2 2的外表面且對應每一凸出之垂直導體2 0上安裝複數個焊接導體2 4，如第一 e圖所示，通常為金屬焊球，以利用垂直導體20之作用，使晶片與焊接導體24形成電性相接，而達到傳遞訊號之目的。在本發明中，於最後一道金屬化製程之前先製造一層彈性體2 2的設計，使此晶片封裝體1 0安裝於主機板之印刷電路板時，可藉由彈性體2 2之可吸收應力或外力的功效，來避免晶片與印刷電路板之間因膨脹係數不同而容易因熱漲冷縮之效應導致晶片、焊接導體或引刷電路板之斷裂損毀，以降低整個晶片封裝的故障率。此外，晶片封裝體1 0的製作係沿用現有之製程生產設備來製造，具有結構單純且製程簡單的特性，且本發明之晶片封裝體可直接藉由焊接導體安裝於印刷電路板上，並無使用任何導線架或封裝基板與引線，除了將可確實使封裝尺寸縮至最小的晶片封裝尺寸，達到縮小封裝體SMT面積之功效，且使其具有良好的散熱效果與電器特性之外，並可避免耗費不必要之材料，以降低製造成本，且有效縮減製程時間，以提高晶片封裝體的製造產量。其中，上述之焊接導體24主要為提供晶片封裝體1 0對外之接點，其除了為金屬焊球之型態外，並可選自針腳、焊料凸塊及凸柱其中之一。且在製作過程中，為使焊接導494505 V. Description of the invention (4) meters to 20 microns; and then a plurality of vertical conductors 20 protruding from the outer surface of the elastomer 22 are formed by a metallization process on the surface of the elastomer 22, as shown in the first figure d. As the contacts outside the chip package 10; after that, a plurality of solder conductors 24 can be installed on the outer surface of the elastic body 2 and corresponding to each protruding vertical conductor 20, as shown in the first e figure As shown, it is usually a metal solder ball to utilize the effect of the vertical conductor 20 to form an electrical connection between the chip and the solder conductor 24 to achieve the purpose of transmitting signals. In the present invention, a layer of elastomer 22 is designed before the last metallization process, so that when this chip package 10 is mounted on the printed circuit board of the motherboard, the stress of the elastomer 22 can be absorbed. Or the effect of external force to avoid the chip and the printed circuit board due to the difference in expansion coefficient and easy to cause the chip, soldering conductor or lead brush circuit board breakage due to the effect of thermal expansion and contraction, so as to reduce the failure rate of the entire chip package. In addition, the production of the chip package 10 is manufactured using the existing process production equipment, and has the characteristics of simple structure and simple process. The chip package of the present invention can be directly mounted on a printed circuit board by a soldering conductor. The use of any lead frame or package substrate and leads can reduce the package size to the smallest chip package size, achieve the effect of reducing the SMT area of the package, and make it have good heat dissipation effects and electrical characteristics. Avoid consumption of unnecessary materials to reduce manufacturing costs, and effectively reduce the process time to increase the manufacturing yield of chip packages. Wherein, the above-mentioned soldering conductor 24 is mainly to provide contacts other than 10 pairs of chip packages. In addition to being a type of metal solder balls, it can be selected from one of pins, solder bumps, and studs. And during the manufacturing process,

494505 五、發明說明（5) 體24的製作安裝更加簡單化，並可在晶片封裝體1 0之製程中，如第二圖所示，於最後一道金屬化製程完成之後，先在彈性體2 2的外表面且每一垂直導體2 0的周圍向内凹陷形成容置槽30，之後再分別將焊接導體24安裝於每一容置槽 3 0内而與垂直導體2 0連接，以使該焊接導體2 4作為對外之接點。494505 V. Description of the invention (5) The production and installation of the body 24 is more simplified, and it can be used in the process of chip package 10, as shown in the second figure. After the last metallization process is completed, the elastomer 2 is first The outer surface of 2 and the periphery of each vertical conductor 20 are recessed inwardly to form an accommodation groove 30, and then the solder conductors 24 are respectively installed in each accommodation groove 30 and connected to the vertical conductor 20 so that the The solder conductors 24 are used as external contacts.

另外，亦可在最後一道金屬化製程完成之後，如第三圖所示，在彈性體2 2表面對應每一垂直導體20之位置設有複數個金屬焊墊32，以使垂直導體20僅露出彈性體22表面而與焊墊3 2形成電連接，而無凸出彈性體2 2之外，之後，再於每一焊墊32上焊接安裝複數個·焊接導體24，使晶片藉由垂直導體20與焊墊32之作用與焊接導體24形成電性相接。而在上述各種實施例中，更可在彈性體的外表面設有一保護層（passivation)，以使凸出於彈性體表面之焊接導體更為堅固而不易斷裂或損毀，且在本發明中，亦可在晶片及彈性體的外表面包覆一封裝膠體，以提供保護之作用而避免受到外力如碰撞、灰塵或水氣等侵害。In addition, after the last metallization process is completed, as shown in the third figure, a plurality of metal pads 32 are provided on the surface of the elastic body 22 corresponding to each vertical conductor 20 so that the vertical conductor 20 is only exposed. The surface of the elastic body 22 is electrically connected to the bonding pad 32 without protruding from the elastic body 22. Then, a plurality of soldering conductors 24 are soldered on each bonding pad 32, so that the chip passes through the vertical conductor. The function of 20 and the bonding pad 32 forms an electrical connection with the bonding conductor 24. In the above-mentioned various embodiments, a protection layer may be further provided on the outer surface of the elastomer, so that the soldering conductor protruding from the surface of the elastomer is stronger and not easily broken or damaged. In the present invention, It is also possible to coat the outer surface of the chip and the elastomer with an encapsulating gel to provide protection against external forces such as collision, dust or water vapor.

惟以上所述者，僅為本發明之較佳實施例而已，-並非用來限定本發明實施之範圍。故即凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍内。However, the above are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention. Therefore, all equivalent changes and modifications of the shape, structure, characteristics and spirit described in the scope of patent application of the present invention shall be included in the scope of patent application of the present invention.

第8頁 494505Page 8 494505

Claims

494505 六、申請專利範圍 1. 一種晶片封裝體之製造方法，包括下列步驟：提供一矽基板，其上配置有許多主動元件；· 在該主動元件上依序形成數層導體連線，每層該導體連線之間係藉由垂直導體連接；於該最外層之該導體連線的表面設置一彈性體；以及在該彈性體表面形成複數個凸出該彈性體外表面之該垂直導體以作為外接點。 2. 如申請專利範圍第1項所述之晶片封裝體之製造方法，其中，在形成該外接點之步驟後，並在該彈性體之外表面且每一凸出之該垂直導體上安裝一焊接導體，以形成電連接。 3. 如申請專利範圍第2項所述之晶片封裝體之製造方法，其中，該焊接導體之型態係選自焊球、針腳、焊料凸塊及凸柱其中之一所組成之群組。 4. 如申請專利範圍第1項所述之晶片封裝體之製造方法，其中，在形成該外接點之步驟後，並在每一該垂直導體周圍的該彈性體外表面形成一容置槽，且分別於每一容置槽中安裝一焊接導體，以與凸出之該垂直導體形成電連接： - 5. 如申請專利範圍第4項所述之晶片封裝體之製造方法，其中，該焊接導體之型態係選自焊球、針腳、焊料凸塊及凸柱其中之一所組成之群組。 6. 如申請專利範圍第1項所述之晶片封裝體之製造方法，其中，在形成該外接點之步驟後，並在該彈性體外表面494505 VI. Application for Patent Scope 1. A method for manufacturing a chip package, including the following steps: Provide a silicon substrate on which many active components are arranged; · Form several layers of conductor connections in sequence on the active component, each layer The conductor lines are connected by vertical conductors; an elastic body is provided on the surface of the outermost layer of the conductor lines; and a plurality of vertical conductors protruding from the outer surface of the elastic body are formed on the surface of the elastomer as External point. 2. The method for manufacturing a chip package as described in item 1 of the scope of the patent application, wherein after the step of forming the external point, an external surface of the elastic body and each protruding vertical conductor is mounted with a Solder the conductors to form an electrical connection. 3. The method for manufacturing a chip package as described in item 2 of the scope of the patent application, wherein the type of the solder conductor is selected from the group consisting of one of a solder ball, a pin, a solder bump, and a bump. 4. The method for manufacturing a chip package according to item 1 of the scope of patent application, wherein after the step of forming the external point, a receiving groove is formed on the outer surface of the elastic body around each of the vertical conductors, and A soldering conductor is installed in each receiving slot to form an electrical connection with the protruding vertical conductor:-5. The method of manufacturing a chip package as described in item 4 of the patent application scope, wherein the soldering conductor The type is selected from the group consisting of solder balls, pins, solder bumps and posts. 6. The method for manufacturing a chip package according to item 1 of the scope of patent application, wherein after the step of forming the external point, the external surface of the elastic body is formed.

第10頁 494505 六、申請專利範圍且對應每一該垂直導體之位置設有複數個焊墊，且每一該焊墊上並連接一焊接導體。 7. 如申請專利範圍第6項所述之晶片封裝體之製造方法，其中，該焊接導體之型態係選自焊球、針腳、焊料凸塊及凸柱其中之一所組成之群組。Page 10 494505 VI. Scope of patent application A plurality of solder pads are provided corresponding to each of the vertical conductors, and a solder conductor is connected to each of the solder pads. 7. The method for manufacturing a chip package as described in item 6 of the scope of patent application, wherein the type of the solder conductor is selected from the group consisting of one of a solder ball, a pin, a solder bump, and a bump.

8. 如申請專利範圍第1項所述之晶片封裝體之製造方法，其中，在形成該外接點之步驟後，更利用一封裝膠體包覆該晶片及該彈性體，並使該垂直導體凸出該封裝膠體外。 9 ·如申請專利範圍第1項所述之晶片封裝體之製造方法，其中，在形成該外接點之步驟後，更在該彈性體之外表面形成有一保護層。 1 0.如申請專利範圍第1項所述之晶片封裝體之製造方法，其中，該彈性體之厚度係介於1微米至2 0 0微米之間。8. The method for manufacturing a chip package as described in item 1 of the scope of the patent application, wherein after the step of forming the external point, a sealing gel is used to cover the chip and the elastomer, and the vertical conductor is convex Out of the encapsulant. 9. The method for manufacturing a chip package according to item 1 of the scope of patent application, wherein a protective layer is formed on the outer surface of the elastomer after the step of forming the external point. 10. The method for manufacturing a chip package according to item 1 of the scope of patent application, wherein the thickness of the elastomer is between 1 micrometer and 200 micrometers.

第11頁Page 11