TW492146B - Manufacturing method of semiconductor device with gate stack dielectric layer - Google Patents

Abstract

This invention provides a manufacturing method of semiconductor device with gate stack dielectric layer. A first dielectric layer is formed on a semiconductor substrate with a first conductivity. A first conductor layer is formed on the first dielectric layer and a second dielectric layer is formed on the first conductor layer, in which the second dielectric layer is formed though stacking a first silicon oxide layer, a silicon nitride layer, a silicon oxynitride and a second silicon oxide layer on the first conductor layer. A second conductor layer is formed on the second dielectric layer. The first dielectric layer, the first conductor layer, the second dielectric layer and the second conductor layer are pattern-etched to form a first gate dielectric layer, a floating logic gate, a second gate dielectric layer and a control gate. Finally, a source/drain with the second conductivity, which is opposite electrically to the first conductivity, is formed at one side of the floating logic gate on the semiconductor substrate.

Description

492146 五、發明說明（1) 5 - 1發明領域： 本發明係有關於一種半導體元件製作方法；特別是有 關於一種半導體記憶體元件之高可靠性介電層製作方法。 5-2發明背景： 傳統堆疊構造的非揮發性半導體記憶體元件中，係使 用一二氧化矽層供做隔離一浮動邏輯閘極（f 1 〇 a t i n g g a t e )與一控制閘極（c ο n t r ο 1 g a t e )之一絕緣層，其稱做第二 閘極介電層。半導體元件係朝向迷你化的趨勢前進，在此 情況下，需要厚度愈來愈薄的第二閘極介電層。 由於具有二氧化矽/氮化矽/二氧化矽堆疊結構的ΟΝΟ 介電層在相當薄的厚度下，仍具有良好的崩潰電壓特性， 並且具有0Ν0介電層的半導體記憶體元件之記憶胞亦具有 較佳的保持特十生(retention characteristic) 〇 因 jtb ’ 0N0介電層已被使用取代二氧化矽層供做第二閘極介電層 。目前0Ν0介電層之製作方法係將一熱氧化二氧化矽層形 成於一多晶矽層上。一氮化矽層沈積於此熱氧化二氧化矽 層上。之後，此氮化矽層之頂部表面係經氧化以於其上形 成一二氧化矽層，或者一二氧化矽層沈積於此氮化矽層上492146 V. Description of the Invention (1) 5-1 Field of the Invention: The present invention relates to a method for manufacturing a semiconductor device; in particular, it relates to a method for manufacturing a high-reliability dielectric layer of a semiconductor memory device. 5-2 Background of the Invention: In a non-volatile semiconductor memory device with a conventional stacked structure, a silicon dioxide layer is used to isolate a floating logic gate (f 1 〇atinggate) and a control gate (c ο ntr ο). 1 gate) is an insulating layer, which is called a second gate dielectric layer. Semiconductor devices are trending toward miniaturization. In this case, a second gate dielectric layer having a thinner thickness is required. Because the ΝΟΟ dielectric layer with the silicon dioxide / silicon nitride / silicon dioxide stack structure has a relatively thin thickness, it still has good breakdown voltage characteristics, and the memory cells of the semiconductor memory device with the ON0 dielectric layer It has a better retention characteristic. Because the jtb '0N0 dielectric layer has been used instead of the silicon dioxide layer for the second gate dielectric layer. At present, the manufacturing method of the ONO dielectric layer is to form a thermally oxidized silicon dioxide layer on a polycrystalline silicon layer. A silicon nitride layer is deposited on the thermally oxidized silicon dioxide layer. Thereafter, the top surface of the silicon nitride layer is oxidized to form a silicon dioxide layer thereon, or a silicon dioxide layer is deposited on the silicon nitride layer.

492146 五、發明說明（2) 然而，為保持市場競爭力，半導體元件之尺寸大小係 繼續縮小中，以提高元件的積集度。在此情況下，ΟΝΟ介 電層厚度縮小到足以使其氮化矽層產生針孔效應（P i nho 1 e issue)，並使其電性特性變差，進而造成低崩潰電壓及漏 電流，而使得半導體記憶體元件的可靠性降低。 據此，亟待提供一種半導體記憶體元件之多晶矽閘極 介電層（polygate dielectric layer)。當多晶石夕閘極介 電層之厚度縮小時，其可提供較高的崩潰電壓及較佳的記 憶胞保持特性(retention characteristic)0 5 - 3發明目的及概述： 本發明之主要目的係提供一種具二氧化矽/氮化矽/氮 氧化矽/二氧化矽閘極堆疊介電層之半導體記憶體元件之 製作方法，其可提供較高的崩潰電壓、較低的漏電流及較 佳的記憶胞保持特性。 本發明之另一目的係提供一種以單晶片加熱製程（ single-wafer thermal process)形成具二氧化石夕/氮化石夕 /氮氧化矽/二氧化矽之閘極堆疊介電層之方法。492146 V. Description of the invention (2) However, in order to maintain market competitiveness, the size of semiconductor components has continued to shrink to increase the accumulation of components. In this case, the thickness of the ONO dielectric layer is reduced enough to cause the silicon nitride layer to have a pinhole effect (P i nho 1 e issue) and worsen its electrical characteristics, thereby causing low breakdown voltage and leakage current. This reduces the reliability of the semiconductor memory device. Accordingly, there is an urgent need to provide a polysilicon gate dielectric layer for a semiconductor memory device. When the thickness of the polycrystalline silicon gate dielectric layer is reduced, it can provide a higher breakdown voltage and better memory cell retention characteristics (0-5-3). Purpose and summary of the invention: The main purpose of the present invention is Provided is a method for manufacturing a semiconductor memory device with a silicon dioxide / silicon nitride / silicon oxynitride / silicon dioxide gate stacked dielectric layer, which can provide a higher breakdown voltage, a lower leakage current, and a better method. Memory cells retain characteristics. Another object of the present invention is to provide a method for forming a gate stacked dielectric layer having a sulphur dioxide / nitride / silicon oxynitride / silicon dioxide using a single-wafer thermal process.

第5頁 492146 五、發明說明（3) 本發明之又一目的係提供一種具閘極堆疊介電層之半 導體記憶體元件之製作方法，其可降低結構應力（ structural stress) ° 根據以上所述之目的，本發明提供一種具閘極堆疊介 電層之半導體記憶體元件之製作方法。一第一介電層形成 於具一第一導電性之一半導體基底上，一第一導電層形成 於第一介電層上，一第二介電層形成於第一導電層上，其 中第二介電層係藉依序堆疊形成一第一二氧化矽層、一氮 化石夕層、一氮氧化石夕層及一第二二氧化石夕層於第一導電層 上而形成。一第二導電層形成於第二介電層上。圖案蝕刻 第一介電層、第一導電層、第二介電層及第二導電層，以 形成一第一閘極介電層、一浮動邏輯閘極、一第二閘極介 電層及一控制閘極。最後，形成具電性相反於第一導電性 之一第二導電性之一汲極/源極於浮動邏輯閘極一側的半 導體基底中。 5 - 4發明詳細說明： 本發明提供一種具閘極堆疊介電層之半導體記憶體元 件構造及其製造方法。本發明可提供一種N通道非揮發性 半導體記憶體元件（N channel non-volatile semiconductor memory device)及P通道非揮發性半導體Page 5 492146 V. Description of the invention (3) Another object of the present invention is to provide a method for fabricating a semiconductor memory device with gate-stacked dielectric layers, which can reduce structural stress ° According to the above The object of the present invention is to provide a method for manufacturing a semiconductor memory device with a gate stacked dielectric layer. A first dielectric layer is formed on a semiconductor substrate having a first conductivity. A first conductive layer is formed on the first dielectric layer. A second dielectric layer is formed on the first conductive layer. The two dielectric layers are formed by sequentially stacking a first silicon dioxide layer, a nitride nitride layer, a nitride oxide layer, and a second dioxide layer on the first conductive layer. A second conductive layer is formed on the second dielectric layer. Pattern-etching the first dielectric layer, the first conductive layer, the second dielectric layer, and the second conductive layer to form a first gate dielectric layer, a floating logic gate, a second gate dielectric layer, and A control gate. Finally, a drain / source electrode having a second conductivity which is electrically opposite to the first conductivity is formed in the semiconductor substrate on the side of the floating logic gate. 5-4 Detailed description of the invention: The present invention provides a semiconductor memory device structure with a gate stacked dielectric layer and a manufacturing method thereof. The invention can provide an N-channel non-volatile semiconductor memory device and an N-channel non-volatile semiconductor memory device.

492146 五、發明說明（4) 記憶體元件。 本發明將藉由下文做一詳細說明。 參照第一圖，提供一具P型導電性之一半導體基底1 0 ，例如是一 P型矽底材。以傳統微影及蝕刻技術定義主 動區域（active region)於半導體基底1 0上。每一主動 區域係位於一對隔離區（未示出）之間，例如是一對區域 場氧化層之間。一第一介電層1 1形成於半導體基底1 0 之一主動區域上。第一介電層1 1可以是以熱氧化法形成 之一隧穿氧化層（tunnel oxide layer)。第一導電層1 2形成於第一介電層11上。第一導電層1 2可以是以傳 統低壓化學氣相沈積法形成的一多晶石夕層。一第二介電層 形成於第一導電層1 2上。第二介電層係藉由依序堆疊形 成一第一二氧化石夕層1 3 、一氮化石夕層（silicon nitride layer) 1 4 、 一 氣氧 4匕石夕層(silicon oxynitride layer )1 5及一第二二氧化矽層1 6於第一導電層1 2上而形 成。藉此，第二介電層具有二氧化矽/氮化矽/氮氧化矽/ 二氧化矽堆疊構造。一第二導電層1 7形成於第二介電層 上。第二導電層1 7可以是以傳統低壓化學氣相沈積法形 成的一多晶^夕層。 參照第二圖，以傳統微影及蝕刻技術圖案蝕刻第一介 電層1 1 、第一導電層1 2 、第二介電層及第二導電層1492146 V. Description of the invention (4) Memory element. The present invention will be described in detail below. Referring to the first figure, a semiconductor substrate 10 with P-type conductivity is provided, such as a P-type silicon substrate. Active lithography and etching techniques are used to define an active region on the semiconductor substrate 10. Each active region is located between a pair of isolation regions (not shown), such as between a pair of field oxide layers. A first dielectric layer 11 is formed on an active region of the semiconductor substrate 10. The first dielectric layer 11 may be a tunnel oxide layer formed by a thermal oxidation method. A first conductive layer 12 is formed on the first dielectric layer 11. The first conductive layer 12 may be a polycrystalline silicon layer formed by a conventional low-pressure chemical vapor deposition method. A second dielectric layer is formed on the first conductive layer 12. The second dielectric layer is formed by sequentially stacking a first SiO 2 layer 1 3, a silicon nitride layer 1 4, a gas oxygen 4 silicon oxynitride layer 1 5 and A second silicon dioxide layer 16 is formed on the first conductive layer 12. Accordingly, the second dielectric layer has a stack structure of silicon dioxide / silicon nitride / silicon oxynitride / silicon dioxide. A second conductive layer 17 is formed on the second dielectric layer. The second conductive layer 17 may be a polycrystalline layer formed by a conventional low-pressure chemical vapor deposition method. Referring to the second figure, the first dielectric layer 1 1, the first conductive layer 1 2, the second dielectric layer and the second conductive layer 1 are etched in a pattern by a conventional lithography and etching technique.

492146 五、發明說明（5) 7 ，以形成一第一閘極介電層、一浮動邏輯閘極、一第二 閘極介電層及一控制閘極於半導體基底1 0上。第二介電 層係由堆疊的第一二氧化矽層1 3 、氮化矽層1 4、氮氧 化矽層1 5及第二二氧化矽層1 6形成。因此，由第二介 電層形成的第二閘極介電層具有二氧化矽/氮化矽/氮氧化 矽/二氧化矽堆疊構造。一絕緣間隙壁1 8形成於浮動邏 輯閘極及控制閘極之一側壁上，以提供保護作用。以傳統 的離子植入方法，形成一包含N型摻質之源極/汲極1 9於 絕緣間隙壁1 8 —側的一半導體基底1 0中。據此，可獲 得具一閘極堆疊介電層之一 N通道非揮性半導體記憶體元 件。 第三圖係根據本發明之第一具體實施例，形成二氧化 矽/氮化矽/氮氧化矽/二氧化矽閘極堆疊介電層於多晶矽 第一導電層1 2上之步驟流程圖。在步驟3 1 ，整個半導 體基底1 0係置放於一快速加熱製程（rapid thermal p r o c e s s )反應室中。在溫度約8 0 0°C至1 2 0 0°C及壓力約5托 至2 0托下，利用Η 2/ 0砗合氣體做為反應氣體，以内部直接 形成蒸氣產生製程（in-situ steam generation process) 形成第一二氧化矽層1 3於多晶矽第一導電層1 2上。Η 2 / 0禺合氣體中之Η氰體流量比率約0 · 1〜4 0 %。在步驟3 2 ，整個半導體基底1 0係置放於一低壓化學氣相沈積反應 室中。利用Ν Η及S i Η麂合氣體做為反應氣體，以低壓化學 氣相沈積方法形成氮化矽層1 4於第一二氧化矽層1 3上492146 V. Description of the invention (5) 7 to form a first gate dielectric layer, a floating logic gate, a second gate dielectric layer and a control gate on the semiconductor substrate 10. The second dielectric layer is formed of a stacked first silicon dioxide layer 13, a silicon nitride layer 14, a silicon nitride oxide layer 15, and a second silicon dioxide layer 16. Therefore, the second gate dielectric layer formed by the second dielectric layer has a stack structure of silicon dioxide / silicon nitride / silicon oxynitride / silicon dioxide. An insulating partition wall 18 is formed on one side wall of the floating logic gate and the control gate to provide protection. According to the conventional ion implantation method, a source / drain 19 including an N-type dopant is formed in a semiconductor substrate 10 on the side of the insulating spacer 18. Accordingly, an N-channel nonvolatile semiconductor memory device having a gate stacked dielectric layer can be obtained. The third figure is a flow chart of steps for forming a silicon dioxide / silicon nitride / silicon oxynitride / silicon dioxide gate stacked dielectric layer on a polysilicon first conductive layer 12 according to a first embodiment of the present invention. In step 31, the entire semiconductor substrate 10 is placed in a rapid thermal process (rapid thermal proce c s s) reaction chamber. At a temperature of about 8 0 ° C to 12 0 0 ° C and a pressure of about 5 Torr to 20 Torr, a Η 2/0 hybrid gas is used as a reaction gas to directly form a vapor generation process (in-situ). steam generation process) forming a first silicon dioxide layer 13 on the first polycrystalline silicon conductive layer 12. The ratio of the flow rate of cyanide in the mixed gas of Η 2/0 is about 0 · 1 ~ 4 0%. In step 32, the entire semiconductor substrate 10 is placed in a low-pressure chemical vapor deposition reaction chamber. A silicon nitride layer 14 is formed on the first silicon dioxide layer 1 3 by using a low pressure chemical vapor deposition method using N Ν and Si Η gas as a reaction gas.

492146 五、發明說明（6) 。在步驟3 3 ，整個半導體基底1 0置放於快速加熱製程 反應室中。在溫度約7 0 0°C至約1 2 0 0°C及壓力約1 0托至7 6 0 托下，在一氧化氮氣氛（NO ambient)中，進行内部直接形 成蒸氣產生製程（in-situ steam generation process) 約3秒至約1 5 0秒，以形成氮氧化矽層1 5於氮化矽層1 4 上。在步驟3 4 ，整個半導體基底1 0仍置放於快速加熱 製程反應室中。利用Η 2/ 0祝合氣體做為反應氣體，藉由内 部直接形成蒸氣產生製程形成第二二氧化矽層1 6於氮氧 化石夕層1 5上。 第四圖係根據本發明第二具體實施例，形成二氧化矽 /氮化矽/氮氧化矽/二氧化矽閘極堆疊介電層於多晶矽第 一導電層1 2上之步驟流程圖。步驟4 1 、4 2及4 4係 與第一具體實施例的步驟3 1 、3 2及3 4相同。在步驟 4 3 ，係以一快速加熱製程（rapid thermal process)取 代内部直接形成蒸氣產生製程。整個半導體基底1 0置放 於一快速加熱製程反應室中。在溫度約7 0 0°C至約1 2 0 0°C 及壓力約1 0托至約5 0 0托下，在含有氧原子及氮原子的氣 體中，例如是一氧化二氮（N 20 )氣體中或一氧化氮（NO )氣 體中，施予回火步驟（a η n e a 1 i n g )於氮化石夕層1 4約5秒至 約1 8 0秒，以形成氮氧化石夕層1 5於氮化石夕層1 4上。此 外，可在溫度約7 0 0°C至約1 2 0 (TC下，在包含NH 3、S i Η 4、 Ν及0钓混合氣體中，施予回火步驟於氮化矽層1 4 ，以 形成氮氧化矽層1 5於其上。492146 V. Description of Invention (6). In step 33, the entire semiconductor substrate 10 is placed in a rapid heating process reaction chamber. In a temperature of about 700 ° C to about 120 ° C and a pressure of about 10 Torr to 7600 Torr, a direct vapor generation process (in- situ steam generation process) for about 3 seconds to about 150 seconds to form a silicon oxynitride layer 15 on the silicon nitride layer 14. In step 34, the entire semiconductor substrate 10 is still placed in the rapid heating process reaction chamber. The Η 2/0 gas is used as a reaction gas, and a second silicon dioxide layer 16 is formed on the oxynitride layer 15 by directly forming a vapor generation process inside. The fourth figure is a flow chart of steps for forming a silicon dioxide / silicon nitride / silicon oxynitride / silicon dioxide gate stacked dielectric layer on the first polysilicon conductive layer 12 according to the second embodiment of the present invention. Steps 4 1, 4 2 and 4 4 are the same as steps 3 1, 3 2 and 34 of the first embodiment. In step 43, a rapid thermal process is used instead of the internal direct vapor generation process. The entire semiconductor substrate 10 is placed in a rapid heating process reaction chamber. At a temperature of about 700 ° C to about 120 ° C and a pressure of about 10 Torr to about 500 Torr, in a gas containing oxygen and nitrogen atoms, for example, nitrous oxide (N 20 ) In a gas or a nitric oxide (NO) gas, a tempering step (a η nea 1 ing) is applied to the nitrided stone layer 14 for about 5 seconds to about 180 seconds to form a nitric oxide layer 1 5 on the nitrided layer 14. In addition, a tempering step may be performed on the silicon nitride layer 1 at a temperature of about 700 ° C. to about 120 ° C. in a mixed gas containing NH 3, Si i 4, N, and 0 °. To form a silicon oxynitride layer 15 thereon.

492146492146

五、發明說明（7) 本發明之第三具體實施例係形成二氧化矽/氮氧化矽/ 氮化矽/氮氧化矽/二氧化矽閘極堆疊介電層於多晶矽第一 導電層1 2上。本發明第三具體實施例與第一具體實施例 不同處在於第一二氧化矽層1 3與氮化矽層1 4之間形成 一氮氧化石夕層。此氮氧化；δ夕層形成方法與第一具體實施例 之氮氧化矽層1 5形成方法相同。即可將整個半導體基底 1 0置放於快速加熱製程反應室中，在溫度約7 0 0°C至約 1 2 0 0°C及壓力約1 〇托至7 6 0托下，在一氧化氮氣氛（NO ambient)中，進行内部直接形成蒸氣產生製程（in-situ steam generation process) ’以形成氮氧化石夕層於第一 二氧化矽層1 3上。另一種方法’係以一快速加熱製程（ rapid thermal process )取代内』直接形成蒸氣產生製私 。將整個半導體基底1 〇置放於一快速加熱製程反應室中 ，在溫度約7 0 0°C至約1 2 0 〇。〇及壓力約1 0托至約5 0 0托下， 在含有氧原子及氮原子的氣體中，例如是一氧化二氮（N 2〇 )氣體中或一氧化氮（NO)氣體中，施予回火步驟（ annealing)於第一二氧化矽層1 3上’以形成一氮氧化矽 層於第一二氧化矽層丄3上。此外，可在溫度約70 (TC至 約120(TC下，在包^關3、siHr N及0钓混合氣體中，施 予回火步驟於第一二氧化層1 3上，以形成氮氧化矽層於 其上。本發明第三具體實施例之第一二氧化矽層1 3 、氮 化矽層14、氮氧化矽層^ 5及第二二氧化矽層1 6之形 成方法皆與第一具體實施例所採用之方法相同。V. Description of the invention (7) The third embodiment of the present invention is to form a silicon dioxide / silicon oxynitride / silicon nitride / silicon oxynitride / silicon dioxide gate stacked dielectric layer on the polycrystalline silicon first conductive layer 1 2 on. The third embodiment of the present invention is different from the first embodiment in that a oxynitride layer is formed between the first silicon dioxide layer 13 and the silicon nitride layer 14. This method of oxidizing nitrogen; the layer of δ is the same as the method of forming the silicon oxynitride layer 15 of the first embodiment. That is, the entire semiconductor substrate 10 can be placed in a rapid heating process reaction chamber at a temperature of about 700 ° C to about 120 ° C and a pressure of about 100 Torr to 760 Torr. In a nitrogen atmosphere (NO ambient), an internal in-situ steam generation process is performed to form an oxynitride layer on the first silicon dioxide layer 13. Another method is to replace the internal method with a rapid thermal process (direct thermal process) to directly form steam to produce private products. The entire semiconductor substrate 10 is placed in a rapid heating process reaction chamber at a temperature of about 700 ° C. to about 120 °. 〇 and pressure of about 10 Torr to about 500 Torr, in a gas containing oxygen and nitrogen atoms, such as nitrous oxide (N 2 0) gas or nitrogen monoxide (NO) gas, A pre-annealing step (annealing) is performed on the first silicon dioxide layer 13 to form a silicon oxynitride layer on the first silicon dioxide layer 丄 3. In addition, a tempering step may be performed on the first dioxide layer 13 at a temperature of about 70 (TC to about 120 (TC) in a mixed gas including Baoguan 3, siHr N and 0, to form nitrogen oxide A silicon layer is formed thereon. The formation method of the first silicon dioxide layer 1 3, the silicon nitride layer 14, the silicon oxynitride layer 5 and the second silicon dioxide layer 16 of the third embodiment of the present invention are the same as those of the first embodiment. The method used in a specific embodiment is the same.

第10頁 492146 五 ΤΞ? 取 埃 〇 於 最 反 室 備 加 閘 的 電 具 體 定 精 中 、發明說明（8) 本發明之閘極堆疊介電層中，第一二氧化矽層丄3 、 後厚度約1 5埃至約7 0埃。氮化矽層1 4的最後^度約的 至約9 0埃。氮氧化；ε夕層1 5的最後厚度約5埃至約/、〇土 第一二氧化石夕層1 6的最後厚度約1 5埃至約1 2 〇埃。矣 第—二氧化矽層1 3與氮化矽層1 4之間之氮氧化矽 後厚度約5埃至約3 0埃。本發明所使用之快速加熱製程曰 應室及低壓化學氣相沈積反應室皆可設計成單晶片反壬應 (single-wafer chamber)。兩者亦可容易地整合於一二 j元中。因此，本發明之閘極堆疊介電層亦可以曰 …、製程（single-wafer thermal pr〇cess)形成。日日 本發明提供 極堆疊介電層 氧化矽閘極堆 氮化矽層針孔 性特性的閘極 有相同問極介 記憶體元件， 以上所述僅 本發明之申請 神下所完成之 晴範圍内。 的二 及二 疊介 效應 堆疊 電層 具有 為本 專利 專效 氧化秒/氮化碎/氮氧化石夕/二氧化矽 t化秒/氮氧切/氮切/氮氧化石夕/ %層可降低或消除傳統_0介電層中 二：時，本發明提供-種具有改曰良的 :電層的半導體記憶體元件，盆較之 ，，的傳統ΟΝΟ閘極堆叠介電層半導 較向的崩潰電壓及較低的漏電流。 Γ; „2例而已，並非用以限 脫離本發明所揭示之 文艾或修飾，均應包含在下述之專利 修正 、I、 jffp~ c v90117293 年 月 曰 修正 圖式簡單說明 第一圖至第二圖係本發明半導體記憶體元件之製作方 法的各種步驟的截面示意圖； 第三圖係根據本發明一第一具體實施例之形成閘極堆 疊介電層之各種步驟流程圖；及 第四圖係根據本發明一第二具體實施例之形成閘極堆 疊介電層之各種步驟流程圖。 主要部份之代表符號： 10 半導體基底 2 4 78 9 第一介電層 第一導電層 第一二氧化石夕層 氮化矽層 氮氧化矽層 第二二氧化矽層 第二導電層 絕緣間隙壁 源極/没極Page 10 492146 5T? Take the electric power in the most anti-chamber electrical gate, the description of the invention (8) In the gate stacked dielectric layer of the present invention, the first silicon dioxide layer 丄 3, The thickness is about 15 angstroms to about 70 angstroms. The last degree of the silicon nitride layer 14 is about 90 angstroms to about 90 angstroms. Nitrogen oxidation; the final thickness of the epsilon layer 15 is about 5 angstroms to about 10,000 angstroms. The final thickness of the first dioxide layer 16 is about 15 angstroms to about 120 angstroms.后 The thickness of the silicon oxynitride between the silicon dioxide layer 13 and the silicon nitride layer 14 is about 5 angstroms to about 30 angstroms. Both the rapid heating process chamber and the low-pressure chemical vapor deposition reaction chamber used in the present invention can be designed as single-wafer chambers. The two can also be easily integrated into one or two j-elements. Therefore, the gate stack dielectric layer of the present invention can also be formed by a single-wafer thermal process. Japan and Japan invented that the gates providing the pin-stacked dielectric layer, silicon oxide gate stack, and silicon nitride layer pinhole characteristics have the same intervening dielectric memory elements. The above description is only within the scope of the application of the present invention. . The two-layer and two-layer Dielectric effect stacking electric layers have specific oxidation seconds / nitrified fragments / nitrogen oxides / silicon dioxide oxides / nitrogen cuts / nitrogen cuts / nitrogen oxides /% layers available for this patent. Reduction or elimination of traditional _0 dielectric layers: at present, the present invention provides a semiconductor memory element with improved: electrical layer, compared with the traditional semiconductor gate dielectric stack semiconductor layer Breakdown voltage and lower leakage current. Γ; „2 examples, not intended to limit the text or modification disclosed in the present invention, all should be included in the following patent amendments, I, jffp ~ c The second figure is a schematic cross-sectional view of various steps of a method for manufacturing a semiconductor memory device according to the present invention; the third figure is a flowchart of various steps for forming a gate stacked dielectric layer according to a first embodiment of the present invention; and the fourth figure It is a flowchart of various steps for forming a gate stacked dielectric layer according to a second embodiment of the present invention. Representative symbols of the main part: 10 semiconductor substrate 2 4 78 9 first dielectric layer first conductive layer first two Stone oxide layer, silicon nitride layer, silicon oxynitride layer, second silicon dioxide layer, second conductive layer, insulation gap wall source / non-polar

第12頁Page 12

Claims (1)

492146 六、申請專利範圍 1. 一種具閘極堆疊介電層之半導體記憶體元件之製作方法 ，至少包括： 形成一第一介電層於具一第一導電性之一半導體基底 上； 形成一第一導電層於該第一介電層上； 形成一第二介電層於該第一導電層上，該第二介電層 係藉依序堆疊形成一第一二氧化碎層、一氮化碎層、一氮 氧化矽層及一第二二氧化矽層於該第一導電層上而形成； 形成一第二導電層於該第二介電層上； 圖案蝕刻該第一介電層、該第一導電層、該第二介電 層及該第二導電層，以形成一第一閘極介電層、一浮動邏 輯閘極、一第二閘極介電層及一控制閘極；及 形成具電性相反於該第一導電性之一第二導電性之一 汲極/源極於該浮動邏輯閘極一側的該半導體基底中。 2. 如申請專利範圍第1項所述之方法，其中上述之第一導 電性係為N型導電性及P型導電性其中任一者。 3. 如申請專利範圍第1項所述之方法，其中上述之第一導 電層包含多晶石夕。 4. 如申請專利範圍第1項所述之方法，其中上述之氮化矽 層係利用Ν Η及S i IU故為反應氣體，以低壓化學氣相沈積方 法形成。492146 VI. Scope of patent application 1. A method for fabricating a semiconductor memory device having a gate stacked dielectric layer, at least comprising: forming a first dielectric layer on a semiconductor substrate having a first conductivity; forming a A first conductive layer is formed on the first dielectric layer; a second dielectric layer is formed on the first conductive layer, and the second dielectric layer is sequentially stacked to form a first fragmented oxide layer and a nitrogen layer. A chip layer, a silicon oxynitride layer, and a second silicon dioxide layer are formed on the first conductive layer; a second conductive layer is formed on the second dielectric layer; the first dielectric layer is pattern-etched , The first conductive layer, the second dielectric layer and the second conductive layer to form a first gate dielectric layer, a floating logic gate, a second gate dielectric layer and a control gate And forming a drain / source electrode electrically opposite to the first conductivity and the second conductivity in the semiconductor substrate on the side of the floating logic gate. 2. The method according to item 1 of the scope of patent application, wherein the first conductivity is any one of N-type conductivity and P-type conductivity. 3. The method according to item 1 of the scope of patent application, wherein the first conductive layer mentioned above comprises polycrystalline silicon. 4. The method according to item 1 of the scope of the patent application, wherein the above silicon nitride layer is formed by using low pressure chemical vapor deposition method using N Η and S i IU as reactive gases. 第13頁 492146 六、申請專利範圍 5 ·如申請專利範圍第1項所述之方法，其中上述之氮氧化 矽層係在溫度約7 0 0°C至約1 2 0 0°C及壓力約1 0托至約7 6 0托 下，在一氧化氮氣氛（NO ambient)中以内部直接形成蒸氣 產生製程(in— situ steam generation process ^ 3 秒至約1 5 0秒而形成。 6 .如申請專利範圍第3項所述之方法，其中上述之第一二 氧化矽層係在溫度約8 0 0°C至約1 2 0 0°C及壓力約5托至約2 0 托下，利用Η 2/ 0做反應氣體，以内部直接形成蒸氣產生製 程形成。 7 ·如申請專利範圍第6項所述之方法，其中上述之Η 2/ 0展 應氣體中，Η夂氣體流量比率約0 . 1〜4 0 %。 8. 如申請專利範圍第1項所述之方法，其中上述之第二二 氧化矽層係利用Η 2/ 0做為反應氣體，以内部直接形成蒸氣 產生製程形成。 9. 如申請專利範圍第1項所述之方法，其中上述之氮氧化 矽層係在包含氧原子及氮原子的氣體中，施予回火步驟（ a η n e a 1 i n g )於該氮化石夕層而形成。 1 〇 .如申請專利範圍第1項所述之方法，其中上述之氮氧化Page 13 492146 VI. Patent Application Range 5 · The method described in item 1 of the patent application range, wherein the above silicon oxynitride layer is at a temperature of about 700 ° C to about 120 ° C and a pressure of about From 10 Torr to about 760 Torr, it is formed in a nitric oxide atmosphere (NO ambient) with an internal steam formation process (in-situ steam generation process ^ 3 seconds to about 150 seconds). The method described in item 3 of the scope of patent application, wherein the first silicon dioxide layer described above is used at a temperature of about 800 ° C to about 120 ° C and a pressure of about 5 torr to about 20 torr. Η 2/0 is used as the reaction gas, which is formed by the internal direct vapor generation process. 7 · The method described in item 6 of the scope of the patent application, wherein the Η 夂 2/0 spontaneous gas in the above-mentioned Η 夂 2 gas flow rate is about 0 1 ~ 40%. 8. The method as described in item 1 of the scope of patent application, wherein the second silicon dioxide layer is formed by using Η 2/0 as a reaction gas and directly forming a vapor generation process inside. 9. The method according to item 1 of the scope of patent application, wherein the above silicon oxynitride layer is contained in Gas atom and a nitrogen atom, administered tempering step (a η n e a 1 i n g) in the nitrogen fossil Xi layer is formed. 1 billion. The application method according to the item 1 patentable scope, wherein said the oxynitride 第14頁 492146 六、申請專利範圍 矽層係在溫度約7 0 0°C至約1 2 0 0°C下，在包含NH 3、S i Η 4、 Ν及Ο Α混合氣體中，施予回火步驟於該氮化矽層而形 成。 1 1 .如申請專利範圍第1項所述之方法，其中上述之氮氧化 矽層係在溫度約7 0 0°C至約1 2 0 0°C及壓力約1 0托至約5 0 0托 下，在包含氧原子及氮原子的氣體中，施予回火步驟於該 氮化矽層上約5秒至約1 8 0秒而形成。 1 2 .如申請專利範圍第1項所述之方法，其中上述之氮氧化 矽層係在一氧化二氮（N 20)氣體中，施予回火步驟於該氮 化石夕層上而形成。 1 3 .如申請專利範圍第1項所述之方法，其中上述之氮氧化 矽層係在一氧化氮（N 0)氣體中，施予回火步驟於該氮化矽 層上而形成。 1 4 .如申請專利範圍第1項所述之方法，其中上述之氮氧化 矽層係在包含氧原子及氮原子的氣體中，以單晶片加熱製 程處理該I化矽層而形成。 1 5 .如申請專利範圍第1項所述之方法，更包含形成一氮氧 化矽層於該第一二氧化矽層與該氮化矽層之間。Page 14 492146 VI. Scope of patent application The silicon layer is applied at a temperature of about 700 ° C to about 120 ° C in a mixed gas containing NH 3, S i Η 4, Ν, and 〇 Α. A tempering step is formed on the silicon nitride layer. 1 1. The method according to item 1 of the scope of patent application, wherein the above silicon oxynitride layer is at a temperature of about 700 ° C to about 12 0 0 ° C and a pressure of about 10 Torr to about 5 0 0 Under the circumstances, in a gas containing oxygen atoms and nitrogen atoms, a tempering step is performed on the silicon nitride layer for about 5 seconds to about 180 seconds. 12. The method according to item 1 of the scope of the patent application, wherein the silicon oxynitride layer is formed in a nitrous oxide (N20) gas, and a tempering step is performed on the nitrogen fossil layer. 13. The method according to item 1 of the scope of the patent application, wherein the silicon oxynitride layer is formed in a nitric oxide (N 0) gas, and a tempering step is performed on the silicon nitride layer. 14. The method according to item 1 of the scope of patent application, wherein the silicon oxynitride layer is formed by processing the silicon nitride layer in a gas containing oxygen atoms and nitrogen atoms by a single wafer heating process. 15. The method according to item 1 of the scope of patent application, further comprising forming a silicon nitride oxide layer between the first silicon dioxide layer and the silicon nitride layer. 第15頁 492146 六、申請專利範圍 1 6 .如申請專利範圍第1 5項所述之方法，其中上述之第一 二氧化矽層與該氮化矽層之間之該氮氧化矽層係在溫度約 7 0 0°C至約1 2 0 0°C及壓力約1 0托至約7 6 0托下，在一氧化氮 氣氛（N 0 a m b i e n t)中以内部直接形成蒸氣產生製程（i η -situ steam generation process)形成。 1 7 .如申請專利範圍第1 5項所述之方法，其中上述之第一 二氧化矽層與該氮化矽層之間之該氮氧化矽層係在溫度約 7 0 0°C至約1 2 0 0°C下，在包含NH 3、S i Η 4、N及0夂混合氣體 中，施予回火步驟於該第一二氧化矽層而形成。 1 8.如申請專利範圍第1 5項所述之方法，其中上述之第一 二氧化矽層與該氮化矽層之間之該氮氧化矽層係在溫度約 7 0 0°C至約1 2 0 0°C及壓力約1 0托至約5 0 0托下，在包含氧原 子及氮原子的氣體中，施予回火步驟於該第一二氧化矽層 而形成。 1 9 .如申請專利範圍第1 5項所述之方法，其中上述之第一 二氧化矽層與該氮化矽層之間之該氮氧化矽層係在一氧化 二氮（N 20)氣體中，施予回火步驟於該第一二氧化矽層上 而形成。 2 0 .如申請專利範圍第1 5項所述之方法，其中上述之第一 二氧化矽層與該氮化矽層之間之該氮氧化矽層係在一氧化Page 15 492146 VI. Patent Application Range 16. The method as described in item 15 of the patent application range, wherein the silicon oxynitride layer between the first silicon dioxide layer and the silicon nitride layer is between At a temperature of about 7 0 ° C to about 12 0 0 ° C and a pressure of about 10 Torr to about 7 600 Torr, a vapor generation process (i η) is formed directly in the interior in a nitric oxide atmosphere (N 0 ambient). -situ steam generation process). 17. The method according to item 15 of the scope of patent application, wherein the silicon oxynitride layer between the first silicon dioxide layer and the silicon nitride layer is at a temperature of about 700 ° C. to about Formed by applying a tempering step to the first silicon dioxide layer in a mixed gas containing NH 3, Si Η 4, N, and 0 下 at 120 ° C. 18. The method as described in item 15 of the scope of patent application, wherein the silicon oxynitride layer between the first silicon dioxide layer and the silicon nitride layer is at a temperature of about 700 ° C. to about It is formed by applying a tempering step to the first silicon dioxide layer in a gas containing oxygen atoms and nitrogen atoms at a temperature of about 120 Torr and a pressure of about 10 Torr to about 500 Torr. 19. The method according to item 15 of the scope of patent application, wherein the silicon oxynitride layer between the first silicon dioxide layer and the silicon nitride layer is a nitrous oxide (N 20) gas During the tempering step, the first silicon dioxide layer is formed. 20. The method according to item 15 of the scope of patent application, wherein the silicon oxynitride layer between the first silicon dioxide layer and the silicon nitride layer is a mono-oxide 第16頁 492146Page 16 492146 第17頁Page 17