490784 五、發明說明（l) 【發明領域】 ί :有關於一種避免形成測試刮痕之半導體-晶圓。 種具有凸塊以及分離測試墊之半導體 【先前技術】 習知積體電路在進行晶圓級測試〔评““490784 V. Description of the invention (l) [Field of invention] ί: There is a semiconductor-wafer that avoids forming test scratches. Semiconductor with bumps and separate test pads [Prior art] It is known that integrated circuits are performing wafer-level testing [review ""
Testing〕時，係以控私r [ 之焊墊或凸塊，其中H? needle〕屢觸在晶圓上 接之端點，如打線或；；部電性連 會在焊墊或凸塊等端點μ、生士m 保針 後續製程及產品可靠度之；題 scrub mark〕，造成 直探=m5: 554,940號「具凸塊之半導體裝置及 八探測方法」中揭不一種避免當探測時直&在外部端點 〔凸塊〕上形成測試刮痕之半導體裝置，其係在一半導體 :曰：上除了原本覆晶結合之凸塊，另形成分離式測試墊， 使侍測試時不再需要探測壓觸凸塊，如第丨、2及3圖所 不，一半導體晶片1 0係具有複數個焊墊丨2，焊墊丨2 於内介電層18、20與絕緣層22之間，利用金屬栓16及金^ 連接線14連接半導體晶片1〇之積體電路，且在焊塾12上具 有穿過絕緣層22之栓38及在上方之導通墊34，以銜接在^ 具焊塾12之表面上之重分佈結構26〔redistributiQn八 structure〕，每一重分佈結構26具有一測試墊28、一凸 塊底墊30、一凸塊連接線32及一測試連接線36〔如第2圖 所示〕’其中凸塊連接線32係電性連接凸塊底墊3〇與其對 490784 五、發明說明（2) --— 應之焊墊12或測試墊28 ,而測試連接線36係電性連接測 墊2 8與其對應之焊墊12，如第2圖所示，上述之複數個重 分佈結構26係被一防護層40〔passivati〇n丨”打〕覆 蓋，且該防護層40具有複數個開口42，以打開測試墊28與 凸塊底墊30〔如第3及4圖所示〕，其中測試墊2 8係可供 針50探壓接觸，此外，如第2及4圖所示，凸塊底墊形 成有一凸塊4 8，並在凸塊48與凸塊底墊30之間形成有一金 屬阻障層44〔metal barrier layer〕，上述之半導體晶 片1 〇在測試過程時，被探針50探觸之測試墊28係經由測試 連接線36、導通墊34及栓38導通至焊墊12，以測試積體 路，測試墊28與焊墊12之連接路徑係不經過凸塊連接線 32，、無法測試凸塊連接線32是否良好，即凸塊連接線“斷 線或短路時，係無法以測試墊28探壓測試其線路狀況， 成測试不破實之現象。 【發明目的及概要】 、…本^明之主要目的在於提供一種避免形成測試刮痕之 ，導體μ圓，在晶圓之一表面形成有複數個金屬連接線， 母金屬連接線連接下層焊墊、測試墊及連接墊，利用作 $外端接點之連接墊係串接於對應焊墊與測試墊之間， 得在探觸測試墊時可測試到在焊墊與測 接線，同時避免形成測試刮痕。 金屬連 依本發明之避免形成測試刮痕之半導體晶圓，复肖 含： ’、0 複數個半導體晶片，每一晶片具有一積體電路形成表 ^0784 五、發明說明（3) =，其形成於該半導體晶圓之同一表面，其中晶片在積體 電路形成表面具有複數個焊墊； 複數個切割道，係形成於相鄰晶片之間； 、 複數個金屬連接線，位於晶片之積體電路形成表面上 並分別電性連接對應之焊墊； 一防護層，覆蓋上述之複數個金屬連接線並具有複數 個第一開口及第二開口； 複數個測試墊，位於防護層之第一開口，經由對應之 一金屬連接線導通至對應焊墊；及 〜Testing], it is to control the pads or bumps of the [r, where H? Needle] repeatedly touches the end point connected on the wafer, such as wire bonding or; the electrical connection will be on the pads or bumps, etc. End point μ, Shengshi m, needle follow-up process and product reliability; question scrub mark], resulting in direct detection = m5: 554,940 "Semiconductor devices with bumps and eight detection methods" can not be found when avoiding detection Straight & a semiconductor device that forms a test scratch on an external terminal [bump], which is a semiconductor: In addition to the bumps that were originally bonded to the chip, a separate test pad is formed to prevent the test It is necessary to detect the pressure bumps. As shown in Figures 丨, 2 and 3, a semiconductor wafer 10 has a plurality of pads 2 and the pads 2 are between the inner dielectric layers 18, 20 and the insulating layer 22. In the meantime, the integrated circuit of the semiconductor wafer 10 is connected with the metal plug 16 and the gold connection wire 14, and the solder pad 12 has a plug 38 passing through the insulating layer 22 and a conduction pad 34 above to connect to the metal mold. A redistribution structure 26 [redistributiQn eight structure] on the surface of the welding pad 12, each redistribution structure 26 has a Test pad 28, a bump bottom pad 30, a bump connection line 32 and a test connection line 36 (as shown in FIG. 2) 'wherein the bump connection line 32 is electrically connected to the bump bottom pad 3 and its opposite 490784 V. Description of the invention (2) --- Corresponding solder pad 12 or test pad 28, and the test connection line 36 is electrically connected to the test pad 28 and its corresponding solder pad 12, as shown in FIG. The plurality of redistribution structures 26 are covered by a protective layer 40 (passivating), and the protective layer 40 has a plurality of openings 42 to open the test pad 28 and the bump bottom pad 30 (such as the third and fourth As shown in the figure, where the test pad 28 is a probe 50 for pressure contact, in addition, as shown in Figures 2 and 4, the bump bottom pad is formed with a bump 4 8, and the bump 48 and the bottom of the bump are formed. A metal barrier layer 44 is formed between the pads 30. During the test process of the semiconductor wafer 10, the test pad 28 touched by the probe 50 passes through the test connection line 36, the conductive pad 34, and the bolt. 38 is connected to the pad 12 to test the integrated circuit. The connection path between the test pad 28 and the pad 12 does not pass through the bump connection line 32, and cannot be tested. Block connection line 32 is good, i.e., bumps connecting line "is the line break or short circuit can not be based test pad 28 to pressure test the probe line condition, do not break into a test false phenomenon. [Objective and Summary of the Invention] The main purpose of the present invention is to provide a conductor μ circle that avoids the formation of test scratches. A plurality of metal connecting lines are formed on one surface of the wafer, and the parent metal connecting lines are connected to the lower pads. The test pads and connection pads are connected in series between the corresponding pads and the test pads by using the connection pads as the outer termination points. When the test pads are touched, the test pads and test wires can be tested, and the test can be avoided. Scratches. The metal wafers according to the present invention are used to avoid the formation of test scratches on semiconductor wafers, including: ', 0 a plurality of semiconductor wafers, each wafer having an integrated circuit formation table ^ 0784 5. Invention description (3) =, which Formed on the same surface of the semiconductor wafer, wherein the wafer has a plurality of bonding pads on the surface of the integrated circuit; a plurality of scribe lines are formed between adjacent wafers; and a plurality of metal connecting lines are located on the integrated body of the wafer The circuit forming surface is electrically connected to corresponding solder pads respectively; a protective layer covering the plurality of metal connecting lines described above and having a plurality of first openings and second openings; a plurality of test pads located at the first openings of the protective layer , Is conducted to the corresponding pad via a corresponding one of the metal connecting lines; and ~
複數個連接墊，位於防護層之第二開口，其中連接墊 係以對應之一金屬連接線串接於對應焊墊與測試墊之間。 【發明詳細說明】 請參閱所附圖式，本發明將列舉以下之實施例說明： 第5圖所示，本發明之半導體晶圓1〇〇係包含有複數個半導 體晶片11 0以及在相鄰晶片間之切割道i 〇 i，沿切割道1 〇工 切斷可分離為個別之半導體晶片J i 〇。 如第6及7圖所示，半導體晶片11〇在積體電路形成表 面具有複數個連搔至積體電路之焊墊112，其位於基板12〇 之上，以及一絕緣層122，如二氧化矽、psG、BpsG、TE〇s 等等，其中絕緣層122具有裸露焊墊112之開口，即為一般 =曰：架構’在絕緣層122上以氣相沉積及姓刻技術形成 有複數個金屬連接線132、136、連接塾13〇、測試塾128， 每一金屬連接線係區分為一重分佈連接線M2及一測 试連接線136，連接墊130係作為半導體晶片u〇之外端接A plurality of connection pads are located in the second opening of the protective layer, wherein the connection pads are serially connected between the corresponding solder pads and the test pads by a corresponding metal connection line. [Detailed description of the invention] Please refer to the attached drawings. The present invention will list the following embodiments: As shown in FIG. 5, the semiconductor wafer 100 of the present invention includes a plurality of semiconductor wafers 110 and adjacent The dicing path i oi between the wafers can be separated into individual semiconductor wafers ji by cutting along the dicing path 10 times. As shown in FIGS. 6 and 7, the semiconductor wafer 11 has a plurality of pads 112 connected to the integrated circuit on the surface of the integrated circuit, which are located on the substrate 12 and an insulating layer 122, such as dioxide. Silicon, psG, BpsG, TE0s, etc., where the insulating layer 122 has an opening of the exposed pad 112, which is general = said: the structure is formed on the insulating layer 122 by vapor deposition and engraving techniques. Connection lines 132, 136, connection 塾 13〇, test 塾 128, each metal connection line is divided into a redistribution connection line M2 and a test connection line 136, and the connection pad 130 is used as a termination outside the semiconductor wafer u0
第7頁 490784 五、發明說明（4) 點而位於半導體晶片11〇之一表面上，並以重分佈連接線 132電性連接至對應焊墊，在連接墊130之上方形成有 阻障層144及凸塊148，使該半導體晶片11〇呈覆晶型態， 而測試墊1 28係作為半導體晶片i丨〇之測試端點，並以測試 連接線136電性連接至對應連接3〇，在本實施例中，測 試墊1 2 8係位於晶片11 〇之四側邊並在切割道1 〇 1上，此 外’在絕緣層122上另形成一防護層140〔passivati〇ri layer〕，如聚亞醯胺〔p〇1yimide〕、苯環丁烯〔benez〇 cjclobutene〕或其它低介電常數材料，該防護層14〇係覆 蓋重分佈連接線132與測試連接線136〔即金屬連接線〕並 具有複數個第一開口丨41及第二開口丨42，其中第一開口 1 41係至y 伤裸露測試墊丨2 8，而第二開口丨4 2 接墊130。 4 由於連接墊1 3 0係以對應之一金屬連接線串接於對應 焊墊112與測試墊丨28之間，當上述之半導體晶圓1〇〇在晶 ，級測試時，係以探針150接觸測試墊128，測試墊128與 焊墊112之導通路徑係通過測試連接線136、重分佈連接線 132，在晶圓級測試時能同時檢測重分佈連接線132，同時 避免形成測試刮痕，此外，當測試墊]28位於 上，使得連接塾130具有較大之分ϊ ;以;;2 ϋ試墊128或連接墊130均能具有較多配置數 重以適用於兩端子數之半導體裝置。 在本發明之第二具體實施例中，h第8圖所示，一半 導體晶片210具有一呈矩形之積體電路形成表面，其上形 490784 五、發明說明（5) 成有複數個焊墊212、凸塊248及測試墊228，焊㈣2與對 應之凸塊248係以一重分佈連接線232連接，而凸塊盥 對應之測，墊228係以一測試連接線236連接，通常另以一 防3蔓層覆蓋重分佈連接線232、測試連接線248與焊墊 212，測試墊228依測試f要可另形成有測試凸塊或呈平墊 狀，測試墊228係、分佈於積體電路形^^面之兩對應侧邊 並呈交錯間隔排列，使得測試墊228之間具有較大的間 距，同樣地，在測試該半導體晶片2 i 0時亦能檢測 佈連接線232。 、在本發明之第三具體實施例中，如第9圖所示，一半 導體晶片310具有一積體電路形成表面，其上形成有位於 一中心線之複數個焊墊312、凸塊348及測試凸塊32 8，焊 墊312與對應之凸塊348係以一重分佈連接線332連接，而 凸塊348與對應之測試凸塊3 28係以一測試連接線6連 接，通常另以一防護層覆蓋重分佈連接線332、測試連接 線348與焊墊312，測試凸塊328係可為凸塊狀或平墊狀並 ^佈於積體電路形成表面之兩對應侧邊，而凸塊348係呈 交錯間隔排列’使得凸塊348之間具有較大的間距。 、故本發明之保護範圍當視後附之申請專利範圍所界定 ^為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 第9頁 4^υ/84 圖式簡單說明 【圖式說明】 第1圖·在美國專利第5,554,94〇號「具凸塊之半導體裝 置及其探測方法」中，該晶月之俯視圖； 第2圖·在第1圖中，該習知晶片之局部放大圖； 第3圖·沿第2圖3 - 3線之剖視圖； 第4圖··沿第2圖4-4線之剖視圖； 第5圖：本發明之一半導體晶圓示意圖； 第6圖··依據本發明之一實施例，一半導體晶圓之局部放 大示意圖； 第7圖··在第6圖中，沿其中一金屬連接線之剖面示意 IS1 · 園，Page 7 490784 V. Description of the invention (4) Point is located on one of the surfaces of the semiconductor wafer 110, and is electrically connected to the corresponding pad with a redistribution connection line 132, and a barrier layer 144 is formed above the connection pad 130 And the bump 148, so that the semiconductor wafer 110 is in a flip-chip type, and the test pad 1 28 is used as a test endpoint of the semiconductor wafer i 丨 〇, and is electrically connected to the corresponding connection 30 with a test connection line 136. In this embodiment, the test pad 1 2 8 is located on the four sides of the wafer 11 〇 and is on the scribe line 101. In addition, a protective layer 140 [passivati ri layer] is formed on the insulating layer 122. Pyroylimide [benzocclobutene] or other low dielectric constant materials, the protective layer 14 covers the redistribution connection lines 132 and the test connection lines 136 (ie, metal connection lines) and There are a plurality of first openings 41 and second openings 42, where the first opening 1 41 is connected to the y-wound bare test pad 218 and the second opening 4 2 is a pad 130. 4 Because the connection pad 130 is connected in series with the corresponding one of the metal connection wires between the corresponding pad 112 and the test pad 28, when the above-mentioned semiconductor wafer 100 is in the crystal, the test is performed with a probe 150 contacts the test pad 128. The conduction path between the test pad 128 and the solder pad 112 is through the test connection line 136 and the redistribution connection line 132, and the redistribution connection line 132 can be detected at the same time during the wafer-level test, while avoiding the formation of test scratches. In addition, when the test pad] 28 is located on the top, the connection 塾 130 has a larger division; ;; 2; either the test pad 128 or the connection pad 130 can have a larger number of configurations to be suitable for two-terminal semiconductors Device. In the second specific embodiment of the present invention, as shown in FIG. 8, a semiconductor wafer 210 has a rectangular integrated circuit forming surface with an upper shape of 490784. V. Description of the invention (5) A plurality of solder pads are formed. 212, the bump 248 and the test pad 228, the welding pad 2 and the corresponding bump 248 are connected by a redistribution connection line 232, and the bump is correspondingly measured, the pad 228 is connected by a test connection line 236, usually another one The anti-three layer covers the redistribution connection line 232, the test connection line 248, and the solder pad 212. The test pad 228 may be formed with a test bump or a flat pad according to the test f. The test pad 228 is distributed on the integrated circuit The two corresponding sides of the shape surface are arranged at staggered intervals, so that the test pads 228 have a relatively large distance. Similarly, the cloth connection line 232 can be detected when the semiconductor wafer 2 i 0 is tested. In a third specific embodiment of the present invention, as shown in FIG. 9, a semiconductor wafer 310 has an integrated circuit forming surface on which a plurality of pads 312, bumps 348, and a center line are formed. The test bump 328, the solder pad 312 and the corresponding bump 348 are connected by a redistribution connection line 332, and the bump 348 and the corresponding test bump 3 28 are connected by a test connection line 6, usually with another protection The layer covers the redistribution connection line 332, the test connection line 348, and the solder pad 312. The test bump 328 can be a bump shape or a flat pad shape and is arranged on two corresponding sides of the integrated circuit forming surface, and the bump 348 The system is arranged in a staggered interval, so that the bumps 348 have a larger distance between them. 2. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to the present invention. protected range. 4 ^ υ / 84 on page 9 Brief description of the drawings [Illustration of the drawings] Figure 1 · In US Patent No. 5,554,940 "Semiconductor Device with Bumps and Detection Method", a top view of the crystal moon; Fig. 2 · In Fig. 1, a partially enlarged view of the conventional wafer; Fig. 3 · Cross-sectional view along line 2-3 of Fig. 2; Fig. 4 · · Cross-sectional view along line 4-4 of Fig. 2; Fig. 5: A schematic diagram of a semiconductor wafer according to the present invention; Fig. 6 ... A partially enlarged schematic diagram of a semiconductor wafer according to an embodiment of the present invention; Fig. 7 ... In Fig. 6, along one of the metals The cross section of the connecting line indicates IS1
第8圖：依據本發明之另一實施例，一半導體晶片之測試 墊分佈及連接示意圖；及 第9圖：依據本發明之再一實施例，一半導體晶片之測試 墊分佈及連接示意圖。 【圖號說明】 10 半導體晶片 12 焊墊 14 金屬連接線 16 金屬卷^ 18 内介電層 20 内介電層 22 絕緣層 24 開口 26 重分佈結構 28 測試墊 30 凸塊底墊 32 凸塊連接線 34 導通墊 36 測試連接線 38 栓 40 防護層 42 開口 44 阻障層 48 凸塊 50 探針 100 半導體晶圓 101 切割道 第10頁8 is a schematic diagram of the distribution and connection of test pads of a semiconductor wafer according to another embodiment of the present invention; and FIG. 9 is a schematic diagram of the distribution and connection of test pads of a semiconductor wafer according to another embodiment of the present invention. [Illustration of the drawing number] 10 Semiconductor wafer 12 Welding pad 14 Metal connection line 16 Metal coil ^ 18 Inner dielectric layer 20 Inner dielectric layer 22 Insulating layer 24 Opening 26 Redistribution structure 28 Test pad 30 Bump bottom pad 32 Bump connection Line 34 Conductive pad 36 Test connection line 38 Pin 40 Protective layer 42 Opening 44 Barrier layer 48 Bump 50 Probe 100 Semiconductor wafer 101 Dicing track page 10
490784 圖式簡單說明 11 〇半導體晶片 112 120基板 122 130連接墊 132 140 防護層 141 1 4 4 阻障層 148 2 1 0半導體晶片 212 232重分佈連接線236 240防護層 248 310半導體晶片 312 332重分佈連接線336 340防護層 348 焊墊 絕緣層 1 2 8測試塾 重分佈連接線1 3 6測試連接線 第一開口 142第二開口 凸塊 150探針 焊墊 228測試墊 測試連接線 凸塊 焊墊 328測試凸塊 測試連接線 凸塊490784 Simple illustration of the diagram 11 〇Semiconductor wafer 112 120 Substrate 122 130 Connection pad 132 140 Protective layer 141 1 4 4 Barrier layer 148 2 1 0Semiconductor wafer 212 232 Redistribution connection line 236 240 Protection layer 248 310 Semiconductor wafer 312 332 Weight Distribution connection line 336 340 Protective layer 348 Pad insulation layer 1 2 8 Test redistribution connection line 1 3 6 Test connection line first opening 142 Second opening bump 150 Probe pad 228 Test pad test connection line bump welding Pad 328 test bump test connection line bump