TW488028B - Manufacturing method for dual damascene with low barrier loss by partial etching - Google Patents

Abstract

The present invention provides a manufacturing method for dual damascene with low barrier loss by partial etching. The method according to the present invention is provided to employ the first-approached via to etch the via until reaching a partial depth without contacting with the barrier to reduce the barrier loss; then, during trench etching, directly etching the barrier with better selectivity program on the pattern defined by the lithography process and the vias partially etched previously, so as to obtain a lower barrier loss to get the dual damascene profile. The present method can increase the window of dual damascene etching process and the remained the barrier.

Description

發明領域： 本發明係有關於一種雙鑲 之製造方法，特別是關於— 入構k ( Dual damascene ) 分蝕刻得到低阻障層指▲ 種以無有機抗反射層填入和部 、的雙鑲嵌構造之製造方法。 發明背景： 以往半導體製程中是 (sputtering)的方式將、為連線材料，通常以濺鍍 線路越來越小，傳輪速戶 2矽晶圓上。但是在1C設計 的可能性也就越高，= = 下主以銅代替- 電性比鋁要高出一❾ ：J疋鋁的-半，也就是導 銅為導線的it件可p 有低電阻的特性’因此以 少所需金屬層的數T電路排列，如此可大大減 ;L;::對:高的❹言是理想的連線材 所謂金屬可靠性是指電流在傳輸時會產 高：金i“eler::grati〇n)的現象’抗電子遷移越 枓，/、金屬可靠性也就越高，在I c設計線路越 來越細1、的技術演進高之金屬材料，對金屬可靠性之要求 S就越咼，因此以銅為導線的元件具有更高的壽命及穩定 989年起’金屬銅之化學氣相沈積法便如雨後春荀 般地開始被廣泛的研究，其主要的原因乃是在於進入VLSi 技術時金屬化（Metallization)變成為一種關鍵步驟， 五、發明說明（2) 而且當元件 此而增加， 遷移及應力 Formation : 學氣相沈積 的鋁線與金 通常，金屬 接觸窗的填 由於雙 成銅金屬的 術，完成栓 氣相沈積等 機械研磨方 與水平連線 材料本身與 可能略有改 技術的成熟 到。這也時 技術突破技 在上述 充技術，在 相沈積完成 料，但在材 意，仍為積 选度增加及绝命@ #，線見交小的同時，其電流密度也因 進導致許多金屬連線上的問題。例如：電 導致气空洞形成（Stress Induced void 金寺的方正：為二些'靠度的問題，使得化 屬鎢之化學H =疋取代目前-般所使用 如々π風*氣相沈積（W —CVD )的最好選擇0 充與金屬連層介層洞及下層 圖#冓=去可以取代傳統的電漿蝕刻方法，完 :(即；：去的製程是先以傳統的乾蝕刻技 二法，埴直導體用）及連線的溝漕，再以化學 式，得到ί :且隔層’銅的薄膜材料，最後則以 。以金屬化的表面，同時完成導體的垂直 嫣、=屬械研磨的技術而言，銅 ，在：ίϊΐ本身及參數控制都是相近。因此 m # ‘ At t -的研發人力與經費後即可以達 銅材料此成為未爽藉雕 術所在。巧禾來積歧電路連線應用的最主要 喪入法的另一 φ 孔洞與拾塞的導ΐ;:的ί點是導體金屬的填 。鎢金屬的電阻係數二疋以鎢金屬的化學氣 料有限（僅提呂合金與同材 體電路工業所使用屬：間的導線）下’雖不滿 ^ 使用。在雙鑲嵌構造法的導體水Field of the Invention: The present invention relates to a method for manufacturing a dual damascene, and more particularly to-a low-barrier layer obtained by dual-mass (Dual damascene) sub-etching. Of manufacturing method. Background of the Invention: In the past, the semiconductor process used sputtering as a wiring material, usually with smaller and smaller sputter lines. However, the higher the possibility of designing in 1C, = = the main is replaced by copper-the electrical conductivity is higher than aluminum: J 疋 aluminum-half, that is, it is a piece of copper conducting wire, but it has a low p The characteristics of the resistors are therefore arranged in a circuit with a small number of required metal layers, which can be greatly reduced; L; :: yes: a high premise is an ideal wiring material. The so-called metal reliability means that current will be generated during transmission. High: The phenomenon of "eler :: grati〇n)" the more the anti-electron migration, the higher the metal reliability, the more and more thin the design circuit in IC, the higher the technological evolution of metal materials, The more demanding the reliability of metal is, the higher the life and stability of copper-based components are. Since 989, the chemical vapor deposition method of metal copper has been widely studied like a spring rain. The main reason is that metallization (Metallization) becomes a key step when entering VLSi technology. V. Description of the invention (2) And when the component is increased, migration and stress Formation: Learn to vapor-deposit aluminum and gold Generally, the filling of metal contact windows is due to the technique of double copper metal. The mechanical polishing method and the horizontal connection materials such as plug vapor deposition have been completed. The technology itself may be slightly modified. At this time, the technical breakthrough technology is in the above-mentioned filling technology, and the material is deposited in the phase, but the material is still intact. Increasing the degree of selection and desperate life @ #, at the same time, the current density also causes many problems on the metal wiring due to the ingression. For example: Electricity causes the formation of air voids (Stress Induced void 'The problem of reliability makes chemical tungsten H = rhenium to replace the current-the best choice such as 々π wind * vapor deposition (W — CVD) 0 charge and metal interlayer vias and underlying layers # 冓 = Go can replace the traditional plasma etching method. End: (ie ;: The process of Go is to use the traditional dry etching technique two method to straighten the conductor) and the trench of the connection, and then use the chemical formula to get ί: And the interlayer 'copper' thin film material is based on the metallized surface, which simultaneously completes the vertical conductor of the conductor, and is a mechanical grinding technology. In terms of: copper itself and the parameter control are similar. Therefore m # 'At t- After a fee, the copper material can be reached. This is where the unsophisticated borrowing technique is located. Another major φ hole method of the Qiaohe Laiqi circuit connection application is the φ hole and the guide of the plug; The point of 是 is a conductive metal The specific resistance of tungsten metal is limited to that of tungsten chemical gas materials (only used in Tilu alloy and homogeneous body circuit industry: between the wires) under 'although unsatisfactory ^ used. In the dual mosaic construction method Conductor of water

第5頁 488028 五、發明說明（3) Z = S二1低電阻係數材料為主要考慮方向，因此銅與 :接、技術也就成為9 〇年代的主要研發·目標。化學 、、疑官》鈉料：都可呈現很好的覆蓋性及填充高的 屬材料:匕’但疋其隱含的雜質則遠大於濺鍍所得到的金Page 5 488028 V. Description of the invention (3) Z = S 2 1 Low-resistivity material is the main consideration, so copper connection and technology have become the main research and development goals in the 1990s. "Chemistry, suspect" sodium material: all can show good coverage and high filling of metal materials: dagger 'but its hidden impurities are much larger than the gold obtained by sputtering

於，i f ^上面所㉛’在積體電路設計線路越來越小，傳 =度二越快的要求下，以銅金屬代替紹的可U ΐ;要：：程的技術在將來的半導體製程技術中-定扮演 ,π * 、Λ色。不過在銅製程的雙鑲嵌構造法中蝕刻介声 洞時，阻障層（s · Ν、 Τ掷幻’丨智 程甚巨。（SlN)的知耗及殘留的多寡，影響飯刻製 錄士現有技術為了要增加S1 N阻障層的殘留’通當#用& 方法，第一種製程方法為在 射層（bare fill in).…時填入有機抗反 的 時，使用對Oxide/SiN之選擇—比(^方+法為在蝕刻介層洞 高選擇比姓刻程式。 擇比（SeleCtlVlty)大於12 有機方法：缺點·：若在1虫刻介層洞時，使用Therefore, if the above ^ 'in the integrated circuit design circuit is getting smaller and smaller, it is necessary to replace copper with copper metal under the requirement of faster and faster; To :: process technology in the future semiconductor process In the technology-fixed play, π *, Λ color. However, when the mesoacoustic cavity is etched in the dual-damascene construction method of the copper process, the barrier layer (s · N, Τ) is very large. The intellectual consumption and the amount of residual (SlN) affect the production of rice. In the prior art, in order to increase the residue of the S1 N barrier layer, the method is used. The first process method is to fill the organic anti-reflection when the layer is filled in .... / SiN selection-ratio (^ method + method is to select the engraving formula in the etching via hole height. Select ratio (SeleCtlVlty) is greater than 12 Organic method: Disadvantages :: If the engraving via hole is used in 1 insect, use

Fad Λ 果填入的深度控制不好丄ί acet的情況發生。而上述第_ 子合易有 刻介層洞時，使用對0xide/^方法的缺點係為：在钕 奋易k成製程的困難度。 發明的目的及概述：Fad Λ The depth of fruit filling is poorly controlled. 丄 acet occurs. When the above-mentioned ziziheyi has engraved via holes, the disadvantage of using the 0xide / ^ method is: the difficulty of the kneading process in Neodymium Fenyi. Purpose and summary of the invention:

層填入，即 刻製程的容 )，以簡單 作雙鑲嵌構造的方法，J:係 处淼方丨山 /、係不使用有機抗反射 月匕蝕刻出降低阻障層損耗之雙鑲嵌構造。 本發明之另一目的係在增加雙鑲嵌構造蝕 Umdow)及提高阻障層的殘留（remain 的製程克服習知之缺失。 為達到上述之目的，本發明所提出之方法，主要是在 雙鑲嵌構造的蝕刻製程中，使用最先接近介層洞（“a first approach )裡，蝕刻介層洞（via )至部分深度而 未接觸到阻障層（Barrier Layer )，繼而在溝槽蝕刻 (trench etch )時，直接在黃光製程種已定義的圖案 (p a 11 e r η )及對之前部分钱刻的介層洞，使用對阻障層 有較佳選擇比的程式進行蝕刻，以減少阻障層損耗，得到 一雙鑲嵌構造輪廓（Dual damascene profile)。 底下藉由具體實施例配合所附的圖式詳加說明，當更 容易暸解本創作之目的、技術内容、特點及其所達成之功 效0 圖號說明 • 10 矽基材 12 金屬層 14 第一阻障層 16 第一介電層 18 第二阻障層 20 第二介電層Layer filling, the capacity of the instant process), with a simple method of double mosaic structure, J: Department of Miaofang Fangshan /, does not use organic anti-reflection moon dagger to etch the dual mosaic structure to reduce the loss of the barrier layer. Another object of the present invention is to increase the dual-mosaic structure etching Umdow and increase the barrier layer residue (remain process) to overcome the lack of knowledge. In order to achieve the above purpose, the method proposed by the present invention is mainly in the dual-mosaic structure. In the etching process, the via hole is etched to a certain depth without touching the barrier layer in a "first approach", and then trench etch is used. ), Directly etch the defined pattern (pa 11 er η) in the yellow light process and the via hole engraved on the previous part of the money, and use a program with a better selection ratio of the barrier layer to etch to reduce the barrier layer. Loss to obtain a dual damascene profile. The detailed description below with specific examples and accompanying drawings will make it easier to understand the purpose, technical content, characteristics and effects of this creation. 0 Description of Drawing Numbers • 10 silicon substrate 12 metal layer 14 first barrier layer 16 first dielectric layer 18 second barrier layer 20 second dielectric layer

第7頁 488028Page 7 488028

22 第一光阻層 2 3 姓刻窗 2 4 介層洞 26殘餘之第一介電層 28第二光阻層 韻刻窗 3 2 溝槽 詳細說明： 本發明之貫施例提出的Η 並以部分钱刻得到低阻障種無有機抗反射層填入， 法。第-圖至第四圖所示心=鑲嵌構造之製造方 驟。 、’、9此钱刻方法的製程與步 上，圖，在一已形成有M0S元件之矽底材1。 理氣相沉積法士金屬層12，而後再利用物 声氮化石夕二氣相沈積法（cvd)，沉積-二-Λ 障層14，在第―阻障層14上再 ::層：玻璃⑴uorinated SiUcate Giass，fsg) 介電層16 ’然後於其上沉積一層氮氧化石夕（si〇n )的弟二阻障層18，箆-阻陸屛18 μ $ “ ⑽）作為第二介電層:8上再次沉積-層氣玻璃 2二介電層20之表面塗佈—層第—光阻層22，並利 顯影姓刻技術形成圖案化之第一光阻層22，其係具 有季乂小尺寸之蝕刻窗23，以定義出所要蝕刻的介層洞大 五、發明說明（6) 小 〇 刻介層洞24，如第：^二大小後’使用現有姓刻技術，姓 罩，罐除丄:以出：光阻層22為幕 層18，至第一介電層16之一-"電層20、弟二阻障 層14，使介層洞24底部存;_ =度而未接觸到該第一阻障 -丨存在有殘餘之第—介雷屏？ A ·為方，丨 介層洞24至部分深度而未 B x 為了減少第-阻障層弟—阻障層14，此目的是 漿⑽Plasma)钱刻移的除\Hs)。接下來利用氧電 當第-光阻層2;去除= ^ # . on . ^ 舌除凡成後，如第三圖所示，在第二 之二^ = f 一圖案化之第二光阻層28，其#刻窗3〇 尺+、，9、；刖所定義的該第一光阻層22之蝕刻窗23之 蝕列、盖：沾備作接下來的蝕刻製程之幕罩，以定義出所要 蝕刻溝槽的大小。 ’文 程是=化ί二光阻層28纖，接下來進行的姓刻製 - 一光阻層28為幕罩進行溝槽蝕刻，如第四圖所 « ^ t介電層/阻障層的選擇比高之程式進行独刻，以 雷：9β蝕刻囪30露出之該第二介電層20及殘留之該第-介 : 以$成溝槽3 2結構並完成介層洞2 4，其中，當蝕 以可腺楚阻P早層丨4時’由於介電層/阻障層的選擇比高所 " 介電層1 6完全消耗掉，而僅蝕刻些微之第一阻 = ^14 ;因此當第二介電層2〇被蝕刻完後，會停留在第二 質早a 士上★’也是利用介電層/阻障層之高選擇比的性 、 此^ ’第一阻障層1 4雖也同時被蝕刻，但仍會有大部22 First photoresist layer 2 3 Named engraved window 2 4 Via hole 26 Residual first dielectric layer 28 Second photoresist layer engraved window 3 2 Trench detailed description: Part of the money is engraved to obtain a low barrier type non-organic anti-reflection layer. Figure-Figure 4 to Figure 4 show the manufacturing process of the mosaic structure. In the process and steps of this method, the figure shows a silicon substrate 1 on which a MOS element has been formed. The vapor-deposited French metal layer 12 is then vapor-deposited using a material acoustic nitride CVD method to deposit a -II-Λ barrier layer 14 on top of the barrier layer 14 :: layer: glass ⑴uorinated SiUcate Giass (fsg) dielectric layer 16 ′, and then deposited thereon a second barrier layer 18 of nitrogen oxide SiO 2, 箆 -blocking 屛 18 μ $ "⑽" as the second dielectric layer Depositioned on 8: -Layered gas glass 2-Dielectric layer 20 is coated on the surface-layer-photoresist layer 22, and the first photoresist layer 22 is patterned by the development technique. Etching window 23 of small size to define the via hole to be etched. V. Description of the invention (6) Small etched via hole 24, such as: ^ After the second size, use the existing surname engraving technology, surname mask, can In addition to: Take out: photoresist layer 22 as the curtain layer 18, to one of the first dielectric layer 16-"electrical layer 20, the second barrier layer 14, so that the bottom of the dielectric hole 24 exists; _ = degree and The first barrier is not touched-there is a residual first-media lightning screen? A · is square, the via hole 24 to a partial depth is not B x In order to reduce the first barrier layer brother-barrier layer 14 ,this The purpose is to remove the engraved Plasma) money. \ Hs). Next use oxygen electricity as the first photoresist layer 2; remove = ^ #. On. ^ After the tongue is removed, as shown in the third figure, Two bis == f A patterned second photoresist layer 28, the #etch window 30 ft. + ,, 9 ,; etch line and cover of the etching window 23 of the first photoresist layer 22 as defined by 刖: Used as a curtain cover for the next etching process to define the size of the trench to be etched. 'The text is = two light-resistant layers of 28 fibers, and the next name is engraved-a light-resistant layer 28 Trench etching is performed for the curtain, and the second dielectric layer 20 and the exposed second dielectric layer 20 and Residual of the first-dielectric: the formation of the trench 3 2 structure and the completion of the interlayer hole 2 4, in which, when the etch resists the early P layer 4, it is due to the selection ratio of the dielectric layer / barrier layer Gaosuo's dielectric layer 16 is completely consumed, and only a slight first resistance is etched = ^ 14; therefore, after the second dielectric layer 20 is etched, it will stay on the second substrate. 'Also a high choice for using dielectric / barrier layers Selectivity, although the first barrier layer 14 is also etched at the same time, there will still be most

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分之第一阻障層1 4殘留 yu r±L 層28，即可得到一雙鑲和η最後再移除第 苴 、、，碾瓜構造輪廓（prof i le )，。 破璃’:FSG )上封述質之所V/去電層16及第二介電層20除了為敦 機之低介電常數的^ 障層18之材料係可€自碳“:弟一阻障層^及第二阻 氮氧化石夕⑶⑽）或1它n :J lC)、氮化矽（SiN)、 ^ 4具匕冋性質之阻障層材料。 本發明之實施例雖以第一 說明，作針於第- Μ人μ , 層（1 )作為範例 對於弟一層介層洞（V i a 2 )塑紹β穿一莊人 ，以致第三層 =二：層介層洞 來解決。 ^ I ;1層，冋製程皆可使用本發明 以 本發明 神下所 申請專 上所述僅為本發 之申請專利範圍 完成之等效改變 利範圍内。 明之較佳實例而 •’凡其他未脫離 或修飾，均應包 已，並非用以限定 本發明所揭示之精 含在本發明所請之 488028 圖式簡單說明 圖式說明： 第一圖至第四圖為本發明之方法的連續製程示意圖。The first barrier layer 14 is left with the yu r ± L layer 28, and a pair of mosaics and η can be obtained. Finally, the 第,, and profiling structures (prof i le) are removed. Broken glass :: FSG) The material of the V / deactivation layer 16 and the second dielectric layer 20 on the substrate is a low dielectric constant ^ The material of the barrier layer 18 can be made from carbon ": Siyi The barrier layer ^ and the second nitrogen-blocking oxidized stone (2) (or Zn: J1C), silicon nitride (SiN), and 4 barrier layer materials having dagger properties. Although the embodiment of the present invention is One explanation is that for the first -M person μ, layer (1) is used as an example. For the first layer of interstitial holes (Via 2), plastic β passes through a village, so that the third layer = two: interstitial holes. ^ I; 1 layer, the process can be used in the present invention within the scope of equivalent changes in the scope of the patent application issued by the God of the present invention, which is completed only by the scope of the patent application. Others that have not deviated or modified should be included, and are not intended to limit the essence disclosed in the present invention to the 488028 requested by the present invention. Brief description of the illustrations: The first to fourth figures are the methods of the present invention. Schematic of continuous process.

Claims (1)

488028 六、申請專利範圍 1. 一種以部 方法，其 在一已形 上依序 及第二 在該第二 所要蝕 以該第一 障層， 障層， 再於該第 溝槽尺 以該第二 障層的 第二介 及第一 2. 如申請專 係為銅金 3. 如申請專 係為鶴金 4. 如申請專 為各種有 5. 如申請專 一阻障層 分蝕刻得到低阻障層損耗的雙鑲嵌構造之製造 係包括下列步驟： ’ 成有M0S元件之底材上形成一金屬層後，於其 形成有第一阻障層、第一介電層、第二阻障層 介電層； 介電層上形成一圖案化第一光阻層，以定義出 刻的介層洞大小； 光阻層為幕罩，蝕刻去除第二介電層、第二阻 至第一介電層之部分深度而未接觸到該第一阻 而後移除該第一光阻層； 二介電層上形成圖案化第二光阻層，以定義出 寸，其尺寸大小係大於該介層洞；以及 光阻層為幕罩進行溝槽蝕刻，利用介電層/阻 選擇比高之程式進行蝕刻，蝕刻去除露出之該 電層及殘留之該第一介電層，直至第二阻障層 阻障層露出為止，以得到一雙鑲嵌構造輪廓。 利範圍第1項所述之製造方法，其中該金屬層 屬。 利範圍第1項所述之製造方法，其中該金屬層 屬。 利範圍第1項所述之製造方法，其中該介電層 機及無機之低介電常數的介電材料。 利範圍第1項所述之製造方法，其中形成該第 、第一介電層、第二阻障層及第二介電層之方488028 VI. Scope of patent application 1. A method based on the first method, which sequentially and firstly etches the first barrier layer, the barrier layer on the second, and then the second trench ruler uses the first barrier layer. The second introduction of the second barrier layer and the first 2. If the application is specifically for copper and gold 3. If the application is specifically for crane gold 4. If the application is specifically for various types 5. If the application is for a single barrier layer, the etching will get low barrier The manufacturing system of the layer-loss dual damascene structure includes the following steps: 'After forming a metal layer on the substrate with the MOS device, a first barrier layer, a first dielectric layer, and a second barrier layer are formed on the substrate. Electrical layer; a patterned first photoresist layer is formed on the dielectric layer to define the size of the etched dielectric layer; the photoresist layer is a screen cover, and the second dielectric layer is etched to remove the second resist to the first dielectric layer Part of the layer without touching the first resist and then removing the first photoresist layer; forming a patterned second photoresist layer on the two dielectric layers to define an inch, the size of which is larger than the hole of the dielectric layer ; And the photoresist layer is used to etch the trench for the mask, and the program with a high dielectric layer / resistance selection ratio is used. The etch layer is etched and removed to expose the remaining of the first dielectric layer, a second barrier layer until the barrier layer is exposed, to obtain a mosaic structure one pair of contours. The manufacturing method according to claim 1, wherein the metal layer is a metal layer. The manufacturing method according to claim 1, wherein the metal layer is a metal layer. The manufacturing method according to claim 1, wherein the dielectric layer and the inorganic low-dielectric constant dielectric material. The manufacturing method according to item 1 of the utility model, wherein the method of forming the first, the first dielectric layer, the second barrier layer, and the second dielectric layer is formed. 第12頁 488028 六、申請專利範圍 法係選自化學氣相沈積法及物理氣相沈積法其中之一 6.如申請專利範圍第1項所述之製造方法，其中該第一阻 障層及第二阻障層之材料係選自碳化矽（S i C )、氮化 矽（S i N )、氮氧化矽（S i 0N )或其它阻障層材料。 $ #Page 12 488028 6. The method of applying for patent scope is selected from one of chemical vapor deposition method and physical vapor deposition method 6. The manufacturing method described in item 1 of the scope of patent application, wherein the first barrier layer and The material of the second barrier layer is selected from silicon carbide (S i C), silicon nitride (S i N), silicon oxynitride (S i 0N) or other barrier layer materials. $ # 第13頁Page 13