484226 A7 5762twf.doc/006 _________B7____ 五、發明說明（(） (請先閱讀背面之注意事項再填寫本頁) 本發明是有關於一種靜電放電（Electrical Static Discharge ;以下簡稱ESD)保護電路，且特別是有關於一種 在靜電發生時，可均勻開啓複晶矽閘極以釋放靜電，有效 增強ESD防護效能之積體電路之靜電放電保護電路。 在積體電路(1C)例如動態隨機存取記憶體(DRAM)、靜 態隨機存取記憶體（SRAM)的製造過程中或是晶片完成 後，靜電放電事件常是導致積體電路損壞的主要原因。例 如在地毯上行走的人體，於相對濕度（RH)較高的情況下可 檢測出約帶有幾百至幾千伏的靜態電壓，而於相對濕度較 低的情況下則可檢測出約帶有一萬伏以上的靜態電壓。當 這些帶電體接觸到晶片時，將會向晶片放電，結果有可能 造成晶片失效。於是，爲了避免靜電放電損傷晶片，各種 防制靜電放電的方法便因應而生。最常見的習知作法是利 用硬體防制靜電放電，也就是在內部電路(Internal Ciixint) 與每一焊墊（Pad)間，均設計一晶片嵌入式（Οη-CMp)的靜電 放電保護電路以保護其內部電路。 經濟部智慧財產局員工消費合作社印製 再者，由於聞極氧化層之形成厚度會隨著製程積集度 增加而縮小，使得閘極氧化層的崩潰電壓將逐步過近源極/ 汲極接面崩潰電壓，甚或更低，此時原來的ESD保護電路 設計效能將大打折扣。此外，內部電路多半依循最小設計 準則（Minimum Design Rules)g曼計’且未適當地设日十（例如接 觸窗到擴散區的邊緣以及接觸窗到閘極邊緣均需要足夠的 空間）以抵抗巨大的靜電放電暫態電流（Transient Cuirent) ’ 致使在高積集度的情況下，晶片極容易受到靜電放電的損 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484226 5 762twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 害。所以，靜電放電的問題已成爲深次微米積體電路故障 的原因之一，故如何有效提昇靜電放電保護電路的效能乃 爲目前業界所亟盼的。 請參照第1圖，第1圖繪示的是習知一種ESD保護電 路的佈局俯視圖。 如第1圖所示，其主要係在一 P型基底10之適當位 置上分設有數個N+源極12,並在N+源極12左右位置分別 對稱設有數個N+汲極14，且N+源極12與其兩側之N+汲 極14上方分別均設有數個接觸區16a與16b，用以分別連 接至接地電壓之端點及供輸入訊號之輸入端點。此外，在 介於每一 N+源極12接觸區16a與兩側N+汲極14接觸區 16b間分設有複晶矽閘極(p〇iy gate)i8，其中在複晶矽閘極 18上方設有數個接觸區16c，以便使對應於每一 n+源極12 胃個J分別形成兩組防靜電保護電路。 請參照第2圖與第3圖，第2圖繪示的是在第1圖之 ESD保護電路中增加了第一金屬層20a、20b與第二金屬層 22a、22b的佈局俯視圖，以及第3圖繪示的是第2圖之A-A， 橫切面的剖面圖。 在第2圖中，第一金屬層20a以指叉狀延伸連接至N+ 汲極14上之接觸區161}，而第一金屬層2〇b亦以指叉狀延 伸連接至N +源極π上之接觸區16a與複晶矽閘極18上之 接觸區16C，此時如圖所示，第一金屬層2〇a與第一金屬層 2〇b兩者呈指叉交錯狀。第二金屬層22a設置於第一金屬層 20a上方’而第二金屬層22b以指叉狀延伸至對應接觸區484226 A7 5762twf.doc / 006 _________B7____ 5. Description of the invention (() (Please read the precautions on the back before filling out this page) The present invention relates to an electrostatic discharge (ESD) protection circuit, and is particularly The invention relates to an electrostatic discharge protection circuit of a integrated circuit which can uniformly turn on a polycrystalline silicon gate to release static electricity when static electricity occurs, which effectively enhances ESD protection performance. In integrated circuit (1C) such as dynamic random access memory (DRAM), static random access memory (SRAM) during the manufacturing process or after the wafer is completed, electrostatic discharge events are often the main cause of damage to integrated circuits. For example, a human walking on a carpet, relative humidity (RH) ) Higher conditions can detect static voltages of about several hundred to several thousand volts, while lower relative humidity can detect static voltages of about 10,000 volts or more. When these charged bodies When contacting the wafer, it will discharge to the wafer, which may cause the wafer to fail. Therefore, in order to prevent the electrostatic discharge from damaging the wafer, various anti-static discharges are prevented. The corresponding method was born. The most common practice is to use hardware to prevent electrostatic discharge, that is, to design a chip embedded between the internal circuit (Internal Ciixint) and each pad (0η- CMp) ESD protection circuit to protect its internal circuit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Furthermore, the thickness of the oxide layer will decrease as the process accumulation increases, making the gate oxide layer The breakdown voltage will gradually exceed the breakdown voltage near the source / drain interface, or even lower. At this time, the original ESD protection circuit design efficiency will be greatly reduced. In addition, the internal circuits mostly follow the Minimum Design Rules. It is not properly set (for example, the contact window to the edge of the diffusion area and the contact window to the gate edge need sufficient space) to resist the huge electrostatic discharge transient current (Transient Cuirent), resulting in high accumulation In the case of wafers, the wafer is extremely susceptible to damage from electrostatic discharge. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 484226 5 762twf. doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Disclosure of Inventions (2). Therefore, the problem of electrostatic discharge has become one of the reasons for the failure of deep sub-micron integrated circuits, so how to effectively promote electrostatic discharge The efficiency of the protection circuit is currently urgently expected by the industry. Please refer to FIG. 1. FIG. 1 shows a top view of a conventional ESD protection circuit layout. As shown in FIG. 1, it is mainly a P-type circuit. Several N + source electrodes 12 are arranged at appropriate positions on the substrate 10, and several N + drain electrodes 14 are symmetrically arranged at the left and right positions of the N + source electrode 12, and the N + source electrode 12 and the N + drain electrodes 14 on both sides thereof are respectively disposed above There are several contact areas 16a and 16b for connecting to the terminal of the ground voltage and the input terminal of the input signal, respectively. In addition, a polycrystalline silicon gate (i8) is provided between each of the N + source 12 contact regions 16a and the N + drain 14 contact regions 16b on both sides, and above the polycrystalline silicon gate 18 A plurality of contact areas 16c are provided so as to form two sets of anti-static protection circuits corresponding to each of the n + source electrodes 12 and J respectively. Please refer to FIG. 2 and FIG. 3. FIG. 2 shows a layout plan view in which the first metal layers 20a, 20b and the second metal layers 22a, 22b are added to the ESD protection circuit in FIG. 1, and FIG. The drawing shows a cross-sectional view of AA in FIG. 2. In FIG. 2, the first metal layer 20 a is connected to the contact region 161} on the N + drain 14 in a finger-like extension, and the first metal layer 20 b is also connected to the N + source π in a finger-like extension. The contact region 16a on the top and the contact region 16C on the polycrystalline silicon gate 18, as shown in the figure, both the first metal layer 20a and the first metal layer 20b are interdigitated. The second metal layer 22a is disposed above the first metal layer 20a 'and the second metal layer 22b extends in a finger-like manner to the corresponding contact area
(請先閱讀背面之注音？事 d. -項再填 裝------ 寫本頁) 訂— 484226 A7 5762twf.doc/006 _______B7___ 五、發明說明（） 16b位置之N+汲極14上方，並透過介層窗插塞24連接至 第一金屬層20a。 依照第2圖之佈局結構，當靜電經由一輸出入焊墊（未 顯示）流至第二金屬層22a進入時，此靜電將會經由指叉狀 佈置之第一金屬層20a進入N+汲極區14中。另一方面’ 在第2圖中，標號26a與26b代表第一金屬層20a重疊於 複晶矽閘極18的區域。由於重疊部分26a與26b所涵蓋的 範圍很小，因此當靜電發生時，將會造成低閘極耦合率的 問題，換言之，這將使得每一複晶矽閘極18無法被均勻開 啓以釋放靜電，而此一現象勢必將影響並降低ESD保護電 路之防靜電效果。 有鑒於此，本發明提出一種積體電路之靜電放電保護 電路，包括基底、數個源極、數個汲極、複晶矽閘極、第 一金屬層與第二金屬層。上述源極位於基底上’且各源極 上方設置有數個第一接觸區，以連接至接地電壓。汲極位 於基底上，各汲極分別對稱設置在各源極之兩側位置上， 使汲極與源極呈指叉交錯狀，且各汲極上方設有數個第二 接觸區，以連接至輸入端點。複晶矽閘極設置於各源極上 之第一接觸區與其兩側各汲極上之第二接觸區間，並且複 晶矽閘極整個延伸至輸出入焊墊所在的區域上。第一金屬 層設置於對應輸出入焊墊之複晶矽閘極上方’且第一金屬 層延伸至各汲極上方，並且覆蓋各汲極兩側之複晶矽閘 極。以及，第二金屬層設置於第一金屬層上方。 本發明提出之積體電路之靜電放電保護電路，由於第 1本紙張尺度家標準（CNS)A4規格（210 X 297公釐） ------^------裝--------訂---------^9. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 484226 5762twf.doc/006 ^ _B7_ 五、發明說明（¥) (請先閱讀背面之注意事項再填寫本頁) 一金屬層覆蓋複晶矽閘極之重疊部分所涵蓋的範圍很大 (幾乎達到100%)，如此將會有高閘極耦合率的效果，因此 當靜電發生時，將可使複晶矽閘極被均勻開啓以釋放靜 電，達到增強ESD保護電路之靜電防護效能的目的，再者， 依照本發明之佈局結構，也不會增加任何額外的佈局面 積。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖繪示的是習知一種ESD保護電路的佈局俯視 圖， 第2圖繪示的是在第1圖之ESD保護電路中增加了第 一金屬層20a、20b與第二金屬層22a、22b的佈局俯視圖； 第3圖繪示的是第2圖之A-A’橫切面的剖面圖；(Please read the Zhuyin on the back? Matter d.-Item and then fill in this page ------ Write this page) Order — 484226 A7 5762twf.doc / 006 _______B7___ 5. Description of the invention () N + Drain at position 16b above 14 And is connected to the first metal layer 20a through the via window plug 24. According to the layout structure of FIG. 2, when static electricity flows into the second metal layer 22 a through an input / output pad (not shown), the static electricity will enter the N + drain region through the first metal layer 20 a arranged in a finger-shaped arrangement. 14 in. On the other hand, in Fig. 2, reference numerals 26a and 26b denote regions where the first metal layer 20a overlaps the polycrystalline silicon gate 18. Since the overlapping areas 26a and 26b cover a small area, when the static electricity occurs, a problem of low gate coupling rate will be caused. In other words, this will prevent each of the multi-crystal silicon gates 18 from being opened uniformly to discharge static electricity. , And this phenomenon is bound to affect and reduce the anti-static effect of the ESD protection circuit. In view of this, the present invention provides an integrated circuit electrostatic discharge protection circuit including a substrate, a plurality of sources, a plurality of drains, a polycrystalline silicon gate, a first metal layer and a second metal layer. The above-mentioned sources are located on the substrate 'and a plurality of first contact regions are provided above each source to be connected to the ground voltage. The drain electrodes are located on the substrate, and each drain electrode is symmetrically arranged on both sides of each source electrode, so that the drain electrode and the source electrode are interdigitated, and a plurality of second contact areas are provided above each drain electrode to connect to Enter the endpoint. The polycrystalline silicon gate is disposed in a first contact region on each source and a second contact section on each of the drain electrodes on both sides, and the polycrystalline silicon gate extends entirely to the area where the input / output pads are located. The first metal layer is disposed above the polycrystalline silicon gate corresponding to the I / O pad, and the first metal layer extends above each drain electrode and covers the polycrystalline silicon gate on both sides of each drain electrode. And, the second metal layer is disposed above the first metal layer. The electrostatic discharge protection circuit of the integrated circuit proposed by the present invention, because of the first paper size home standard (CNS) A4 specification (210 X 297 mm) ------ ^ ------ install --- ----- Order --------- ^ 9. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 484226 5762twf.doc / 006 ^ _B7_ 5 2. Description of the invention (¥) (Please read the precautions on the back before filling out this page) A metal layer covering the overlapped area of the polycrystalline silicon gate covers a large area (almost 100%), so there will be a high gate Effect of the coupling ratio, so when static electricity occurs, the polycrystalline silicon gate can be opened uniformly to discharge static electricity, to achieve the purpose of enhancing the electrostatic protection performance of the ESD protection circuit. Furthermore, according to the layout structure of the present invention, No additional layout area is added. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1 FIG. 2 shows a layout top view of a conventional ESD protection circuit, and FIG. 2 shows a layout top view in which first metal layers 20a, 20b and second metal layers 22a, 22b are added to the ESD protection circuit of FIG. 1; Figure 3 shows a cross-sectional view of the AA 'cross section of Figure 2;
第4圖繪示的是依照本發明一較佳實施例的一種ESD 保護電路的佈局俯視圖； 經濟部智慧財產局員工消費合作社印製 第5圖繪示的是在第4圖之ESD保護電路中增加了第 一金屬層20a、20b與第二金屬層22a、22b的佈局俯視圖； 以及 第6圖繪示的是第5圖之B-B’橫切面的剖面圖。 圖式之標號說明_· 10、40 : P型基底 12、42 : N+源極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484226 5 762twf.doc/006 ______B7 _ 五、發明說明（又） 14、44 ·· N+汲極 16a、16b、16c、46a、46b :接觸區 (請先閱讀背面之注意事項再填寫本頁) 18、48 :複晶矽閘極 20a、20b、50a、50b :第一金屬層 22a、22b、52a、52b :第二金屬層 24、54 :介層窗插塞 26a、26b、58 ··重疊部分 56 :氧化層 實施例 請參照第4圖，其繪示的是依照本發明一較佳實施例 的一種ESD保護電路的佈局俯視圖。 經濟部智慧財產局員工消費合作社印製 如第4圖所示，本發明係在一 P型基底40之適當位 置上分設有數個N+源極42,並在N+源極42左右位置分別 對稱設有數個N+汲極44，且N+源極42與其兩側之N+汲 極44上方分別均設有數個接觸區46a與46b，用以分別連 接至接地電壓之端點及供輸入訊號之輸入端點。此外’在 介於每一 N +源極42接觸區46a與兩側N+汲極44接觸區 46b間分設有複晶矽閘極48,以便使對應於每一 N+源極42 兩側分別形成兩組防靜電保護電路。値得注意的是’所設 置之複晶矽閘極48整個延伸至輸出入焊墊（未顯示）所在的 區域上，如第4圖所示。 請參照第5圖與第6圖，第5圖繪示的是在第4圖之 ESD保護電路中增加了第一金屬層50a、50b與第二金屬層 52a、52b的佈局俯視圖，以及第6圖繪不的是第5圖之B-B’ 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 484226 5762twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（<) 橫切面的剖面圖。 在第5圖中，第一金屬層50a設置於對應輸出入焊墊 (未顯示）位置之複晶矽閘極48上方，且第一金屬層50a延 伸至每一 N +汲極44上方，並且覆蓋每一 N+汲極44兩側 之複晶矽閘極48，使得第一金屬層50a幾乎覆蓋複晶矽閘 極48達到100%。第一金屬層50b以指叉狀延伸連接至N+ 源極42上之接觸區46a。第二金屬層52a設置於第一金屬 層50a上方，而第二金屬層52b以指叉狀延伸至對應接觸 區46b位置之N+汲極44上方，並透過介層窗插塞54連接 至第一金屬層50a，其中第二金屬層52b也連接至一內部電 路（未顯示沖。此外，如第6圖所示，在複晶砍閘極48與 第一金屬層50a間設置有一層氧化層56 ’使其相當於一耦 合電容器。 依照第5圖之佈局結構，當靜電經由一輸出入焊墊（未 顯示）流至第二金屬層52a進入時，此靜電將會經由第一金 屬層50a進入N+汲極區44中。另一方面，在第5圖中’ 標號58代表第一金屬層50a重疊於複晶矽閘極48的區域。 由於重疊部分58所涵蓋的範圍很大（如上所述，第一金屬 層50a覆蓋複晶矽閘極48幾乎達到100%)，如此將會有高 閘極耦合率的效果，因此當靜電發生時，將可使每一複晶 矽閘極48被均勻開啓以釋放靜電，增強ESD保護電路之 靜電防護效能。而且，依照本發明之佈局結構，並不會增 加任何額外的佈局面積。 必須注意的是，在上述本發明實施例中，係以P型基 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂---- #· 484226 5762twf.doc/006 五、發明說明（7 ) 底（用以形成NMOS電晶體）爲例，當然也可以使用N型基 底（用以形成PMOS電晶體）。換言之，可以N型基底取代P 型基底，以P型源極取代N型源極，以P型汲極取代N型 汲極。 綜上所述，依照本發明之積體電路之靜電放電保護電 路，具有以下的優點： (1) 第一金屬層50a覆蓋複晶矽閘極48的重疊部分幾 乎達到100%，由於高閘極耦合率的效果，故在靜電發生的 情況下，將可使複晶矽閘極48被均勻開啓以釋放靜電，有 效增強ESD保護電路之靜電防護效能。 (2) 不會增加任何額外的佈局面積。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ------------—.AW- --------訂·----I--- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Figure 4 shows a top view of the layout of an ESD protection circuit according to a preferred embodiment of the present invention; printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs; Figure 5 shows the ESD protection circuit in Figure 4; Added layout top views of the first metal layers 20a, 20b and the second metal layers 22a, 22b; and FIG. 6 shows a cross-sectional view of the BB ′ cross section of FIG. 5. Explanation of the symbols of the drawings _ · 10, 40: P-type substrate 12, 42: N + source This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 484226 5 762twf.doc / 006 ______B7 _ 5 、 Explanation of the invention (again) 14, 44 ·· N + drains 16a, 16b, 16c, 46a, 46b: contact area (please read the precautions on the back before filling this page) 18, 48: polycrystalline silicon gate 20a, 20b, 50a, 50b: first metal layers 22a, 22b, 52a, 52b: second metal layers 24, 54: interlayer window plugs 26a, 26b, 58 · overlapping part 56: oxide layer embodiment, please refer to Section 4 FIG. Is a top view of a layout of an ESD protection circuit according to a preferred embodiment of the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as shown in FIG. 4, the present invention is provided with a plurality of N + source electrodes 42 at appropriate positions on a P-type substrate 40, and is symmetrically arranged at the left and right positions of the N + source electrode 42 respectively. There are several N + drains 44, and there are several contact areas 46a and 46b above the N + source 42 and the N + drain 44 on both sides, respectively, for connecting to the terminal of the ground voltage and the input terminal of the input signal . In addition, a polycrystalline silicon gate 48 is provided between each N + source 42 contact region 46a and the N + drain 44 contact region 46b on both sides, so that two sides corresponding to each N + source 42 are formed respectively. Two sets of anti-static protection circuits. It should be noted that the multiplexed silicon gate 48 is extended to the area where the input / output pads (not shown) are located, as shown in FIG. 4. Please refer to FIG. 5 and FIG. 6. FIG. 5 shows a layout plan view in which the first metal layers 50a, 50b and the second metal layers 52a, 52b are added to the ESD protection circuit in FIG. 4, and FIG. What is not shown in Figure 5 is B-B'7. This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 484226 5762twf.doc / 006 A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs System V. Description of the invention (&); In FIG. 5, the first metal layer 50 a is disposed above the polycrystalline silicon gate 48 corresponding to the position of the I / O pad (not shown), and the first metal layer 50 a extends above each N + drain 44, and The polycrystalline silicon gates 48 covering both sides of each N + drain 44 make the first metal layer 50a almost cover the polycrystalline silicon gates 48 to 100%. The first metal layer 50b is connected to the contact region 46a on the N + source electrode 42 in an interdigitated manner. The second metal layer 52a is disposed above the first metal layer 50a, and the second metal layer 52b extends in a finger-like manner over the N + drain 44 corresponding to the position of the contact area 46b, and is connected to the first through the via window plug 54 A metal layer 50a, in which the second metal layer 52b is also connected to an internal circuit (not shown). In addition, as shown in FIG. 6, an oxide layer 56 is provided between the polycrystalline gate 48 and the first metal layer 50a. 'Make it equivalent to a coupling capacitor. According to the layout structure of Fig. 5, when static electricity flows in through an input / output pad (not shown) to the second metal layer 52a, the static electricity will enter through the first metal layer 50a. N + drain region 44. On the other hand, in FIG. 5, the reference numeral 58 represents a region where the first metal layer 50a overlaps the polycrystalline silicon gate 48. Since the overlapping portion 58 covers a large area (as described above) , The first metal layer 50a covers the polycrystalline silicon gate 48 to almost 100%). This will have the effect of high gate coupling rate. Therefore, when static electricity occurs, each polycrystalline silicon gate 48 will be uniformed. Turn on to discharge static electricity and enhance the electrostatic protection effect of ESD protection circuit In addition, according to the layout structure of the present invention, it does not increase any additional layout area. It must be noted that in the above-mentioned embodiments of the present invention, the P-type base 8 paper size is applicable to the Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) Binding ---- Order ---- # · 484226 5762twf.doc / 006 V. Description of the invention (7) Bottom (for Forming an NMOS transistor) as an example, of course, an N-type substrate (for forming a PMOS transistor) can also be used. In other words, an N-type substrate can be used instead of a P-type substrate, a P-type source can be used to replace an N-type source, and a P-type drain Electrode to replace the N-type drain electrode. In summary, the electrostatic discharge protection circuit of the integrated circuit according to the present invention has the following advantages: (1) The overlapping portion of the first metal layer 50a covering the polycrystalline silicon gate electrode 48 almost reaches 100%, due to the effect of high gate coupling rate, in the case of static electricity, the polycrystalline silicon gate 48 can be opened uniformly to discharge static electricity, which effectively enhances the electrostatic protection performance of the ESD protection circuit. (2) No Will add any additional layout area. Although The invention has been disclosed in the preferred embodiment as above, but it is not intended to limit the invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the invention, so the protection of the invention The scope shall be determined by the scope of the attached patent application. ------------—. AW- -------- Order · ---- I --- ( Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm)