TW483109B

TW483109B - Method for forming dual damascene structure

Info

Publication number: TW483109B
Application number: TW90112146A
Authority: TW
Inventors: Shiue-Jung Chen; Teng-Chiun Tsai; Yi-Min Huang
Original assignee: United Microelectronics Corp
Priority date: 2001-05-21
Filing date: 2001-05-21
Publication date: 2002-04-11

Abstract

The present invention discloses a method for forming dual damascene structure. The method comprises the steps of: first, providing a substrate; then, forming a first low-k dielectric layer on the substrate; next, forming a second low-k dielectric layer on the first low-k dielectric layer; next, removing part of the second low-k dielectric layer and first low-k dielectric layer to form a first via in the first low-k dielectric layer; then, removing part of the second low-k dielectric layer to form a second via in the second low-k dielectric layer and communicating to the first via; next, forming a conductive layer to be filled in the first via and second via; next, removing the second low-k dielectric layer; and finally forming a low-k dielectric layer on the first low-k dielectric layer to expose the conductive layer.

Description

483109 五、發明說明（1) 5 - 1發明領域：本發明係有關於一種形成一雙鑲後結構的方法，特別是有關於一種在在銅/低介電材料製程中形成一雙鑲嵌結構的方法。 5 - 2發明背景：在超大型積體電路（VLSI)與極大型積體電路（ULSI )的在雙鑲嵌製程中，半導體元件中的絕緣或介電物質，如氧化矽，被轉移圖案而形成數千個開口以作為導電線和介層洞開口填入金屬物質，例如鋁，用作積體電路中主動元件或被動元件的内連線。然而，雙鑲嵌製程也被用來在半導體元件上形成多重金屬内連線，如金屬銅，而多層的絕緣層，如聚醯亞胺（ρ ο 1 y i m i d e)。鑲欲（damascene)程序是一種内連線的製造程序，用來在絕緣層上形成溝洞（groove)再填入金屬以形成導電線（conductive lines)。而雙鑲欲程序則是一多重金屬内連線的製造程序，除了如同在鑲嵌程序中所形成的溝洞外，也同時形成介層洞開口。在一般雙鑲嵌製程中，首先，在絕緣層上塗上一的光阻材料。此光阻材料係具所需介層洞開口圖案並暴露出一第一遮罩層。接著’以非等相钱483109 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for forming a double damascene structure, in particular to a method for forming a double damascene structure in a copper / low dielectric material manufacturing process. method. 5-2 Background of the Invention: In the dual damascene process of very large scale integrated circuits (VLSI) and very large scale integrated circuits (ULSI), the insulating or dielectric substances in the semiconductor elements, such as silicon oxide, are formed by transferring patterns. Thousands of openings are used as conductive lines and via openings filled with metal materials, such as aluminum, for use as interconnects of active or passive components in integrated circuits. However, the dual damascene process is also used to form multiple metal interconnects on semiconductor devices, such as copper metal, and multiple layers of insulation, such as polyimide (ρ ο 1 y i m i d e). The damascene process is a manufacturing process for interconnects, which is used to form grooves in the insulating layer and then fill the metal to form conductive lines. The double damascene process is a multi-metal interconnect manufacturing process. In addition to the trenches formed in the damascene process, interstitial hole openings are also formed. In a general dual damascene process, first, a photoresist material is coated on the insulating layer. The photoresist material has a desired opening pattern of the interposer and exposes a first mask layer. Then ’as non-equal money

第4頁一圖蝕而序驟另口相層程步上開等半刻些塗線非上姓一再電以的在去料導。層。省材有層緣成可阻具罩絕形屬光係遮在時金出料二成同入移材第形被填後阻一會層中之光出口半洞。此露開下溝層而暴線的和半，並電層洞上上口導緣層的層開，絕介層緣洞層在在緣絕層緣則時絕在介絕口同刻料於刻開，蝕材準蝕洞後法阻對法層成刻光案刻介完。 483109 五、發明說明（2) 當積體電路縮小尺寸時，解決RC延遲現象和提高内連線高效能的重點在於如何整合銅/低介電材料（介電值小於 3. 0 )製程。金屬銅可以有效降低導電線的電阻，而低介電材質則可減少内金屬導線間的電容。現今旋塗式介電材料 (S0D)是一有潛力的製程作為量產的應用，使用的材料包含芳香族熱固樹脂聚合物（aromatic thermoset polymer )或其他物質。通常，當所使用的低介電材料的含碳量和孔係度增加時，低介電材料的機械強度會遠差於傳統使用的二氧化石夕。因此，又增加了整合銅/低介電材料製程的困難度，特別是使用極低介電材料（ultra-low-k，k<2_5 )時有更差的機械強度。如何形成雙鑲嵌結構就成了製造積體電路的一個挑戰。 5 - 3發明目的及概述：Page 4 A picture is etched and another step is taken. The other steps are opened. Wait for half a while. The painting line is not the last name. Floor. The material can be layered to prevent the material from covering the shape. The light system is covered with gold. The material is 20% into the same. After the shape of the material is filled, it blocks the light exit half hole in the layer for a while. This exposes the lower trench layer and the violent line is half and half, and the upper layer of the upper layer of the conductive edge layer is opened. The insulating layer edge hole layer is at the edge of the insulating layer at the same time. After the quasi-etching of the corroded material, the method of resisting the engraving of the normal layer is finished. 483109 V. Description of the invention (2) When the size of the integrated circuit is reduced, the focus of solving the RC delay phenomenon and improving the high-efficiency of the interconnect is how to integrate the copper / low-dielectric material (dielectric value less than 3.0) process. Copper metal can effectively reduce the resistance of conductive wires, while low dielectric materials can reduce the capacitance between the inner metal wires. Today's spin-on dielectric materials (S0D) are a promising manufacturing process for mass production applications, using materials that include aromatic thermoset polymers or other substances. Generally, when the carbon content and porosity of the low-dielectric material used are increased, the mechanical strength of the low-dielectric material will be far worse than that of the conventionally used dioxide. Therefore, the difficulty of integrating the copper / low-dielectric material manufacturing process is increased, and the mechanical strength is worse when using ultra-low-k (k < 2-5). How to form a dual damascene structure has become a challenge in manufacturing integrated circuits. 5-3 Invention Purpose and Overview:

第5頁 483109 五、發明說明（3) 本發明的一目的在提供一形成一雙鑲嵌結構的方法。本發明的另一目的為提供一在銅/低介電材料製程中形成一雙鑲後結構的方法。根據以上所述之目的，本發明提供之方法至少包括下列步驟。首先，提供一底材。然後，形成一第一低介電層在此底材上。之後，再形成一第二低介電層在此第一低介電層上。接著，除去部分第二低介電層和第一低介電層以形成一第一介層洞於第一低介電層内。然後’除去部分第二低介電層以形成一第二介層洞於第二低介電層内且連通至第一介層洞。接下來，形成一導體層填滿第一介層洞和第二介層洞。下一步，移除此第二低介電層。最後，形成一低介電值介電層在此第一低介電層上並暴露出導體層。 5 - 4發明詳細說明：本發明的半導體設計可被廣泛地應用到許多半導體設計中，並且可利用許多不同的半導體材料製作，當本發明以一較佳實施例來說明本發明方法時，習知此領域的人士應有的認知是許多的步驟可以改變，材料及雜質也可替換，這些一般的替換無疑地亦不脫離本發明的精神及範疇。Page 5 483109 V. Description of the invention (3) An object of the present invention is to provide a method for forming a double mosaic structure. Another object of the present invention is to provide a method for forming a double post-mount structure in a copper / low-dielectric material process. According to the above-mentioned object, the method provided by the present invention includes at least the following steps. First, a substrate is provided. Then, a first low dielectric layer is formed on the substrate. After that, a second low dielectric layer is formed on the first low dielectric layer. Then, a part of the second low dielectric layer and the first low dielectric layer are removed to form a first dielectric layer hole in the first low dielectric layer. Then, a portion of the second low dielectric layer is removed to form a second dielectric hole in the second low dielectric layer and communicate with the first dielectric hole. Next, a conductor layer is formed to fill the first via hole and the second via hole. Next, this second low dielectric layer is removed. Finally, a low-k dielectric layer is formed on the first low-k dielectric layer and the conductor layer is exposed. 5-4 Detailed description of the invention: The semiconductor design of the present invention can be widely applied to many semiconductor designs, and can be made of many different semiconductor materials. When the present invention is described by a preferred embodiment, Those skilled in the art should recognize that many steps can be changed, materials and impurities can be replaced, and these general replacements undoubtedly do not depart from the spirit and scope of the present invention.

第6頁 483109 五、發明說明（4) 其次，本發明用示意圖詳細描述如下，在詳述本發明實施例時’表不半導體結構的剖面圖在半導體製程中會不依一般比例作局部放大以利說明，然不應以此作為有限定的認知。此外，在實際的製作中，應包含長度、寬度及深度的三維空間尺寸。本發明的一些實施例會詳細描述如下。然而，除了詳細描述外，本發明還可以廣泛地在其他的實施例施行，且發明的範圍不受限定，其以之後的專利範圍為準。本發明提出一新程序步驟來形成一雙鑲嵌結構。本方法至少包含下列步驟且在第一圖到第五圖會被詳細地解釋參照第一一第一低介電，第一低介電低介電層20的。而第二低介第二低介電層等。第二低介的蝕刻選擇性間也可能會使圖，首先層2 0和一層2 0的厚材質係為電層22的 2 2的材質電層2 2的。而在第用黏著促下一步，形成一遮罩層，提供一底材1 0。然後，依序形成第二低介電層2 2在底材1 0上。其中度範圍約為5 0 0到4 0 0 0埃，且第一低介電質，如氧化物或氟矽玻璃等厚度範圍約為1 5 0 0到2 0 0 0 0埃，且係為低介電質，如氮化矽或碳化矽蝕刻選擇性不同於第一低介電層2 0 二低介電層2 2和第一低介電層2 0之進劑或停止層來幫助製程的進行。 3 0在第二低介電層2 2上。此遮罩層Page 6 483109 V. Description of the invention (4) Secondly, the present invention is described in detail with a schematic diagram. In the detailed description of the embodiment of the present invention, the cross-sectional view of the “Semiconductor Structure” will not be partially enlarged according to the general scale in the semiconductor manufacturing process to facilitate Explain, but this should not be used as a limited recognition. In addition, the actual production should include three-dimensional space dimensions of length, width and depth. Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the invention is not limited, which is subject to the scope of subsequent patents. The present invention proposes a new program step to form a double mosaic structure. This method includes at least the following steps and will be explained in detail in the first to fifth drawings. Referring to the first to the first low dielectric, the first low dielectric low dielectric layer 20. And the second low dielectric layer, the second low dielectric layer, and so on. The second low dielectric etch selectivity may also make the figure. First, the thickness of the layer 20 and the layer 20 is made of the material 22 2 of the electrical layer 22. In the next step, adhesion is used to form a mask layer to provide a substrate 10. Then, a second low-dielectric layer 22 is sequentially formed on the substrate 10. The degree range is about 5 0 to 4 0 0 angstroms, and the thickness of the first low dielectric material, such as oxide or fluorosilicate glass, is about 1 500 to 2 0 0 0 angstroms, and is Low dielectrics, such as silicon nitride or silicon carbide, have different etch selectivity than the first low dielectric layer 220, the low dielectric layer 22, and the first low dielectric layer 20, or a stopper layer to aid the process Carry on. 3 0 is on the second low dielectric layer 22. This mask layer

第7頁 483109Page 7 483109

五、發明說明（5) 3 0的厚度範圍約為} 〇〇到2 〇〇〇埃V. Description of the invention (5) The thickness range of 30 is about} 〇〇 2 〇〇〇 angstrom

參照第二圖，在一連串的微影程序後，在〜一層2 2和第一低介電層2 〇内形成一雙鑲嵌結構。弟—低介電構係至少包含一第一介層洞在第一低介電層内1^雙鑲嵌結介層洞在第二低介電層内22並暴露出底材丨曰〇。发0與—第二介層洞係與第一介層洞相通且此第二介層洞係^中第二的空間。其中第一低介電層2 0係作為一介層洞作導電線 (via-1 eve ：[ dielectric)，故第一低介^層介電質小於第二低介電層2 2的厚度。然後，共形地^一厚度遠 4 0在遮罩層3 0和雙鑲嵌結構上並把雙鑲嵌結埴厂導體層體層40的材質係可使用金屬銅。下一步，以一化j。此導磨程序將在雙鑲嵌結構外多餘的導體層4 〇移除，學機械研機械研磨程序係停止在遮罩層3 〇上。在本方法且此化學導體層前更包含形成一金屬襯裡層（圖中未示在形成層係共形地形成在遮罩層3 〇和在雙鑲嵌結構之—=襯裡部表面上。此金屬襯裡層使用的材質可為鈦/則壁和底氮化鈕’且在遮罩層3 〇上的金屬襯裡層會鈦或鈕/ 程序中同時被移除。化予機械研磨參照第三圖，移除硬遮罩層30後再將第二低八“ 除。因為第二低介電層2 2的蝕刻選擇性不同於第二電層移層2 0的蝕刻選擇性，因此可以使用簡單的蝕刻程，介電第二低介電層2 2，如濕蝕刻程序或乾蝕刻程序。:移除在本方法Referring to the second figure, after a series of lithography procedures, a double damascene structure is formed in ~ one layer 22 and the first low dielectric layer 200. The brother-low dielectric structure comprises at least a first dielectric hole in the first low dielectric layer and a double-damascene junction. The dielectric hole is in the second low dielectric layer 22 and the substrate is exposed. The second space of the second interstitial cave system is in communication with the first interstitial cave and the second interstitial cave system ^. The first low dielectric layer 20 is used as a via hole as a conductive line (via-1 eve: [dielectric), so the dielectric of the first low dielectric layer is smaller than the thickness of the second low dielectric layer 22. Then, conformally ^ a thickness of 40 on the mask layer 30 and the dual-mosaic structure and the dual-mosaic junction factory conductor layer body layer 40 can be made of metallic copper. The next step is to normalize j. This guide grinding procedure will remove the extra conductor layer 40 outside the double damascene structure. The mechanical grinding procedure is stopped on the mask layer 30. Before the method and the chemical conductor layer, it further comprises forming a metal backing layer (not shown in the figure, the forming layer system is conformally formed on the masking layer 30 and on the surface of the double-inlay structure— = the backing portion. The material used for the backing layer can be titanium / wall and bottom nitride button 'and the metal backing layer on the cover layer 30 will be removed at the same time in the titanium or button / procedure. Refer to the third figure for mechanical grinding, After removing the hard mask layer 30, the second lower eight is removed. Because the etching selectivity of the second low dielectric layer 22 is different from the etching selectivity of the second electrical layer transfer layer 20, a simple Etching process, dielectric second low dielectric layer 22, such as wet etch process or dry etch process.:Remove in this method

483109 五、發明說明（6) 中，取決於硬遮罩層3 0的材質，硬遮罩層3 0和第二低介電層2 2也可被同時移除。在此，第二低介電層2 2係作為低介電材料之模子（mold)。參照第四圖，接下來，一低介電值介電層2 4，特別是介電值小於2. 5，被回填在第一低介電層2 0上。然後，進行一平坦化程序移除多餘的低介電值介電層24並暴露出導體層4 0。第一低介電層2 0係作為低介電值介電層2 4堅固的支撑物（s t r ο n g b a s i s)，特別是低介電材料有較差的機械強度。更甚者，由於第一低介電層2 0的厚度遠小於低介電值介電層24的厚度，因此並不會大幅提昇總和介電層的介電值。參照第五圖，最後，形成一覆蓋層42(cap layer)在低介電值介電層2 4和導體層4 0上。此覆蓋層4 2的厚度範圍約為2 0 0到1 0 0 0埃，且覆蓋層4 2的材質係可為氮化矽，碳化矽，鈦，或氮化鈦。綜合上述，本發明提供一形成一銅/低介電材料雙鑲嵌結構的方法。首先，本方法使用一第一和一第二低介電物質來形成一雙鑲嵌結構。其中，第一低介電物質（如氧化物，氟矽玻璃等）係用作為一介層洞同層介電質（v i a -level dielectric)。而第二低介電物質與第一低介電物質則是有不同的蝕刻選擇性，且第二低介電物質係用作一483109 5. In the description of the invention (6), depending on the material of the hard mask layer 30, the hard mask layer 30 and the second low dielectric layer 22 can also be removed at the same time. Here, the second low dielectric layer 22 is used as a mold of a low dielectric material. Referring to the fourth figure, next, a low dielectric value dielectric layer 24, especially a dielectric value less than 2.5, is backfilled on the first low dielectric layer 20. Then, a planarization process is performed to remove the excess low-k dielectric layer 24 and expose the conductive layer 40. The first low dielectric layer 20 is used as a solid support (s t r ο n g b a s i s) of the low dielectric value dielectric layer 24, and especially the low dielectric material has poor mechanical strength. Furthermore, since the thickness of the first low dielectric layer 20 is much smaller than the thickness of the low dielectric value dielectric layer 24, the dielectric value of the total dielectric layer is not greatly improved. Referring to the fifth figure, finally, a cap layer 42 (cap layer) is formed on the low-k dielectric layer 24 and the conductor layer 40. The thickness of the covering layer 42 is about 200 to 100 angstroms, and the material of the covering layer 42 can be silicon nitride, silicon carbide, titanium, or titanium nitride. To sum up, the present invention provides a method for forming a dual embedded structure of copper / low dielectric material. First, the method uses a first and a second low dielectric substance to form a dual damascene structure. Among them, the first low-dielectric substance (such as oxide, fluorosilica glass, etc.) is used as a via-layer dielectric (v i a -level dielectric). The second low-dielectric substance and the first low-dielectric substance have different etching selectivities, and the second low-dielectric substance is used as a

第9頁 483109 五、發明說明（7) , 模子（mo 1 d )以完成雙鑲嵌結構。接下來，使用乾或濕蝕刻法移除第二低介電物質。最後，將極低介電值材料（k<2. 5 : )填入雙鑲嵌結構。其中，第一低介電物質可作為極低介電值材料堅固的支樓物（strong basis)。以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍内。Page 9 483109 V. Description of the invention (7), mold (mo 1 d) to complete the dual mosaic structure. Next, dry or wet etching is used to remove the second low dielectric substance. Finally, a very low dielectric material (k < 2.5: 5) is filled into the dual damascene structure. Among them, the first low dielectric substance can be used as a strong basis for very low dielectric material. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

第10頁 483109 圖式簡單說明第一圖係依據本發明所揭露之方法在底材上依序形成具一第一低介電層的剖面示意圖。第二低介電層層，以及一硬遮罩層第二圖係為在第一圖之結構上形成一雙鑲嵌結構並填入導體物質的剖面示意圖。第三圖係為在第二圖之結構上移除硬遮罩層和第二低介電層的剖面示意圖。第四圖係為在第三圖之結構上回填入一低介電值介電層的剖面示意圖。第五圖係為在第四圖之結槔上形成一覆蓋層在低介電值介電層和導體物質上的剖面示意圖。主要部分之代表符號： 10底材 2 0第一低介電層 2 2第二低介電層 2 4低介電值介電層 3 0硬遮罩層 4 0導體物質，金屬銅層 42覆蓋層Page 10 483109 Brief Description of Drawings The first drawing is a schematic cross-sectional view of a substrate with a first low dielectric layer formed sequentially on a substrate according to the method disclosed in the present invention. The second low-dielectric layer and a hard mask layer The second diagram is a schematic cross-sectional view of a double-mosaic structure formed on the structure of the first diagram and filled with a conductive substance. The third figure is a schematic cross-sectional view of the structure of the second figure with the hard mask layer and the second low dielectric layer removed. The fourth figure is a schematic cross-sectional view of the structure of the third figure backfilled with a low-k dielectric layer. The fifth diagram is a schematic cross-sectional view of a low-k dielectric layer and a conductive substance formed on the scab of the fourth diagram. Representative symbols of the main parts: 10 substrate 2 0 first low dielectric layer 2 2 second low dielectric layer 2 4 low dielectric value dielectric layer 3 0 hard mask layer 4 0 conductor material, metal copper layer 42 covering Floor

Claims

的層電 ο 介性二擇第選該刻其一，的法層方電之介項一 1 第該圍於範同利不專性請擇申選如刻 2 0 483109 六、申請專利範圍 1. 一種形成一雙鑲嵌結構的方法，該方法至少包括：提供一底材；形成一第一介電層在該底材上，其中該第一介電層的厚度約為5 0 0埃至4 0 0 0埃；形成一第二介電層在該第一介電層上，其中該第二介電層的厚度約為1 5 0 0埃到2 0 0 0 0埃；除去部分該第二介電層和該第一介電層以形成一第一介層洞於該第一介電層内；除去部分該第二介電層以形成一第二介層洞於該第二介電層内且連通至該第一介層洞；形成一導體層填滿該第一介層洞和該第二介層洞；移除该弟《—介電層，以及形成一低介電值介電層在該第一介電層上並暴露出該導體層。 3.如申請專利範圍第1項之方法，其中上述之第一介電層係可由下列材質選出：氧化物和氟矽玻璃。 4.如申請專利範圍第1項之方法，其中上述之第二介電層係可由下列材質選出：氮化石夕和碳化石夕。The layer of electricity ο The second choice of the dielectric is one of the moment, the one of the law of the Fangfang electric is 1 The first one is the one that is not specific to Fan Tongli, please choose the application as the moment 2 0 483109 6. The scope of patent application 1 A method for forming a double damascene structure, the method at least comprises: providing a substrate; forming a first dielectric layer on the substrate, wherein the thickness of the first dielectric layer is about 50 Angstroms to 4 Angstroms 0 0 0 angstroms; forming a second dielectric layer on the first dielectric layer, wherein the thickness of the second dielectric layer is about 1 500 angstroms to 2 0 0 0 0 angstroms; excluding part of the second dielectric layer A dielectric layer and the first dielectric layer to form a first dielectric layer hole in the first dielectric layer; removing part of the second dielectric layer to form a second dielectric layer hole in the second dielectric layer Inside and connected to the first interlayer hole; forming a conductor layer to fill the first interlayer hole and the second interlayer hole; removing the "dielectric layer" and forming a low dielectric value dielectric A layer is on the first dielectric layer and exposes the conductor layer. 3. The method according to item 1 of the scope of patent application, wherein the first dielectric layer is selected from the following materials: oxide and fluorosilicate glass. 4. The method according to item 1 of the scope of patent application, wherein the above-mentioned second dielectric layer can be selected from the following materials: nitride stone and carbide stone.

第12頁 483109 六、申請專利範圍 5. 如申請專利範圍第1項之方法，更包含一步驟在形成該第二介電層後形成一硬遮罩層在其上。 6. 如申請專利範圍第1項之方法，在沉積該導體層之前更包含一步驟在該第一介層洞和該第二介層洞的一側壁和一底部表面上形成一金屬襯裡層。 7. 如申請專利範圍第1項之方法，其中上述之導體層的材質係為金屬銅。 8. 如申請專利範圍第1項之方法，在形成該導體層後更包含一步驟以一化學機械研磨程序移除多餘的該導體層。 9. 如申請專利範圍第1項之方法，其中係使用一蝕刻程序移除該第二介電層。 1 0.如申請專利範圍第1項之方法，其中上述之低介電值介電層的一介電值係小於2. 5。 1 1.如申請專利範圍第1項之方法，其中上述之低介電值介電層係使用一沉積程序形成。 1 2.如申請專利範圍第11項之方法，在沉積該低介電值介電層後更包含一平坦化步驟。Page 12 483109 6. Scope of Patent Application 5. The method of the first scope of patent application further includes a step of forming a hard mask layer on the second dielectric layer after the method is formed. 6. According to the method of claim 1 in the patent application scope, before depositing the conductor layer, a step of forming a metal backing layer on a sidewall and a bottom surface of the first via hole and the second via hole is further included. 7. The method according to item 1 of the scope of patent application, wherein the material of the aforementioned conductor layer is metallic copper. 8. According to the method of claim 1 in the scope of patent application, after forming the conductor layer, a step of removing the excess conductor layer by a chemical mechanical polishing process is included. 9. The method of claim 1, wherein the second dielectric layer is removed using an etching process. 10. The method according to item 1 of the scope of patent application, wherein a dielectric value of the above-mentioned low dielectric value dielectric layer is less than 2.5. 1 1. The method of claim 1 in the scope of patent application, wherein the above-mentioned low dielectric value dielectric layer is formed using a deposition process. 1 2. The method according to item 11 of the patent application scope, further comprising a planarization step after depositing the low dielectric value dielectric layer.

第13頁 483109 六、申請專利範圍 1 3.如申請專利範圍第1項之方法，更包含一步驟在該低介電值介電層和該導體層上形成一覆蓋層（cap layer)。 1 4. 一種形成一雙鑲嵌結構的方法，該方法至少包括：提供一底材；形成一第一介電層在該底材上；形成一第二介電層在該第一介電層上，其中該第二介電層的一蝕刻選擇性不同於該第一介電層的一蝕刻選擇性 j 形成一硬遮罩層在該第二介電層上；除去部分該硬遮罩層，該第二介電層，和該第一介電層以形成一第一介層洞於該第一介電層内；除去部分該硬遮罩層和該第二介電層以形成一第二介層洞於該第二介電層内且連通至該第一介層洞；形成一金屬銅層填滿該第一介層洞和該第二介層洞；使用一化學機械研磨程序移除多餘的該金屬銅層並停止在該硬遮罩層；移除該硬遮罩層；使用一蝕刻程序移除該第二介電層；形成一低介電值介電層在該第一介電層上並暴露出該金屬銅層，其中該低介電值介電層的一介電值係小於2.5 ;以及形成一覆蓋層（cap layer)在該低介電值介電層和該Page 13 483109 6. Scope of patent application 1 3. The method of the scope of patent application 1 further includes a step of forming a cap layer on the low-k dielectric layer and the conductor layer. 1 4. A method of forming a dual damascene structure, the method at least comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a second dielectric layer on the first dielectric layer Wherein an etch selectivity of the second dielectric layer is different from an etch selectivity of the first dielectric layer to form a hard mask layer on the second dielectric layer; removing a portion of the hard mask layer, The second dielectric layer and the first dielectric layer to form a first dielectric layer hole in the first dielectric layer; removing a part of the hard mask layer and the second dielectric layer to form a second A via hole is in the second dielectric layer and communicates with the first via hole; a metal copper layer is formed to fill the first via hole and the second via hole; and a CMP process is used to remove the via hole Excess the metal copper layer and stop at the hard mask layer; remove the hard mask layer; use an etching process to remove the second dielectric layer; form a low-k dielectric layer at the first dielectric The metal copper layer is exposed on the electrical layer, wherein a dielectric value of the low dielectric value dielectric layer is less than 2.5; and A cap layer is formed between the low-k dielectric layer and the low-k dielectric layer.

第14頁 483109 六、申請專利範圍金屬銅層上。 1 5.如申請專利範圍第1 4項之方法，其中上述之第一介電層係可由下列材質選出：氧化物和氟石夕玻璃。 1 6.如申請專利範圍第1 4項之方法，其中上述之第二介電層係可由下列材質選出：氮化石夕和碳化石夕。 1 7.如申請專利範圍第1 4項之方法，在形成該金屬銅層之前更包含一步驟在該第一介層洞和該第二介層洞的一側壁和一底部表面上形成一金屬襯裡層。 1 8 .如申請專利範圍第1 4項之方法，其中上述之低介電值介電層係使用一沉積程序形成。 1 9 .如申請專利範圍第1 4項之方法，在沉積該低介電值介電層後更包含一平坦化步驟。Page 14 483109 VI. Scope of patent application On the copper metal layer. 15. The method according to item 14 of the scope of patent application, wherein the first dielectric layer is selected from the following materials: oxide and fluorspar glass. 16. The method according to item 14 of the scope of patent application, wherein the second dielectric layer is selected from the following materials: nitride stone and carbide stone. 17. According to the method of claim 14 in the scope of patent application, before forming the metal copper layer, a method is further included to form a metal on a sidewall and a bottom surface of the first via hole and the second via hole. Lining layer. 18. The method according to item 14 of the scope of patent application, wherein the above-mentioned low-k dielectric layer is formed using a deposition process. 19. The method according to item 14 of the scope of patent application, further comprising a planarization step after depositing the low dielectric value dielectric layer.

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